GB2273202A - Field effect transistor - Google Patents

Field effect transistor Download PDF

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Publication number
GB2273202A
GB2273202A GB9321642A GB9321642A GB2273202A GB 2273202 A GB2273202 A GB 2273202A GB 9321642 A GB9321642 A GB 9321642A GB 9321642 A GB9321642 A GB 9321642A GB 2273202 A GB2273202 A GB 2273202A
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gate electrode
layer
source
substrate
insulating film
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GB9321642D0 (en
GB2273202B (en
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Minoru Noda
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority claimed from JP2104038A external-priority patent/JP2786307B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The field effect transistor having an asymmetric gate 2 comprises a source region 4, a drain region 5 and a side wall 9a. The side wall acts as a mask during ion implantation to form the source and drain regions so that the drain region is separated from the gate 2. The transistor has a reduced short channel effect, reduced source resistance, improved transconductance and improved drain breakdown voltage. <IMAGE>

Description

Field Effect Transistor and Production Method Thereof The present invention relates to a field effect transistor (hereinafter referred to as "FET") having an asymmetrical gate and a production method thereof.
Figure 5 shows a prior art production method of a selfaligned gate FET recited in Electronics Information and Communication Engineer's Society of Japan, Electronic Device Research Institute report, ED86-9, pp.23 to 28, "Optimization of MMIC GaAs Advanced SAINT Structure" (reference No.1).
In figure 5, reference numeral 1 designates a GaAs substrate. A p well 24 is produced in the substrate 1. Nchannel region 3 is produced in the p well 24. N+ ion implanted regions 16 and 17 constitute a source and a drain region, respectively. Numeral 12 designates a through-film for implantation comprising SiN which functions as a mask for ion implantation. Numeral 23 designates a dummy gate comprising a T-shaped photoresist. Numeral 25 designates a SiO2 film. Numeral 26 designates a gate electrode.
Numerals 61 and 71 designate a source and a drain electrode, respectively.
It is described in the reference No. 1 that an n+ ion implantation is carried out using the T-shaped photoresist as a mask (figure (a)), and further a pattern inversion is carried out and a gate electrode is produced by lift-off method, resulting in a structure shown in figure 5(b).
However, in the FET produced in this way, because the source and drain regions are produced symmetric with respect to the gate electrode 26, the interval between the source region 16 and the drain region 17 is reduced accompanying with the shortening of the gate length and the substrate leakage current between source and drain increases, thereby arising a short channel effect. In addition, when the distance between the gate and source is shortened to reduce the source resistance, the distance between the gate and drain is also necessarily shortened and the gate drain breakdown voltage is reduced.
In order to reduce the short channel effect and increase the gate drain breakdown voltage, a conventional production method of an FET having an asymmetrical gate which is described in the following is proposed.
As one of them, that which is also recited in the reference No. 1 will be described with reference to figure 6. In figure 6 the same reference numerals designate the same parts. It is described in the reference No. 1 that the device is produced as follows: After p well 24 and n type layer 3 are produced by ion implantation, a plasma CVD SiN film 12 is deposited, and a T-shaped dummy gate 23 is produced thereon. Using this dummy gate 23 as a mask, n+ ion implantation is carried out (figure 8(a)). Then, the angle of ion implantation is determined such that the distance between gate electrode and the end of the n+ layer at the drain side (Lgd) becomes larger than the distance between gate electrode and that at the source side (Lsg). Next, using an inverted pattern of dummy gate 23 as a mask, a Schottky junction part is apertured and metal of Mo/Au is deposited by DC sputtering.
Then, by flattening Au using diagonal direction ion milling, a gate electrode 26 is produced only on the Schottky junction part and finally ohmic electrodes 61, 71 are produced by lift-off and sintered, thereby resulting in a device of figure 6(b).
The n+ implanted layers which are produced by the diagonal direction ion implantation using the T-shaped gate electrode which is symmetric with respect to both of source and drain as a mask results in a difference between the distance between the gate-source distance Lsg and the gatedrain distance Lgd. This makes it possible to reduce the source resistance and to enhance the gate drain breakdown voltage at the same time. Furthermore, this enables providing a long distance between the source and the drain region, resulting in reduction in the short channel effect.
Figure 7 shows another prior art production method of FET having an asymmetric self-aligned gate, which is recited in IEEE Transactions on Electron Devices, Vol.35, No.5, May 1988, pp.615 to 622, "A New Refractory Self-Aligned Gate Technology for GaAs Microwave Power FET's and MMIC's" (reference No.2 ).
The production method will be described.
As shown in figure 7(a), a SiON film 12 is produced as through-film for implantation on a GaAs substrate 1, and thereafter, an active channel region 3 of FET is produced by selective ion implantation of silicon ions. Thereafter, the SiON film 12 is removed, a TiWN film is produced on the entire surface by sputtering, an etching mask comprising Ni 14 is produced at a gate electrode production region and the TiWN layer is processed so as to have a gate configuration 13 by reactive ion etching (figure 7(b)).
Next, photoresist pattern 15 of configuration that covers the drain side of the gate electrode 13 is produced as a mask for n+ ion implantation, and n+ ion implantation is carried out using the same as a mask to produce asymmetrical n+ ion implanted regions 16 and 17 among which the drain region is located more far from the gate electrode 13 than the source region (figure 7(c)).
Next, the photoresist 15 and Ni film 14 are removed, a SiON film 18 is provided on the entire surface of the substrate as a protection film which functions as an anneal cap at the annealing, and then an annealing is carried out to activate the implanted ions in the regions 16 and 17 (figure 7(d)). Thereafter, a flattening photoresist 19 is provided on the entire surface of substrate (figure 9(e)), a gate metal 13 is exposed by etching back, and ohmic metals 20 and 21 which are to be a source electrode and a drain electrode are produced by burying metal (-figure 7(f)).
Next, a low resistance metal 22 of Ti/Au is produced on the gate electrode 13 by evaporation and lift-off method (figure 7(g)), and thereafter a SiN film 27 is produced on the surface and Au electrodes 28 are produced on the ohmic electrodes 20 and 21 via TiWN layers 29. Further, an opening is provided at a part of the source electrode 20 from the rear surface of the substrate 1 and Au electrode 28 is plated on the rear surface covering the side wall of the opening and the entire rear surface of substrate, thereby completing the device (figure 7(h)).
In this production method, the photoresist pattern 15 covering the gate is produced only covering the drain side of the gate electrode 13, and at the n+ ion implantation of next process, so that n+ layer producing ions are not implanted into the vicinity of the gate electrode at the drain side. Thus an asymmetrical gate FET is produced; In the prior art production method shown in figure 6 the asymmetry of the production position of n+ layer with respect to the gate is realized by a diagonal implantation, and the angle of the diagonal implantation would vary depending on a position in the GaAs wafer surface and the position of the end portion of n+ layer is likely to vary depending on the configuration of T-shaped gate which functions as an implantation mask.That is, the position where the n+ layer is produced is likely-to be affected by variations in the configuration of T-shaped gate and this possibly cause to arise variations in the element characteristics.
In the prior art production method shown in figure 7 the photoresist mask which is produced at the drain side of the gate is position determined only by the alignment technique of photolithography and therefore the positioning of the photoresist mask is quite unstable. That is, the precision of the photoresist mask largely depends on the performance of the photolithography apparatus and it may possibly vary run to run. Therefore, an asymmetrical gate FET having a stable gate drain distance and a gate source distance as designed can not be produced at high reproducibility.
The present invention is concerned with solving the above-described problems as in our co-pending application no. 9105442.9 from which the present application has been divided.
In accordance with a first aspect of the present invention there is provided a method of producing a field effect transistor having a drain and a source comprising the steps of: producing a gate electrode on a surface of a substrate; covering said gate electrode and the surface of the substrate with a insulating layer; producing insulating film side walls on either side of said gate electrode by etching away said insulating film; applying a photoresist to the substrate, gate electrode and side walls and etching away part of the photoresist so as to expose at least a part of the side wall and the surface of the substrate at that side of the gate electrode which is to be the source side; etching away the side wall so exposed;; removing the photoresist, and producing source and drain regions on either side of said gate electrode using the remaining side wall as a mask for the drain region.
In accordance with a second aspect of the present invention there is provided a method of producing a field effect transistor comprising producing a gate electrode on a surface of a substrate forming a first insulating layer on the upper surface of the gate electrode, covering the gate electrode with its first insulating layer and the surface of the substrate with a second insulating layer of a material different from the first insulating layer; exposing the first insulating layer by etching;; covering the second layer and the exposed first layer with a photoresist mask having an opening above what will be the source region of the transistor etching away the second insulating layer at the side of the gate electrode which is to be the source side of the transistor, partially removing the second insulating layer on the other side of the gate electrode so as to leave a side wall, and carrying out ion implantation to produce a drain region at that side of the gate electrode still having a side wall with the side wall acting as a mask, and a source region at the other side of the gate electrode.
In accordance with a third aspect of the present invention there is provided a method of producing a field effect transistor comprising producing a gate electrode on a surface of a substrate, covering said gate electrode and the surface of the substrate with a first insulating layer, etching the first insulating layer to expose the uppermost part of the gate electrode, forming a second insulating layer over the first layer and the exposed gate electrode, processing the second insulating film so as to expose that part of .the.first insulating film which covers what is to be the source region of the transistor, covering the remaining second layer and the exposed first layer with photoresist having an opening above where the source region of the transistor is to be formed; etching away that part of the first layer which extends from one side of the gate electrode over that part of the substrate which is to be the source side of the transistor; removing the photoresist and partially removing the second insulating layer on the other side of the gate electrode so as to leave a side wall containing the gate electrode, and carrying out ion implantation to produce a drain region at that side of the gate electrode having the side wall with the side wall acting as a mask, and to produce a source region at the other side of the gate electrode.
In order that the present invention may be more readily understood an embodiment thereof will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a diagram showing a cross-sectional structure of a field effect transistor manufactured by a production method according to the present invention; Figure 2 is a diagram showing a production method for producing the FET of figure 1; Figure 3 is a diagram showing a production method of a second embodiment according to the present invention; Figure 4 is a diagram showing a production method of a third embodiment according to the present invention; Figure 5 is a diagram showing a prior art production method of an FET; Figure 6 is a diagram showing another prior art production method of an FET; and Figure 7 is a diagram showing a third prior art production method of an FET.
Referring now to the accompanying drawings reference numeral 1 indicates a GaAs substrate, 2 a refractory gate and 3 an n-channel region produced at the surface of substrate 1. Numerals 4 and 5 designate a source n+ layer and a drain n+ layer respectively.
Additionally numeral 41 designates a source electrode and numeral 51 designates a drain electrode. Numerals 7 and 7' designate photoresist patterns and 8 an opening of the photoresist 7. Reference numeral 9 designates an insulating film and reference numerals 9a and 9b designate side walls comprising the insulating film 9.
The following describes a production method.
Silicon ions are implanted by selective ion implantation into the GaAs substrate 1 at an energy of 10 to 50 keV and at a dose of 1 x 1012 to 1 x 1014cm-2. Or after a film of A1N, SiN, SiON or SiO (not shown) is deposited on the substrate 1 to a thickness of approximately 100 to 1000 angstroms as a through-film for implantation, silicon ions are implanted through that film at an energy of 30 to 100 KeV and at a dose of approximately 1 x 1012 to 1x1014cm-2 thereby producing an n-channel region 3.
Thereafter, refractory metal such as tungsten silicide is provided on the entire surface of the substrate and processed to a gate configuration 2.
Subsequently an insulating film 9 is deposited on the surface of substrate 1 and the surface of gate electrode 2 to cover the same (figure 4(a)).- Thereafter1 the insulating film 9 is etched so as to remain as side walls 9a and 9b at the both sides of the gate electrode 2 (figure 4(b)).
Then, a photoresist is applied so as to cover the surface of the substrate 1, the gate electrode 2, and the insulating film side walls 9a and 9b, and etching is carried out to produce an opening 8 at the photoresist 7 (figure 4(c)) so as to expose a portion of the surface of the side wall 9b at the source side and a portion of the substrate 1 at the side of source region.
Next, the insulating film side wall 9b is etched and removed (figure 4(d)) using such as plasma etching, by the similar process as that shown in figure 2(d).
Thereafter, as shown in figure 4(e), after the photoresist 7 is removed, photoresist pattern 7' is produced and ion implantation for producing n+ regions is carried out using the photoresist 7' as a mask, so that a drain n+ layer 5 separated from the gate and a source n+ layer 4 in contact with the gate are produced (figure 4(f)).
Thereafter, after the photoresist 7' is removed, a source electrode 41 and a drain electrode 51 are produced, thereby completing the element of figure 3.
In this embodiment the separation length between the gate electrode 2 and the drain n+ layer 5 is selfalignedly determined by the width of the insulating film side wall 9a. Since the insulating film 9b on the source n+ region and the insulating film 9a on the drain n; region are produced interposing the gate electrode 2 therebetween, only the insulating film 9b on the source n+ region is easily and selectively removed at high controllability.Furthermore, in this embodiment, since neither variation in position of the n+ layer edge is caused by an unstable implantation such as diagonal ion implantation nor the mask for implantation is produced by photolithography, an element in which the separation length of the source n+ layer and the drain n+ layer from the gate electrode 2 can be set to desired values with high precision is obtained with high reproducibility and high controllability. Furthermore, in this production method, the source n+ layer 4 and drain n+ layer 5 are produced at the same concentrations and the same depths.
Next, second and third embodiments of the present invention which are alternatives of the first embodiment will now be described.
In these embodiments a stopper that prevents removal of the insulating film just above the gate and the insulating film above the drain n+ layer is produced while the insulating film on the source n+ layer is selectively removed, thereby enhancing the preference of etching. That is, different kinds of insulating films having different properties of being etched are inserted so that the source n+ layer insulating film and the drain n+ layer insulating film are not connected with each other as the same film.
Figure 3 shows a production process of this third embodiment.
As shown in figure 3(a), a refractory gate 2 is produced on-the n-channel region 3 of GaAs substrate 1 and an insulating film (first insulating film) 10 is plated thereon and these are processed to a gate configuration in a two layer structure. Thereafter an insulating film (second insulating film) 6 having a property of being etched different from that of the first insulating film 10 is provided on the entire surface (figure 3(b)).
Thereafter, the second insulating film 6 is etched back to expose the surface of the first insulating film 10 (figure 5(c)), and a photoresist 11 is provided on the entire surface and an opening 8 which reaches the second insulating film 6 is produced at a portion of the photoresist 11 on the source n+ region (figure 3(d)).
Thereafter, the second insulating film 6 on the source n+ region is selectively removed by etching using this photoresist Pattern 11 as a mask. Here, in a case where SiN is used for the second insulating film 6 and SiO2 or SiO are used for the first insulating film 10, a plasma etching (PE) using SF6 series gas for the selective removal of the first insulating film is preferable and it is possible for the second insulating film 6 to have a large selectivity to the first insulating film 10. Furthermore, when SiO2 or SiO are used for the second insulating film 6 and SiN is used for the first insulating film 10, it is quite effective to utilize a reactive ion etching using CHF3 + C2H6 series gas for the selective removal of the second insulating film 6.
Next, as shown in Figure 3(e), after the photoresist 11 is removed, the second insulating film 6 remaining on the drain n+ region is etched and processed so as to remain only at the side wall part of the gate electrode at the drain side. At this time, since the width of this side wall becomes the distance between the gate and the drain n+ region, it should be previously produced at a design value.
Next, as shown in figure 3(g), ion implantation for producing n+ regions is carried out onto the entire surface of the substrate and a drain n+ region 5 separated by a predetermined distance from the gate electrode 2 and a source n+ region 4 in contact with the gate electrode 2 are produced self-alignedly with the gate electrode and the second insulating film side wall 6.
A production process flow of the fourth embodiment will be described with reference to figure 6.
As shown in figure 4(a), a refractory gate 2 is produced at the surface of GaAs substrate 1 on which the n-channel region 3 is produced and the first insulating film 6 is plated on the entire surface so as to cover the surface of the substrate 1 and the. gate 2. Thereafter, the first insulating film 6 is etched back to expose the surface of the gate electrode 2 (figure 4(b)).
Thereafter, a second insulating film 10 having a property of being etched different from that of the first insulating film 6 is provided so as to cover the entire surface of the first insulating film 6 and that of the exposed gate electrode 2 (figure 4(c)), and this insulating film 10 is processed so as to remain only at the surface of the gate electrode 2 and the surface of the first insulating film 6 on the drain n+ region (figure 4(d)).
Next, as shown in figure 4(e), a photoresist pattern 11 having an opening 8 at a portion on the source region is provided, and on the etching condition described in the process of figure 3(d) of the above described embodiment only the first insulating film 6 on the source n+ region is selectively removed. After the photoresist 11 is removed (figure 4(f)), the second insulating film 10 is removed and thereafter the remaining first insulating film 6 is etched and processed so as to remain only at the side wall of the gate electrode at the drain side, and the ion implantation for producing n+ layers is carried out using the gate electrode 2 and the side wall insulating film 6 as a mask, and a drain n+ region 5 is produced separated from the gate electrode by the width of the side wall and a source n+ region 4 is produced adjacent to the gate electrode 2.
In the above described second and third embodiments, a different kind of insulating film 10 that has different property of being etched is inserted in order that the insulating film 6 on the source n+ layer and the insulating film 6 on the drain n+ layer are not connected with each other as the same film. -In this production method, the insulating film 6 on the source n+ layer and the insulating film 6 on the drain n+ layer are separated and so selective removal of only the insulating film 6 on the source n+ layer is surely carried out.
In the above illustrated embodiments, only GaAs MESFETs are described, transverse transistors in which respective layers are provided transversely to the substrate surface horizontally, such as HEMT, MIS-like FET or Si MOSFET can be constructed with the same effects.
While in the above illustrated embodiments, GaAs is used for the substrate material 1, silicon or InP can be used therefor.
In summary, in the second embodiment of the present invention the separation length between the drain n+ layer and the gate is determined self-alignedly by the width of the side wall 9. In addition, in the second and third embodiments, since the insulating film on the source n+ layer and the insulating film on the drain n+ layer are separated, the insulating film on the source n+ layer can be surely selectively .remqved.
As is evident from the foregoing description, in those embodiments where a drain n+ layer is made shallow and of low concentration compared with the source layer and only the drain n+ layer is separated from the gate in an FET having an asymmetric gate, a high efficiency FET having reduced short channel effect, reduced source resistance, and further high transconductance, and high drain breakdown voltage is obtained.
In addition, when the drain n+ layer is produced by the implantation through the insulating film and the source n+ layer is produced either by implantation to bare surface or by implantation through a film thinner than the implantation through film for producing the drain n+ layer, only the drain n+ layer is separated from the gate. Then, a good efficiency FET having reduced short channel effect, reduced source resistance, improved transconductance, and improved drain breakdown voltage is self-alignedly produced at high controllability and high reproducibility, without utilizing the diagonal implantation which introduces unstable factors. This means that a high efficiency FET having a stable characteristics for run to run is resulted. In addition, when a structure in which the insulating film on the source n layer is separated from the insulating film on the drain n+ layer is obtained in the fabrication process, the insulating film on the source n+ layer can be surely selectively removed, thereby resulting in high controllability and high reproducibility in the fabrication process.

Claims (6)

1. A method of producing a field effect transistor having a drain and a source comprising the steps of: producing a gate electrode on a surface of a substrate; covering said gate electrode and the surface of the substrate with a insulating layer; producing insulating film side walls on either side of said gate electrode by etching away said insulating film; applying a photoresist to the substrate, gate electrode and side walls and etching away part of the photoresist so as to expose at least a part of the side wall and the surface of the substrate at that side of the gate electrode which is to be the source side; etching away the side wall so exposed; removing the photoresist, and producing source and drain regions on either side of said gate electrode using the remaining side wall as a mask for the drain region.
2. A method of producing a field effect transistor comprising producing a gate electrode on a surface of a substrate forming a first insulating layer on the upper surface of the gate electrode, covering the gate electrode with its first insulating layer and the surface of the substrate with a second insulating layer of a material different from the first insulating layer; exposing the first insulating layer by etching;; covering the second layer and the exposed first layer with a photoresist mask having an opening above what will be the source region of the transistor etching away the second insulating layer at the side of the gate electrode which is to be the source side of the transistor, partially removing the second insulating layer on the other side of the gate electrode so as to leave a side wall, and carrying out ion implantation to produce a drain region at that side of the gate electrode still having a side wall with the side wall acting as a mask, and a source region at the other side of the gate electrode.
3. A method of producing a field effect transistor comprising producing a gate electrode on a surface of a substrate, covering said gate electrode and the surface of the substrate with a first insulating layer, etching the first insulating layer to expose the uppermost part of the gate electrode, forming a second insulating layer over the first layer and the exposed gate electrode, processing the second insulating film so as to expose that part of the first insulating film which covers what is to be the source region of the transistor, covering the remaining second layer and the exposed first layer with photoresist having an opening above where the source region of the transistor is to be formed; etching away that part of the first layer which extends from one side of the gate electrode over that part of the substrate which is to be the source side of the transistor; removing the photoresist and partially removing the second insulating layer on the other side of the gate electrode so as to leave a side wall containing the gate electrode, and carrying out ion implantation to produce a drain region at that side of the gate electrode having the side wall with the side wall acting as a mask, and to produce a source region at the other side of the gate electrode.
4. A field effect transistor when constructed, adapted and arranged to operate substantially as described hereinbefore with reference to and as shown in figure 1 of the accompanying drawings.
5. A method for producing an asymmetric gate field effect transistor performed substantially as described hereinbefore with reference to any one of figures 2, 3 or 4.
6. A field effect transistor when manufactured by the method of any one of claims 1 to 3 or claim 5.
GB9321642A 1990-04-19 1993-10-20 Field effect transistor and production method thereof Expired - Fee Related GB2273202B (en)

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JP2104038A JP2786307B2 (en) 1990-04-19 1990-04-19 Field effect transistor and method of manufacturing the same
GB9105442A GB2243950B (en) 1990-04-19 1991-03-14 Field effect transistor and production method thereof

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0160255A2 (en) * 1984-04-30 1985-11-06 General Electric Company Field effect transistor device and method of making same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0160255A2 (en) * 1984-04-30 1985-11-06 General Electric Company Field effect transistor device and method of making same

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GB2273202B (en) 1994-10-12

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