JPH1140578A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of surface oxidation at the time of resist elimination, realize uniform substrate etching, and obtain a semiconductor device which can restrain the influence of surface level by a simple manufacturing method. SOLUTION: This equipment forms an upper resist layer 13 and a lower resist layer 14 different in photosensitivity on a semiconductor substrate 10, exposes to light and develops the upper resist layer 14, and exposes the lower resist layer 13. A part of an exposed region 13a is exposed to light and developed, and a semiconductor substrate 10 is exposed. The lower resist layer 13 is used as a mask, a recess trench 20a is formed by etching the semiconductor substrate 10. The upper layer resist 14 is used as a mask, the exposed region 13a of the lower resist layer is exposed to light and developed, and the exposed region 10a of the semiconductor substrate is enlarged. The lower layer resist 13 is used as a mask, a two-step type recess trench 20b is formed by etching the semiconductor substrate 10. A gate electrode 15 covering the deeper bottom surface and side surface of the recess trench 20b is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a Schottky junction type gate electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher performance of devices, an FET (Field Effect Transistor) using a compound semiconductor such as GaAs, which is advantageous for speeding up, has been developed.
Stor) or IC (Integrated Circuit)
It) has been actively developed. Generally, the gate electrode of the above FET is a Schottky electrode,
By modulating the width of the depletion layer immediately below the gate electrode by the input voltage applied to the gate electrode, the drain current is extracted as an output.

However, many trap levels exist on the surface of the substrate on which the source and drain electrodes forming an ohmic junction with the substrate and the gate electrode forming a Schottky junction are formed. Since the time constant of the exchange is longer than the period of the normal signal voltage input to the gate electrode, the change in the depletion layer width cannot follow the change in the signal voltage. Therefore, there is a problem that the output waveform is distorted and the normal operation of the semiconductor device is hindered.

The above problem becomes more pronounced as the thickness of the channel layer becomes thinner and the concentration thereof becomes lower. For example, in an n-channel type FET, the problem becomes larger as the FET has a higher threshold voltage. That is, a depletion type FET (hereinafter, referred to as a depletion type FET)
It is called "D-FET". ), The above-mentioned problem appears more remarkably in the enhancement type FET (hereinafter, referred to as “E-FET”).

Therefore, recently, the influence of the trap level on the substrate surface has been suppressed by forming the gate electrode so as to fill the recess groove provided on the main surface of the GaAs substrate and increasing the distance between the substrate surface and the channel layer. Then, a technique for solving the above problem has been developed.

An example of such a conventional FET in which a Schottky junction type gate electrode is buried in a recess groove is disclosed in Japanese Unexamined Patent Publication No. Hei 8-330329.
Will be described with reference to FIG. Here, FIG. 7 is a cross-sectional view of a main part showing a conventional method for manufacturing an FET in the order of steps.

First, as shown in FIG. 7A, for example,
An n-type G is placed on a semi-insulating substrate body 31 made of GaAs.
channel layer 32 made of aAs, undoped GaAs
Intrinsic semiconductor layer 33 of high concentration n-type (hereinafter referred to as "n ⁺ ")
It is described. ) Contact layer 34 made of GaAs
For example, MBE (Molecular Beam E)
pitaxy) method or MOCVD (Metal Or)
ganic Chemical Vapor Depo
A semiconductor substrate 40 is formed by growing the semiconductor substrate 40 in this order by using an epitaxial growth technique such as a sition method, an insulating film 35 made of, for example, a silicon oxide film is formed thereon, and a photolithography technique using a resist 36 is used. An opening 35a is formed in the insulating film 35.

Next, as shown in FIG. 7B, the resist 36 is removed, and then a resist having an opening 37a wider than the insulating film 35 surrounding the opening 35a of the insulating film is formed on the insulating film 35. 37 is formed. At this time, the resist 36
An oxide film 38 is formed on the surface of the semiconductor substrate 40 by an oxidation reaction due to the removal of the oxide film 38.

Next, as shown in FIG.
Using the mask 5 as a mask, the semiconductor substrate 40 is etched,
A recess groove 40a is formed in the substrate 40.

Next, as shown in FIG. 7D, the insulating film 35 is etched again using the resist 37 as a mask to enlarge the opening 35a of the insulating film.

Next, as shown in FIG. 7E, using the etched insulating film 35 as a mask,
By etching 0 again, a two-step recessed groove 40 b is formed in the substrate 40. At this time, FIG.
In the previous step shown in FIG.
Since 0a is formed, the portion where the recess groove 40a has been formed is eventually etched deeper than the other portions, so that the recess groove 40b is formed in a two-step shape. .

Next, as shown in FIG. 7 (f), Ti / A
A gate electrode 39 made of a 1-layer film is formed by a lift-off method.

The gate electrode 39 thus formed is
Since it is formed on the bottom surface of the substrate recess 40b, the substrate 40
Since the surface is hardly affected by the trap level of the surface, and the deep bottom surface and the side surface of the concave portion 40b are completely covered, the influence of the surface trap level can be further suppressed.

[0014]

However, in the above-described method of manufacturing the gate electrode 39 of the Schottky junction type FET, as shown in FIG. In other words, the step of removing the resist is required, that is, the step of removing the resist 36 is required, which causes a problem that the process becomes complicated. or,
By removing the resist 36, an oxide film 38 is formed on the surface of the semiconductor substrate 40. Due to the influence of the oxide film 38, the shape of the recess groove 40a in the etching process of the substrate 40 shown in FIG. Problems such as non-uniformity and poor reproducibility.

The present invention has been made in view of the above points, and solves the problem of surface oxidation of a substrate when removing a resist, enables uniform substrate etching, and uses a simpler process. It is an object of the present invention to obtain a semiconductor device capable of suppressing the influence of a surface trap level.

[0016]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming upper and lower two-layer resists having different photosensitivity on a semiconductor substrate, and exposing the upper resist to the two-layer resist. And developing, exposing the lower layer resist, exposing a part of the exposed area of the lower layer resist, developing and exposing the semiconductor substrate, and using the lower layer resist as a mask, Etching the exposed semiconductor substrate to form a concave portion in the semiconductor substrate, and exposing the exposed region of the lower resist using the upper resist as a mask;
Developing and expanding the exposed region of the semiconductor substrate, and etching the semiconductor substrate in which the concave portion is formed using the lower resist as a mask to form a two-step step-shaped concave portion in the semiconductor substrate. And a step of forming an electrode made of metal to cover the deeper bottom and side surfaces of the two-step recess.

A step of forming upper and lower two-layer resists having different photosensitivity on the semiconductor substrate; and a step of exposing and developing a plurality of regions of the upper-layer resist of the two-layer resist to form a plurality of lower-layer resists. And exposing a portion of the other exposed regions, excluding at least one of the exposed regions of the plurality of exposed regions of the underlying resist, developing and exposing the semiconductor substrate A first concave portion forming step of etching the exposed semiconductor substrate using the lower resist as a mask to form a concave portion in the semiconductor substrate; and exposing the exposed region of the lower resist using the upper resist as a mask. And developing, and etching the semiconductor substrate using the lower resist layer as a mask to form a two-step recess in the region of the semiconductor substrate where the recess is formed. A second recess forming step of forming a one-stage recess in at least one other region, an electrode made of a metal covering a deeper bottom surface and side surfaces of the two-stage recess, and Forming an electrode made of metal covering the bottom surface.

Further, the method includes a step of forming an element isolation region between a region in which the two-stepped concave portion is formed and a region in which the one-step concave portion is formed in the semiconductor substrate.

A step of forming, in this order, two upper and lower resist layers having different photosensitivity from the insulating film on the semiconductor substrate; exposing and developing the upper resist layer of the two resist layers to form a lower resist layer; Exposing a part of the exposed region of the lower resist, exposing and developing the insulating film, and etching the insulating film using the lower resist as a mask, the semiconductor Exposing the substrate, etching the exposed semiconductor substrate to form a concave portion in the semiconductor substrate, and etching the insulating film using the lower resist as a mask to form the insulating film. Retreating the end face of the film under the lower resist, exposing the exposed area of the lower resist using the upper resist as a mask, and developing. Etching the semiconductor substrate in which the recess is formed using the insulating film as a mask to form a two-step recess in the semiconductor substrate; and forming a deep recess in the two-step recess. Forming an electrode made of metal that covers the bottom and side surfaces.

Further, in the step of etching the insulating film using the lower resist as a mask and retreating the end face of the insulating film below the lower resist, the end face of the insulating film is exposed to the exposed area of the lower resist. It is characterized in that it is retracted below.

Further, the semiconductor substrate is characterized by comprising a plurality of semiconductor layers having different etching resistance under the etching conditions in the first or second recess forming step.

According to the semiconductor device of the present invention, there is provided a first element forming region including one stepped concave portion on one main surface, a second element forming region including a two stepped concave portion, and the first and second elements. A semiconductor substrate having an element isolation region for isolating the first element formation region, a first Schottky electrode formed in the first element formation region and covering a bottom surface of the one-stage concave portion, and the first Schottky electrode A first field-effect transistor having a pair of ohmic electrodes formed with the electrodes interposed therebetween;
A second Schottky electrode formed in the second element formation region and covering a deeper bottom surface and side surfaces of the two-step concave portion, and a pair of ohmics formed with the second Schottky electrode interposed therebetween; And a second field-effect transistor having electrodes.

The first field-effect transistor is a depletion-type field-effect transistor, and the second field-effect transistor is a second field-effect transistor.
Is characterized in that it is an enhancement type field effect transistor.

Also, a semiconductor substrate having one stepped recess and two stepped recesses on one main surface, and a pair of semiconductor layers formed on the main surface of the semiconductor substrate with the one stepped and two stepped recesses interposed therebetween. Ohmic electrode, and a pair of parallel Schottky electrodes formed between the pair of ohmic electrodes on the semiconductor substrate, one of the pair of Schottky electrodes covers the bottom surface of the one-stage recess, the other One is characterized in that it covers the deeper bottom and side surfaces of the two-step concave portion.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a fragmentary cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention in the order of steps.

First, as shown in FIG. 1A, for example,
On a semi-insulating substrate body 1 made of GaAs, for example, MB
E (Molecular Beam Epitaxy)
Method or MOCVD (Metal Organic C)
n-type GaAs using an epitaxial growth technique such as a chemical vapor deposition method.
The semiconductor substrate 10 is formed by growing the channel layer 2 made of s, for example, AuGe alloy / Ni / Au at a desired position on the semiconductor substrate 10 by using a normal deposition lift-off technique and a sintering technique. Source and drain electrodes 11 and 12 made of a laminated film are formed.

Subsequently, on the semiconductor substrate 10, for example, PMGI (Polymethyl Glutari)
deep UV (Ultra Vio)
Let) a lower resist 13 sensitive to light or electron beam (EB) is applied, and an upper resist 1 sensitive to UV light (for example, i-line) such as AZ5206E is applied thereon.
4 is applied. Thereafter, the upper resist 14 is processed into a desired shape by performing an exposure using an i-line stepper and an image reversal process, thereby exposing the lower resist 13. Here, 13a represents an exposed region of the lower resist. The reason why the image reversal process is used here is to facilitate lift-off in a later gate electrode manufacturing process.

Next, as shown in FIG. 1B, a portion of the exposed region 13a is exposed and developed by an excimer stepper or EB to expose the semiconductor substrate 10. here,
10a represents an exposed region of the semiconductor substrate.

Next, as shown in FIG. 1C, the semiconductor substrate 10 is etched to a desired depth using a tartaric acid-based solution using the lower resist 13 as a mask to form a first recess groove 20a. To form

Next, as shown in FIG.
The entire upper surface is exposed with deep UV light and developed. As a result, the upper resist 14 serves as a mask, the lower resist 13 is removed, and the exposed region 10a of the substrate is enlarged.

Next, as shown in FIG. 1E, the second recess groove 20b is formed by etching the semiconductor substrate 10 in which the exposed region 10a is enlarged for a desired time using the lower resist 13 as a mask. I do. The second recess groove 20b has a two-step shape because the portion where the first recess groove 20a was formed is etched deeper.

Next, as shown in FIG.
A gate electrode 15 is formed by depositing a Ti / Al laminated film on the entire upper surface and performing lift-off. Here, the gate electrode 15 has a shape that covers the bottom and side surfaces of the deeply etched portion of the second recess groove 20b.

In the first embodiment, since the step of removing the resist is only the lift-off step at the time of forming the gate electrode 15, the problem of the conventional surface oxidation of the substrate at the time of removing the resist can be solved. Thus, the substrate 10 can be etched with good reproducibility. Therefore, a high-performance and highly reliable semiconductor device can be obtained. Further, it is possible to obtain a semiconductor device capable of suppressing the influence of the surface trap level by using a simpler process than in the related art.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.

First, as shown in FIG. 2A, for example,
On a semi-insulating substrate body 1 made of GaAs, for example, MB
E (Molecular Beam Epitaxy)
Method or MOCVD (Metal Organic C)
n-type GaAs using an epitaxial growth technique such as a chemical vapor deposition method.
The semiconductor substrate 10 is formed by growing the channel layer 2 made of s, for example, AuGe alloy / Ni / Au at a desired position on the semiconductor substrate 10 by using a normal deposition lift-off technique and a sintering technique. Source and drain electrodes 11 and 12 made of a laminated film are formed.

Subsequently, an insulating film 16 made of, for example, a silicon oxide film is formed on the semiconductor substrate 10 and, for example, PMGI (Polydimethyty) is formed on the insulating film 16.
Deep UV (U) such as lGlutarimide
(Lower Violet) Light or electron beam (EB) is applied with a lower resist 13 and, for example, A
An upper resist 14 that is sensitive to UV light (for example, i-line) such as Z5206E is applied.

After that, the upper resist 14 is processed into a desired shape by performing an exposure using an i-line stepper and an image reversal process, thereby forming the lower resist 1.
Expose 3 Here, 13a represents an exposed region of the lower resist. Here, the image reversal process is used in a later gate electrode manufacturing process.
This is to facilitate lift-off. Subsequently, a portion of the exposed region 13a is exposed and developed by an excimer stepper or EB to expose the insulating film 16. continue,
The semiconductor substrate 10 is exposed by etching the insulating film 16 using the lower resist 13 as a mask. Here, 10a represents an exposed region of the semiconductor substrate.

Next, as shown in FIG. 2B, the semiconductor substrate 10 is etched to a desired depth using a tartaric acid solution to form a first recess groove 20a.

Next, as shown in FIG.
6 is side-etched using the lower resist 13 as a mask, so that the side surface 16a of the insulating film penetrates beneath the exposed region 13a of the lower resist.
6, the area of the opening portion is enlarged.

Next, as shown in FIG.
The entire upper surface is exposed with deep UV light and developed. Thus, the upper resist 14 serves as a mask, and the lower resist 13 is removed.

Next, as shown in FIG.
Using the mask 6 as a mask, the second recess groove 20b is formed by etching the semiconductor substrate 10 for a desired time. The second recess groove 20b is formed in the first recess groove 20b.
Since the portion where a has been formed is etched deeper, it has a two-step shape.

Next, as shown in FIG.
A gate electrode 17 is formed by depositing a Ti / Al laminated film on the entire upper surface and performing lift-off. At this time, the gate electrode 17 covers the bottom and side surfaces of the deeply etched portion of the second recess groove 20b, and the insulating film 16
It has a T-shaped shape extending upward.

In the second embodiment, since the step of removing the resist is only the lift-off step at the time of forming the gate electrode 17, the conventional problem of surface oxidation of the substrate at the time of removing the resist can be solved. Thus, the substrate 10 can be etched with good reproducibility. Therefore, a high-performance and highly reliable semiconductor device can be obtained. Further, it is possible to obtain a semiconductor device capable of suppressing the influence of the surface trap level by using a simpler process than in the related art.
Further, it is possible to obtain a semiconductor device having a T-shaped gate electrode 17 that can suppress an increase in gate resistance when the gate width per gate is large with a short gate length.

Embodiment 3 FIG. Hereinafter, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is based on HEMT (High Electron Mobile).
and a method of manufacturing a lite transistor. FIG. 3 is a fragmentary cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention in the order of steps.

First, for example, as shown in FIG.
On a semi-insulating substrate body 1 made of GaAs, for example, MB
E (Molecular Beam Epitaxy)
Method or MOCVD (Metal Organic C)
undoped A using an epitaxial growth technique such as a chemical vapor deposition method.
lGaAs buffer layer 3, n-type AlGaAs lower electron supply layer 4, undoped InGaAs channel layer 5, n-type A
lGaAs upper electron supply layer 6, low concentration n-type (hereinafter referred to as "n
^- ". ) GaAs layer 7, n-type AlGaAs
Etching stop layer 8, n ⁺ GaAs contact layer 9
Are formed in this order to form a semiconductor substrate 10 and, for example, AuG is formed at a desired position on the semiconductor substrate 10 by using a normal deposition lift-off technique, a sintering technique, or the like.
Source and drain electrodes 11 and 12 made of a laminated film of e alloy / Ni / Au are formed.

Subsequently, for example, PMGI (Polymethyl Glutari) is formed on the semiconductor substrate 10.
deep UV (Ultra Vio)
Let) a lower resist 13 sensitive to light or electron beam (EB) is applied, and an upper resist 1 sensitive to UV light (for example, i-line) such as AZ5206E is applied thereon.
4 is applied. Thereafter, the upper resist 14 is processed into a desired shape by performing an exposure using an i-line stepper and an image reversal process, thereby exposing the lower resist 13. Here, 13a represents an exposed region of the lower resist. The reason why the image reversal process is used here is to facilitate lift-off in a later gate electrode manufacturing process. Subsequently, a portion of the exposed region 13a is exposed and developed by an excimer stepper or EB to expose the semiconductor substrate 10. Here, 10a represents an exposed region of the semiconductor substrate.

Next, as shown in FIG. 3B, using the lower resist 13 as a mask, a citric acid-based solution is used.
The contact layer 9 is etched. Here, the etching of AlGaAs is very slow in a citric acid-based solution, and the etching is almost stopped when the etching stop layer 8 is exposed.

Next, as shown in FIG. 3C, the etching stop layer 8 is etched using a phosphoric acid-based solution to expose the n ^- GaAs layer 7, and the first recess groove 20a is formed.
To form

Next, as shown in FIG.
The entire upper surface is exposed with deep UV light and developed. As a result, the upper resist 14 serves as a mask, the lower resist 13 is removed, and the exposed region 10a of the substrate is enlarged.

Next, as shown in FIG. 3E, using the lower resist 13 as a mask, the semiconductor substrate 10 in which the exposed region 10a is enlarged is etched by using a citric acid-based solution for a desired time. The second recess 20b is formed by selectively removing GaAs. As a result, the second recess groove 20b has a two-step shape.

Next, as shown in FIG.
A gate electrode 15 is formed by depositing a Ti / Al laminated film on the entire upper surface and performing lift-off. At this time, the gate electrode 15 has a bottom surface (ie, the surface of the upper electron supply layer 6) and a side surface (ie, the etching stop layer 8 and the n ⁻ GaAs) of the deeply etched portion of the second recess groove 20b.
(a side surface of the s layer 7).

In the third embodiment, since the step of removing the resist is only the lift-off step at the time of forming the gate electrode 15, the problem of the conventional surface oxidation of the substrate at the time of removing the resist can be solved. Thus, the substrate 10 can be etched with good reproducibility. Therefore, a high-performance and highly reliable semiconductor device can be obtained. Further, it is possible to obtain a semiconductor device capable of suppressing the influence of the surface trap level by using a simpler process than in the related art.
Furthermore, by inserting the etching stop layer 8 as one of a plurality of layers forming the semiconductor substrate 10 and performing selective etching, the first and second recess grooves 2 are controlled with good control.
0a and 20b can be formed. Therefore, the gate electrode 15 can be formed with high accuracy, and a highly reliable semiconductor device can be obtained.

Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device described in Embodiment 4 includes an E-FET and a D-FET on the same substrate,
The E-FET, which is greatly affected by the surface trap level, has a structure having higher performance and higher reliability than the conventional one by forming its gate electrode so as to completely cover the bottom and side surfaces of the recess groove. It is. Here, the reason why the E-FET is easily affected by the surface trap level is as follows.
When the carrier concentration of T and the D-FET are the same, E-
The FET requires a shorter distance from the gate electrode to the channel layer than the D-FET, and thus is more susceptible to the trap level on the substrate surface.

4, reference numeral 10 denotes a GaAs semi-insulating substrate body 1, an undoped GaAs buffer layer 22, an undoped InGaAs channel layer 23, an n-type InGaP first electron supply layer 24, and an n-type AlGaAs second electron supply layer 2.
5 and a semiconductor substrate comprising an n-type GaAs contact layer 26.

Reference numerals 27a and 28a denote element forming regions formed on one main surface of the semiconductor substrate 10, and E-F
An ET 27 or a D-FET 28 is formed. The element formation regions 27a and 28a are electrically isolated by an element isolation region 21 formed by implanting hydrogen into the substrate 10.

Reference numeral 20b denotes a two-step recessed groove formed in the element formation region 27a, and the gate electrode 18 of the E-FET is formed so as to cover the deeper bottom and side surfaces. 11a and 12a are E-FETs formed in the element forming region 27a with the recess groove 20b interposed therebetween.
Source and drain regions.

Reference numeral 20c denotes a one-step recess formed in the element forming region 28a.
A gate electrode 19 of the FET is formed. Also, 11
b and 12b are source and drain regions of the D-FET formed in the element formation region 28a with the recess groove 20c interposed therebetween.

Here, the gate electrodes 18 and 19 are
And the source and drain regions 11a, 11b, 12a, and 12b are
An ohmic junction is made to 0.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIG. FIG. 5 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor device in the order of steps.

First, as shown in FIG. 5A, for example,
On a semi-insulating substrate body 1 made of GaAs, for example, MB
E (Molecular Beam Epitaxy)
Method or MOCVD (Metal Organic C)
undoped G by using an epitaxial growth technique such as a chemical vapor deposition method.
aAs buffer layer 22, undoped InGaAs channel layer 23, n-type InGaP first electron supply layer 24, n-type A
The semiconductor substrate 10 is formed by growing the lGaAs layer second electron supply layer 25 and the n-type GaAs contact layer 26 in this order, and ion-implanting, for example, hydrogen between the element forming regions 27a and 28a, thereby providing a high resistance. Element isolation region 2
Form one.

Next, as shown in FIG. 5B, for example, a PMGI (Polydimet) is formed on the semiconductor substrate 10.
deep U, such as hyl Glutarimide)
V (Ultra Violet) light or electron beam (E
B) is coated with a lower resist 13 which is sensitive to light, and
UV light such as AZ5206E (for example, i-line)
Is coated with an upper resist 14 which is exposed to light. Thereafter, the upper resist 14 is processed into a desired shape by performing an exposure using an i-line stepper and an image reversal process, thereby exposing the lower resist 13. here,
Reference numeral 13a denotes an exposed region of the lower resist. Also, where
The reason for using the image reversal process is to facilitate lift-off in the subsequent gate electrode manufacturing process.

Next, as shown in FIG. 5C, the E-FE
An excimer stepper or an EB is formed in a part of the exposed region 13a of the lower resist on the element forming region 27a on the side where T is formed.
Exposure and development are performed to expose the semiconductor substrate 10. Here, 10a represents an exposed region of the semiconductor substrate.

Next, as shown in FIG. 5D, using the lower resist 13 as a mask, a citric acid-based solution is used.
The contact layer 26 is etched. Here, since etching of AlGaAs is very slow in a citric acid-based solution, the etching is almost stopped when the second electron supply layer 25 is exposed. Subsequently, the second electron supply layer 25 is etched using a tartaric acid-based solution to expose the first electron supply layer 24 and form a first recess groove 20a.
Here, since etching of InGaP is extremely slow in a tartaric acid-based solution, the etching is almost stopped when the first electron supply layer 24 is exposed.

Next, as shown in FIG.
The entire upper surface is exposed with deep UV light and developed. As a result, the upper layer resist 14 serves as a mask, the lower layer resist 13 is removed, the exposed region 10a of the substrate is enlarged in the element formation region 27a, and the element formation region 28a is removed.
Also, the substrate 10 is exposed.

Next, as shown in FIG. 5F, using the lower resist 13 as a mask, the semiconductor substrate 10 is etched for a desired period of time using a citric acid-based solution in both element forming regions 27a and 28a. In this manner, by selectively removing GaAs, a two-step stepped second recess groove 20b is formed in the element forming region 27a, while a single step recess groove 20b is formed in the element forming region 28a.
Form c. Here, in the citric acid solution, AlGa
Since the etching of As and InGaP is very slow, G
The aAs contact layer 26 is selectively etched.

Thereafter, a Ti / Al laminated film is deposited on the entire surface of the substrate 10 and lifted off, so that the gate electrode 18 of the E-FET is formed in the device forming region 27a and the gate electrode of the D-FET is formed in the device forming region 28a. 19 are formed simultaneously. At this time, the gate electrode 18 has a bottom surface (ie, the surface of the first electron supply layer 24) and a side surface (ie, the second electron supply layer 2) of the deeply etched portion of the second recess groove 20b.
5, while the gate electrode 19 is formed on the bottom surface of the one-step recess groove 20 c (that is, the second electron supply layer 2).
5 surface).

Finally, AuGe is deposited at a position on the substrate 10 opposite to the gate electrode 18 or 19 using, for example, an ordinary deposition lift-off technique and a sintering technique.
Source / drain electrodes 11a, 12a or 11b, 12b made of a laminated film of alloy / Ni / Au are formed.
Incidentally, the source and drain electrodes 11a, 1
The formation of 2a or 11b, 12b may be performed after the formation of the substrate 10 and before the formation of the gate electrode 18 or 19.

In the fourth embodiment, since the step of removing the resist is only the lift-off step at the time of forming the gate electrodes 18 and 19, the problem of the conventional surface oxidation of the substrate at the time of removing the resist can be solved. The substrate 10 can be uniformly etched with good reproducibility. Therefore, a high-performance and highly reliable semiconductor device can be obtained. Further, it is possible to obtain a semiconductor device including the E-FET 27 capable of suppressing the influence of the surface trap level and the D-FET 28 formed on the same substrate as the E-FET 27 by using a simpler process than in the related art. . Further, since the semiconductor substrate 10 is formed by the plurality of semiconductor layers 24, 25, and 26 having different etching resistances under the etching conditions in the process of forming the recess grooves 20a, 20b, and 20c, the semiconductor substrate 10 can be selectively etched. The recess grooves 20a, 20b, 20c can be formed with good controllability. Therefore, the gate electrodes 18 and 19 can be formed with high accuracy, and a highly reliable semiconductor device can be obtained.

Embodiment 5 Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention. The semiconductor device according to the fifth embodiment relates to an FET having a dual gate electrode.

In FIG. 6, reference numeral 10 denotes a GaAs semi-insulating substrate body 1, an undoped GaAs buffer layer 22, an undoped InGaAs channel layer 23, an n-type InGaP first electron supply layer 24, and an n-type AlGaAs second electron supply layer 2.
5 and a semiconductor substrate comprising an n-type GaAs contact layer 26.

Reference numeral 20b denotes a two-step recessed groove formed in the main surface of the substrate 10, and a first gate electrode 29 is formed so as to cover the deeper bottom and side surfaces.
Reference numeral 20c denotes a one-step recess formed on the main surface of the substrate 10, and a second gate electrode 30 is formed so as to cover the bottom surface.
Are formed. Here, the first and second gate electrodes 29 and 30 are formed in parallel. Here, the gate electrodes 29 and 30 have a Schottky junction with the substrate 10, while the source and drain regions 11 and 12 have an ohmic junction with the substrate 10.

Reference numerals 11 and 12 denote source and drain regions formed on the main surface of the substrate 10 with the first and second gate electrodes 29 and 30 interposed therebetween.

The method of manufacturing a semiconductor device according to the fifth embodiment is different from the method of manufacturing a semiconductor device described in the fourth embodiment only in that the step of forming element isolation region 21 is omitted. .

In the fifth embodiment, the only step of removing the resist is the lift-off step when forming the first and second gate electrodes 29 and 30. Problem can be solved,
The substrate 10 can be etched with good reproducibility. Therefore, a high-performance and highly reliable semiconductor device can be obtained. Further, it is possible to obtain a semiconductor device having a dual gate FET that can suppress the influence of the surface trap level by using a simpler process than in the related art.

Further, in the fifth embodiment, the semiconductor substrate 10 is formed by the plurality of semiconductor layers 24, 25 and 26 having different etching resistances under the etching conditions in the process of forming the recess grooves 20b and 20c.
Etching can be selectively performed, and the recess grooves 20b and 20c can be formed with good controllability. Therefore, the first and second gate electrodes 29 and 30 can be formed with high accuracy, and a highly reliable semiconductor device can be obtained.
In addition, the dual gate FET according to the fifth embodiment is operated as an amplifier by biasing the first gate electrode 29 to a desired voltage, and is changed by changing the bias voltage applied to the second gate electrode 30. It can be applied as a gain amplifier or the like.

[0076]

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming two upper and lower resist layers having different photosensitivity on a semiconductor substrate, exposing and developing the upper resist layer of the two resist layers. A step of exposing the underlying resist, and exposing a portion of the exposed area of the underlying resist,
Developing, exposing the semiconductor substrate, and etching the exposed semiconductor substrate using the lower resist as a mask to form a recess in the semiconductor substrate.
A step of exposing an exposed region of the lower resist using the upper resist as a mask and developing the exposed region of the semiconductor substrate, and a step of expanding the exposed region of the semiconductor substrate using the lower resist as a mask. A second recess forming step of forming a two-step recess in the semiconductor substrate by etching the semiconductor substrate on which the two-step recess is formed, and a metal covering the deep bottom and side surfaces of the two-step recess. Since it includes a step of forming an electrode, it is possible to solve the problem of the surface oxidation of the substrate at the time of the conventional resist removal, to enable uniform substrate etching, and to use a simpler process than the conventional method to reduce the surface trap level. It is possible to obtain a semiconductor device whose influence can be suppressed.

A step of forming two upper and lower resist layers having different photosensitivity on a semiconductor substrate; and a step of exposing and developing a plurality of regions of the upper resist layer to form a plurality of lower resist layers. And exposing a portion of the other exposed regions, excluding at least one of the exposed regions of the plurality of exposed regions of the underlying resist, developing and exposing the semiconductor substrate A first concave portion forming step of etching the exposed semiconductor substrate using the lower resist as a mask to form a concave portion in the semiconductor substrate; and exposing the exposed region of the lower resist using the upper resist as a mask. And developing, and etching the semiconductor substrate using the lower resist layer as a mask to form a two-step recess in the region of the semiconductor substrate where the recess is formed. A second recess forming step of forming a one-stage recess in at least one other region, an electrode made of a metal covering a deeper bottom surface and side surfaces of the two-stage recess, and Forming a metal electrode covering the bottom surface, and further forming a first gate electrode which is an electrode made of metal covering the deeper bottom surface and side surfaces of the two-stage recess, and a bottom surface of the one-stage recess. A semiconductor device having a dual gate FET having a second gate electrode which is an electrode made of a covering metal can be formed. Therefore, by operating the first gate electrode as an amplifier and changing the bias voltage of the second gate electrode, It is also possible to obtain a semiconductor device whose gain can be controlled.

Further, the method includes a step of forming an element isolation region between a region where a two-step step-shaped recess is formed and a region where a single-step recess is formed in the semiconductor substrate. Device that includes a transistor of the type and an enhancement-type field-effect transistor on the same semiconductor substrate.

A step of forming two upper and lower resist layers having different photosensitivities from the insulating film on the semiconductor substrate in this order; exposing and developing the upper resist layer of the two resist layers to form a lower resist layer; Exposing a part of the exposed region of the lower resist, exposing and developing the insulating film, and etching the insulating film using the lower resist as a mask, the semiconductor Exposing the substrate, etching the exposed semiconductor substrate to form a concave portion in the semiconductor substrate, and etching the insulating film using the lower resist as a mask to form the insulating film. Retreating the end face of the film under the lower resist, exposing the exposed area of the lower resist using the upper resist as a mask, and developing. Etching the semiconductor substrate in which the recess is formed using the insulating film as a mask to form a two-step recess in the semiconductor substrate; and forming a deep recess in the two-step recess. Forming a metal electrode covering the bottom and side surfaces, so that the conventional problem of substrate surface oxidation during resist removal can be solved, enabling uniform substrate etching and a simpler process than before. By using the semiconductor device, a semiconductor device capable of suppressing the influence of the surface trap level can be obtained.

In the step of etching the insulating film using the lower resist as a mask and retreating the end face of the insulating film below the lower resist, the end face of the insulating film is exposed to the exposed area of the lower resist. The semiconductor device is provided with a T-shaped gate electrode that can suppress an increase in gate resistance when the gate width per gate is large with a short gate length. It becomes possible.

Further, since the semiconductor substrate comprises a plurality of semiconductor layers having different etching resistances under the etching conditions in the first or second recess forming step, the first or second recess forming step is performed. In this case, the recess can be formed with good controllability.

The semiconductor device according to the present invention has a first element formation region including one stepped recess on one main surface, a second element formation region including a two stepped recessed portion, and the first and second element formation regions. A semiconductor substrate having an element isolation region for isolating the first element formation region, a first Schottky electrode formed in the first element formation region and covering a bottom surface of the one-stage concave portion, and the first Schottky electrode A first field-effect transistor having a pair of ohmic electrodes formed with the electrodes interposed therebetween;
A second Schottky electrode formed in the second element formation region and covering a deeper bottom surface and side surfaces of the two-step concave portion, and a pair of ohmics formed with the second Schottky electrode interposed therebetween; An enhancement-type field-effect transistor having a second field-effect transistor having an electrode and capable of suppressing the influence of a surface trap level, and a depletion-type field-effect transistor formed on the same substrate as the enhancement-type field-effect transistor Can be realized, and high performance and high reliability can be obtained as compared with the conventional semiconductor device.

The first field-effect transistor is a depletion-type field-effect transistor, and the second field-effect transistor is a second field-effect transistor.
The field-effect transistor is characterized by being an enhancement-type field-effect transistor, so that it can have higher performance and higher reliability than the conventional one.

Further, a semiconductor substrate having one stepped concave portion and two stepped concave portions on one main surface, and a pair of semiconductor layers formed on the main surface of the semiconductor substrate with the one stepped concave portion and two stepped concave portions interposed therebetween. Ohmic electrode, and a pair of parallel Schottky electrodes formed between the pair of ohmic electrodes on the semiconductor substrate, one of the pair of Schottky electrodes covers the bottom surface of the one-stage recess, the other Is characterized in that it covers the deeper bottom surface and side surfaces of the two-step concave portion, so that the first gate electrode, which is a Schottky electrode that covers the deeper bottom surface and side surfaces of the two-step concave portion, A dual gate FET having a second gate electrode which is a Schottky electrode covering the bottom surface of the concave portion can be formed. Therefore, the first gate electrode operates as an amplifier and the bias voltage of the second gate electrode is changed. By, it is possible to control the gain to obtain a semiconductor device capable.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention in the order of steps;

FIG. 2 is an essential part cross sectional view showing a method of manufacturing a semiconductor device in a second embodiment of the present invention in the order of steps;

FIG. 3 is an essential part cross sectional view showing a method of manufacturing a semiconductor device in a third embodiment of the present invention in the order of steps;

FIG. 4 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device in the fourth embodiment in order of steps.

FIG. 6 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view showing a method for manufacturing the conventional field-effect transistor in the order of steps.

[Explanation of symbols]

6, 7, 8, 9 Plural semiconductor layers having different etching resistances, 10 semiconductor substrate, 10a exposed region of semiconductor substrate, 11, 12 pair of ohmic electrodes, 11
a, 12a A pair of ohmic electrodes, 11b, 12b
A pair of ohmic electrodes, 13 underlying resist, 1
3a exposed area of lower resist, 14 upper resist, 15 metal electrode, 16 insulating film,
16a end face of insulating film, 17 electrode made of metal,
18 electrode made of metal (second Schottky electrode),
19 metal electrode (first Schottky electrode),
Reference Signs List 20a recess in semiconductor substrate, 20b recess in two steps, 20c recess in one step, 21 element isolation region, 24, 25, 26 plural semiconductor layers with different etching resistances, 27 second field effect transistor, 28
First field effect transistor, 27a second element formation region, 28a first element formation region, 29, 30
An electrode made of metal (a pair of parallel Schottky electrodes),

Claims (9)

[Claims] A step of forming upper and lower two-layer resists having different photosensitivity on a semiconductor substrate; a step of exposing and developing a resist in an upper layer of the two-layer resist to expose a lower layer resist; Exposing and developing a part of the exposed region of the lower resist, exposing the semiconductor substrate, and etching the exposed semiconductor substrate using the lower resist as a mask to form a recess in the semiconductor substrate. Forming a first concave portion, exposing and developing the exposed region of the lower resist using the upper resist as a mask, and enlarging the exposed region of the semiconductor substrate; A second recess forming step of etching the semiconductor substrate on which the recess is formed as a mask to form a two-step recess in the semiconductor substrate; Forming a metal electrode covering the deeper bottom and side surfaces of the semiconductor device. 2. A step of forming upper and lower two-layer resists having different photosensitivity on a semiconductor substrate; and exposing and developing a plurality of regions of the upper-layer resist of the two-layer resist to form a plurality of lower-layer resists. Exposing a region of the plurality of exposed regions of the lower layer resist, excluding at least one exposed region, exposing a part of the other exposed region, developing, and exposing the semiconductor substrate; A first recess forming step of etching the exposed semiconductor substrate using the lower resist as a mask to form a recess in the semiconductor substrate; and exposing the exposed region of the lower resist using the upper resist as a mask. And developing, and etching the semiconductor substrate using the resist of the lower layer as a mask to form a two-step recess in a region of the semiconductor substrate where the recess is formed. A second recess forming step of forming and forming a one-step recess in at least one other region; an electrode made of a metal covering a deeper bottom surface and side surfaces of the two-step recess; Forming a metal electrode covering the bottom surface. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming an element isolation region between a region where a two-step recess is formed and a region where a single recess is formed in the semiconductor substrate. . 4. A step of forming upper and lower two-layer resists having different photosensitivity from an insulating film on a semiconductor substrate in this order, exposing and developing the upper resist of the two-layer resist, and forming a lower resist. Exposing a portion of the exposed region of the lower resist, exposing and developing the insulating film, etching the insulating film using the lower resist as a mask, and etching the semiconductor Exposing the substrate; etching the exposed semiconductor substrate to form a concave portion in the semiconductor substrate; forming a concave portion in the semiconductor substrate; etching the insulating film using the lower resist as a mask; Retreating the end face of the film below the lower resist, exposing the exposed area of the lower resist using the upper resist as a mask, and developing; Etching the semiconductor substrate in which the recess is formed using the insulating film as a mask to form a two-step recess in the semiconductor substrate; and forming a deep recess in the two-step recess. Forming a metal electrode covering the bottom surface and the side surfaces. 5. The step of etching an insulating film using a lower resist as a mask and retreating an end face of the insulating film below the lower resist, wherein the end face of the insulating film is formed in an exposed region of the lower resist. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is retracted downward. 6. The semiconductor substrate according to claim 1, wherein the semiconductor substrate comprises a plurality of semiconductor layers having different etching resistances under etching conditions in the first or second concave portion forming step. A method for manufacturing a semiconductor device. 7. A first element forming region including one stepped concave portion on one main surface, a second element forming region including a two stepped concave portion, and the first and second element forming regions are separated from each other. A semiconductor substrate having an element isolation region to be formed, a first Schottky electrode formed in the first element formation region and covering a bottom surface of the one-stage concave portion, and a first Schottky electrode formed with the first Schottky electrode interposed therebetween. A first field-effect transistor having a pair of ohmic electrodes, a second Schottky electrode formed in the second element formation region and covering a deeper bottom surface and side surfaces of the two-step concave portion, and A semiconductor device comprising: a second field-effect transistor having a pair of ohmic electrodes formed with the second Schottky electrode interposed therebetween. 8. The field effect transistor according to claim 7, wherein the first field effect transistor is a depletion type field effect transistor, and the second field effect transistor is an enhancement type field effect transistor. Semiconductor device. 9. A semiconductor substrate having a one-step concave portion and a two-step step-shaped concave portion on one main surface, and a pair formed on the main surface of the semiconductor substrate with the one-step concave portion and the two-step concave portion interposed therebetween. And a pair of parallel Schottky electrodes formed between the pair of ohmic electrodes on the semiconductor substrate, and one of the pair of Schottky electrodes covers the bottom surface of the one-stage recess, and the other. One of the semiconductor devices covers a deeper bottom surface and side surfaces of the two-step concave portion.