JP2003037116A - Semiconductor device and method for manufacturing the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be driven by single positive power supply voltage and whose gate length can be effectively reduced, and to provide a method for manufacturing the device. SOLUTION: This semiconductor device comprises a channel layer 14 for forming current channels, semiconductor layers 15, 16, 17, 18 and 19 formed on the channel layer 14, gate electrodes 21 formed on at least one of the semiconductor layers, and conductive impurity regions 20 formed in the semiconductor layers 15, 16, 17, 18 and 19 under the gate electrodes 21 to control the threshold of the current flowing through the channel layer 14. The semiconductor layer 15 in the region under the gate electrodes 21 is formed thinner compared with the thickness in the other region to suppress the conductive impurity regions 20 from spreading in the direction that the current channel is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor device in which charges are confined inside a laminated structure of a plurality of semiconductor layers so that the charges can travel at high speed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a rapid increase in demand for communication systems using microwave high frequency bands such as mobile phones. Further, development of a communication system using a millimeter wave / quasi-millimeter wave band, which is a higher frequency band, is also being rapidly developed. Along with this, also in devices constituting a high frequency communication system, a transistor, a microstrip line, a high dielectric constant capacitor and the like having a gate length reduced to about 0.1 μm are being developed.

Taking a power amplifier and a switch IC which are one of the pillar devices of the current mobile communication system (microwave high frequency band) as an example, a single positive power supply drive, a low voltage drive, and a high efficiency are described. Driven things are needed. It is considered that the same function is basically required also in power amplifiers and switch ICs in the millimeter wave / quasi-millimeter wave band.

At present, as a device for power amplifiers used in the microwave high frequency band, a high electron mobility transistor (HEMT: High) is aimed at high efficiency driving.
Electron Mobility Transistor) and a modified example of it, a pseudo-lattice junction high electron mobility transistor (PHEMT: Pseudomorphic HE) that allows a certain degree of lattice mismatch and realizes higher electron mobility with an epitaxial structure.
MT) etc. In each of these, current modulation is performed using a heterojunction structure.

FIG. 11 shows a sectional view of one structural example of the PHEMT. The PHEMT shown in FIG. 11 includes a substrate 31 made of semi-insulating single crystal GaAs, a buffer layer 32 made of GaAs to which impurities are not added, and
A first barrier layer 33 made of AlGaAs and InGaA
A channel layer 34 made of s and a second barrier layer 35 made of AlGaAs are sequentially stacked. Each barrier layer 33,
35 is a carrier supply layer 33a, 35 containing n-type impurities
a and high resistance layers 33b, 33c and 35b, 35c, respectively.

An insulating film 37 is formed on the second barrier layer 35 via an n-type GaAs layer 36 containing n-type impurities. An opening is formed in the insulating film 37, and a source electrode 39a and a drain electrode 39b are formed on the n-type GaAs layer 36 in the opening. A gate electrode 38 is formed in the other opening of the insulating film 37, and when a voltage is applied to the gate electrode 38, the current flowing between the source electrode 39a and the drain electrode 39b is modulated. .

In the PHEMT described above, generally, as shown in FIG. 11, a source electrode 39a and a drain electrode 39 are provided.
Immediately below b, an n-type GaAs layer 3 in which a high concentration of n-type impurities for realizing a low ohmic contact resistance is introduced.
6 exists, and the n-type GaAs is present just below the gate electrode 38.
The recess structure is formed by etching the layer 36. As a result, the region of the channel layer 34 immediately below the gate electrode 38 is depleted of carriers, or a region with less carriers is formed as compared with other channel regions.

In the PHEMT having such a structure,
By applying a positive voltage to the gate electrode 38, the channel layer 3
Carriers are accumulated in 4 and, in principle, Schottky junction field effect transistor (MES-FET: Metal Semi
Compared to a conductor FET), the carriers accumulated in the channel are not subjected to impurity scattering from the carrier supply layers 35a and 33a, so that the electron mobility can be kept high and the efficiency of the power amplifier is improved. It is a great advantage over.

On the other hand, for driving a single positive power supply, by doping an impurity of the second conductivity type immediately below the gate electrode, a semiconductor of the first conductivity type in the channel layer and a semiconductor of the second conductivity type immediately below the gate are formed. Junction type field effect transistor (JFET: Juncti) that makes it possible to increase Φbi (built-in potential) and use only a positive operating power supply.
onFET) exists. At this time, in addition to the method of doping the second conductivity type impurity (gate impurity) in order to increase Φbi, a method of selecting a semiconductor having a bandgap larger than that of the channel layer in the semiconductor layer immediately below the gate. And the PHEM shown in FIG. 11 above.
T uses the method.

FIG. 12 shows an example of the structure of a junction-pseudo-lattice junction high electron mobility transistor (JPHEMT) that combines the advantages of the above JFET and PHEMT.

The JPHEMT shown in FIG. 12 comprises a substrate 41 made of semi-insulating single crystal GaAs, a buffer layer 42 made of GaAs to which impurities are not added, and
The first barrier layer 43 made of AlGaAs and InGaA
A channel layer 44 made of s and a second barrier layer 45 made of AlGaAs are sequentially stacked. Each barrier layer 43,
45 has carrier supply layers 43a and 45a containing first conductivity type (n-type) impurities, and high resistance layers 43b and 43c and 45b and 45c, respectively.

An insulating film 47 having an opening is formed on the second barrier layer 45, and a source electrode 49a and a drain electrode 49b are formed in the opening. A gate electrode 48 is formed in another opening of the insulating film 47, and a second conductivity type (p-type) impurity (Zn) is introduced into the second barrier layer 45 immediately below the gate. Gate impurity region 50 is formed. JPHEMT with the above configuration
Also, when a voltage is applied to the gate electrode 48, the current flowing between the source electrode 49a and the drain electrode 49b is also modulated.

In the JPHEMT having the above structure, the smaller the distance d between the gate impurity region 50 and the channel layer 44, the smaller the diameter Φbi (built-in potential) between the semiconductor forming the channel layer 44 and the gate impurity region 50 immediately below the gate. Can be increased and only a positive operating power supply can be used.

[0014]

However, in JPHEMT using the above-mentioned gate impurity region 50, single positive power supply drive and high efficiency drive in the existing microwave band are possible, but at a higher frequency in millimeters. As shown in FIG. 12, when a transistor having a gate length reduced to about 0.1 μm for communication in the millimeter wave / quasi-millimeter wave band is produced, the presence of the lateral spread x of the gate impurity region 50 is relatively large. Therefore, there is a problem that the shortening of the gate length does not appear as effectively as in the conventional HEMT, which is disadvantageous in terms of parasitic capacitance and parasitic resistance.

Here, in the current JPHEMT, the gate impurity region 50 is manufactured by vapor phase diffusion of p-type impurities (for example, Zn). In this case, the lateral expansion x of the gate impurity region 50 is deep. It is thought that there is as much as the spread in the vertical direction. The gate electrode impurity region 50
There is also a method of manufacturing the device by ion implantation of p-type impurities and subsequent heat treatment. However, in the case of a device using an epitaxial structure such as this device, the heat treatment temperature is close to the epitaxial substrate manufacturing temperature, and reliability is improved. Problems may occur and it is difficult to realize.

In the case of the conventional HEMT, since the gate impurity region 50 is not used, the above problem does not occur, and the gate length can be effectively shortened by using the electron exposure method. There is a problem that it is difficult to drive a single positive power supply not only in the band but also in the microwave band gate length (about 0.5 μm).

That is, as a transistor for the millimeter wave / quasi-millimeter wave band, it is desired to develop a transistor that can operate with a single positive power supply and can effectively reduce the gate length by an electron exposure method or the like.

The present invention has been made in view of the above circumstances, and an object thereof is to enable a single positive power supply operation,
It is an object of the present invention to provide a semiconductor device that can effectively reduce the gate length and a manufacturing method thereof.

[0019]

In order to achieve the above object, a semiconductor device of the present invention comprises a channel layer forming a current channel, a semiconductor layer formed on the channel layer, and at least part of the semiconductor layer. A semiconductor device having a gate electrode formed on a semiconductor layer, wherein a conductive impurity region for controlling a threshold value of a current flowing through the channel layer is formed in the semiconductor layer below the gate electrode. The semiconductor layer under the gate electrode is formed thinner than the other regions, and the spread of the conductive impurity region in the formation direction of the current channel is suppressed.

The semiconductor device further includes a source electrode and a drain electrode formed on the semiconductor layer so as to be separated from each other with the gate electrode interposed therebetween, and the semiconductor layer below the gate electrode, the source electrode and the drain electrode is It is formed thinner than the region.

For example, the semiconductor layer is formed of a semiconductor having a band gap larger than that of the material forming the channel layer.

For example, the semiconductor layer includes a carrier supply layer containing an impurity of the first conductivity type for supplying electric charges to the channel layer, and the semiconductor layer between the carrier supply layer and the gate electrode has a second layer. The conductive impurity region of the conductive type is formed.

For example, it further has a second semiconductor layer formed below the channel layer and made of a semiconductor having a bandgap larger than that of the material forming the channel layer. In this case, the second semiconductor layer includes a carrier supply layer containing an impurity of the first conductivity type that supplies charges to the channel layer.

According to the above semiconductor device of the present invention, since the semiconductor layer under the gate electrode is formed thinner than the other regions, the distance between the conductive impurity region and the channel layer is desired. The spread of the conductive impurity region in the depth direction for reducing the value can be reduced, and as a result, the spread of the conductive impurity region in the formation direction of the current channel can be suppressed. Therefore, the conductive impurity region is formed in the semiconductor layer below the gate electrode, the threshold value of the current flowing through the channel layer is controlled, and the spread of the conductive impurity region in the formation direction of the current channel is suppressed.

Further, in order to achieve the above object, the method for manufacturing a semiconductor device of the present invention comprises a step of forming a channel layer, and a step of forming a semiconductor layer on the channel layer.
Forming a groove in a part of the semiconductor layer; forming a conductive impurity region for controlling a threshold value of a current flowing in the channel layer in at least the groove of the semiconductor layer; And forming a gate electrode.

Preferably, in the step of forming the conductive impurity region, after the step of forming the conductive impurity region on the entire surface of the semiconductor layer and forming the gate electrode,
The method further includes removing the semiconductor layer having the conductive impurity region formed under the gate electrode, and removing the semiconductor layer having the conductive impurity region formed in another region.

For example, in the step of removing the semiconductor layer in which the conductive impurity region in the other region is formed, the semiconductor in which the conductive impurity region in the other region is formed using the gate electrode as a mask. The layer is removed by etching.

For example, in the step of forming the conductive impurity region, the conductive impurity is formed by vapor diffusion. Alternatively, in the step of forming the conductive impurity region, the conductive impurity is formed by ion implantation.

After the step of removing the semiconductor layer in which the conductive impurity region is formed in the other region, a source electrode and a drain electrode are formed on the semiconductor layer with the gate electrode sandwiched therebetween. It further has a process.

Preferably, after the step of removing the semiconductor layer in which the conductive impurity region is formed in the other area and before the step of forming the source electrode and the drain electrode, the source electrode and the drain are concerned. The method further includes a step of forming a groove in the semiconductor layer in a region where an electrode is formed, and in the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed in the groove.

For example, in the step of forming the semiconductor layer, the semiconductor layer is formed of a semiconductor having a band gap larger than that of the material forming the channel layer.

For example, in the step of forming the semiconductor layer, the semiconductor layer including a carrier supply layer containing an impurity of the first conductivity type for supplying charges to the channel layer is formed.

According to the above-described method for manufacturing a semiconductor device of the present invention, a groove is formed in a part of the semiconductor layer on the channel layer, and the threshold value of the current flowing through the channel layer is controlled in at least the groove of the semiconductor layer. By forming the conductive impurity region to be formed and forming the gate electrode at least in the groove, the semiconductor layer below the gate electrode can be made thinner than other regions. Therefore, it is possible to reduce the spread of the conductive impurity region in the depth direction in order to set the distance between the conductive impurity region and the channel layer to a desired value, and to reduce the conductive impurity region in the direction of forming the current channel. The spread will be suppressed.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a structural example of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG.
For example, on a substrate 11 made of semi-insulating single crystal GaAs, undoped-Ga to which impurities are not added is added.
A first barrier layer 13 made of a III-V group compound semiconductor and a channel layer 1 via a buffer layer 12 made of As.
4, second barrier layer 15, first stopper layer 16, third barrier layer 17, second stopper layer 18, fourth barrier layer 19
Are formed.

The fourth barrier layer 19 and the second stopper layer 1
8. The gate opening M having a depth exposing the first stopper layer 16 is formed in the third barrier layer 17, and the fourth barrier layer 19 and the second barrier layer 19 exposed in the gate opening M are formed. In the stopper layer 18, the third barrier layer 17, the first stopper layer 16, and the second barrier layer 15, a gate impurity region 20 doped with an impurity of the second conductivity type is formed. Since the entire surface of the fourth barrier layer 19 is doped with the impurity of the second conductivity type to form the gate impurity region 20, the fourth barrier layer 19 and the gate impurity region 20 are different from each other in the figure. It is shown as one.

A gate electrode 21 is formed on the gate impurity region 20, and the fourth barrier layer 19 and the second stopper layer 18 are removed in regions other than under the gate electrode.

The third barrier layer 17 is provided with two openings which expose the first stopper layer 16 at appropriate intervals, and the source electrode 22a and the drain electrode 2 are provided in the openings.
2b is formed.

Each layer will be described in detail below. First
The second barrier layers 13 and 15 are made of a semiconductor having a wider bandgap than the semiconductor of the channel layer 14. For example, Al _x Ga _{1- x} As mixed crystal is preferable, and the composition ratio of aluminum (Al) is usually x =
It is 0.2 to 0.3.

The barrier layers 13 and 15 are basically high-resistance layers containing no impurities, but carrier supply containing high-concentration n-type impurities is provided approximately 2 to 4 nm away from the channel layer 14. It has layers 13a and 15a.

Here, the carrier supply layers 13a and 15a
Has a thickness of, for example, about 4 nm, and silicon (Si) as an n-type impurity is 1.0 × 10 ^{12 to} 2.0 × 10 ¹² / c.
m ^{2 is} added.

The high resistance layer 13b between the carrier supply layers 13a and 15a and the channel layer 14 to which no impurities are added,
15b has a thickness of about 2 nm, and the channel layer 14
Carriers (electrons in the case of this structure) stored in (1) have a role as a spacer layer so as not to be scattered by impurities in the carrier supply layers 13a and 15a.

The channel layer 14 is a current path between the source electrode 22a and the drain electrode 22b, and is the barrier layer 1
It is composed of a semiconductor having a bandgap narrower than that of the semiconductors forming the parts 3 and 15. For example, In _x G
a _1-x As is preferable, and the composition ratio of In is usually x = 0.1.
Undoped without adding about 0.2 impurities
-InGaAs mixed crystal. As a result, in the channel layer 14, the carrier supply layer 13a of the first barrier layer 13 and the carrier supply layer 15a of the second barrier layer 15 are formed.
Carriers supplied from are accumulated.

The first stopper layer 16 is the third barrier layer 1
It plays the role of stopping the etching when etching 7. For example, if the third barrier layer 17 is AlGaAs
If it is formed of, the first stopper layer 16
Are formed of AlGaAs having a composition ratio different from that of the third barrier layer 17.

The third barrier layer 17 is composed of a semiconductor having a bandgap wider than that of the semiconductor forming the channel layer 14. For example, Al _x Ga _{1 -x} As mixed crystal is preferable, and the composition ratio of aluminum (Al) is usually x =
It is 0.2 to 0.3. The third barrier layer 17 is preferably formed of the same semiconductor as the second barrier layer 15.

The second stopper layer 18 is for etching the gate impurity region 20 (also the fourth barrier layer 19) existing on the second stopper layer 18 when the gate impurity region 20 is formed by patterning. , Has the role of stopping the etching at this time. For example, when the fourth barrier layer 19 is made of AlGaAs, the second stopper layer 18 is made of AlGaAs having a composition ratio different from that of the fourth barrier layer 19.

As described above, the gate impurity region 20 has the fourth barrier layer 19, the second stopper layer 18, the third barrier layer 17, the first stopper layer 16, and the second barrier layer 19 under the gate electrode 21. The barrier layer 15 is formed by doping a p-type impurity such as zinc (Zn) by vapor phase diffusion. The gate impurity region 20 is formed right below the gate electrode 21 to a depth of about 50 nm, for example.

The gate electrode 21 is made of titanium (T
i), platinum (Pt), and gold (Au) are sequentially laminated.

Source electrode 22a and drain electrode 22b
Is formed by sequentially stacking and alloying gold germanium (AuGe), nickel (Ni), and gold (Au) from the substrate side, and the second barrier layer 15 via the first stopper layer 16 Is in ohmic contact with.

According to the semiconductor device of this embodiment, the semiconductor layers 19, 18 and 17 immediately below the gate electrode are
Since the gate opening M is formed, it is possible to reduce the spread in the depth direction of the gate impurity region 20 in order to set the distance d between the gate impurity region 20 and the channel layer 14 to a desired value. As a result, the spread of the gate impurity region 20 in the lateral direction can be reduced. Therefore, even if the gate length is shortened to about 0.1 μm in order to fabricate a transistor for communication in a higher frequency millimeter wave / quasi-millimeter wave band, the influence of the lateral extension of the gate impurity region 20 is reduced. This effectively reduces the gate length. Therefore, the gate length can be effectively shortened while enabling the single positive power supply operation by the gate impurity region 20.

The third barrier layer 17 is used as the source electrode 2
Since the opening is formed in the formation region of the 2a and the drain electrode 22b, the distance between the source electrode 22a and the drain electrode 22b and the channel layer 14 becomes small,
The parasitic source / drain resistance can be reduced.

Furthermore, by keeping the film thickness of the barrier layers 17 and 15 existing on the channel layer 14 between the gate electrode 21 and the source / drain electrodes 22a and 22b large, charges are effectively accumulated in the channel layer 14. can do.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, for example, MO is formed on a substrate 11 made of semi-insulating single crystal GaAs.
Undoped-GaAs with no impurities added by CVD (Metal Organic Chemical Vapor Deposition) method
Is epitaxially grown to about 3 to 5 μm to form the buffer layer 12.

Next, as shown in FIG. 2B, 200 nm of undoped-AlGaAs to which no impurities are added is formed on the buffer layer 12 by, for example, the MOCVD method.
The high resistance layer 13c is formed by epitaxial growth to some extent.

Next, as shown in FIG. 2C, about 4 nm of n-type AlGaAs doped with silicon as an n-type impurity is formed on the high resistance layer 13c by, for example, MOCVD.
The carrier supply layer 13a is formed by epitaxial growth.

Next, as shown in FIG. 3D, about 2n of undoped-AlGaAs, which is not doped with impurities, is formed on the carrier supply layer 13a by, for example, the MOCVD method.
The high resistance layer 13b is formed by epitaxial growth of about m. Thereby, the high resistance layer 13c and the carrier supply layer 1
The first barrier layer 13 composed of 3a and the high resistance layer 13b is formed.

Next, as shown in FIG. 3E, undoped-InGaAs without addition of impurities is deposited on the first barrier layer 13 by MOCVD, for example, to a thickness of about 15 nm.
The epitaxial growth is performed to some extent to form the channel layer 14.

Next, as shown in FIG. 3F, undoped-AlGaAs without addition of impurities is epitaxially grown to a thickness of about 2 nm on the channel layer 14 by MOCVD, for example, to form a high resistance layer 15b.

Next, as shown in FIG. 4G, about 4 nm of n-type AlGaAs doped with silicon as an n-type impurity is formed on the high resistance layer 15b by, for example, MOCVD.
The carrier supply layer 15a is formed by epitaxial growth to some extent.

Next, as shown in FIG. 4 (h), about 80 undoped-AlGaAs containing no impurities is formed on the carrier supply layer 15a by, for example, the MOCVD method.
The high resistance layer 15c is formed by epitaxial growth of about nm. As a result, the second barrier layer 15 including the high resistance layer 15c, the carrier supply layer 15a, and the high resistance layer 15b is formed.

Next, as shown in FIG. 5I, AlGaAs having a composition different from that of the AlGaAs forming the third barrier layer 17 to be formed later is formed on the second barrier layer 15 by, for example, the MOCVD method. , About 5 nm is epitaxially grown to form the first stopper layer 16.

Next, as shown in FIG. 5J, an impurity having the same composition as that of the second barrier layer 15 is not added on the first stopper layer 16 by, for example, MOCVD.
Doped-AlGaAs is epitaxially grown to a thickness of about 80 nm to form the third barrier layer 17.

Next, as shown in FIG. 6K, AlGaAs having a different composition from the AlGaAs forming the fourth barrier layer 19 to be formed later is formed on the third barrier layer 17 by, for example, the MOCVD method. , About 5 nm is epitaxially grown to form the second stopper layer 18.

Next, as shown in FIG. 6 (l), undoped-AlGaAs to which no impurity is added is epitaxially grown to a predetermined film thickness on the second stopper layer 18 by, for example, the MOCVD method to form a gate impurity. A fourth barrier layer 19 for forming the region is formed. afterwards,
The elements are separated by removing the epitaxial layer other than the region where the transistor is formed by mesa etching.

Next, as shown in FIG. 7 (m), a resist (not shown) is applied on the fourth barrier layer 19 and patterned by electron beam exposure to form a resist having an opening in the gate electrode portion. By forming a pattern and etching using the resist pattern as a mask, the first
A gate opening M exposing the stopper layer 16 is formed. As the etching step at this time, after the fourth barrier layer 19 is etched, the second stopper layer 18 is etched, and further the third barrier layer 17 is etched.

Next, as shown in FIG. 7 (n), p-type impurity zinc Zn as a second conductivity type impurity is vapor-phase-diffused over the entire surface of the wafer including the gate opening M to form a gate impurity. A region 20 is formed. Here, it is possible to dope the p-type impurity by ion implantation, but in this case, vapor-phase diffusion is preferable because it is necessary to activate the doped impurity by high temperature heat treatment. Here, when vapor phase diffusion is performed, the diffusion depth is controlled by time control.

Next, as shown in FIG. 8O, Ti / P is formed as a gate metal on the entire surface of the gate impurity region 20.
t / Au is 100 nm / 50 nm / 220 nm, respectively
Each by vapor deposition, by the resist method and electron beam exposure,
The gate metal other than the gate electrode portion is sputter-etched to form the gate electrode 21.

Next, as shown in FIG. 8P, with the gate electrode 21 as a mask, the gate impurity region 20 (which is also the fourth barrier layer 19) in a portion other than the gate electrode portion is covered with the second stopper layer 18. Etch until it reaches.

Next, as shown in FIG. 9 (q), by using the gate electrode 21 as a mask, a second portion other than the gate electrode portion is formed.
The stopper layer 18 is etched until it reaches the third barrier layer 17.

Next, as shown in FIG. 9 (r), a resist pattern R having openings in the source electrode portion and the drain electrode portion is formed, and the third barrier layer 17 in both electrode portions is formed.
Are removed by etching until they reach the first stopper layer 16.

In the subsequent steps, the resist pattern R
On the entire surface, leaving gold germanium alloy AuG
e, nickel Ni, and gold Au are sequentially vapor-deposited to form a metal layer, and the resist pattern R and the unnecessary portion of the metal layer are removed by a lift-off method to leave the metal layer only in the electrode formation portion. By alloying by heat treatment to form the source electrode 22a and the drain electrode 22b, the semiconductor device shown in FIG. 1 can be manufactured.

In the method of manufacturing a semiconductor device according to the present embodiment described above, the semiconductor layers 19 and 18 immediately below the gate electrode 21,
By previously forming the gate opening M in 17 by etching using the electron beam exposure method (see FIG. 7 (m)), the distance d between the gate impurity region 20 and the channel layer 14 is set to a predetermined value. It is possible to reduce the doping depth of the gate impurity region 20, which is necessary to achieve the above. As a result, JHEMT (JHEMT: Junction High Electr
On Mobility Transistor), lateral expansion of the gate impurity region 20, which is a problem when fabricating short gate length transistors, can be suppressed to a small level, and it is compatible with millimeter-wave / quasi-millimeter-wave band communication systems. In addition, it becomes possible to fabricate a transistor having a short gate length and a single positive power supply.

In the conventional junction type transistor shown in FIG. 12, the gate opening C is formed in the insulating film 47 such as silicon nitride in the pattern shown in FIG. 10A, and the insulating film is used as a mask. The gate impurity region 50 is formed by phase diffusion, the gate opening C is covered, and the gate electrode 4 is formed.
8 may be formed in the pattern shown in FIG. 10B and used as the gate electrode 48 having a comb-shaped pattern. In this case, FIG. 12 corresponds to a cross-sectional view taken along the line AA ′ of FIG. At this time, in the gate openings C1 and C2 of the insulating film 47, the insulating film 4 existing around the openings is formed.
Due to the difference in the area of 7, the stress applied to the gate opening differs. As a result, when vapor phase diffusion is performed in the gate opening to form the gate impurity region 50, the stress applied to the gate opening varies depending on the position, so that the diffusion depth varies between the openings, and the gate The threshold value may vary between the fingers 48a and 48b, which may make it difficult to control the threshold voltage (Vth). However, in the present embodiment, even when the above comb-shaped gate is adopted, the gate impurity region 20 is manufactured by
As shown in FIG. 7 (m), without using the insulating film as a mask,
Since vapor phase diffusion is performed over the entire surface of the wafer, the above problems caused by the difference in stress difference between the insulating films do not occur, and devices can be manufactured with high yield.

The semiconductor device of the present invention is not limited to the description of the above embodiment. For example, in this embodiment,
From the viewpoints of productivity and reproducibility, two stopper layers of the first stopper layer 16 and the second stopper layer 18 are provided below the barrier layers 17 and 19 that require etching to manufacture a stable device structure. However, the present invention is not limited to this, and a configuration in which p-type impurities are diffused into the gate opening in a normal recess structure is also possible. In this case, for example, after forming a barrier layer on the channel layer, a gate opening (groove) is formed in the barrier layer, and a p-type impurity is introduced into the entire surface to form a gate impurity region. The gate electrode may be formed in the opening, the gate impurity region in the region other than the gate opening may be removed, and then the source / drain electrodes may be formed.

Further, for example, the buffer layer 12, the high resistance layer 13c, and the carrier supply layer 13a may be omitted to form a single hetero structure. Furthermore, the present invention provides Ga
It is applicable not only to As-based substrates but also to InP-based substrates. For example, when the substrate 11 is made of InP, the buffer layer 12 is made of InP to which no impurities are added, and the high resistance layers (13b, 13c, 15b, 15) are formed.
c) is Al _X In _1-X As (x =
Formed by 0.4 to 0.5), the channel layer 14 is undoped _{In X Ga 1-X As (} x = 0.5~0.6)
And the carrier supply layer (13a, 15a) is n
It may be formed of a type Al _X In _1-X As (x = 0.4 to 0.5). Besides, various modifications can be made without departing from the scope of the present invention.

[0077]

According to the present invention, it is possible to effectively reduce the gate length while enabling a single positive power supply operation.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to this embodiment.

FIG. 2 is a plan view of a semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after formation of the carrier supply layer of a 1st barrier layer.

FIG. 3 is a cross-sectional view subsequent to FIG. 2 after formation of the high resistance layer of the second barrier layer.

FIG. 4 is a cross-sectional view subsequent to FIG. 3 after formation of a second barrier layer.

5 is a cross-sectional view subsequent to FIG. 4 after formation of a third barrier layer.

6 is a cross-sectional view subsequent to FIG. 5 after formation of a fourth barrier layer.

7 is a cross-sectional view subsequent to FIG. 6 after formation of a gate impurity region.

8 is a cross-sectional view subsequent to FIG. 7 after formation of a gate electrode.

FIG. 9 is a cross-sectional view subsequent to FIG. 8 after formation of source / drain openings in the third barrier layer.

FIG. 10 is a diagram for explaining the effect of the method for manufacturing the semiconductor device according to the present embodiment.

FIG. 11 is a sectional view showing a configuration example of a PHEMT according to a conventional example.

FIG. 12 is a cross-sectional view showing one configuration example of JPHEMT according to a conventional example.

[Explanation of symbols]

11 ... Substrate, 12 ... Buffer layer, 13 ... First barrier layer,
13a ... Carrier supply layer, 13b, 13c ... High resistance layer,
14 ... Channel layer, 15 ... Second barrier layer, 15a ... Carrier supply layer, 15b, 15c ... High resistance layer, 16 ... First stopper layer, 17 ... Third barrier layer, 18 ... Second stopper layer , 19 ... Fourth barrier layer, 20 ... Gate impurity region,
21 ... Gate electrode, 22a ... Source electrode, 22b ... Drain electrode, 31,41 ... Substrate, 32, 42 ... Buffer layer, 33, 43 ... First barrier layer, 33a, 43a ... Carrier supply layer, 33b, 33c, 43b, 43c ... High resistance layer, 34, 44 ... Channel layer, 35, 45 ... Second barrier layer, 35a, 45a ... Carrier supply layer, 35b, 35
c, 45b, 45c ... High resistance layer, 36 ... N-type GaAs
Layer, 37, 47 ... Insulating film, 38, 48 ... Gate electrode, 3
9a, 49a ... Source electrode, 39b, 49b ... Drain electrode, 50 ... Gate impurity region.

Claims (15)

[Claims] 1. A channel layer forming a current channel, a semiconductor layer formed on the channel layer, and a gate electrode formed on at least a part of the semiconductor layer,
A semiconductor device in which a conductive impurity region for controlling a threshold value of a current flowing through the channel layer is formed in the semiconductor layer under the gate electrode, wherein the semiconductor layer under the gate electrode is another region. And a semiconductor device in which the conductive impurity region is suppressed from spreading in the formation direction of the current channel. 2. A source electrode and a drain electrode formed on the semiconductor layer so as to be separated from each other with the gate electrode sandwiched therebetween, wherein the semiconductor layer below the gate electrode, the source electrode and the drain electrode is formed. The semiconductor device according to claim 1, wherein the semiconductor device is formed thinner than other regions. 3. The semiconductor device according to claim 1, wherein the semiconductor layer is formed of a semiconductor having a band gap larger than that of a material forming the channel layer. 4. The semiconductor layer includes a carrier supply layer containing an impurity of a first conductivity type for supplying charges to the channel layer, and a second semiconductor layer is provided between the carrier supply layer and the gate electrode. The semiconductor device according to claim 3, wherein the conductive impurity region of conductivity type is formed. 5. The semiconductor device according to claim 3, further comprising a second semiconductor layer formed below the channel layer and made of a semiconductor having a band gap larger than that of a material forming the channel layer. 6. The semiconductor device according to claim 5, wherein the second semiconductor layer includes a carrier supply layer containing an impurity of the first conductivity type for supplying charges to the channel layer. 7. A step of forming a channel layer, a step of forming a semiconductor layer on the channel layer, a step of forming a groove in a part of the semiconductor layer, and a step of forming a groove in at least the groove of the semiconductor layer. A method of manufacturing a semiconductor device, comprising: a step of forming a conductive impurity region for controlling a threshold value of a current flowing through a channel layer; and a step of forming a gate electrode in at least the groove. 8. In the step of forming the conductive impurity region, the conductive impurity region is formed on the entire surface of the semiconductor layer, and after the step of forming the gate electrode, the conductive impurity under the gate electrode is formed. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of removing the semiconductor layer in which the conductive impurity region is formed in another region while leaving the semiconductor layer in which the region is formed. 9. In the step of removing the semiconductor layer in which the conductive impurity region is formed in the other region,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor layer in which the conductive impurity region is formed in another region is removed by etching using the gate electrode as a mask. 10. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the conductive impurity region, the conductive impurity is formed by vapor diffusion. 11. The method of manufacturing a semiconductor device according to claim 7, wherein conductive impurities are ion-implanted in the step of forming the conductive impurity regions. 12. After the step of removing the semiconductor layer in which the conductive impurity region is formed in the other region,
9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a source electrode and a drain electrode separately from each other on the semiconductor layer with the gate electrode interposed therebetween. 13. A source electrode and a drain electrode are formed after the step of removing the semiconductor layer in which the conductive impurity region is formed in the other area and before the step of forming the source electrode and the drain electrode. The semiconductor device according to claim 12, further comprising a step of forming a groove in the semiconductor layer in a region to be formed, wherein the source electrode and the drain electrode are formed in the groove in the step of forming the source electrode and the drain electrode. Manufacturing method. 14. In the step of forming the semiconductor layer,
8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor layer is formed of a semiconductor having a band gap larger than that of a material forming the channel layer. 15. In the step of forming the semiconductor layer,
8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor layer including a carrier supply layer containing an impurity of the first conductivity type for supplying charges to the channel layer is formed.