JPH0217933B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field of the Invention> The present invention relates to a method of manufacturing a semiconductor device such as a field effect transistor having a Schottky barrier gate formed by a metal-semiconductor junction.

<Technical background of the invention and its problems> GaAs has an electron mobility 4 to 5 times greater than that of Si, and it is also used in high frequency field effect transistors (FETs) because it provides a semi-insulating high resistance substrate. ) and high-speed memory IC materials. However, GaAs has low hole mobility and high surface state density, so it is not suitable for manufacturing bipolar transistors and MOSFETs due to the Fermi level pin-nanning effect, and rather it is not suitable for manufacturing bipolar transistors and MOSFETs. FET (Metal-Semiconductor FET or below,
Abbreviated as MESFET. ) have been prototyped and manufactured.

When creating high-frequency transistors or high-speed memory ICs using such MESFETs, the cutoff frequency, which is an indicator of high speed, is determined by the product of gate capacitance and (source resistance + gate resistance).

The gate capacitance is determined by the substrate carrier concentration, gate width, and gate length, but since the substrate carrier concentration and gate width are regulated by the operating characteristics of the FET, the gate capacitance is determined almost only by the gate length. Therefore, in order to increase the speed of FETs, it is necessary to reduce the source resistance and gate resistance in addition to shortening the gate length, and many proposals have been made in the past.

Conventional methods for manufacturing low source resistance GaAs MESFETs can be roughly divided into two methods.

One is a method using an epitaxial wafer, and the other is a method using selective ion implantation.

In the former method, undoped layers, n-layers,
This method uses a wafer on which n ⁺ layers are epitaxially grown in sequence. Using the wafer prepared in this way, an Au-Ge ohmic electrode was selectively formed on the surface of the above n ⁺ layer, and then a part between the source and drain was chemically etched using photolithography. After selectively removing the n ⁺ layer using dry etching or dry etching, a gate electrode is formed on the exposed n ⁺ layer. The FET structure based on this method is called a recess structure, and is a well-known method. However, when creating a recessed structure FET, it is extremely difficult to selectively etch an extremely narrow local region of the n ⁺ layer, from submicron to about 2 μm, with good controllability and uniformity within the wafer surface, so the pinch-off voltage of the FET There are many problems in terms of controllability, uniformity of device characteristics, and improvement in yield, and it cannot be said to be an excellent manufacturing method. Therefore, recessed MESFETs are not often used, especially in the production of devices such as logic devices that require strict control of threshold voltage.

On the other hand, selective ion implantation is considered to be an excellent method for controlling pinch-off voltage and threshold voltage. In this method, to reduce the source resistance,
When selectively forming the n ⁺ layer, it is preferable that the boundary between the n ⁺ layer and the n layer be as close to the gate as possible. However, when the distance between the source and drain is short and a gate of submicron to 1 micron size is to be formed, it is necessary to perform mask alignment for gate formation in the gap between the n ⁺ layer on the source side and the n ⁺ layer on the drain side. The reality is that it is extremely difficult to improve the reproducibility of characteristics and yield improvement.

In response, a method has been proposed in which a heat-resistant gate metal electrode is formed in advance, ions are implanted using this gate as a mask, and an n ⁺ layer is formed in a self-aligned manner near the gate. Silicon compounds of Mo are thermally stable and are relatively popular materials used in Si devices, so the application of such silicon compounds to Schottky metals is being considered.

However, compared to the commonly used Au-based multilayer gate metal, Al has a high specific resistance due to the high melting point metal silicon compound, resulting in a high gate resistance, which is problematic for high-speed or high-frequency transistors.

Furthermore, in the case of a recessed structure FET or an ion-implanted FET with an n ⁺ layer, the channel direction distribution of the product of carrier concentration and thickness (nd) must be symmetrical with respect to the gate, which reduces the source resistance. Therefore, increasing the nd product of the source side region near the gate also increases the nd product of the drain side region near the gate.

During FET operation, the depletion layer under the gate expands more widely on the drain side, so increasing the nd product on the drain side region lowers the gate breakdown voltage, which is extremely problematic in terms of device characteristics and reliability.

<Purpose of the Invention> An object of the present invention is to provide a method for manufacturing a semiconductor device capable of high-speed operation by eliminating the drawbacks of the above-mentioned conventional techniques and achieving low source resistance, low gate resistance, and low gate capacitance. That is.

<Structure of the Invention> In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention provides an
After forming an insulating film on the whole or a part of the surface of the n ⁺ layer and forming an etching mask on this insulating film using photolithography,
The above insulating film is etched to have an undercut region of ~5 μm in size (first step), and when etching the semiconductor surface exposed by this first step, the area between the covered region and the non-covered region by the insulating film is etched. The desired gate region is selectively etched deeply by utilizing accelerated etching due to the strain stress generated from the insulating film to the semiconductor layer, and the carrier concentration/thickness product on the drain side is made smaller than that on the source side. An asymmetric carrier concentration distribution shape is formed on both sides of the gate (second step), and then the etching mask used in the first step is used as a vapor deposition mask on the semiconductor surface exposed in the first and second steps. After depositing an insulating film, the mask is melted to insulate the semiconductor surface except for the undercut region formed in the first step (third step);
Next, a line-shaped or loop-shaped shot junction gate electrode is formed in the undercut region formed in the above step and a part of the insulating film adjacent to that region, and then a positive photoresist is applied and exposed to form the gate electrode. Only the side walls are coated with resist, the source and drain regions of this semiconductor surface region are opened (fourth step), and an ohmic electrode is formed in the opening formed in this fourth step. The source, drain, and gate are electrically isolated by dissolving the resist formed in the step (fifth step).

<Examples of the Invention> The present invention will be described in detail below based on Examples. 1 to 9 are each according to the present invention.
FIG. 1 and FIG. 2 are diagrams showing the manufacturing process of FET, FIG. 1 and FIG. 2 are the first step, FIG. 3 is the second step, FIG. 4 is the third step, and FIGS. 5 to 7 are the Step 4,
FIG. 8 shows the fifth step, and FIG. 9 shows a completed drawing.

As an example, an example of a prototype high-frequency GaAs MESFET was shown.

The substrate used was made semi-insulating in advance as shown in Figure 1.
A 2″φ wafer with a buffer 2, an n layer 3, and an n ⁺ layer 4 formed on a GaAs substrate 1, each layer having a film thickness of 1.0μ.
m, 0.1 μm and 0.1 μm, and the carrier concentrations of each layer are 1×10 ¹³ cm ⁻³ , 3×10 ¹⁷ cm ⁻³ and 10 ¹⁸ cm ⁻³ . The formation method of each conductive layer is VPE method, MBE method,
Either the MOCVD method may be used, or a wafer in which n and n ⁺ layers are formed using the ion implantation method may be used.

Plasma is applied to the surface of the wafer thus prepared.
A SiNx film 5 with a thickness of 0.4 μm is formed by the CVD method. Next, SiNx film 5, n ⁺ layer 4, and n layer 3 are formed for isolation between elements.
Then, a part 6 of the buffer layer 2 is etched into a mesa shape.

A resist pattern 7 is formed in the source region on a portion of the SiNx film 5 of the processed wafer using photolithography. The photoresist used was
It was AZ-1350J, and the resist thickness was 2.0 μm.

Subsequently, as shown in FIG. 2, the SiNx film 5 is subjected to plasma etching using CF ₄ gas to remove the SiNx film 5 in areas other than the resist pattern 7. At this time, if over-etching is performed by controlling the etching time, an undercut region 8 is formed in a closed loop around the resist pattern 7. The width of the undercut region 8 is preferably controlled to about 0.01 to 5 .mu.m, and in this embodiment, the width of the undercut region 8 was controlled to 0.3 .mu.m.

Next, as shown in FIG. 3, an etchant having a small etching rate with good controllability, e.g.
A part of the n ⁺ GaAs layer is etched for 30 seconds at a solution temperature of 20° C. using an etching solution of H ₂ SO ₄ :H ₂ O ₂ :H ₂ O=2:1:50. Even at a liquid temperature of 20℃, the etching speed is
It is 0.1 μm/min.

During etching, the etching rate is increased due to the presence of strain stress in the SiNx film in the vicinity 9 of the undercut region 8, and the etching depth in the vicinity of the same region 9 is approximately
0.1 μm, the n ⁺ layer in the gate region is removed, and the nd product of the drain region 11 near the gate region becomes smaller than that of the source region 10 near the gate region, and the gate breakdown voltage can be increased. .
Control of this strain stress is controlled by the SiNx film thickness and annealing temperature.

As shown in Figure 4, a film with a thickness of 0.4 μm was deposited on the surface of the wafer prepared in this way using the electron beam evaporation method.
A SiNx film 12 is formed. Next, when the photoresist pattern 7 is dissolved using acetone, the SiNx film 1 on the resist pattern 7 is dissolved as shown in FIG.
2 is removed, and the SiNx film 12 on the semiconductor conductive layer 3 is removed.
remains, and a lobe-shaped opening is formed in the gate region 13 in a self-aligned manner.

Subsequently, as shown in FIG. 6, after forming a resist pattern 14 for forming a gate electrode on the thus prepared wafer, Ti, Ti,
A closed loop three-layer gate electrode 15 made of Pt and Au as shown in FIG. 7 is formed. The thickness of this gate electrode 15 was 0.6 μm. Gate electrode 1
Unnecessary metal 16 in areas other than 5 can be removed by lift-off by dissolving the hole resist pattern 14.

In this example, a three-layer electrode of Ti, Pt, and Au and a lift-off method were used to form the gate electrode, but the type of metal does not matter and it is also possible to use a normal photolithography method. The gate electrode 15 has a length of 2 μm, and the effective gate length lg in contact with the n-layer 3 is 0.3 μm. In this example, the gate width was 280 μm. After forming the gate electrode 15, the wafer is cleaned, and then the SiNx films 5 and 12 on the n ⁺ layer 4 are removed by plasma etching using CF ₄ gas using the gate electrode 15 as an etching mask.

Subsequently, as shown in FIG. 8, a positive photoresist pattern 17 for forming an ohmic electrode is formed on the surface of the wafer, similar to the step of forming the gate electrode 15. Since the photoresist 18 under the wing-shaped portion of the gate electrode 15 is not exposed, it remains on the gate sidewall and electrical connection with the gate electrode 15 is avoided during subsequent ohmic electrode formation. After completing the photoresist pattern 17, Au-Ge and Ni are sequentially deposited to a thickness of 0.1 μm to form a source electrode 19 and a drain electrode 2.
form 0. Next, photoresist pattern 17
By dissolving and removing resist pattern 1
The unnecessary Au-Ge/Ni on 7 is removed. Au-Ge and Ni on the gate electrode 15 contribute to reducing gate resistance. After completing the source electrode 19 and drain electrode 20 in a self-aligned manner, the wafer is heat-treated at 420° C. for 30 seconds to obtain ohmic properties.

After the above steps are completed, Ti is applied to the source electrode 19, drain electrode 20, and gate electrode pad portions to facilitate bonding, as shown in FIG.
An electrode 21 made of Au is formed with a thickness of 1.0 μm.
In addition, in order to stabilize the surface of the area other than the bonding electrode 21, a sputtering method was used to form a film with a thickness of 0.4 μm.
The SiO ₂ film 24 is formed to complete the device fabrication process.

By using the manufacturing method described above, the distance between the source and drain electrodes is 2 μm, the gate length is 0.3 μm, and the gate width is
It was possible to form a MESFET with a distance of 280 μm, a distance between the source and gate electrodes of 0.5 μm, and a distance between the gate and drain electrodes of 1.2 μm. In addition, in this FET, the parasitic capacitance caused by both wings of the gate electrode was as small as 0.03 pF, and the increase in capacitance between the gate and source was negligible. Also, the source resistance is 1.5Ω,
Since the gate resistance is extremely small at 1.5Ω, the minimum noise figure at 12GHz was 1.1dB, showing excellent characteristics.

In addition, with this manufacturing method, the product of carrier concentration x active layer thickness (n.d) near the drain end of the gate electrode can be made smaller than that on the source side, so the gate withstand voltage is more than 50% higher than that of the conventional device. It has become possible to improve characteristics, prevent short channel effects, and improve device reliability. Furthermore, since the gate shape is a closed loop, it has the advantage of reducing VSWR.

Furthermore, the manufacturing of this device uses an optical process,
Furthermore, since the distance between the gate electrode and the electrodes between the source and drain can be determined in a self-aligned manner, it is possible to improve the yield and reduce the device manufacturing cost.

<Effects of the Invention> As described above, according to the present invention, low source resistance,
A semiconductor device with low gate resistance and low gate capacitance and capable of high-speed operation can be manufactured.

[Brief explanation of drawings]

1 to 9 are each according to the present invention.
FIG. 1 and FIG. 2 are diagrams showing the manufacturing process of FET, FIG. 1 and FIG. 2 are the first step, FIG. 3 is the second step, FIG. 4 is the third step, and FIGS. 5 to 7 are the Step 4,
FIG. 8 shows the fifth step, and FIG. 9 shows a completed drawing. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAS substrate, 2... Buffer layer, 3... N layer, 4... N ⁺ layer, 5... SiNx film (insulating film), 8... Undercut region, 10... Source region, 11...Drain region, 12...
SiNx film (insulating film), 13...gate region, 15...
...Three-layer structure gate electrode, 17...Positive photoresist pattern, 19...Source electrode, 20...Drain electrode, 21...Bonding electrode, 24...
... _SiO2 film.

Claims (1)

[Claims] 1. An insulating film is formed in advance on the whole or a part of the surface of a semiconductor conductive layer formed on the whole or a part of an insulating substrate or a semiconductor substrate, and a photolithography method is applied on the insulating film. forming an etching mask, etching away the insulating film in areas other than the etching mask area to expose the surface of the semiconductor conductive layer, and forming an undercut with a width of 0.01 to 5 μm in the peripheral area of the etching mask area. a first step of forming a region; and a difference in strain stress on the semiconductor layer caused by the insulating film between the insulating film covered region and the non-covered region in the undercut region formed in the first step. By making the amount of etching of the semiconductor layer under the undercut region faster than the amount of etching in the non-covered region, an asymmetric carrier concentration distribution with a different product of the carrier concentration and the thickness of the semiconductor conductive layer on both sides of the undercut region is created. 2
After forming an insulating film by vapor deposition using the etching mask as a vapor deposition mask on the surface of the semiconductor conductive layer exposed in the first and second steps, the vapor deposition mask is dissolved and the insulating film on the mask is removed. a third step of insulatingly coating the surface of the semiconductor conductive layer other than the undercut region formed in the first and second steps; and a loop-shaped undercut region formed in the step and the periphery of the region. After forming a line-shaped or loop-shaped shot junction gate electrode on a part of the insulating film, the insulating film formed in the first step and the third step is removed by etching using the gate electrode as an etching mask. a fourth step of coating and exposing a positive photoresist to cover the gate electrode sidewall with the resist and forming a resist opening in the semiconductor conductive layer region; and a resist opening formed in the fourth step. and a fifth step of forming an ohmic electrode in the area and dissolving the resist pattern formed in the fourth step to separate the source and drain gate electrode terminals in a self-aligned manner. A method for manufacturing a semiconductor device.