JPS58124277A - Manufacture of schottky gate type field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the resistance between a gate and a source and the resistance between the gate and a drain and to make gm large, by providing operating layers whose carrier number per unit area is large at a part below the part between a source electrode and gate and source electrodes and a part below the part between the a drain electrode and gain and drain electrodes, respectively. CONSTITUTION:On the surface of a semi-insulating semiconductor crystal substrate 1, a one conductive type semiconductor crystal layer 11, which has a thickness and carrier concentration inparting a specified pinch off voltage, is formed. On the surface of the layer 11, a stripe shaped implanting mask 12 is formed. With said mask as a mask material, impurities, which are to become the same conductive type as that of the crystal layer 11 formed previously, are ion-implanted by a specified dose amount, and the deep operating layers 13 and 14 are formed. Then annealing is performed and the source and drain electrodes 17 and 18 are formed by an ordinary method. Thereafter, a Schottky gate electrode 16 is formed so as to cover a first operating layer 15. At this time, since gate capacitance is made as small as possible, the length of the overlapped part is made to be 1mum or less.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a Schottky gate field effect transistor.

Schottky gate field effect transistor (ME
(abbreviated as SFET) has been praised as an excellent amplification or oscillation element, especially at ultra-high frequencies. It is also well known that it is an excellent basic component for integrated circuits operating at ultra-high speeds.

One of the drawbacks of the conventional MESFET structure as shown in FIG.
The problem is that a sufficiently large gmQ value cannot be obtained because the resistance value between the gate and the source is large, and the noise characteristics are deteriorated due to the large gate-source series resistance. Especially when the absolute value of the pinch-off voltage Vp is small or normally-off (V
When p>o), the value of the carrier concentration in the film thickness becomes smaller, so the series resistance between the gate and the source becomes a larger value. In addition, when the active layer 2 uses a GaAs crystal, there are high density surface states in the crystal surface portions 6 and 7 between the gate and source and between the gate and drain, so that the surface potential is approximately Since the gate-source series resistance is fixed and a depletion layer is formed near the surface of the semiconductor crystal, the gate-source series resistance becomes even larger, especially in normally-off type.
This was an extremely serious issue.

As one method to solve these drawbacks, as shown in FIG. 2, active layers 9. It is practiced to make lO thicker than the thickness of the active layer 8 directly under the gate electrode. In this method, it is necessary to determine the thickness and carrier concentration of the active layer 8 so as to obtain the desired pinch-off voltage, but in such a step structure, the thickness of the active layer 8 must be precisely controlled with good reproducibility by etching, etc. This is difficult to do with current technology.

The present invention provides a new ME that solves the above-mentioned drawbacks of the prior art.
The present invention provides an SFET and a method for manufacturing the same.

The present invention will be explained below based on the drawings.

An example of the MESFET of the present invention is shown in FIG.

FIG. 3 shows a semiconductor crystal substrate 1 with an active layer 15 below a Schottky gate electrode 16, a source electrode 17, an active layer 13 with a large number of carriers per unit area below the gate and source electrodes, and a drain electrode. 18 and a 1" operating layer 14 (with a large number of carriers per unit area) below between the gate and drain electrodes.
It is an SFET. MESFETs having such a structure are excellent in that the gate-source resistance and gate-drain resistance are small and the resistance is large. It can be manufactured with high yield.

4th. - Figures (a) to 4-(d) are M according to the present invention.
FIG. 3 is a cross-sectional view for explaining the manufacturing process of the ESFET.

First, as shown in FIG. 46(a), a semiconductor crystal layer 11 of one conductivity type is formed on the surface of a high resistivity or semi-insulating semiconductor crystal substrate l. At this time, the thickness of layer 11 and the concentration of key layer 3 are determined so that the pinch-off voltage becomes a desired value. The method for producing 11 may be a vapor phase epitaxial method, a liquid phase epitaxial method, or a method of ion-implanting impurities into the semi-insulating substrate 1. For example, GaA
How to obtain an operating layer with a pinch-off voltage of O volts (normally off) by ion-implanting T851+ into a semi-insulating crystal substrate! The implantation amount of 85i+ was 1.3X10” dose/c
An example of this is implantation at m' and an accelerating voltage of 50 KeV. (However, the activation rate is 100%) Next, a striped implantation mask 12 is formed on the surface of the crystal layer 11, as shown in FIG. Although photoresist is suitable as the material for 12, other materials may be used as long as they can be used as a selective mask for ion implantation and can be easily formed and peeled off. Next 1
2 as a mask material, impurities having the same conductivity type as the previously formed crystal layer 11 are introduced into the crystal substrate by ion implantation or thermal diffusion to form deep active layers 13 and 14.

It goes without saying that the larger the dose in the deep active layer 18, 14, the lower the source resistance.However, as the dose increases, the surface carrier density increases, which increases the gate capacitance and increases the gate capacitance. A voltage applied to the capacitor causes a breakdown breakdown. Therefore, there is an optimum dose amount for a certain acceleration voltage. FIG. 5 shows the results of theoretical calculations of the capacitance in the region of overlap between the gate metal and the deep injection layer (region A in FIG. 5).

The horizontal axis is the gate applied voltage, with the dose of deep implantation as a parameter. However, the size of the overlap area is
The size is 1 μm×50 μm, and the ion implantation conditions are 50 KeV t3xio””Se/,g for implantation of the active layer, and 180 KeV for the acceleration voltage of X implantation. From this result, when the overlap length is 1 μm or less, the dose amount is 3XIO”dos.
It can be seen that the amount of increase in capacitance is relatively small if it is less than e/♂.

Now, the minimum propagation delay time of the inverter when a sufficient supply voltage is applied is given by the product of the on-resistance of the FET and the gate capacitance. Based on the calculation results in Figure 5, when the gate capacitance and the product of gate capacitance and FET on-resistance are plotted against the dose of deep implantation when the gate applied voltage is +0.3V, Figure 6 shows. It comes to show. (The broken line is the calculation result when the length A of the overlapping region is 0.4 μm.) The circle in the figure is the propagation delay per stage calculated from the actual measured value of the oscillation frequency of the manufactured ring oscillator. This is the average value over time and shows almost the same tendency as the theoretical curve.

From the above results, the dose for deep implantation at acceleration voltage] and 80 KeV is 3x 101 Rdome/a
~3 X1018 dose/, - is considered to be optimal.

Next, if layers 13, 14, or 15 are formed by ion implantation, then annealing is performed for the purpose of activating these ion implanted layers. At this time, the crystal substrate is GaAs, I
In the case of a compound semiconductor such as nP, GaAs,
Either InP wafers are stacked and annealed, or Si
Annealing is performed by forming an insulating film such as a N film or a SiO□ film, or by controlling As pressure or P pressure to prevent surface deterioration.
Annealing is performed for 0 minutes. Thereafter, as shown in FIG. 41(c), source/drain electrodes 17 and 18 are formed in the cylinder 4 in a conventional manner, and then a Schottky gate electrode 16 is formed on the first active layer 15 as shown in FIG. 41(d). Form to cover. Naturally, the shorter the length of the overlap region between the gate electrode and the second active layer 13, 14, the smaller the gate capacitance, so it is desirable, but as shown in FIG. It has been shown that sufficiently high-speed operation can be obtained by using the optimum dose amount even if it is 1 μm. This means that the MESFE according to the present invention
Mask alignment margin of T gate electrode formation process is 1μ
This shows that the gate electrode 16 can be easily formed on the active layer 15.

Further, in the present invention, since the Schottky electrode is formed after annealing, there is a degree of freedom in selecting the annealing conditions and the type of metal for the Schottky electrode. This is an extremely important advantage in the case of GaAs, where the crystal surface is susceptible to thermal deterioration and the Schottky junction is significantly dependent on the type of Schottky electrode metal.

71 The present invention is not limited to the content explained based on the above drawings, and the purpose of the present invention is to
This can be achieved using many semiconductor crystals such as P and Si, and is not limited to only one semiconductor crystal. Moreover, the material of the mask etc. can be arbitrarily selected without changing the intention of the present invention.

As described above, according to the present invention, a MESFET with a small series resistance between the gate and the source and a large ring can be easily produced.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a Schottky gate field effect transistor according to a conventional method, FIG. 3 is a cross-sectional view of a Schottky gate field effect transistor of the present invention, and FIGS. (d) is a cross-sectional structural diagram showing the manufacturing process according to the present invention, FIG. 5 is a diagram showing the gate voltage dependence of gate capacitance, and FIG. 6 is a diagram showing the gate capacitance of ν;'ira. FIG. 3 is a diagram showing the dose dependence of an injection layer with a deep layer. 1 in the figure is a semiconductor crystal substrate, 2.8.9.10.13.1
4゜8-15 is the active layer, 3.16 is the Schottky gate electrode, 4
．． 17 is a source electrode, 5 and 18 are drain electrodes, 12 is a striped mask -346- Gate voltage (V) Figure 6

Claims (1)

[Claims] A first semiconductor crystal operating layer of one conductivity type is formed on one main surface of a high resistivity or semi-insulating semiconductor crystal substrate by selecting its thickness and carrier concentration so that the pinch-off voltage is a desired value. a step of forming a striped mask pattern on the semiconductor crystal, and using the mask pattern as a mask, adding an impurity having the same conductivity type as that of the first active layer to 3×10 l' dOS e/ “crn”
A step of forming a second deep active layer on both sides of the first active layer by ion implantation at a dose of ~3XIQ'8dO8e&* and an implantation energy of 100 KeV or more, and removing the striped pattern. a step of performing annealing, a step of forming source and drain electrodes on the second deep active layer, a step of forming a Schottky electrode on the semiconductor crystal, completely covering the first semiconductor active layer and forming a second semiconductor active layer; The length of the overlapped part with the layer is 1.
A method for manufacturing a Schottky gate field effect transistor, comprising a step of forming the transistor to have a thickness of 0 μm or less.