JPS6336151B2 - - Google Patents
Info
- Publication number
- JPS6336151B2 JPS6336151B2 JP56062999A JP6299981A JPS6336151B2 JP S6336151 B2 JPS6336151 B2 JP S6336151B2 JP 56062999 A JP56062999 A JP 56062999A JP 6299981 A JP6299981 A JP 6299981A JP S6336151 B2 JPS6336151 B2 JP S6336151B2
- Authority
- JP
- Japan
- Prior art keywords
- mask
- active layer
- impurity
- forming
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 description 16
- 238000002513 implantation Methods 0.000 description 10
- 238000009826 distribution Methods 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Description
【発明の詳細な説明】
本発明は、シヨツトキゲート電界効果トランジ
スタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a shot gate field effect transistor.
シヨツトキゲート電界効果トランジスタ（以下
MESFETと略記する）は、特に超高周波におけ
るすぐれた増幅あるいは発振用素子として賞用さ
れている。また、超高速動作の集積回路の基本構
成素子としてもすぐれたものであることは周知で
ある。 Short gate field effect transistor (hereinafter referred to as
MESFET (abbreviated as MESFET) is prized as an excellent amplification or oscillation element, especially at ultra-high frequencies. It is also well known that it is an excellent basic component for integrated circuits operating at ultra-high speeds.
従来最も普通に用いられているMESFETの構
造は第１図に示したようなものである。ここで１
は高比抵抗または半絶縁性半導体結晶基板、２は
導電性半導体結晶層で通常、動作層と称されてい
るものである。３はシヨツトキゲート電極、４，
５はそれぞれオーシツク特性を有するソース、ド
レイン電極である。２の動作層のキヤリア濃度
Ndおよび厚さａは、MESFETのピンチオフ電圧
Vpと次の第１式のような関係がある。 The structure of the MESFET most commonly used in the past is shown in Figure 1. Here 1
2 is a high resistivity or semi-insulating semiconductor crystal substrate, and 2 is a conductive semiconductor crystal layer which is usually called an operating layer. 3 is a short gate electrode, 4,
Reference numerals 5 denote source and drain electrodes each having oscilloscope characteristics. Carrier concentration of active layer 2
Nd and thickness a are the pinch-off voltage of MESFET
There is a relationship between Vp and the following equation 1.
Vp＝Vb−qNd／2εa2 (1)
ただしVbはビルトイン電圧、εは半導体結晶
の誘電率、ｑは電荷素量
Vpは回路設計上の要求から与えられるが、こ
のVpの値を満足するよう(1)式を用いてNd、ａの
値が定められる。 Vp=Vb−qNd/2εa 2 (1) where Vb is the built-in voltage, ε is the dielectric constant of the semiconductor crystal, and q is the elementary charge amount. The values of Nd and a are determined using equation (1).
第１図のような従来の構造の欠点の一つは、ゲ
ート３とソース４あるいはゲート３とドレイン５
の間の抵抗値が高くなるためにgmが充分大きな
値が得られないこと、また雑音特性が劣化するこ
とである。特にピンチオフ電圧Vpの絶対値が小
さいとき、あるいはノーマリオフ（Vp＞０）に
おいては、(1)式から明らかなように、Ndあるい
はａは小さな値とせねばならないためにゲート・
ソース間の直列抵抗はより大きな値となる。また
動作層２がGaAs結晶を用いている場合には、ゲ
ート・ソース間およびゲート・ドレイン間の結晶
表面部６，７に高密度の表面準位が存在して、そ
れにより表面電位がほぼ固定され、半導体結晶内
の表面近くでは空乏層ができるため、ゲート・ソ
ース間直列抵抗はいつそう大きな値となり、特に
ノーマリオフ型ではきわめて重大な問題であつ
た。 One of the drawbacks of the conventional structure as shown in FIG.
Since the resistance value between the two ends increases, it is not possible to obtain a sufficiently large value for gm, and the noise characteristics deteriorate. In particular, when the absolute value of the pinch-off voltage Vp is small, or when normally off (Vp > 0), as is clear from equation (1), Nd or a must be a small value, so the gate
The series resistance between the sources becomes larger. In addition, when the active layer 2 is made of GaAs crystal, there are high-density surface states in the crystal surface areas 6 and 7 between the gate and source and between the gate and drain, which causes the surface potential to be almost fixed. Since a depletion layer is formed near the surface of the semiconductor crystal, the series resistance between the gate and source becomes very large, which is an extremely serious problem especially in normally-off type devices.
このような欠点を解決するための方法の一つと
して第２図のようにゲート・ソース間およびゲー
ト・ドレイン間の動作層９，１０をゲート電極直
下の動作層８の厚さよりも厚くすることが行われ
ている。しかし、この方法では８の動作層の厚
さ、キヤリア濃度を(1)式の条件を満すよう定める
必要があるが、このような段差構造において、エ
ツチング等で、８の部分の厚さを精密に再現性良
く制御することは現在の技術では困難である。 One way to solve this problem is to make the active layers 9 and 10 between the gate and source and between the gate and drain thicker than the active layer 8 directly under the gate electrode, as shown in FIG. is being carried out. However, in this method, it is necessary to determine the thickness of the active layer 8 and the carrier concentration so as to satisfy the conditions of equation (1), but in such a stepped structure, the thickness of the active layer 8 must be determined by etching, etc. It is difficult with current technology to control accurately and with good reproducibility.
また従来のMESFETの他の欠点は、ゲート長
が３のゲート電極金属の長さで定まるため、リソ
グラフイ技術あるいはエツチング技術の精度によ
る限界によつてゲート長が定まり、現在の技術で
は0.5μｍ以下の短いゲート長を有するFETの作成
が困難であつたことである。高周波特性あるい
は、ICの応答速度はゲート長が短いほど良好な
ものとなるのは周知であり、より短いゲート長を
作成する技術が強く求められている。 Another disadvantage of conventional MESFETs is that the gate length is determined by the length of the gate electrode metal, so the gate length is determined by the limits of the precision of lithography or etching technology, and with current technology it is less than 0.5 μm. It was difficult to create an FET with a short gate length. It is well known that the shorter the gate length, the better the high frequency characteristics or response speed of an IC, and there is a strong need for technology to create shorter gate lengths.
本発明は上記の従来技術の欠点を解決すべくな
されたものであり、イオン注入法により短いゲー
ト部の動作層および深いゲート・ソース間、ゲー
ト・ドレイン間の動作層を作成するものである。 The present invention has been made to solve the above-mentioned drawbacks of the prior art, and uses ion implantation to create a short gate active layer and deep gate-source and gate-drain active layers.
以下本発明を図に基づいて説明する。 The present invention will be explained below based on the drawings.
第３図は本発明により作製されるMESFETの
構造を示す断面図である。図中１１はピンチオフ
電圧Vpを与えるべく第１式の条件式を満すよう
な短く、浅い動作層、１２，１３は直列抵抗を小
さくするために深く、およびまたは高濃度に形成
された動作層、１４，１５はオーミツクコンタク
トのための高濃度注入層である。 FIG. 3 is a cross-sectional view showing the structure of a MESFET manufactured according to the present invention. In the figure, 11 is a short and shallow active layer that satisfies the first condition to provide the pinch-off voltage Vp, and 12 and 13 are active layers that are deep and/or highly concentrated to reduce series resistance. , 14, 15 are high concentration implantation layers for ohmic contact.
このような構造を有する本発明による
MESFETは深い動作層１２，１３の存在のため
に、寄生抵抗が小さくそのためgmの大きい、高
周波特性にすぐれたものである。また、そのゲー
ト長は実動的に浅い動作層１１の長さで定まり、
この動作層１１は本発明によれば微小なものが容
易に作成できるため、よりすぐれた高周波特性を
与えるものである。 According to the present invention having such a structure
Because of the presence of deep active layers 12 and 13, the MESFET has a small parasitic resistance, a large gm, and excellent high frequency characteristics. In addition, the gate length is determined by the length of the actually shallow active layer 11,
According to the present invention, this active layer 11 can be easily formed into a minute one, so that it provides better high frequency characteristics.
第４−ａ図〜第４−ｅ図は本発明による
MESFETの製造工程を説明するための断面図で
ある。 Figures 4-a to 4-e are according to the present invention.
FIG. 3 is a cross-sectional view for explaining the manufacturing process of MESFET.
まず第４−ａ図に示したごとく、高比抵抗また
は半絶縁性半導体結晶基板１の表面に一導電型の
半導体結晶層１６を作成する。このとき１６の厚
さ、キヤリア濃度は第(1)式よりVpが所望の値と
なるよう定める。１６の作成法は気相エピタキシ
ヤル法、液相エピタキシヤル法、あるいは半絶縁
性基板１へ不純物をイオン注入する方法等のいず
れを用いても良い、例えばイオン注入方法とし
て、GaAs半絶縁性結晶基板へ 28Si+をイオン注
入して、ピンチオフ電圧０ボルト（ノーマリオ
フ）の動作層を得るには、 28Si+の注入量を5.5×
1011ドーズ／cm2、加速電圧120KeVで注入するの
がその一例である。（ただし活性化率100％）この
ときのキヤリア濃度分布の理論値を第５図中の実
線２３に示した。（横軸は半導体結晶層の表面か
らの距離即ち深さ（μｍ）、縦軸はキヤリア濃度
（cm-3）である。）
次に上記結晶層１６の表面に、第４−ｂ図に示
すようにストライプ状の注入マスク１７を形成す
る。マスク１７の材料としてはフオトレジスト、
電子線レジストが適当であるが、イオン注入の選
択マスクとして用い得る材料で、容易に形成、は
く離できるものであれば他のものであつても良
い。次に１７をマスク材として先に形成された結
晶層１６と同一の導伝型となる不純物をイオン注
入または熱拡散法で結晶基板中に導入し、深い動
作層１２，１３を形成する。熱拡散法で行うとき
は、マスク材１７は充分な耐熱性を有する材料を
用いるべきであることは勿論である。 First, as shown in FIG. 4-a, a semiconductor crystal layer 16 of one conductivity type is formed on the surface of a high resistivity or semi-insulating semiconductor crystal substrate 1. At this time, the thickness and carrier concentration of 16 are determined from equation (1) so that Vp becomes a desired value. 16 may be produced using a vapor phase epitaxial method, a liquid phase epitaxial method, or a method of ion-implanting impurities into the semi-insulating substrate 1. For example, as an ion-implanting method, GaAs semi-insulating crystal In order to obtain an operating layer with a pinch-off voltage of 0 volts (normally off) by ion-implanting 28 Si + into the substrate, the amount of 28 Si + implanted should be 5.5×.
An example is implantation at a dose of 10 11 /cm 2 and an acceleration voltage of 120 KeV. (However, the activation rate was 100%) The theoretical value of the carrier concentration distribution at this time is shown by the solid line 23 in FIG. (The horizontal axis is the distance from the surface of the semiconductor crystal layer, that is, the depth (μm), and the vertical axis is the carrier concentration (cm -3 ).) Next, on the surface of the crystal layer 16, as shown in FIG. 4-b, A striped implantation mask 17 is formed as shown in FIG. The material of the mask 17 is photoresist,
Electron beam resist is suitable, but other materials may be used as long as they can be used as a selective mask for ion implantation and can be easily formed and removed. Next, using 17 as a mask material, impurities having the same conductivity type as the previously formed crystal layer 16 are introduced into the crystal substrate by ion implantation or thermal diffusion to form deep active layers 12 and 13. Of course, when the thermal diffusion method is used, the mask material 17 should be made of a material with sufficient heat resistance.
前記の深い動作層をイオン注入で行うときの条
件としては、浅い動作層１６よりも深く注入する
ために注入エネルギが浅い動作層１６の注入に用
いたエネルギよりも大きく、かつ注入量は最終ピ
ークキヤリア濃度が動作層１６のピークキヤリア
濃度に比べて極度に過大にならないような値に選
択するのが好ましい。これはゲートに印加される
電圧によつて絶縁破壊が生じないようにするため
である。このような注入条件の一例として、注入
エネルギを400KeV、注入量を1.07×1012ドー
ズ／cm2の値に選択した場合のキヤリア密度分布の
理論値を第５図の破線２４で例示する。１７によ
つてマスクされない部分１２，１３の濃度は１回
目の浅いイオン注入による濃度に２回目の深いイ
オン注入による濃度を加算した値となり、その分
布は第５図の一点破線２５で例示される。 The conditions for implanting the deep active layer by ion implantation are that in order to implant deeper than the shallow active layer 16, the implantation energy is greater than the energy used for implanting the shallow active layer 16, and the implantation amount is at the final peak. It is preferable to select a value such that the carrier concentration is not extremely excessive compared to the peak carrier concentration of the active layer 16. This is to prevent dielectric breakdown from occurring due to the voltage applied to the gate. As an example of such implantation conditions, the theoretical value of the carrier density distribution when the implantation energy is 400 KeV and the implantation amount is 1.07×10 12 dose/cm 2 is illustrated by the broken line 24 in FIG. The concentration of the portions 12 and 13 not masked by 17 is the sum of the concentration obtained by the first shallow ion implantation and the concentration obtained by the second deep ion implantation, and its distribution is illustrated by the dotted line 25 in FIG. .
第５図より明らかなように、ピンチオフ電圧を
与える主要な動作層１１内のキヤリア総数に比べ
て、深い動作層１２，１３のキヤリア総数は約３
倍大きく、従つて動作層１２，１３が、１１と全
く同一に形成された従来法の第１図における場合
と比較すると本方法では少なくともゲート・ソー
ス間抵抗は1/3以下に低減できる。 As is clear from FIG. 5, compared to the total number of carriers in the main active layer 11 that provides the pinch-off voltage, the total number of carriers in the deep active layers 12 and 13 is approximately 3.
Compared to the case of the conventional method shown in FIG. 1, in which the active layers 12 and 13 are formed exactly the same as 11, the gate-source resistance can be reduced to at least one-third or less in this method.
なお２回目の注入条件としてより大きなドーズ
量を選定すれば、よりゲート・ソース間抵抗を減
少することが可能であるが、このとき不純物濃度
が過大となつてゲート逆耐圧が所望値より小さく
ならない範囲でドーズ量を選定すべきである。 Note that if a larger dose is selected as the second implantation condition, it is possible to further reduce the gate-source resistance, but in this case, the impurity concentration becomes excessive and the gate reverse breakdown voltage does not become smaller than the desired value. The dose should be selected within a range.
次に基板全面に対してAlなどの金属膜１８，
１９，２０を図４−ｃのごとく蒸着する。 Next, a metal film 18 such as Al is applied to the entire surface of the substrate.
19 and 20 are deposited as shown in FIG. 4-c.
この後マスク材１７を適当な溶剤、例えばフオ
トレジストの場合には有機溶剤で除去すると、マ
スク材１７の上部の蒸着膜１９は同時に除去され
て、（リフトオフ）、第４−ｄ図に示したようにマ
スク材１７の反転像となる蒸着膜パターン１８，
２０が得られる。しかる後に１８，２０をマスク
材として窓部の一部２１の部分が、深い動作層１
２，１３とほぼ同一の不純物濃度分布を示すよう
に図示のごとくななめよりイオン注入を行う。こ
こで重要なことは、浅い部分が残るように必らず
ななめから注入を行うことである。この残された
浅い動作層が後にピンチオフを与える主要な動作
層として用いられる。この浅い主要動作層１３の
長さは、注入角度およびマスク材２０の厚さを適
当に選定することにより、容易に精密に制御でき
ることは明らかであろう。例えばマスク材の厚さ
を5000Åとし、注入角度を垂直より30゜とすると、
主要動作層１１の長さはほぼ2900Åとなる。（実
際には注入原子は横方向にも散乱されるため動作
層１１の長さは上記値よりもさらに短くなる。）
従来のリソグラフイ技術を用いて0.5μｍのゲート
長を有するMESFETを再現性良く作成すること
は困難であり、そのため短ゲート長MESFETの
高集積度ICを作成することはいつそう困難な状
況にあつたが、本方法では、本質的に再現性にす
ぐれ、高歩留で短い動作層（実効ゲート長）を作
成できることは明らかである。なおマスク材１
８，２０は単にイオン注入のためのマスク材であ
るから、注入イオンを阻止し、容易に形成・除去
できる材料であればAlに必らず他の材料であつ
ても良い。 After that, when the mask material 17 is removed with a suitable solvent, for example, an organic solvent in the case of photoresist, the vapor deposited film 19 on the top of the mask material 17 is simultaneously removed (lift-off), as shown in FIG. 4-d. The vapor deposited film pattern 18 is an inverted image of the mask material 17 as shown in FIG.
20 is obtained. Thereafter, a portion 21 of the window portion is covered with the deep active layer 1 using masks 18 and 20.
Ion implantation is performed diagonally as shown in the figure so as to exhibit impurity concentration distributions that are substantially the same as those shown in FIGS. 2 and 13. The important thing here is to be sure to perform the injection diagonally so that a shallow portion remains. This remaining shallow active layer is later used as the main active layer that provides pinch-off. It will be appreciated that the length of this shallow primary active layer 13 can be easily and precisely controlled by appropriate selection of the implant angle and the thickness of the masking material 20. For example, if the thickness of the mask material is 5000 Å and the implantation angle is 30° from the vertical,
The length of the main active layer 11 is approximately 2900 Å. (Actually, since the implanted atoms are also scattered in the lateral direction, the length of the active layer 11 becomes even shorter than the above value.)
It is difficult to fabricate MESFETs with a gate length of 0.5 μm with good reproducibility using conventional lithography techniques, and therefore it is difficult to fabricate highly integrated ICs with short gate length MESFETs. However, it is clear that the present method can produce a short active layer (effective gate length) with essentially excellent reproducibility and high yield. Furthermore, mask material 1
Since 8 and 20 are simply mask materials for ion implantation, other materials may be used instead of Al as long as they block implanted ions and can be easily formed and removed.
次にマスク材１８，２０を除去した後、望まし
くは第４−ｅ図に示すごとく、２２をマスクとし
てオーミツクコンタクト部となるべき部分にイオ
ン注入または熱拡散法で選択的に高不純物層１
４，１５を形成し、その後マスク材２２を除去
し、注入層の活性化のためのアニールを行う。ア
ニールを行うに際しては結晶材料がGaAs、InP
等の化合物半導体である場合は、結晶表面を保護
するために、Si3N4膜等のコート、または／およ
びAs圧、あるいはＰ圧制御のもとでアニールを
行う等の留意が必要である。 Next, after removing the mask materials 18 and 20, as shown in FIG. 4-e, a high impurity layer 1 is selectively formed by ion implantation or thermal diffusion into the portion to become an ohmic contact portion using 22 as a mask.
4 and 15 are formed, then the mask material 22 is removed and annealing is performed to activate the injection layer. When performing annealing, the crystal material is GaAs, InP.
In the case of compound semiconductors such as, it is necessary to take care to protect the crystal surface by coating with a Si 3 N 4 film, etc., and/or annealing under As pressure or P pressure control. .
アニール後、通常の良く知られた方法によりゲ
ート電極３、ソース電極４、ドレイン電極５を形
成して、第３図に示す如きMESFETを得ること
が出来る。 After annealing, a gate electrode 3, a source electrode 4, and a drain electrode 5 are formed by a conventional well-known method to obtain a MESFET as shown in FIG.
以上説明したごとく、本発明によれば、ゲート
長が短く、かつゲートソース間直列抵抗が小さい
MESFETを容易に再現性良く作成できるもので
あり、本発明は工業的価値の高いものである。 As explained above, according to the present invention, the gate length is short and the series resistance between the gate and source is small.
MESFETs can be easily produced with good reproducibility, and the present invention has high industrial value.
第１図、第２図は従来法による電界効果トラン
ジスタの構造を示す断面図、第３図は本発明によ
り作製される電界効果トランジスタの構造を示す
断面図、第４ａ〜ｅ図は本発明の製造工程を説明
するための断面図、第５図は本発明によつて動作
層を作成したときのキヤリア濃度分布の一例を示
す図である。
図中、１は半絶縁性半導体結晶、２，８，９，
１０，１１，１２，１３，１６，２１は動作層、
３はシヨツトキゲート金属、４はソース電極、５
はドレイン電極、６はゲート・ソース間結晶表
面、７はゲート・ドレイン間結晶表面、１４，１
５は高不純物濃度層、１７，２２はマスク、１
８，１９，２０は金属蒸着膜、２３は浅い動作層
のキヤリア濃度分布の一例、２４は２回目のイオ
ン注入によるキヤリア濃度分布の一例、２５は深
い動作層のキヤリア濃度分布の一例、である。
1 and 2 are cross-sectional views showing the structure of a field effect transistor produced by a conventional method, FIG. 3 is a cross-sectional view showing the structure of a field effect transistor manufactured according to the present invention, and FIGS. FIG. 5, which is a sectional view for explaining the manufacturing process, is a diagram showing an example of carrier concentration distribution when an active layer is created according to the present invention. In the figure, 1 is a semi-insulating semiconductor crystal, 2, 8, 9,
10, 11, 12, 13, 16, 21 are operating layers,
3 is shot gate metal, 4 is source electrode, 5 is
is the drain electrode, 6 is the crystal surface between the gate and source, 7 is the crystal surface between the gate and drain, 14,1
5 is a high impurity concentration layer, 17 and 22 are masks, 1
8, 19, and 20 are metal vapor deposited films, 23 is an example of carrier concentration distribution in a shallow active layer, 24 is an example of carrier concentration distribution due to the second ion implantation, and 25 is an example of carrier concentration distribution in a deep active layer. .
Claims (1)
体結晶動作層を、ピンチオフ電圧が所望の値とな
るような厚さ、キヤリア濃度を選択して、形成す
る工程と、ストライプ状のレジストパターンを前
記半導体結晶動作層上に形成する工程と、該レジ
ストパターンをマスクとして前記動作層と同一導
電型を与える不純物を選択的にイオン注入または
熱拡散法により導入する工程と、前記レジストパ
ターンに対して正しく反転したパターンを有する
蒸着金属膜のマスクをリフトオフ法により形成す
る工程と、該反転マスクパターンをマスクとして
前記動作層と同一の導電型を与える不純物を斜め
よりイオン注入し、蒸着金属膜のマスクの窓部の
一部に不純物を導入する工程と、該金属膜を除去
する工程と、イオン注入不純物の活性化のための
アニールを行う工程と、少なくとも前記蒸着金属
膜のマスクの窓部の、不純物が導入されなかつた
領域を覆つてシヨツトキゲート電極を形成する工
程と、ソース電極およびドレイン電極とを形成す
る工程とを備えることを特徴とするシヨツトキゲ
ート電界効果トランジスタの製造方法。1. A step of forming a semiconductor crystal operating layer of one conductivity type on one main surface of a semi-insulating semiconductor substrate by selecting a thickness and a carrier concentration such that the pinch-off voltage becomes a desired value, and forming a striped resist pattern. on the semiconductor crystal active layer; using the resist pattern as a mask, selectively introducing impurities that give the same conductivity type as the active layer by ion implantation or thermal diffusion; A step of forming a mask of a vapor deposited metal film having a correctly inverted pattern using a lift-off method, and using the inverted mask pattern as a mask, ions of an impurity giving the same conductivity type as the active layer are obliquely implanted to form a mask of the vapor deposited metal film. A step of introducing an impurity into a part of the window portion of the mask, a step of removing the metal film, a step of performing annealing to activate the ion-implanted impurity, and a step of introducing an impurity into a portion of the window portion of the mask of the vapor deposited metal film. 1. A method for manufacturing a shot gate field effect transistor, comprising the steps of: forming a shot gate electrode covering a region into which no impurity has been introduced; and forming a source electrode and a drain electrode.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299981A JPS57177571A (en) | 1981-04-24 | 1981-04-24 | Field effect transistor and manufacture thereof |
| US06/342,912 US4694563A (en) | 1981-01-29 | 1982-01-26 | Process for making Schottky-barrier gate FET |
| DE8282300499T DE3273695D1 (en) | 1981-01-29 | 1982-01-29 | A schottky-barrier gate field effect transistor and a process for the production of the same |
| CA000395215A CA1187206A (en) | 1981-01-29 | 1982-01-29 | Schottky-barrier gate field effect transistor and a process for the production of the same |
| EP82300499A EP0057605B1 (en) | 1981-01-29 | 1982-01-29 | A schottky-barrier gate field effect transistor and a process for the production of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299981A JPS57177571A (en) | 1981-04-24 | 1981-04-24 | Field effect transistor and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57177571A JPS57177571A (en) | 1982-11-01 |
| JPS6336151B2 true JPS6336151B2 (en) | 1988-07-19 |
Family
ID=13216579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6299981A Granted JPS57177571A (en) | 1981-01-29 | 1981-04-24 | Field effect transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57177571A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60241271A (en) * | 1984-05-16 | 1985-11-30 | Nec Corp | Schottky type fet |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS535581A (en) * | 1976-07-06 | 1978-01-19 | Toshiba Corp | Schottky gate type field effect transistor |
-
1981
- 1981-04-24 JP JP6299981A patent/JPS57177571A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS535581A (en) * | 1976-07-06 | 1978-01-19 | Toshiba Corp | Schottky gate type field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57177571A (en) | 1982-11-01 |
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