JPS5879770A - Schottky gate field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce resistance between a gate and a source, and to improve a microwave characteristic by forming an operating layer in the vicinity of a gate electrode in shape that its thickness is made thicker than an operating layer just under the gate electrode and its impurity concentration is made higher than that of the operating layer just under the gate electrode. CONSTITUTION:<28>Si<+> Ions are implanted in the surface of a semi-insulating semiconductor substrate 21 made of GaAs, etc. and the operating layer 22' with uniform thickness is formed. A high-melting point metal is evaporated onto the operating layer 22', and a resist pattern is shaped onto the metal. A metallic layer is etched by using the resist pattern, and the gate electrode 25 is molded. Layers 26, 27 with high concentration are formed through the second ion implantation while employing the resist pattern as a mask. The resist pattern is removed, and the operating layer 22'' is shaped through the third ion implantation by using the gate electrode 25 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky gate field effect transistor that has good microwave characteristics and is easy to manufacture.

The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as St or compound semiconductors. Explanation will be given by taking GaAs among semiconductors as an example.

The general structure of a conventional Schottky gate field effect transistor is made of GaAs, as illustrated in the cross-sectional view of FIG.
An n-type active layer 12 with a uniform thickness is formed on the surface of a semi-insulating semiconductor substrate 110 by epitaxial growth or ion implantation.
After forming the active layer, a source electrode 18, a train electrode 14, and a Schottkycate electrode 15 are formed by a method such as vapor deposition of metal on the surface of this active layer. It is known that in a Schottky gate field effect transistor having such a conventional structure, if the gate-source resistance is large, the microwave characteristics, particularly the noise characteristics, of the transistor deteriorate. In order to improve the microwave characteristics, it is necessary to lower the gate-source resistance, and to achieve this purpose, it is necessary to increase the carrier concentration in the active layer 12 or increase the thickness of the active layer. In either method, the problem arises that the pinch-off voltage becomes excessive. Further, when the carrier concentration is increased, another problem arises in that the breakdown voltage of the gate decreases.

In order to solve this problem, as illustrated in FIG.
A structure has been proposed in which the thickness of the active layer 12'' near the source electrode is increased while maintaining the thickness of the source electrode 18 and the drain voltage [r 1
After forming an active layer with a uniform thickness corresponding to the thickness directly under the gate electrode 15, only the portion 12' that should be directly under the gate electrode 15 is thinned by etching etc., and then each electrode 13.14 is formed.
and 15.

However, in such a structure, not only is it difficult to perform fine photolithography for electrode formation because the surface of the active layer is not flat, but also the yield is low because extremely strict precision is required to control the etching of the active layer. It has the disadvantage of being low.

That is, in order to improve the high frequency characteristics of the MESFET, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in manufacturing the device. but,
In the conventional manufacturing method of the structure shown in FIG. 2, when forming the pattern f of the gate electrode 15 in the resist, a step formed by the source electrode 13 and the drain electrode 14 is created in the vicinity of the gate pattern in the operating area. In addition to the 12 steps, the resolution of the photoresist pattern was lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as about 1 μm. In particular, in compound semiconductors such as GaAs, the gate electrode 15
Before forming the source electrode 13 and the train electrode 14
Generally, alloying is performed to lower the contact resistance, but if the alloying is performed at a sufficiently high temperature and for a long time in order to sufficiently reduce the contact resistance, the source and drain electrode metals will deteriorate. Agglomeration tends to occur and extremely large steps are likely to occur, which also causes deterioration in the resolution of the gate photoresist pattern.

Further, the gate electrode 5 is the source electrode 1 which has already been formed.
3 and the drain 14 with a positional accuracy of ±0.27 rm or less. Furthermore, the distance between the source electrode 8 and the gate electrode 15 is directly influenced by the parasitic resistance and capacitance between the source and gate in the electrical characteristics of the MESFET, so the distance between the two electrodes should be as small as possible. ,
It is also necessary to control with high precision, and the above-mentioned positional precision is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.

Another effective means of reducing the source resistance is to form a highly impurity-concentrated n-soil layer under the source electrode 18, but in order for this method to be sufficiently effective, the n-soil layer and gate The distance between the electrode and the electrode needs to be sufficiently close.

However, with conventional phosphorography techniques, it is difficult to place the n-soil layer and the gate electrode close to each other within 1 μm.

Therefore, as detailed above, it has been desired to develop a method for effectively reducing the source resistance in order to be able to use the device at a higher frequency or to obtain a larger gain.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a Schottky gate field effect transistor with good microwave characteristics and good yield.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 is a cross-sectional view of a short gate field effect transistor according to an embodiment of the present invention, in which 21 is a semi-insulating semiconductor substrate such as GaAs, 22 is an n-type active layer, 23 is a source electrode, and 24 is a drain electrode. , 25 are Schottky gate electrodes. As illustrated in FIG. 3, the field effect transistor of the present invention has a flat surface of the active layer, and the thickness of the active layer 22'' between the source and drain is the same as that of the active layer 22' directly below the gate.
thickness.

2, the gate electrode 25 is located precisely in the part of the active layer 22' that determines the pinch-off voltage, and
5 has no overlap with the active layer 22''.

In addition, the n-soil layers 2Q and 27 are on both sides of the gate electrode.
．． It is formed in the vicinity of about 5 μm.

As mentioned above, in the Schottky gate field effect transistor according to the present invention, the gate electrode 25 and the source electrode 23
The thick active layer 22' and the n-soil layer 26 are provided between the n-soil layer 26 and the gate electrode, and the n-soil layer 26 and the gate electrode are formed sufficiently close to each other, e.g., about 0.5 μm, so that the source resistance is reduced and a good It is characterized by having high frequency characteristics.

FIG. 4 is a cross-sectional view showing an example of a method for manufacturing the field effect transistor shown in FIG. 3.

First, as shown in FIG. 4 (6), a value is selected to realize the semi-insulating property of GaAs. For example, pinch-off voltage 0.
In order to realize 2■, the carrier concentration is 1 ol'lClF
It is necessary to form an active layer with a thickness of about 3 and a thickness of about 0.1 μm, and the conditions for ion implantation include an implantation energy of 120K.
eV, and the implantation amount is 2 x 1012'dos/cm" (assuming the activation rate is 100%). The theoretical value of the carrier concentration distribution obtained under these conditions is shown at one point in Figure 5. It is shown by a chain line 81.

FIG. 4(g))K As shown in the example, after forming the active layer 22' with a uniform thickness, a metal having a high melting point and not easily reacting with GaAs, such as Ti%Ta, W%V, Nb, is formed on the active layer 22'.
, M.

Alternatively, these alloys 25 are deposited, and a photoresist pattern 28 is further formed thereon.

The metal pattern 25 is etched using the resist 28 as a mask, and the metal pattern 25 is formed under the metal pattern 28 by side etching, as illustrated in FIG. 4(C). After this, a second ion implantation is performed using the resist pattern 28 as a mask to form a 1/Cn soil layer gap 27 in the unmasked area.

Thereafter, the resist 28 is removed, and a third ion implantation is performed using the pattern 25 as a mask as shown in FIG. The conditions for implantation are that the implantation energy is higher than the first time in order to implant deeper than the first time, and the implantation amount is set to a value such that the final peak carrier concentration does not become excessive compared to the first peak carrier concentration. This is to prevent dielectric breakdown from occurring due to the voltage applied to the gate, and to prevent the gate capacitance from becoming excessive.An example of such an implantation condition is The theoretical value of the carrier density distribution when the energy is 400 KeV and the implantation amount is 8.9×1012 dose Δ- is illustrated by the dotted line 32 in FIG. The concentration of the unimplanted portion 22'' is the sum of the concentration resulting from the first ion implantation and the concentration resulting from the eighth ion implantation, and its distribution is illustrated by the solid line 33 in FIG.

As is clear from FIG. 5, the total number of carriers in the active layer 22'' between the n-soil layer 26 or 27 and the active layer 22' is smaller than the total number of carriers in the active layer 22' directly below the gate electrode 25. Therefore, the gate-source resistance is reduced to about one-eighth compared to when the active layer 22' is uniformly formed.On the other hand, the maximum carrier concentration in the active layer 22'' is Since the increase is only about 13% compared to the value within 22', the associated increase in reverse breakdown voltage of the gate and increase in gate capacitance remain extremely small.

Next, the implanted element is activated by annealing, and n
By forming the source electrode field and the drain electrode 24 at predetermined positions on the soil layers 26 and 27, a transistor having the structure shown in FIG. 8 is completed.

As is clear from the above explanation, the MESFE in the present invention
T is characterized in that the gate electrode 25 is formed in proper alignment over the active layer 22', and this advantage will be described in detail below.

To explain the relationship between the length of the active layer 22' and the length of the gate electrode 25, in a normally-on type where the active layer 22' is relatively thick, the length of the active layer 22' is somewhat longer than the length of the gate electrode 25. However, sufficient characteristics can be obtained for practical use. This is because the active layer 22' is relatively thick, so the thickness of the depletion layer that spreads from the surface into the inside of the device does not account for the entire thickness of the active layer 22'. This is because the problem of extremely increasing source-to-source resistance does not occur. On the other hand, in a normally-off type in which the thickness of the depletion layer from the surface occupies the entire thickness of the active layer 22', the length of the active layer 22' is the same as that of the gate electrode 22'.
If the length is larger than the length, a depletion layer will be formed to the full thickness in the active layer 22' except for the part directly below the gate, and as a result, the gate-source resistance will become significantly large, and in extreme cases, the current will be completely reduced. The problem arises that it is blocked by

Therefore, in the normally-off type, the length of the gate electrode 25 must be longer than the operating layer 22'. However, in the overlapping portion of the gate electrode 25 and the active layer 22'', that is, in the gate electrode 25, the active layer 22'
A portion that is longer than the capacitance simply increases the capacitance and has no effective effect. Therefore, it is effective to shorten this portion as much as possible in order to increase the operating speed of the element. be.

That is, ideally, as illustrated in FIG. 8, it is an effective means to form the length of the gate electrode 25 and the length of the active layer 22' to be equal, especially in the normally-off type.

In the present invention, by performing ion implantation using the pattern 25 as a mask, 22'
Since the length of the gate electrode 25 and the length of the gate electrode 25 are equal and are formed at the same position, normally-off characteristics are significantly improved.

In addition, a working layer 22'' located between the first layer and the working layer 22'
The shorter the length, the smaller the series resistance between the gate and source, which is advantageous in terms of characteristics, but in the present invention, this length is determined by the difference in reduction between patterns 25 and 28 in FIG. It is possible to make the amount as small as about 0.5 μm.

As explained in detail above, the Schottky gate field effect transistor of the present invention has a thick active layer between the gate and source, the carrier concentration is almost constant throughout the entire active layer, and the active layer directly below the gate electrode and the gate electrode are Since the structure is formed at the same location, high frequency characteristics are good.
A Schottky gate field effect transistor with a high gate reverse breakdown voltage and a good yield can be realized through a simpler process than the conventional one.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a conventional example, FIG. 3 is a cross-sectional view of an embodiment of the present invention, and FIGS. FIG. 5 is a carrier concentration distribution diagram in the active layer of the field effect transistor shown in FIG. 3. 21... Semi-insulating semiconductor substrate, 22... Operating layer, 2
2'... First part of the active layer, 22''... Second part of the active layer, 23... Source electrode, 24... Drain electrode, 25... Gate electrode, 26.27・・・
n Soil layer, 28...Resist 1r1 Figure 2 Figure 7t3 Figure 22 (A')

Claims (1)

[Claims] (1) A Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a Schottky gate electrode, and a drain electrode formed on the active layer; a first portion formed directly under the gate electrode with an impurity concentration and thickness that provides a predetermined pinch-off voltage in the active layer; and an impurity concentration that is approximately equal to the impurity concentration in the first portion. and a second portion having a thickness greater than the thickness of the first portion, and a gate electrode is formed at the same position and the same length as the first active layer portion, and the gate electrode is formed at the same position and the same length as the first active layer portion. A Schottky gate field effect transistor characterized by having active layers with high impurity concentration near the gate electrode on both sides of the electrode.