JPS5879770A - Schottky gate field-effect transistor - Google Patents
Schottky gate field-effect transistorInfo
- Publication number
- JPS5879770A JPS5879770A JP17853581A JP17853581A JPS5879770A JP S5879770 A JPS5879770 A JP S5879770A JP 17853581 A JP17853581 A JP 17853581A JP 17853581 A JP17853581 A JP 17853581A JP S5879770 A JPS5879770 A JP S5879770A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- active layer
- gate
- electrode
- thickness
- Prior art date
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- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract 5
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 238000002844 melting Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000002689 soil Substances 0.000 description 11
- 238000002513 implantation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はマイクロ波特性が良好でしかも製造が容易なシ
ョットキゲート電界効果トランジスタに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky gate field effect transistor that has good microwave characteristics and is easy to manufacture.
本発明は、材料については何ら制限されるものではなく
、Ｓｔ などの単元素半導体あるいは化合物半導体など
広く一般の半導体材料に適用できるものであるが、以下
半導体材料として動作速度の大きい利点をもつ化合物半
導体のうちＧａ Ａｓを例にとって説明を行う。The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as St or compound semiconductors. Explanation will be given by taking GaAs among semiconductors as an example.
従来のショットキゲート電界効果トランジスタの一般的
な構造は、第１図の断面図に例示するように、ＧａＡｓ
なとの半絶縁性半導体基板１１０表面にエピタキシャル
成長やイオン注入によって一様な厚さのｎ型動作層１２
を形成したのち、この動作層の表面に金属を蒸着させる
方法等によりソース電極１８、トレイン電極１４及びシ
ョットキケート電極１５を形成したものである。このよ
うな従来構造のショットキゲート電界効果トランジスタ
においては、ゲート・ソース間抵抗が大きいと、このト
ランジスタのマイクロ波特性、特に雑音特性が劣化する
ことが知られている。マイクロ波特性を改良するにはゲ
ート・ソース間抵抗を下げることが必要であり、この目
的を達成するには動作層１２のキャリア濃度を高めるか
又は動作層を厚くすることが必要であるが、いずれの方
法においてもピンチオフ電圧が過大になるという問題を
生ずる。また、キャリア濃度を高めた場合にはゲートの
耐圧が小さくなるという問題がさらに生ずる。The general structure of a conventional Schottky gate field effect transistor is made of GaAs, as illustrated in the cross-sectional view of FIG.
An n-type active layer 12 with a uniform thickness is formed on the surface of a semi-insulating semiconductor substrate 110 by epitaxial growth or ion implantation.
After forming the active layer, a source electrode 18, a train electrode 14, and a Schottkycate electrode 15 are formed by a method such as vapor deposition of metal on the surface of this active layer. It is known that in a Schottky gate field effect transistor having such a conventional structure, if the gate-source resistance is large, the microwave characteristics, particularly the noise characteristics, of the transistor deteriorate. In order to improve the microwave characteristics, it is necessary to lower the gate-source resistance, and to achieve this purpose, it is necessary to increase the carrier concentration in the active layer 12 or increase the thickness of the active layer. In either method, the problem arises that the pinch-off voltage becomes excessive. Further, when the carrier concentration is increased, another problem arises in that the breakdown voltage of the gate decreases.
このような問題を解決するため、第２図に例示するよう
に１ピンチオフ電圧を支配するゲート直下の動作層１２
’の厚みを所望値に保ったまま、ソース電極近傍の動作
層１２″の厚みを大きくする構造が提案されている。こ
の構造は、まずソース電極１８及びドレイン電［ｒ １
４直下の厚みに相当する一様な厚みの動作層を形成した
のち、ゲート電極１５の直下となるべき箇所１２’のみ
をエツチング等により薄くしたのち、各電極１３．１４
及び１５を形成している。In order to solve this problem, as illustrated in FIG.
A structure has been proposed in which the thickness of the active layer 12'' near the source electrode is increased while maintaining the thickness of the source electrode 18 and the drain voltage [r 1
After forming an active layer with a uniform thickness corresponding to the thickness directly under the gate electrode 15, only the portion 12' that should be directly under the gate electrode 15 is thinned by etching etc., and then each electrode 13.14 is formed.
and 15.
しかしながらこのような構造では、動作層表面カ平担で
ないから電極形成のための微細なホトリソグラフィ等が
困難であるばかりでなく、動作層のエツチング制御に極
めて厳しい精度が要求されるために歩留りが低くなって
しまう欠点がある。However, in such a structure, not only is it difficult to perform fine photolithography for electrode formation because the surface of the active layer is not flat, but also the yield is low because extremely strict precision is required to control the etching of the active layer. It has the disadvantage of being low.
即ち、ＭＥＳＦＥＴの高周波特性を向上させるためには
、ゲート長を極力小さくする必要があり、そのために素
子製作上極めて微細な精密加工が要求される。しかし、
第２図のような構造のものの従来の製造方法においては
、ゲート電極１５のパターンｆレジストに形成する際に
、そのゲートパターンの極く近傍にソース電極１３およ
びドレイン電極１４による段差が、動作領域１２の段差
に加えて存在するため、平担面におけるときよりもフォ
トレジストパターンの解像度が低下し、１μｍ程度の短
いゲートパターンを確実に形成することが困難であった
。特にＧａＡｓ等の化合物半導体では、ゲート電極１５
を形成する前にソース電極１３おヨヒトレイン電極１４
の合金処理を行なって、その接触抵抗の低下を図ること
が一般に行なわれているが、接触抵抗を充分小さくしよ
うとして充分な高温で、しかも長時間の合金処理を行な
うとソース、ドレイン電極金属の凝集がおこり、著しく
大きな段差が生じ易く、このこともゲート用フォトレジ
ストパターンの解像度を悪化させる原因になっている。That is, in order to improve the high frequency characteristics of the MESFET, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in manufacturing the device. but,
In the conventional manufacturing method of the structure shown in FIG. 2, when forming the pattern f of the gate electrode 15 in the resist, a step formed by the source electrode 13 and the drain electrode 14 is created in the vicinity of the gate pattern in the operating area. In addition to the 12 steps, the resolution of the photoresist pattern was lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as about 1 μm. In particular, in compound semiconductors such as GaAs, the gate electrode 15
Before forming the source electrode 13 and the train electrode 14
Generally, alloying is performed to lower the contact resistance, but if the alloying is performed at a sufficiently high temperature and for a long time in order to sufficiently reduce the contact resistance, the source and drain electrode metals will deteriorate. Agglomeration tends to occur and extremely large steps are likely to occur, which also causes deterioration in the resolution of the gate photoresist pattern.
また、ゲート電極５は既に形成されているソース電極１
３とドレイン１４の中間に±０．２７ｒｍ以下の位置精
度で形成する必要がある。さらにソース電極８とゲート
電極１５の間隔は、ＭＥ Ｓ Ｆ ＥＴの電気的特性に
あって、ソース・ゲート間の寄生抵抗、寄生容量にて直
接影響するので、両電極間の距離はできる限り小さく、
かつ高精度に制御する必要があり、上述の位置精度はこ
の電極間距離の点でも必要となる。しかしこの様な微細
パターンを高精度で形成することは、従来の技術では極
めて困難であり、従って製造歩留りが著しく低いという
問題点があった。Further, the gate electrode 5 is the source electrode 1 which has already been formed.
3 and the drain 14 with a positional accuracy of ±0.27 rm or less. Furthermore, the distance between the source electrode 8 and the gate electrode 15 is directly influenced by the parasitic resistance and capacitance between the source and gate in the electrical characteristics of the MESFET, so the distance between the two electrodes should be as small as possible. ,
It is also necessary to control with high precision, and the above-mentioned positional precision is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.
ソース抵抗を低減する他の一つの有力な手段はソース電
極１８の下部に高不純物濃度ｎ土層を形成することであ
るが、この方法が充分に有効であるためには、ｎ土層と
ゲート電極との間隔は十分に近接している必要がある。Another effective means of reducing the source resistance is to form a highly impurity-concentrated n-soil layer under the source electrode 18, but in order for this method to be sufficiently effective, the n-soil layer and gate The distance between the electrode and the electrode needs to be sufficiently close.
しかしながら従来のリングラフィ技術では、ｎ土層とゲ
ート電極とを１μｍ以下に近接することは困難であった
。However, with conventional phosphorography techniques, it is difficult to place the n-soil layer and the gate electrode close to each other within 1 μm.
このため以上に詳述したようにより高い周波数で使用可
能な、あるいはより大きな利得を得るため、ソース抵抗
の効果的な低減法の開発が望まれていた。Therefore, as detailed above, it has been desired to develop a method for effectively reducing the source resistance in order to be able to use the device at a higher frequency or to obtain a larger gain.
本発明は上述した従来の問題点に鑑みてなされたもので
あり、その目的とするところは、マイクロ波特性及び歩
留りが良好なショットキゲート電界効果トランジスタを
提供することにある。The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a Schottky gate field effect transistor with good microwave characteristics and good yield.
以下本発明の詳細を実施例によって説明する。The details of the present invention will be explained below with reference to Examples.
第３図は本発明の一実施例のショーツトキゲート電界効
果トランジスタの断面図であり、２１はＧａＡｓなどの
半絶縁性半導体基板、２２はｎ型動作層、２３はソース
電極、２４はドレイン電極、２５はショットキゲート電
極である。本発明の電界効果トランジスタは第３図に例
示するように、動作層表面が平担でかつソース・ドレイ
ン間の動作層２２″の厚さをゲート直下の動作層２２′
の厚さ。FIG. 3 is a cross-sectional view of a short gate field effect transistor according to an embodiment of the present invention, in which 21 is a semi-insulating semiconductor substrate such as GaAs, 22 is an n-type active layer, 23 is a source electrode, and 24 is a drain electrode. , 25 are Schottky gate electrodes. As illustrated in FIG. 3, the field effect transistor of the present invention has a flat surface of the active layer, and the thickness of the active layer 22'' between the source and drain is the same as that of the active layer 22' directly below the gate.
thickness.
よりも大きくした構造で、ゲート電極２５はピンチオフ
電圧を決定する動作層２２′の部分に正確に位置し、２
５は動作層２２″とは重なりを有しない。2, the gate electrode 25 is located precisely in the part of the active layer 22' that determines the pinch-off voltage, and
5 has no overlap with the active layer 22''.
またｎ土層２Ｑ、２７がゲート電極をはさんで両側に０
．５μｍ程度の近傍に形成せられている。In addition, the n-soil layers 2Q and 27 are on both sides of the gate electrode.
．． It is formed in the vicinity of about 5 μm.
上述のように、本発明によるショットキゲート電界効果
トランジスタでは、ゲート電極２５ とソース電極２３
との間に厚い動作層２２′とｎ土層２６とが設けられか
つ、ｎ土層２６とゲート電極は、例えば０．５μｍ程度
に充分近傍に形成せられるためソース抵抗が低減し、良
好な高周波特性を有するのが特徴である。As mentioned above, in the Schottky gate field effect transistor according to the present invention, the gate electrode 25 and the source electrode 23
The thick active layer 22' and the n-soil layer 26 are provided between the n-soil layer 26 and the gate electrode, and the n-soil layer 26 and the gate electrode are formed sufficiently close to each other, e.g., about 0.5 μm, so that the source resistance is reduced and a good It is characterized by having high frequency characteristics.
第４図は、第３図の電界効果トランジスタの製造方法の
一例を示す断面図である。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing the field effect transistor shown in FIG. 3.
まず第４図（６）に示すように、ＧａＡｓの半絶縁性を
実現する値に選択される。例えば、ピンチオフ電圧０．
２■を実現するために、キャリア濃度１ｏｌ′ｌＣｌＦ
３程度、厚み０．１μｍ程度の動作層を形成する必要が
あり、イオン注入の条件として、注入エネルギ１２０Ｋ
ｅＶ 、注入量２Ｘ１０１２’ド一ズ／ｃｍ” （ただ
し活性率を１００％とする。）が選択される。このよう
な条件のもとに得られるキャリア濃度分布の理論値を第
５図の一点鎖線８１で示す。First, as shown in FIG. 4 (6), a value is selected to realize the semi-insulating property of GaAs. For example, pinch-off voltage 0.
In order to realize 2■, the carrier concentration is 1 ol'lClF
It is necessary to form an active layer with a thickness of about 3 and a thickness of about 0.1 μm, and the conditions for ion implantation include an implantation energy of 120K.
eV, and the implantation amount is 2 x 1012'dos/cm" (assuming the activation rate is 100%). The theoretical value of the carrier concentration distribution obtained under these conditions is shown at one point in Figure 5. It is shown by a chain line 81.
第４図（ト））Ｋ例示するように、一様な厚みの動作層
２２′を形成したのち、その上に高融点でＧａＡｓと反
応しにくい金属、例えばＴｉ％Ｔａ、 Ｗ％Ｖ、 Ｎｂ
、 Ｍ。FIG. 4(g))K As shown in the example, after forming the active layer 22' with a uniform thickness, a metal having a high melting point and not easily reacting with GaAs, such as Ti%Ta, W%V, Nb, is formed on the active layer 22'.
, M.
あるいはこれらの合金２５を蒸着し、さらにその上部に
フォトレジストパターン２８を形成する。Alternatively, these alloys 25 are deposited, and a photoresist pattern 28 is further formed thereon.
このレジスト２８をマスクに用いて金属２５をエツチン
グし、第４図（Ｃ）に例示したように、サイドエッチに
より２８よりも縮少された金属パターン２５を２８の下
に形成する。かかる後にレジストパターン２８をマスク
として用いて第２回目のイオン注入を行い、マスクされ
ない箇所１／Ｃｎ土層飢２７を形成する。The metal pattern 25 is etched using the resist 28 as a mask, and the metal pattern 25 is formed under the metal pattern 28 by side etching, as illustrated in FIG. 4(C). After this, a second ion implantation is performed using the resist pattern 28 as a mask to form a 1/Cn soil layer gap 27 in the unmasked area.
その後レジスト２８を除去し、第４図０）に示したよう
にパターン２５をマスクとして用いて３回目のイオン注
入を行い、マスクされない箇所に新たな動作層２２″を
形成する。８回目のイオン注入の条件としては、１回目
よりも深く注入するために注入エネルギが１回目のもの
よりも大きく、かつ注入量は最終ピークキャリア濃度が
１回目のピークキャリア濃度に比べて過大にならないよ
うな値に選択される。これはゲートに印加される電圧に
よって絶縁破壊が生じないようにするためであり、また
ゲートキャパシタンスが過大とならないようにするため
である。このような注入条件の一例として、注入エネル
ギを４００ＫｅＶ 、注入量を８．９Ｘ１０１２ドーズ
Δ−の値に選択した場合のキャリア密度分布の理論値を
第５図の点線３２で例示する。動作層２２内のマスクさ
れない部分のうち第２回目の注入がなされていない部分
２２″の濃度は１回目のイオン注入による濃度に８回目
のイオン注入による濃度を加算した値となり、その分布
は第５図の実線３３で例示される。Thereafter, the resist 28 is removed, and a third ion implantation is performed using the pattern 25 as a mask as shown in FIG. The conditions for implantation are that the implantation energy is higher than the first time in order to implant deeper than the first time, and the implantation amount is set to a value such that the final peak carrier concentration does not become excessive compared to the first peak carrier concentration. This is to prevent dielectric breakdown from occurring due to the voltage applied to the gate, and to prevent the gate capacitance from becoming excessive.An example of such an implantation condition is The theoretical value of the carrier density distribution when the energy is 400 KeV and the implantation amount is 8.9×1012 dose Δ- is illustrated by the dotted line 32 in FIG. The concentration of the unimplanted portion 22'' is the sum of the concentration resulting from the first ion implantation and the concentration resulting from the eighth ion implantation, and its distribution is illustrated by the solid line 33 in FIG.
第５図から明らかなように、ｎ土層２６ または２７と
動作層２２′との間の動作層２２″内のキャリア総数は
ゲート電極２５の直下の動作層２２′内のキャリア総数
に比べて約８倍大きく、そのためゲート・ソース間抵抗
は動作層２２′が一様に形成される場合に比べて約８分
の１に低下する。一方、動作層２２″内の最大キャリア
濃度は動作層２２′内の値に比べて約１３％増加しただ
けであるから、これに伴なうゲートの逆耐圧の増加およ
びゲートキャパシタンスの増加は極めてわずかな量にと
どまる。As is clear from FIG. 5, the total number of carriers in the active layer 22'' between the n-soil layer 26 or 27 and the active layer 22' is smaller than the total number of carriers in the active layer 22' directly below the gate electrode 25. Therefore, the gate-source resistance is reduced to about one-eighth compared to when the active layer 22' is uniformly formed.On the other hand, the maximum carrier concentration in the active layer 22'' is Since the increase is only about 13% compared to the value within 22', the associated increase in reverse breakdown voltage of the gate and increase in gate capacitance remain extremely small.
次いで、アニールにより注入元素の活性化を行ない、ｎ
土層２６．２７上の所定位置にソース電極田、ドレイン
電極２４を形成することにより第８図の構造のトランジ
スタが出来上る。Next, the implanted element is activated by annealing, and n
By forming the source electrode field and the drain electrode 24 at predetermined positions on the soil layers 26 and 27, a transistor having the structure shown in FIG. 8 is completed.
以上の説明で明らかなように本発明におけるＭＥＳＦＥ
Ｔではゲート電極２５は動作層２２′の上部に正しく位
置合わせされて形成されているのが特徴であるが、以下
にこの利点につき詳細する。As is clear from the above explanation, the MESFE in the present invention
T is characterized in that the gate electrode 25 is formed in proper alignment over the active layer 22', and this advantage will be described in detail below.
動作層２２′の長さとゲート電極２５の長さの関係を説
明すれば、動作層２２′が比較的厚いノーマリオン型に
おいては、動作層２２′の長さがゲート電極２５の長さ
より多少長くても実用上十分な特性が得られる。これは
、動作層２２′が比較的厚いため表面から素子内部に拡
がっている空乏層の厚みが動作層２２′の全厚みを占め
ず、従って動作層２２′のゲート直下を除く部分がゲー
ト・ソース間抵抗を極端に増大させるような問題を生じ
ないからである。これに対して、表面からの空乏層厚み
が動作層２２′の厚みの全体を占めるようなノーマリオ
フ型においては、動作層２２′の長さがゲート電極２５
の長さより大であれば、動作層２２′のゲート直下を除
く部分において空乏層が厚み方向一杯に形成され、この
結果ゲート・ソース間抵抗が著じるしく大となり、極端
な場合電流が完全に阻止されるという問題が生ずる。To explain the relationship between the length of the active layer 22' and the length of the gate electrode 25, in a normally-on type where the active layer 22' is relatively thick, the length of the active layer 22' is somewhat longer than the length of the gate electrode 25. However, sufficient characteristics can be obtained for practical use. This is because the active layer 22' is relatively thick, so the thickness of the depletion layer that spreads from the surface into the inside of the device does not account for the entire thickness of the active layer 22'. This is because the problem of extremely increasing source-to-source resistance does not occur. On the other hand, in a normally-off type in which the thickness of the depletion layer from the surface occupies the entire thickness of the active layer 22', the length of the active layer 22' is the same as that of the gate electrode 22'.
If the length is larger than the length, a depletion layer will be formed to the full thickness in the active layer 22' except for the part directly below the gate, and as a result, the gate-source resistance will become significantly large, and in extreme cases, the current will be completely reduced. The problem arises that it is blocked by
従ってノーマリオフ型においては、ゲート電極２５の長
さが動作層２２′よりも大きくなければならない。しか
しながらゲート電極２５ と、動作層２２″との重なり
部分、すなわちゲート電極２５において、動作層２２′
よりも長さが過大となる部分は、単に静電容量を増大す
るのみで有効な作用をしないので、この過大部分を可能
な限り短くすることが、素子の動作速度を速くする上で
有効である。Therefore, in the normally-off type, the length of the gate electrode 25 must be longer than the operating layer 22'. However, in the overlapping portion of the gate electrode 25 and the active layer 22'', that is, in the gate electrode 25, the active layer 22'
A portion that is longer than the capacitance simply increases the capacitance and has no effective effect. Therefore, it is effective to shorten this portion as much as possible in order to increase the operating speed of the element. be.
すなわち、理想的には第８図に例示するように、ゲート
電極２５の長さと動作層２２′の長さを等しく形成する
ことが特にノーマリオフ型においては有効な手段である
。That is, ideally, as illustrated in FIG. 8, it is an effective means to form the length of the gate electrode 25 and the length of the active layer 22' to be equal, especially in the normally-off type.
本発明においてはパターン２５ をマスクに用いてイ
オン注入を行うことにより七ルファラインにより２２′
の長さと、ゲート電極２５の長さが等しく、かつ同一位
置に形成されるため、ノーマリオフ型の特性が著しく向
上するものである。In the present invention, by performing ion implantation using the pattern 25 as a mask, 22'
Since the length of the gate electrode 25 and the length of the gate electrode 25 are equal and are formed at the same position, normally-off characteristics are significantly improved.
また１層と動作層２２′との間に位置する動作層２２″
の長さは、短いほどゲート・ソース間の直列抵抗が小さ
くなって特性上有利であるが、本発明においては、この
長さは第４図（Ｃ）のパターン２５と２８ との縮小差
によって定まり、０．５μｍ程度の微小量とすることが
可能である。In addition, a working layer 22'' located between the first layer and the working layer 22'
The shorter the length, the smaller the series resistance between the gate and source, which is advantageous in terms of characteristics, but in the present invention, this length is determined by the difference in reduction between patterns 25 and 28 in FIG. It is possible to make the amount as small as about 0.5 μm.
以上詳細に説明したように、本発明のショットキゲート
電界効果トランジスタはゲート−ソース間の動作層が厚
く、キャリア濃度は動作層全体にわたってほぼ一定であ
り、しかもゲート電極直下の動作層とゲート電極が同一
位置に形成される構造であるから、高周波特性が良く、
ゲート逆耐圧が高く、かつ歩留りの良好なショットキゲ
ート電界効果トランジスタを従来より簡便な工程で実現
することができる。As explained in detail above, the Schottky gate field effect transistor of the present invention has a thick active layer between the gate and source, the carrier concentration is almost constant throughout the entire active layer, and the active layer directly below the gate electrode and the gate electrode are Since the structure is formed at the same location, high frequency characteristics are good.
A Schottky gate field effect transistor with a high gate reverse breakdown voltage and a good yield can be realized through a simpler process than the conventional one.
第１図、第２図は従来例の断面図、第３図は本発明の一
実施例の断面図、第４図（Ａ）〜ｐ）は第３図の電界効
果トランジスタの製造方法の一例を示す断面図、第５図
は第３図の電界効果トランジスタの動作層内のキャリア
濃度分布図である。
２１ ・・半絶縁性半導体基板、２２・・動作層、２
２′・・・動作層の第１の部分、２２″・・・動作層の
第２の部分、２３・・・ソース電極、２４・・・ドレイ
ン電極、２５ ・・・ゲート電極、２６．２７ ・・
ｎ土層、２８・・・レジスト１ｒ１図
方２図
７ｔ３図
２２
（Ａ’）1 and 2 are cross-sectional views of a conventional example, FIG. 3 is a cross-sectional view of an embodiment of the present invention, and FIGS. FIG. 5 is a carrier concentration distribution diagram in the active layer of the field effect transistor shown in FIG. 3. 21... Semi-insulating semiconductor substrate, 22... Operating layer, 2
2'... First part of the active layer, 22''... Second part of the active layer, 23... Source electrode, 24... Drain electrode, 25... Gate electrode, 26.27・・・
n Soil layer, 28...Resist 1r1 Figure 2 Figure 7t3 Figure 22 (A')
Claims (1)
された動作層ならびに該動作層上に形成されたソース電
極、ショットキゲート電極、及びドレイン電極を備えた
ショットキゲート電界効果トランジスタにおいて、前記
動作層で所定のピンチオフ電圧を与えるような不純物濃
度と厚みを有して前記ゲート電極直下に形成されている
第１の部分と、該第１の部分内の不純物濃度と略々等し
い不純物濃度を有しかつ該第１の部分の厚みよりも大き
な厚みを有する第２の部分とから構成されており、かつ
ゲート電極が第１の動作層部分と同位置に同一の長さで
形成され、ゲート電極を介して両側にゲート電極近傍に
高不純物濃度の動作層を具備したことを特徴とするショ
ットキゲート電界効果トランジスタ(1) A Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a Schottky gate electrode, and a drain electrode formed on the active layer; a first portion formed directly under the gate electrode with an impurity concentration and thickness that provides a predetermined pinch-off voltage in the active layer; and an impurity concentration that is approximately equal to the impurity concentration in the first portion. and a second portion having a thickness greater than the thickness of the first portion, and a gate electrode is formed at the same position and the same length as the first active layer portion, and the gate electrode is formed at the same position and the same length as the first active layer portion. A Schottky gate field effect transistor characterized by having active layers with high impurity concentration near the gate electrode on both sides of the electrode.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17853581A JPS5879770A (en) | 1981-11-06 | 1981-11-06 | Schottky gate field-effect transistor |
| EP82300499A EP0057605B1 (en) | 1981-01-29 | 1982-01-29 | A schottky-barrier gate field effect transistor and a process for the production of the same |
| DE8282300499T DE3273695D1 (en) | 1981-01-29 | 1982-01-29 | A schottky-barrier gate field effect transistor and a process for the production of the same |
| US06/361,070 US4601095A (en) | 1981-10-27 | 1982-03-23 | Process for fabricating a Schottky-barrier gate field effect transistor |
| CA000401059A CA1184320A (en) | 1981-10-27 | 1982-04-15 | Schottky-barrier gate field effect transistor and a process for the production of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17853581A JPS5879770A (en) | 1981-11-06 | 1981-11-06 | Schottky gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5879770A true JPS5879770A (en) | 1983-05-13 |
Family
ID=16050168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17853581A Pending JPS5879770A (en) | 1981-01-29 | 1981-11-06 | Schottky gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5879770A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857975A (en) * | 1986-08-15 | 1989-08-15 | Nec Corporation | GaAs field effect transistor having a WSi Schottky gate electrode improved for high-speed operation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425171A (en) * | 1977-07-27 | 1979-02-24 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| JPS5646562A (en) * | 1979-09-25 | 1981-04-27 | Sony Corp | Semiconductor device |
-
1981
- 1981-11-06 JP JP17853581A patent/JPS5879770A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425171A (en) * | 1977-07-27 | 1979-02-24 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| JPS5646562A (en) * | 1979-09-25 | 1981-04-27 | Sony Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857975A (en) * | 1986-08-15 | 1989-08-15 | Nec Corporation | GaAs field effect transistor having a WSi Schottky gate electrode improved for high-speed operation |
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