JPS60101974A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60101974A JPS60101974A JP20937683A JP20937683A JPS60101974A JP S60101974 A JPS60101974 A JP S60101974A JP 20937683 A JP20937683 A JP 20937683A JP 20937683 A JP20937683 A JP 20937683A JP S60101974 A JPS60101974 A JP S60101974A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- gaas
- resistance
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 15
- 238000005036 potential barrier Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 125000005842 heteroatom Chemical group 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 45
- 238000010586 diagram Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、縦型ＦＥＴあるいは静電誘導トランジスタ（
ＳＩＴ ）と呼ばれる素子構造を用いて特に順方向のダ
ート電圧を印加して動作をさせる場合に有用な半導体装
置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a vertical FET or a static induction transistor (
The present invention relates to a semiconductor device which is particularly useful when operated by applying a forward dart voltage using an element structure called SIT.
第１図は縦型ＦＥＴの一例の断面構造を示している。１
ノはｎ＋ｌ’レイン層、１２は高抵抗ｎ一層、１３はｎ
＋ソース層であり、ｎ一層１２内に格子状にｐ＋ベース
層１４が埋設されている。FIG. 1 shows a cross-sectional structure of an example of a vertical FET. 1
No is an n+l' rain layer, 12 is a high resistance n single layer, and 13 is an n layer.
This is a + source layer, and a p+ base layer 14 is buried in the n layer 12 in a lattice pattern.
この素子を例えばノーマリ・オン型とした場合、ケ゛−
ト・ソース間に逆バイアスを印加してダート層１４で挾
まれたチャネル領域の電流を絞ることにより、トランジ
スタ動作が行なわれる。For example, if this element is a normally-on type,
A transistor operation is performed by applying a reverse bias between the source and source to narrow the current in the channel region sandwiched by the dirt layer 14.
ところでこの縦型ＦＥＴにおいて、ケゝ−ト・ソース間
に順方向バイアスを与えると１、オン抵抗が著しく低下
することが知られている。しかしながら、ゲート・ソー
ス間にその接合のビルトイン電圧以上の深い順方向バイ
アスを与えて動作をさせた場合、ゲート電流が非常に大
きくなって直流電流増幅率ｈＦＥが極端に小さいものと
なる。例えば第１図の素子をＧａＡｓを用いて構成した
場合、ドレイン・ソース間に１〔Ｖ〕を与えてダート・
ン〜ス閤電圧Ｖｇに対するオン抵抗Ｒｏｎとダート電流
Ｉｇの変化を測定すると第２図のようになる。そしてゲ
ート・ノース間電圧がＶｇ＝１．０８（Ｖ）のときｈゆ
をコレクタ電流とダートｒｔ流の比として定義するとｈ
ＦＥ≧２７４テするのに対し、Ｖ、＝１．２（Ｖ〕では
ｈＦＥ；２０にまで低下してしまう。By the way, in this vertical FET, it is known that when a forward bias is applied between the gate and the source, the on-resistance is significantly reduced. However, when operating with a deep forward bias higher than the built-in voltage of the junction between the gate and source, the gate current becomes extremely large and the DC current amplification factor hFE becomes extremely small. For example, if the device shown in Figure 1 is constructed using GaAs, a voltage of 1 [V] is applied between the drain and the source.
When the changes in the on-resistance Ron and the dirt current Ig are measured with respect to the ground voltage Vg, the results are as shown in FIG. When the gate-north voltage is Vg = 1.08 (V), h is defined as the ratio of the collector current to the dirt rt current.
Whereas FE≧274te, when V=1.2 (V), hFE drops to 20.
本発明は上記の点に鑑み、縦型ＦＥＴ構造によシ、十分
高いｈＦＦ、をもちながらよシ低いオン抵抗で動作する
領域を広くすることを可能とした半導体装置を提供する
ことを目的とする。In view of the above points, an object of the present invention is to provide a semiconductor device that has a vertical FET structure, has a sufficiently high hFF, and can widen the operating region with a low on-resistance. do.
本発明は前述の如き縦型ＦＥＴ構造において、ソース層
側に、ダート層からのキャリア注入を抑制するヘテロ接
合を設けたことを特徴としている。The present invention is characterized in that, in the vertical FET structure as described above, a heterojunction is provided on the source layer side to suppress carrier injection from the dirt layer.
本発明は以下のような知見に基づく。縦型ＦＥＴ構造で
ダートに順方向バイアスを与えて動作をさせた場合にオ
ン抵抗が低下する理由は、ソース、ドレイン間の高抵抗
半導体層にダート層から注入された多くの少数キャリア
が蓄積して導電度変調をおとすことによる。これはバイ
ポーラトランジスタにはない動作モードである。The present invention is based on the following findings. The reason that the on-resistance decreases when a vertical FET structure is operated with a forward bias applied to the dart is that many minority carriers injected from the dart layer accumulate in the high-resistance semiconductor layer between the source and drain. by reducing the conductivity modulation. This is an operating mode that bipolar transistors do not have.
この蓄積ギヤリアの（ｉｉ−Ｃは一般に次の式で表わさ
れる。(ii-C of this storage gear) is generally expressed by the following formula.
Ｃ＝ｎＩｅｘｐ （Ｖｇ ） （１）
ｋＴ
ここでｎｌは真性ギヤリア濃度、ｖｇはダート・ソース
間電圧である。高抵抗半導体層が同じ材料であれば（１
）式のｎｉは同じであるから、この条件下でダート・ソ
ース間のビルトイン電圧を高く設計すれば、ケ゛−ト電
流を増やすこと女く高い稲をかけて蓄積キャリア′ｆ＃
Ｃをより大きくすることができる。つ１リゲート電流を
増やすことなくオン抵抗を下げることができる。そして
、高抵抗半導体層を同じ材料としてしかもダート・ソー
ス間のビルトイン電圧を高くするには、ソース層側に禁
制帯幅の広い半導体材料を用いてヘテロ接合を形成すれ
ばよい。C=nIexp (Vg) (1) kT where nl is the intrinsic gearia concentration and vg is the dirt-source voltage. If the high-resistance semiconductor layers are made of the same material (1
) is the same, so if we design the built-in voltage between the dirt and the source to be high under this condition, we can increase the gate current and reduce the accumulated carrier 'f#' by increasing the gate current.
C can be made larger. The on-resistance can be lowered without increasing the gate current. In order to increase the built-in voltage between the dirt and the source while using the same material for the high-resistance semiconductor layer, a heterojunction may be formed on the source layer side using a semiconductor material with a wide forbidden band width.
この場合へテロ接合の位置は、高濃度ソース層と高抵抗
半導体層の間でもよいし、高濃度ソース層の内部でも、
或いは高濃度ソース層に近い高抵抗半導体層内部でもよ
く、要するにダート層からみてソース層側に形成されれ
ばよい。In this case, the position of the heterojunction may be between the high concentration source layer and the high resistance semiconductor layer, or inside the high concentration source layer.
Alternatively, it may be formed inside the high-resistance semiconductor layer near the highly doped source layer, in short, it may be formed on the source layer side when viewed from the dirt layer.
このように形成きれたへテロ接合Ｈ六ゲートからソース
に注入されるキャリアに対して大きなポテンシャル障壁
として働くので、ダート電流を大きくすることなく高い
ゲート・ソース間順方向電圧を印加することを可能とす
る。Since this heterojunction acts as a large potential barrier against carriers injected into the source from the H6 gate, it is possible to apply a high forward voltage between the gate and the source without increasing the dart current. shall be.
本発明によれば、ダート・ソース間順方向電圧を大きく
してもダート電流の増大を抑えることができるので、縦
型ＦＥＴ構造によってダート電圧を順方向として動作を
させた場合に、十分オン抵抗を低くした！ま高いｈＦＥ
を得ることができるダート電圧の上限の値を太きくシ、
シかもさらに蓄積キャリアを大きくすることによってよ
シ低いオン抵抗を実現することができる。According to the present invention, it is possible to suppress the increase in dart current even if the forward voltage between the dart and the source is increased, so when the vertical FET structure is operated with the dart voltage in the forward direction, the on-resistance is sufficient. lowered! High hFE
Increase the upper limit of the dart voltage that can be obtained,
Furthermore, by increasing the amount of stored carriers, even lower on-resistance can be achieved.
第３図はＧａＡｓ −ＧａＡ、ｇＡｓ系を用いた一実施
例の素子構造を示している。これを製造プロセスに従っ
て説明すると、まずドレインとなる一−ＧａＡｓ基板２
ノを用意し、この上にＭｏｃＶＤ法によυ高抵抗のｎ”
−ＧａＡｓ ）脅２２ ｔを成長させる。次に選択的に
ｐ型不純物を′イオン注入して格子状に畝−ＧａＡｓダ
ート層２３全２３し、その上に再びＭＯＣＶＤ法によシ
高抵抗のｎ−−ＧａＡｓ層２２２を成長させる。次に反
応ガス成分を異ならせたＭＯＣＶＤ法によシ高抵抗のｎ
−−ＧａＡＡＡｓ層２４を成長させ、その表面にｎ型不
純物を高濃度にイオン注入してソースとなるｎ” −Ｇ
ａＡＡ’Ａ８層２５を形成する。そ［７てダート層２３
に対するオーミックコンタクトをとるために端部をエツ
チングしてダート層２３を露出させ、ソース電極２６、
ダート電極２７およびドレイン電極２８を形成して完成
する。FIG. 3 shows the structure of an example device using GaAs-GaA, gAs. To explain this according to the manufacturing process, first - GaAs substrate 2, which will become the drain.
Prepare a high-resistance n” on top of it using the MocVD method.
-GaAs) Threat 22 t to grow. Next, p-type impurities are selectively ion-implanted to form the ridge-GaAs dirt layer 23 in a lattice pattern, and a high-resistance n--GaAs layer 222 is grown thereon again by MOCVD. Next, high resistance n
--A GaAAAs layer 24 is grown, and n-type impurities are ion-implanted into the surface at a high concentration to become a source.
An aAA'A8 layer 25 is formed. So [7 dirt layer 23
The ends are etched to expose the dirt layer 23 in order to make ohmic contact with the source electrode 26,
A dart electrode 27 and a drain electrode 28 are formed to complete the process.
この素子においては、ＧａＡｊ？Ａａの禁制帯幅がＱａ
Ａｓのそれより大きいことから、ソース層近傍にヘテロ
接合が形成されている。即ちダート層２３とソースであ
るｎ” −ＧａＡＡｉＡｓ層２５開のバ層上５開は第４
−図に示す如くなり、ソースからダートへの電子注入に
対する。］？テンシャル障壁の高さＥｇ工に比べて、ダ
ートからソースへの正孔注入に対するポテンシャル障壁
の高さＥｇ ２は大きいものとなる。In this element, GaAj? The forbidden band width of Aa is Qa
Since it is larger than that of As, a heterojunction is formed near the source layer. That is, the fifth opening on the dirt layer 23 and the n''-GaAAiAs layer 25 which is the source is the fourth layer.
- for electron injection from the source to the dart, as shown in the figure. ]? The height Eg2 of the potential barrier for hole injection from the dart to the source is larger than the height Eg2 of the potential barrier.
従ってこの素子を、ダート・ソース間に順方向バイアス
を与えて動作させた場合、従来のように大きいダート電
流を流すことなくダート・ソース間電圧をかけることが
でき、低いオン抵抗を維持しなからｈゆの高い動作が可
能となる。Therefore, when this device is operated with a forward bias applied between dart and source, voltage can be applied between dart and source without flowing a large dart current as in the conventional case, and a low on-resistance can be maintained. This enables high-speed operation.
第５図は本発明の別の実施例の素子構造である。第３図
と対応する部分には同一符号を付して詳細な説明は省く
。第３図の実施例と異なる点は、ソースとなるｎ十−Ｇ
ａＡｌＡｓ層２５を選択的に形成していること、および
ゲート電極取出しのためにエツチングする代シに畝ゲー
ト層２３に達する深いｐ＋拡散層２９を形成しているこ
とである。FIG. 5 shows the device structure of another embodiment of the present invention. Portions corresponding to those in FIG. 3 are given the same reference numerals and detailed explanations will be omitted. The difference from the embodiment shown in FIG. 3 is that the source n+-G
The aAlAs layer 25 is selectively formed, and a deep p+ diffusion layer 29 reaching the ridged gate layer 23 is formed instead of etching to take out the gate electrode.
この実施例によっても先の実施例と同様の効果が得られ
ることは明らかである。It is clear that this embodiment also provides the same effects as the previous embodiment.
既に述べたように、ペテロ接合を形成する位置は上記実
施例に限られず、ソース層内部であってもよいし、ソー
ス層と高抵抗層の間であってもよい。即ち第３図でいえ
ば、ｎ−−ＧａＡ７Ａｓ層２４をｎ” −ＧａＡｓ層と
してもよいし、またとのｎ−−Ｇａ／１／Ａｓ層２４が
ない状態としてもよい。As already mentioned, the location where the Peter junction is formed is not limited to the above embodiments, and may be inside the source layer or between the source layer and the high resistance layer. That is, in FIG. 3, the n--GaA7As layer 24 may be an n''-GaAs layer, or the n--Ga/1/As layer 24 may be omitted.
また本発明はＧａＡｓ −ＧａＡｌＡｓ系に限らず他の
化合物半導体を用いて実施することもできる。Furthermore, the present invention is not limited to GaAs-GaAlAs-based semiconductors, but can also be implemented using other compound semiconductors.
第１図は従来の縦型ＦＥＴを示す図、第２図はその特イ
仕を説明するための図、第３図は本発明の一実施例の素
子構造を示す図、第４図はそのケ゛−ト・ソース間のバ
ンド構造を示す図、第５図は他の実Ｍ１１例の素子構造
を示す図である。
２１− ｎ ＧａＡｓ基板（ドレイン層）、２２１゜２
２２ − ｎ−−ＧａＡｓ 層、２ ３ − ｐ＋ −
ＧａＡｓ ケゞ−ト層、２４− ｎ−−ＧａＡｓ基板層
、２５ ・−ｎ＋−ＧａＡｌＡｓ層（ソース層）。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
００．２０．４０．６０．８１．０１．２１．４１．６
Ｖｇ（Ｖ）
第３図
第４図
ｎ”−ＧａＡ４Ａｓ
第５図Fig. 1 is a diagram showing a conventional vertical FET, Fig. 2 is a diagram for explaining its special features, Fig. 3 is a diagram showing an element structure of an embodiment of the present invention, and Fig. 4 is a diagram of the device structure. FIG. 5 is a diagram showing the band structure between the gate and the source, and FIG. 5 is a diagram showing the element structure of another example of actual M11. 21-n GaAs substrate (drain layer), 221°2
22-n--GaAs layer, 23-p+-
GaAs Kate layer, 24-n--GaAs substrate layer, 25--n+-GaAlAs layer (source layer). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 00.20.40.60.81.01.21.41.6
Vg (V) Figure 3 Figure 4 n''-GaA4As Figure 5
Claims (1)
よび高不純物濃度ドレイン層がこの順に接して形成され
、前記高抵抗半導体層内にソース・ドレイン間の電流チ
ャネルを規定する第２導電型のダート層が設けられた半
導体装置において、前記ソース層側に、前記ダート層か
らのキャリア注入に対して高い障壁を形成するヘテロ接
合を設けたことを特徴とする半導体装置。A high impurity concentration source layer, a high resistance semiconductor layer, and a high impurity concentration drain layer of a first conductivity type are formed in contact with each other in this order, and a second conductivity type defines a current channel between the source and the drain in the high resistance semiconductor layer. A semiconductor device provided with a dirt layer, characterized in that a heterojunction forming a high barrier against carrier injection from the dirt layer is provided on the source layer side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20937683A JPS60101974A (en) | 1983-11-08 | 1983-11-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20937683A JPS60101974A (en) | 1983-11-08 | 1983-11-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60101974A true JPS60101974A (en) | 1985-06-06 |
| JPH0210586B2 JPH0210586B2 (en) | 1990-03-08 |
Family
ID=16571893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20937683A Granted JPS60101974A (en) | 1983-11-08 | 1983-11-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60101974A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142873A (en) * | 1986-12-05 | 1988-06-15 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH0482275A (en) * | 1990-01-31 | 1992-03-16 | Res Dev Corp Of Japan | Semiconductor device and manufacture thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223275A (en) * | 1975-08-15 | 1977-02-22 | Hitachi Ltd | Field effect transistor and its manufacturing method |
| JPS56124273A (en) * | 1980-03-04 | 1981-09-29 | Semiconductor Res Found | Semiconductor device |
-
1983
- 1983-11-08 JP JP20937683A patent/JPS60101974A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223275A (en) * | 1975-08-15 | 1977-02-22 | Hitachi Ltd | Field effect transistor and its manufacturing method |
| JPS56124273A (en) * | 1980-03-04 | 1981-09-29 | Semiconductor Res Found | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142873A (en) * | 1986-12-05 | 1988-06-15 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH0482275A (en) * | 1990-01-31 | 1992-03-16 | Res Dev Corp Of Japan | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0210586B2 (en) | 1990-03-08 |
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