JP3256643B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky field effect transistor, and more particularly to a high performance field effect transistor having improved Schottky characteristics.

[0002]

2. Description of the Related Art As shown in FIG. 4A, for example, a conventional Schottky field effect transistor has a high-purity I-type layer on its surface, that is, on the side of a gate metal layer 44 serving as a gate electrode.
An nGaP layer 43 is provided in a thickness range of 100 to 300 mm,
An n-type InGaAs layer 42 serving as a channel is provided therebelow. In FIG. 4A, reference numeral 41 denotes a semi-insulating G
aAs substrate. FIG. 4 is an energy band diagram of the conductor electrons in this Schottky field effect transistor.
It is shown in (b). As is clear from the figure, high purity InGaP
A Schottky barrier height of 0.9 V for layer 43 can be achieved. This is a considerable improvement over the GaAs layer of 0.6-0.8 V, but is still not a satisfactory barrier height. In addition, as this conventional technology,
For example, “Self-Aligned InGaP / InG” by the present inventors
aAs / GaAs Heterostructure MESFET Technology for An
alogu-Digital Hybride Type ICs ”GaAs IC Symp.Dig.,
(1994) p.123-.

[0003]

As described above, in the conventional Schottky field effect transistor, the height of the Schottky barrier is not sufficient, and the leakage current from the gate electrode cannot be sufficiently suppressed. There was a problem.

An object of the present invention is to solve the above-mentioned problems in the prior art. In a Schottky field effect transistor, a Schottky barrier is sufficiently increased to suppress a leak current from a gate electrode. It is an object of the present invention to provide a highly efficient field effect transistor having a structure capable of performing the above.

[0005]

In order to achieve the above object, the present invention basically has a structure in which a hetero pn junction is introduced into a Schottky field effect transistor to provide an electron barrier for a band gap. Is what you do. Specifically, the configuration is as described in the claims. That is, the present invention provides a field-effect transistor comprising a compound semiconductor, comprising: a first semiconductor layer having a small electron affinity on a surface side, that is, a gate side; In a semiconductor device having a second semiconductor layer having an electron affinity higher than that of a second semiconductor layer, and the second semiconductor layer is formed of an n-type conductive layer, a part of the surface side of the first semiconductor layer is defined as p The n-type layer and part of the side close to the substrate are formed as an n-type layer. It has a structure to which impurities are added. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first semiconductor layer includes an n-type layer, a p-type layer, an i-type layer, a p-type layer, and an n-type layer. Of the gate. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, a part or the whole of the p-type layer and the n-type layer is constituted by an atomic layer doping layer. is there.

[0006]

According to the present invention, a hetero-pn junction is introduced into a Schottky field-effect transistor to provide a structure capable of providing an electron barrier corresponding to a band gap. Or pn
They differ in that they use bonding. Specifically, the present invention provides a first semiconductor layer having a small electron affinity on the surface side, that is, a gate side, and a second semiconductor layer having a large electron affinity as compared with the first semiconductor layer. In a semiconductor device having a semiconductor layer and the second semiconductor layer including an n-type conductive layer, a part of the surface side of the first semiconductor layer is a p-type layer, and a part of the first semiconductor layer is a part near the substrate. No n-type layer, p
The structure is such that the impurity amount per unit area of the mold layer is the same as the impurity amount per unit area of the n-type layer, and impurities are added so as to be mutually depleted. That is, a hetero pn junction is introduced into a Schottky field effect transistor to obtain an electron barrier corresponding to a band gap. For example, 1.6 V which is a band gap of an InGaP layer is used as an electron barrier. And the leakage current from the gate can be suppressed. Further, since a structure in which neither a hole nor an electron exists in the gate layer is employed, a high-performance Schottky field effect transistor can be realized without adding extra capacitance.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first semiconductor layer is an n-type layer,
The gates of the p-type layer, the i-type layer, the p-type layer, and the n-type layer are configured as gates, and the n-type layer and the p-type layer and the p-type layer and the n-type layer have the same carrier amount in pairs. Therefore, they are mutually depleted, and the carrier does not exist in the i-type layer.
An electron barrier corresponding to the band gap of the mold layer can be ensured, and the thickness of the electron barrier can also be ensured, so that an ideal structure is obtained as the electron barrier. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, a part or the whole of the p-type layer and the n-type layer is an atomic layer doping layer. Since the potential profile in the energy band diagram of the conductor electrons becomes steeper, the effect of suppressing the gate leak current and the improvement of the reverse breakdown voltage can be improved. In addition, the impurity concentration can be extremely high added to the fine region, there is no need to provide a margin according to the pattern as in the case of ion implantation, there is no expansion of the implantation region due to thermal diffusion, and the device can be miniaturized. An easy and high performance Schottky field effect transistor can be realized.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in more detail with reference to the drawings. <Embodiment 1> FIG. 1A is a schematic view showing a layer structure of a Schottky field effect transistor exemplified in this embodiment, and FIG. 1B is an energy band diagram of the conductor electrons. Show. In FIG. 1A, reference numeral 11 denotes semi-insulating Ga.
As substrate, 12 is n-type InGaAs layer, 13a is p-type InGa
A P layer 13b is an n-type InGaP layer, and 14 is a gate metal layer. At this time, the concentration of the n-type layer is made sufficiently high, and the barrier between the gate metal layer 14 and the n-type InGaP layer 13b is set to be negligible. As shown in the energy band diagram of the conductor electrons in FIG. 1B, the height of the barrier is 1.6 V in the p-type layer, and the barrier against electrons is as large as the band gap of the p-type InGaP layer 13a. Can be. In this structure, since the total carrier amount of pn is equal and depleted with each other, no carrier remains in this gate, and no element deterioration due to hole injection or the like occurs.

Embodiment 2 FIG. 2A is a schematic diagram showing a layer structure of a Schottky field effect transistor exemplified in this embodiment, and FIG. 2B is a diagram showing the energy of the conductor electrons. The band diagram is shown. In FIG. 2A, 21 is a semi-insulating GaAs substrate, 22 is an n-type InGaAs layer, 23a
Is an n-type InGaP layer, 23b is a p-type InGaP layer, 23c is a high-purity InGaP layer, 23d is a p-type InGaP layer, 23e is an n-type InGaP layer, and 24 is a gate metal layer. Note that n
The type InGaP layer 3a and the p-type InGaP layer 3b are paired, have the same carrier amount, and are mutually depleted. Also, p-type In
The GaP layer 3d and the n-type InGaP layer 3e are also paired, and have a structure in which they are mutually depleted. Therefore, no carrier exists in the InGaP layer. As is clear from the energy band diagram of the conductor electrons in FIG. 2B, an electron barrier corresponding to the band cap of the InGaP layer can be secured, and the barrier thickness can be secured. It becomes an ideal layer structure. In this structure, since the total carrier amount of pn is equal and depleted with each other, no carrier remains in this gate, and no element deterioration due to hole injection or the like occurs.

<Embodiment 3> FIG. 3A is a schematic view showing a layer structure of a Schottky field effect transistor exemplified in this embodiment, and FIG. The band diagram is shown. In FIG. 3A, 31 is a semi-insulating GaAs substrate, 32 is an n-type InGaAs layer, 33 is a high-purity InGaP layer, 34 is a gate metal layer, and a pair of p, A p-type atomic layer doping layer 33a and an n-type atomic layer doping layer 33b, which are n-type atomic layer doping layers, are further provided.
a and an n-type atomic layer doping layer 33b are provided.
FIG. 3B shows an energy band diagram of the conductor electrons realized by the above-described layer structure. As is clear from the figure, the rise and fall of the potential are steeper than in the energy band diagram of the conductor electrons shown in the above-mentioned Example 2 (FIG. 2B). In addition,
Although not shown here, a high-concentration n-type layer is provided between the gate metal layer 34 and the high-purity InGaP layer 33, and a barrier between the gate metal layer 34 and the high-purity InGaP layer 33 can be ignored. It is also possible to make it thinner. Also, a p-type atomic layer doping layer (ADL) 33a and an n-type ADL 33b
Must be arranged close to each other so that neutral impurities do not remain. In the second embodiment, the doping is thin and uniform. In the second embodiment, the doping is replaced with the atomic layer doping. Thus, by providing a pair of p and n atomic layer doping layers, the potential profile in the energy band diagram becomes steeper, and the effect of suppressing the gate leak current and further improving the reverse breakdown voltage can be achieved. .

[0010]

As described in detail above, in the Schottky field effect transistor of the present invention, the conventional I
Although the Schottky barrier of the nGaP layer can obtain only an electron barrier of 0.9 V, the band gap of 1.6 V corresponding to the band gap of the InGaP layer can be entirely used as an electron barrier. Can be suppressed, and since neither holes nor electrons exist in the gate,
It is possible to realize a highly efficient field effect transistor without adding extra capacitance.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a layer structure of a Schottky field effect transistor exemplified in Example 1 of the present invention and an energy band diagram of its conductive electrons.

FIG. 2 is a schematic diagram showing a layer structure of a Schottky field effect transistor exemplified in Example 2 of the present invention, and an energy band diagram of its conductive electrons.

FIG. 3 is a schematic diagram showing a layer structure of a Schottky field effect transistor exemplified in a third embodiment of the present invention, and an energy band diagram of its conductive electrons.

FIG. 4 is a schematic diagram showing a layer structure of a conventional Schottky field effect transistor and an energy band diagram of its conductive electrons.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semi-insulating GaAs substrate 12 ... N-type InGaAs layer 13a ... P-type InGaP layer 13b ... N-type InGaP layer 14 ... Gate metal layer 21 ... Semi-insulating GaAs substrate 22 ... N-type InGaAs layer 23a ... N-type InGaP layer 23b ... p-type InGaP layer 23c ... i-type InGaP layer 23d ... p-type InGaP layer 23e ... n-type InGaP layer 24 ... gate metal layer 31 ... semi-insulating GaAs substrate 32 ... n-type InGaAs layer 33 ... high-purity InGaP layer 33a ... p N-type atomic layer doping layer (ADL) 33b n-type atomic layer doping layer (ADL) 34 gate metal layer 41 semi-insulating GaAs substrate 42 n-type InGaAs layer 43 high-purity InGaP layer 44 gate metal layer

Claims (3)

(57) [Claims] 1. A field effect transistor comprising a compound semiconductor, comprising: a first semiconductor layer having a small electron affinity on a surface side, that is, a gate side; and a first semiconductor layer having a large electron affinity as compared with the first semiconductor layer. In a semiconductor device having two semiconductor layers, the second semiconductor layer being an n-type conductive layer, a part of the surface side of the first semiconductor layer is a p-type layer, The part is an n-type layer, and the impurity amount per unit area of the p-type layer and the impurity amount per unit area of the n-type layer are the same, and impurities are added so as to be mutually depleted. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer comprises an n-type layer, a p-type layer, an i-type layer, a p-type layer, and an n-type layer.
A semiconductor device characterized in that it is configured to be a gate of a mold layer. 3. The semiconductor device according to claim 1, wherein a part or the whole of the p-type layer and the n-type layer is an atomic layer doping layer.