JP2713905B2 - Field effect transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and particularly to a structure of a GaAs field effect transistor.
The present invention relates to the following high-performance field-effect transistor. [Prior Art] Conventionally, a high-performance field-effect transistor using GaAs and having a gate length of 0.5 μm or less is described, for example, in the 34th Preliminary Proceedings of the 34th Joint Lecture Meeting on Applied Physics, Vol. 3, 28PX-5 (1987). 805
Page, and the structure is as shown in FIG.
An undoped GaAs layer 1 is provided with a very thin GaAs high carrier concentration active layer 2. [Problems to be Solved by the Invention] As a method of preventing a short channel effect in which a threshold voltage value of a transistor shifts to a negative side as a gate length is shortened,
A method for forming a p-type layer below an active layer is known. However, this method is not very effective when the gate length is 0.5 μm or less.
In a high-performance transistor of the order, the short channel effect is prevented by making the active layer extremely thin, and p
No mold layer was formed. However, as shown in FIG. 4 (b), as the thickness of the active layer is reduced, the present inventors have determined that the threshold voltage value can be increased by the heat treatment required for the protective film after the formation of the transistor region, the wiring step, and the like. Was found to be large. Although the details of this cause are unknown, the heat treatment causes impurities in the active layer to diffuse below the active layer and change the thickness of the active layer. Probably because it is remarkable. [Means for Solving the Problems] By using a technique of embedding a p-type layer, which has not been conventionally used when the thickness of the active layer is small, the present inventors have proposed a technique for reducing the threshold voltage value due to this heat treatment. It has been found that fluctuation can be reduced. When the active layer is p-type, the buried layer is n-type. [Operation] It is considered that even if impurities in the active layer diffuse into the lower portion of the active layer due to the heat treatment, the impurities are offset by the p-type impurities, and the thickness of the active layer does not largely change. Example (Example 1) An example of the present invention is shown in FIG. Semi-insulating GaAs substrate 3
A p-type GaAs buried layer 7 doped with Be at about 10 ¹⁷ cm ^-3
Epitaxial growth was performed using the E method. If the active layer thickness is small, it is necessary to increase the carrier concentration of the active layer. Therefore, a high carrier concentration of 1-5 × 10 ¹⁸ cm ^-3 doped with Si is required.
The GaAs active layer 2 was grown on the p-type buried layer 7 to a thickness of 30 to 1000 °. Next, a gate electrode 6 having a gate length of 0.3 μm is formed using WSi, and an ohmic electrode is formed on both sides of the gate electrode.
Field effect transistors were fabricated by forming 4,5. Further, after a SiO ₂ protective film was formed under a heat treatment condition of 400 ° C. for 20 minutes using a CVD method, a variation ΔV _{th of a} threshold voltage was measured. As a result, as shown in FIG. 2, the difference between the case where the p-type buried layer is used as in the present invention and the conventional case is that the thickness of the active layer is 500 mm.
It became clearer gradually below, and suddenly increased below 300 mm. Embodiment 2 FIG. 3 shows Embodiment 2 of the present invention. As in the first embodiment, a p-type GaAs buried layer 7 and a 2 × 10
^A GaAs active layer 2 having a high carrier concentration of ¹⁸ cm ^-3 was epitaxially grown by MBE, and an n-type GaAs active layer 8 having a low carrier concentration of 3 × 10 ¹² cm ^{-3 was} further grown. Thereafter, the gate electrode 6 and the ohmic electrodes 4 and 5 were formed by a usual method to manufacture a field effect transistor. Further, a SiO ₂ protection was formed under a heat treatment condition of 400 ° C. for 20 minutes using a CVD method (not shown). In this structure, the gate electrode 6 and the high carrier concentration active layer 2
Since the carrier concentration at the interface with the gate is as low as 3 × 10 ¹² cm ⁻³ , the gate breakdown voltage can be improved. [Effects of the Invention] According to the present invention, it is possible to obtain a high-performance field-effect transistor having stable performance with little characteristic fluctuation. In the above embodiment, an example is described in which an n-type semiconductor is used for the active layer and a p-type semiconductor is used for the buried layer. However, the same applies to a structure using a p-type semiconductor for the active layer and an n-type semiconductor for the buried layer. The effect can be obtained. Also, for materials other than GaAs, by inverting the conductivity types of the active layer and the buried layer, fluctuations in the thickness of the active layer due to heat treatment can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 3 are cross-sectional views of a field effect transistor according to the first and second embodiments of the present invention, and FIG. FIG. 4 (a) is a cross-sectional view of a conventional field-effect transistor, and FIG. 4 (b) is a diagram showing a change in threshold voltage value due to heat treatment of the conventional field-effect transistor. is there. DESCRIPTION OF SYMBOLS 1 ... Undoped layer, 2 ... High carrier concentration active layer, 3 ... Semi-insulating GaAs substrate, 4, 5 ... Ohmic electrode, 6 ... Gate electrode, 7 ... P-type layer, 8 ... Low carrier concentration active layer.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Takahiro Kobashi               2326 Imai, Ome City Hitachi, Ltd.               Computer Division, Device Development Center               Inside (72) Inventor Yasushi Hatta               2326 Imai, Ome City Hitachi, Ltd.               Computer Division, Device Development Center               Inside (72) Inventor Naoyuki Kawai               2326 Imai, Ome City Hitachi, Ltd.               Computer Division, Device Development Center               Inside                (56) References JP-A-62-45078 (JP, A)                 JP-A-62-49671 (JP, A)

Claims (1)

(57) [Claims] A gate having a gate length of 0.5 μm or less, an active layer made of a compound semiconductor of one conductivity type having a thickness of 500 ° or less, and a compound semiconductor of a conductivity type opposite to the one conductivity type in contact with one surface of the active layer A field effect transistor comprising a layer. 2. 2. The field effect transistor according to claim 1, wherein said active layer has a thickness of 300 [deg.] Or less. 3. The gate is a Schottky barrier gate, the carrier concentration of the active layer is not uniform in the thickness direction, and the carrier concentration near the interface with the Schottky barrier gate is lower than the carrier concentration in the region adjacent thereto. The field-effect transistor according to claim 1 or 2, wherein the field-effect transistor is low. 4. The maximum value of the carrier concentration in the active layer in the thickness direction is 1
4. The field-effect transistor according to claim 3, wherein the field-effect transistor is in the range of about 5 * 10 < ¹⁸ > cm < ^-3 >. 5. The field effect transistor according to any one of claims 1 to 4, wherein the one conductivity type is n-type, and the opposite conductivity type is p-type. 6. The field effect transistor according to claim 1, wherein the compound semiconductor is gallium arsenide.