JP3090451B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a field-effect transistor for forming an operation layer by epitaxial growth.

[Conventional technology]

Conventionally, since the compound semiconductor element is formed on a semi-insulating substrate, the substrate bias effect from the back surface is not considered,
Research on the leakage current flowing through the semi-insulating substrate has been mainly focused on between elements. This means that while the element spacing is on the order of several μm, the spacing between the element and the backside is 500-1000.
This is because there is also μm.

As a conventional example of increasing the resistance between elements on a semi-insulating substrate, see the No. 387 Proceedings of the Subcommittee of Applied Electronic Properties,
Pages 21 to 24 discuss a method of forming a deep level between elements by implanting Cr ions to increase the resistance.

[Problems to be solved by the invention]

The above prior art relates to increasing the resistance between elements on a semi-insulating substrate, and no consideration is given to increasing the resistance between the element and the back surface of the substrate.

In addition, the substrate bias effect, which is a problem in a Si semiconductor using a conductive substrate, is based on a compound semiconductor using a semi-insulating substrate such as MESFET (Metal Semicondvctor Field Effect Transis).
tor), JFET (Junction Field Effect Transis tor),
MISFET (Metal Insulator Semiconductor FET), HEMT
(High Electron Mobility Transistor) is not considered.

By the way, in the MESFET, JFET, etc., suppression of the two-dimensional effect such as the electron flowing through the channel toward the substrate direction,
A layer having a conductivity type opposite to that of the operation layer has been provided under the operation layer for the purpose of reducing charges induced by α-rays that cause a soft error. In GaAs MESFETs, the "buried p
Although known as a "layer," it has been found that the formation of this buried p-layer causes a problem that the semi-insulating substrate has a low resistance and is vulnerable to a substrate bias effect from the back surface.

FIG. 2 shows the threshold voltage (V _th ) of a GaAsFESFET as an example.
3 shows the substrate bias effect of FIG. (A) shows the case where there is no buried p-layer, and (B) shows the case where the buried p-layer is provided. If the acceptor concentration of the p-layer is increased, the fluctuation of the threshold voltage due to the substrate bias is further increased. Both substrate crystals are undoped
It is a GaAs crystal and has a thickness of about 500 μm.

In semiconductor devices, the back surface is grounded so that floating charges in the substrate do not cause malfunctions.
FET elements take various potentials depending on the circuit. Therefore, if the fluctuation of the threshold voltage due to the substrate potential is large,
The threshold voltage deviates from the design value due to the potential of the substrate viewed from the side (actually, the substrate is grounded and the FET takes the potential according to the circuit), making normal circuit operation difficult. I do.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of reducing a change in threshold voltage (substrate bias effect) due to a voltage from the back surface and enabling a stable circuit operation.

[Means for solving the problem]

In order to achieve the above object, a high resistance layer is provided as an intermediate layer between an element on a substrate and a back surface of the substrate. As a method of forming the high-resistance layer, there is a method of adjusting a mixed crystal ratio during epitaxial growth.

[Action]

As an example, by epitaxial growth on a substrate,
In a semiconductor device in which an element is formed by stacking a buffer layer, a p layer, and an operation layer, an intermediate layer provided below or above the buffer layer is injected from the back surface of the substrate to the element or from the element to the back surface of the substrate. The carrier is prevented, the isolation between the back surface of the substrate and the element is improved, and the substrate bias effect is reduced.

〔Example〕

Hereinafter, as an embodiment of the present invention, a GaAs MESFET (Metal Semicondvctor) forming an operation layer by epitaxial growth will be described.
The case of Field Effect Transistor) will be described with reference to FIG.

In a MESFET manufactured by sequentially stacking a buffer layer 3, a buried 4p layer, and an operation layer 5 on a semi-insulating GaAs substrate 1 by epitaxial growth, an intermediate layer 2 is formed below the buffer layer 3 (see FIG. 1). (A)) or above (FIG. 1 (b)).

The buffer layer 3 is made of undoped GaAs and has a thickness of about 400 n.
m, the buried p layer 4 is doped with Be ion as an acceptor impurity by about 3 × 10 ¹⁶ cm ^-8 and has a thickness of about 300 nm. The operation layer 5 contains Si ⁺ ions of about 2 × 10 ¹⁸ cm as donor impurities.
^The thickness is about 30 nm with ^-3 doping.

When the buffer layer 3 is formed from a compound semiconductor composed of three or more elements, the mixed crystal ratio is adjusted when the buffer layer 3 is formed, and a high-resistance layer having a different mixed crystal ratio from the buffer layer 3 is added. It is also possible to form it and use it as the intermediate layer 2.

The active layer 5 is removed by wet etching in the other regions, leaving only the region to be the channel layer of the FET. After WSi (tungsten silicide) is sputter-deposited as a gate material, the gate 7 is formed by dry etching.

The source and drain are formed by selectively growing n ⁺ -GaAs6 by MOCVD (metal organic chemical vapor deposition). About 3 × 10 ¹⁸ cm ⁻³ of Si is doped as a donor impurity. The thickness of the n ⁺ layer 6 is about 300 nm. AuGe is deposited as a source and drain ohmic electrode 8 by a lift-off method. Thereafter, wiring of the electrodes is performed, whereby the GaAs MESF according to the present invention is formed.
A semiconductor device using ET is completed.

FIG. 2C shows the change in the threshold voltage with respect to the substrate bias in this embodiment. It can be seen that it is improved as compared with the case of (B).

As another embodiment of the present invention, it is possible to use a compound semiconductor other than GaAs, or a semiconductor such as Si or Ge, and it is also possible to apply MISFET, IGFET, JFET, etc. other than MESFET. . The semiconductor substrate 1 can be an amorphous substrate or a glass substrate.

〔The invention's effect〕

According to the present invention, the isolation between the substrate and the element can be improved, so that there is an effect of reducing the substrate bias effect.

By reducing the body bias effect, the FET used in the circuit is less likely to have different characteristics depending on the potential in the circuit, and there is an effect that the reliability of the circuit can be improved.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are cross-sectional views of a GaAs MSFET formed by epitaxial growth according to an embodiment of the present invention.
1 (a) is a cross-sectional view in which an intermediate layer is provided on a buffer layer, FIG. 1 (b) is a cross-sectional view in which an intermediate layer is provided below a buffer layer, and FIG. 7A and 7B are diagrams showing a change in threshold voltage when the back surface voltage is changed in the related art, and FIG. 7A shows a case where there is no buried p layer in the related art, and FIG. , (C) are the present invention. 1 ... semiconductor substrate, 2 ... intermediate layer, 3 ... buffer layer (i-
GaAs), 4... P-GaAs, 5... Operating layer (n-GaAs),
6 ... ohmic layer (n ⁺ -GaAs), 7 ... gate electrode,
8. Ohmic electrode.

────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shinichiro Takaya 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-131565 (JP, A) JP-A-1 JP-A-223773 (JP, A) JP-A-1-223776 (JP, A) JP-A-60-263472 (JP, A) JP-A-63-104484 (JP, A) JP-A-63-308965 (JP, A) JP-A-2-2637 (JP, A) JP-A-57-53927 (JP, A) JP-A-61-274369 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (1)

(57) [Claims] In a semiconductor device having a field-effect transistor in which an active layer is formed on a semiconductor substrate by epitaxial growth, a high-resistance isolation layer and a buffer are sequentially arranged between the active layer and the semiconductor substrate from the semiconductor substrate side. A semiconductor layer, wherein the high resistance isolation layer and the buffer layer are made of compound semiconductors having different mixed crystal ratios.