CN114141786A - Ternary logic transistor device structure and preparation method thereof - Google Patents

Ternary logic transistor device structure and preparation method thereof Download PDF

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Publication number
CN114141786A
CN114141786A CN202111648298.3A CN202111648298A CN114141786A CN 114141786 A CN114141786 A CN 114141786A CN 202111648298 A CN202111648298 A CN 202111648298A CN 114141786 A CN114141786 A CN 114141786A
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China
Prior art keywords
oxide layer
region
transistor device
device structure
logic transistor
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CN202111648298.3A
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Chinese (zh)
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毕津顺
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Tianjin Binhai New Area Microelectronics Research Institute
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Tianjin Binhai New Area Microelectronics Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

The invention provides a three-valued logic transistor device structure and a preparation method thereof, wherein the structure comprises the following components: a substrate to provide support; a heavily doped tunneling region; the buried oxide layer is positioned above the heavily doped tunneling region; a top silicon film on the buried oxide layer; heavily doping a source region and a drain region on two sides of the tunneling region; a gate oxide layer and a gate electrode on the source region, the drain region and the heavy top silicon film. The invention uses the semiconductor structure on the insulator, namely, a buried oxide layer is added above the heavily doped tunneling region, thereby effectively avoiding the influence of high-concentration doping on the threshold Voltage (VT) above the channel while realizing the ternary logic of the CMOS device.

Description

Ternary logic transistor device structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a ternary logic transistor device structure and a preparation method thereof.
Background
The implementation of a three-value CMOS device may be based on a multiple threshold voltage scheme and a single threshold voltage scheme. Currently, a commonly used method is to use Band-to-Band Tunneling (BTBT) of quantum mechanics to obtain multiple thresholds or a single threshold voltage, so as to implement three-value logic. The principle of quantum tunneling effect is that when a negative high voltage and a positive voltage are applied to the gate and the source respectively and the substrate is grounded, a high longitudinal electric field is established at the overlapping part of the gate and the source, and the PN junction of the source junction and the substrate is biased under a high reverse electric field. Under the combined action of transverse and longitudinal electric fields, the surface energy band of the source junction is bent upwards, and deep depletion occurs. When the energy band is bent to be larger than the forbidden band width, electrons in the valence band can tunnel into the conduction band through the forbidden band barrier to form current, namely, the band-band tunneling effect (BTBT) occurs. The electrons generated by BTBT will be collected by the source and the holes will be mostly collected by the substrate across the junction region under acceleration of the PN junction lateral electric field to form a band-to-band tunneling current (IBTBT). The control of high concentration doping in the IBTBT primary acceptor, low concentration doping near the surface determines the threshold Voltage (VT).
Fig. 1 shows a structure of a three-valued logic transistor device in the prior art, which includes a gate 1, a gate oxide layer 2, a source region 3, a drain region 4, a heavily doped tunneling region 7 disposed between the source region 3 and the drain region 4, and a substrate 8. The T-CMOS (Ternary CMOS, hereinafter referred to as T-CMOS) structure generates an inter-band tunneling current (IBTBT) through high-concentration ion implantation, and generates a third voltage state between a high threshold voltage and a low threshold voltage so as to realize three-value logic.
However, BTBT caused by high concentration doping may cause an increase in leakage current and affect the channel doping concentration, causing threshold Voltage (VT) fluctuation, thereby reducing on-current, slowing down boosting, slowing down the speed of T-CMOS devices, and further affecting the overall performance of the chip. On the other hand, the T-CMOS is a local dielectric isolation, high-concentration doping easily causes latch-up effect in the device, and the isolation region between the devices occupies too large chip area, which also results in increase of parasitic capacitance and is not favorable for integration of the device.
Disclosure of Invention
In view of this, the present invention provides a transistor device structure with a ternary logic and a method for fabricating the same, based on a Silicon On Insulator (SOI) and combined with a T-CMOS technology, to obtain a novel transistor with a ternary logic (SOI T-CMOS), which is beneficial to enhance channel controllability, have a better performance of maintaining threshold Voltage (VT) stability, and simultaneously, to eliminate latch-up effect and reduce the influence of parasitic capacitance, compared with the same type of devices, by using the existing commercial SOI on the basis of the T-CMOS technology.
In order to solve the technical problems, the invention adopts the technical scheme that: a three-value logic transistor device structure, the structure comprising:
a substrate to provide support;
a heavily doped tunneling region;
the buried oxide layer is positioned above the heavily doped tunneling region;
a top silicon film on the buried oxide layer;
heavily doping a source region and a drain region on two sides of the tunneling region;
a gate oxide layer and a gate electrode on the source region, the drain region and the heavy top silicon film.
Preferably, the depth of the source region and the drain region extending to the bottom of the substrate is deeper than the depth of the buried oxide layer so as to form a tunneling structure.
Preferably, the thickness of the buried oxide layer is greater than that of the gate oxide layer, so as to realize the isolation of the heavily doped tunneling region from the gate.
A method of fabricating a ternary logic transistor device structure, comprising:
selecting an SOI wafer;
etching the SOI wafer;
heavily doping to form a heavily doped tunneling region, and selectively epitaxially growing silicon to obtain a source region and a drain region;
and depositing a gate oxide layer, and manufacturing a grid electrode on the gate oxide layer.
Preferably, the SOI wafer comprises a substrate, a buried oxide layer and a top silicon film.
Preferably, during the etching process of the SOI wafer, the etching depth is deeper than the top silicon film and the buried oxide layer.
Preferably, the thickness of the heavily doped tunneling region is ensured to be larger than that of the gate oxide layer.
Preferably, the doping concentration of the source and drain regions needs to be high enough to form a tunneling structure.
The invention has the advantages and positive effects that: the invention uses the semiconductor structure on the insulator, namely, a buried oxide layer is added above the heavily doped tunneling region, thereby effectively avoiding the influence of high-concentration doping on the threshold Voltage (VT) above the channel while realizing the ternary logic of the CMOS device.
Drawings
FIG. 1 is a schematic diagram of a prior art three-valued logic transistor device structure;
FIG. 2 is a schematic diagram of a three-value logic transistor device structure according to the present invention;
FIG. 3 is a schematic diagram of a structure of an optional SOI wafer according to the present invention;
FIG. 4 is a schematic diagram of the structure of the SOI wafer of the present invention after etching;
fig. 5 is a schematic structural diagram after forming a heavily doped tunneling region and source and drain regions in the present invention.
Detailed Description
For a better understanding of the present invention, reference is made to the following detailed description and accompanying drawings that illustrate the invention.
As shown in fig. 2, the present invention provides a three-valued logic transistor device structure, which comprises:
a substrate 8;
a heavily doped tunneling region 7;
a buried oxide layer 6 located above the heavily doped tunneling region 7;
a top silicon film 5 on the buried oxide layer 6;
a source region 3 and a drain region 4 which are extended from two sides of the tunneling region 7 are heavily doped;
a gate oxide layer 2 and a gate electrode 1 on the source region 3, the drain region 4 and the heavy top silicon film 5.
The substrate 8, which can be a conventional semiconductor substrate such as a silicon substrate, a sapphire substrate, or the like, supports the entire structure; the source region 3, the drain region 4 and the heavy doping tunneling region 7 provide conditions for manufacturing a T-CMOS device, and a tunneling structure is formed by high-concentration source-drain doping so as to obtain a three-value logic system; the buried oxide layer 6 is an effective isolation layer (Channel-on-Box) which can avoid influence of heavy doping below the buried oxide layer on threshold Voltage (VT), and the buried oxide layer 6 can be a silicon dioxide, silicon oxide and silicon nitride composite dielectric layer; the gate oxide layer 2 and the top silicon film 5 can provide physical support for the gate 1, and can be used as a mask for diffusion and ion implantation to prevent doped impurity loss, and the gate oxide layer 2 can be SiO2 or high-k dielectric; the grid 1 controls the on-resistance and carries information, and the grid 1 can be a polysilicon or metal grid.
The invention uses the semiconductor structure on the insulator, namely a buried oxide layer 6 is added above a heavily doped tunneling region 7, thereby effectively avoiding the influence of high-concentration doping on the threshold Voltage (VT) above the channel while realizing the three-value logic of the CMOS device.
Specifically, the parasitic capacitance of the source region 3 and the drain region 4 is reduced by adding the buried oxide layer 6, the electric leakage is reduced, under the same external voltage, larger band-to-band tunneling current (IBTBT) can be obtained, the power consumption is reduced, the delay of the device is also reduced, and the latch-up effect in the traditional T-CMOS device can be thoroughly eliminated and the anti-irradiation property of the device is improved because the SOI T-CMOS is an all-dielectric isolation structure. Therefore, the structure has better isolation effect, can reduce the influence of the tunneling structure on the threshold Voltage (VT) and eliminate the latch-up effect, and improves the overall performance of the device.
Further, the depth of the source region 3 and the drain region 4 extending towards the bottom of the substrate is deeper than the depth of the top silicon film 5 and the buried oxide layer 6, so as to form a tunneling structure; the thickness of the buried oxide layer 6 is larger than that of the gate oxide layer 2 so as to realize the isolation of the heavy doped tunneling region 7 from the grid electrode 1
A second aspect of the invention provides a method of fabricating a ternary logic transistor device structure, the method comprising:
selecting an SOI wafer comprising a substrate 8, a buried oxide layer 6 and a top silicon film 5, as shown in FIG. 3;
etching the SOI wafer to a depth deeper than the top silicon film 5 and the buried oxide layer 6, as shown in FIG. 4;
heavily doping to form a heavily doped tunneling region 7, and selectively epitaxially growing silicon to obtain a source region 3 and a drain region 4, as shown in fig. 5;
a gate oxide layer 2 is deposited and a gate 1 is fabricated on the gate oxide layer 2.
In one embodiment of the present invention, a high resistance wafer close to intrinsic silicon is selected as the substrate 1, the etching depth of the source region 3 and the drain region 4 needs to be greater than the depth of the top silicon film 5 and the buried oxide layer 6, and the doping concentration of the source region 3 and the drain region 4 needs to be high enough to form a tunneling structure. The method of forming the tunneling structure includes, but is not limited to, increasing the ion implantation concentration of the source region 3 and the drain region 4 and decreasing the applied energy.
In the invention, the SOI T-CMOS structure can be fused with the traditional CMOS process, the SOI T-CMOS is directly manufactured on the existing commercial SOI wafer, and the structures of field oxidation, wells and the like in the traditional CMOS process are not needed, so that some working procedures are reduced, the minimum interval of devices is reduced, the integration density is greatly improved, and the SOI T-CMOS can be better applied to integrated circuits.
The SOI T-CMOS is a partially depleted silicon-on-insulator structure, the width of a depletion region is not influenced by the thickness of a silicon film, and the threshold voltage is less influenced by back grid bias. The threshold voltage adjustment and the short channel effect control can adopt the control method of the traditional bulk silicon device and are easy to control.
The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.

Claims (8)

1. A three-value logic transistor device structure, characterized by: the structure includes:
a substrate to provide support;
a heavily doped tunneling region;
the buried oxide layer is positioned above the heavily doped tunneling region;
a top silicon film on the buried oxide layer;
heavily doping a source region and a drain region on two sides of the tunneling region;
a gate oxide layer and a gate electrode on the source region, the drain region and the heavy top silicon film.
2. The tri-value logic transistor device structure of claim 1, wherein: the depth of the source region and the drain region extending to the bottom of the substrate is deeper than the depth of the buried oxide layer so as to form a tunneling structure.
3. The tri-value logic transistor device structure of claim 1, wherein: the thickness of the buried oxide layer is larger than that of the gate oxide layer so as to realize the isolation of the heavily doped tunneling region and the gate.
4. A method of fabricating a ternary logic transistor device structure, comprising: the method comprises the following steps:
selecting an SOI wafer;
etching the SOI wafer;
heavily doping to form a heavily doped tunneling region, and selectively epitaxially growing silicon to obtain a source region and a drain region;
and depositing a gate oxide layer, and manufacturing a grid electrode on the gate oxide layer.
5. The method of fabricating a tri-value logic transistor device structure of claim 4, wherein: the SOI wafer comprises a substrate, a buried oxide layer and a top silicon film.
6. The method of fabricating a tri-value logic transistor device structure of claim 5, wherein: and in the process of etching the SOI wafer, the etching depth is deeper than the top silicon film and the buried oxide layer.
7. The method of fabricating a tri-value logic transistor device structure of claim 4, wherein: and ensuring that the thickness of the heavily doped tunneling region is greater than that of the gate oxide layer.
8. The method of fabricating a tri-value logic transistor device structure of claim 4, wherein: the doping concentration of the source and drain regions needs to be high enough to form a tunneling structure.
CN202111648298.3A 2021-05-24 2021-12-29 Ternary logic transistor device structure and preparation method thereof Pending CN114141786A (en)

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CN2021105685861 2021-05-24
CN202110568586.1A CN113299663A (en) 2021-05-24 2021-05-24 Ternary logic transistor device structure and preparation method thereof

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CN202111648298.3A Pending CN114141786A (en) 2021-05-24 2021-12-29 Ternary logic transistor device structure and preparation method thereof

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