CN110148626B - Polarization doped InN-based tunneling field effect transistor and manufacturing method thereof - Google Patents
Polarization doped InN-based tunneling field effect transistor and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Abstract
The invention discloses a polarization-doped InN-based tunneling field effect transistor, which mainly solves the problems of reduced device performance, complex manufacturing process and low reliability caused by random doping fluctuation caused by the traditional physical doping technology. It includes from bottom to top: the device comprises a substrate (1), a buffer layer (2) and a body region (3), wherein a polarization inversion layer (4) is arranged on the upper right portion of the body region, a dielectric layer (8) is deposited on the upper portion of the body region, the left side and the upper portion of the polarization inversion layer, a grid step (9) is etched on the left side of the dielectric layer, a modulation plate (10), a grid (11) and a tunneling grid (12) are sequentially deposited on the upper portion of the dielectric layer from right to left, lower steps (5) are etched on two sides of the body region, and a source electrode (7) and a drain electrode (6) are respectively. The invention avoids the annealing process in the traditional physical doping technology, improves the output current and the sub-threshold swing amplitude of the device, inhibits the reverse electric leakage, improves the reliability of the device, and can be used for a low-power-consumption circuit system.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a tunneling field effect transistor which can be used for a low-power-consumption circuit system.
Technical Field
The CMOS process technology enters the 14nm era and continues to be miniaturized, and the technical nodes of 7nm and below are continuously pushed forward, nowadays, dozens of billions of devices can be integrated on a single chip, however, as the transistor size is miniaturized to the nanometer level, the problems of short channel effect and the like are increasingly serious, particularly, the power consumption is increased sharply along with the increase of the number of devices per unit area, so that the power consumption becomes an important limiting and non-negligible factor of the integrated circuit design, see CO L OMBODM, WIRTH G I, FAYOMI C.Design method using the chip for low-power-low-voltage circuit reference [ C ], the improvement of the power consumption of the CMOS chip is a high power consumption and low-consumption circuit technology, and the like, and the high power consumption efficiency and the high power consumption of the CMOS chip are considered as the high power consumption and low power consumption of the CMOS chip-low-power-voltage circuit reference [ C ] and the high power consumption of the CMOS chip is considered as the high power consumption of the CMOS process technology, the CMOS process, the CMOS technology is considered as the high power consumption of the CMOS chip-high power consumption and high power consumption of the integrated circuit, the CMOS-low power consumption of the CMOS technology, the CMOS-low power consumption of the integrated circuit, the CMOS-low power consumption of the CMOS technology, the CMOS-high power consumption of the CMOS-low power consumption of the CMOS integrated circuit, the CMOS technology, the CMOS process, the CMOS.
In the application of nano electronic devices, the pursuit of low power consumption of the devices is always a catalyst for promoting the technical innovation of field effect transistors, wherein Tunneling Field Effect Transistors (TFETs) are widely concerned as an unprecedented substitute device. Compared with the conventional metal oxide semiconductor field effect transistor MOSFET, the tunneling field effect transistor has the advantages that the subthreshold swing can be less than 60mV/decade, the off-state leakage current is lower, and the Short channel effect can be effectively inhibited, see K.K. Young, "Short-channel effect in full depleted SOI MOSFETs," IEEETrans. Electron Devices, vol.36, No.2, pp.399-402, Feb.1989.
To date, considerable research has been devoted to the development of TFETs, and good progress has been made. In recent years, due to the small electronic effective mass and moderate band gap of channel materials, tunneling field effect transistors based on group iii nitride materials such as InN and InGaN have received extensive research and attention. Compared with the traditional silicon-based tunneling field effect transistor, the performance of the tunneling field effect transistor based on the III-nitride material is obviously improved. However, similar to conventional silicon-based tunneling field effect transistors, most of the tunneling field effect transistors based on iii-nitride materials are still based on conventional physical doping techniques.
Fig. 1 is a conventional physically doped group iii nitride based tunneling field effect transistor, comprising: the transistor comprises a body region 1, a source region 2, a drain region 3 and a dielectric layer 4, wherein a grid 5 is deposited on the upper portion of the dielectric layer 4, a drain 6 is deposited on the drain region 3, and a source 7 is deposited on the source region 2, wherein: the body region 1 adopts [ 0001%]InN semiconductor material with crystal orientation, source region 2 is located at left side of body region 1 and formed by P-type doping with doping concentration of 1 × 1018～1×1020cm-3The drain region 3 is located on the right side of the body region 1 and is formed by N-type doping with a doping concentration of 1 × 1017～1×1019cm-3The dielectric layer 4 is located on the upper part of the body region 1, has the same width as the body region 1, and can be made of SiO2Or SiN or Al2O3Or HfO2Or TiO2The thickness a of the insulating dielectric material is 1-20 nm; the gate 5 has the same width as the dielectric layer 4. The device with the structure has the same problems with the traditional physically-doped silicon-based tunneling field effect transistor due to the adoption of the traditional physical doping technology, such as the inherent high cost of the ion implantation process and the accompanying expensive annealing technology, and the random doping fluctuation RDFs, so that the performance of the device is reduced, the process complexity is increased, and the reliability of the device is reduced.
Disclosure of Invention
The invention aims to provide a polarization doped InN-based tunneling field effect transistor and a manufacturing method thereof aiming at the defects of the prior art, so as to avoid the attenuation of random doping fluctuation on the performance of a device and a complex and expensive annealing process in the traditional physical doping technology, reduce the manufacturing difficulty of the device, effectively improve the output current and subthreshold swing of the device, inhibit the reverse electric leakage of the device and improve the reliability of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
A polarization doped InN-based tunneling field effect transistor, comprising: body region 3, drain 6, source 7, gate 11, characterized by:
a buffer layer 2 and a substrate 1 are sequentially arranged below the body region 3, and the buffer layer 2 is made of a [0001] crystal orientation unintentionally doped GaN semiconductor material;
the upper right part of the body region 3 is deposited with a polarization inversion layer 4, which uses [0001]]Unintentionally doped In of crystal orientationxGa1-xThe width f of the N semiconductor material is 10-100 nm, and the thickness h of the polarization inversion layer (4) and the In component x approximately satisfy the relation:
lower steps 5 are etched on two sides of the body region 3, a drain electrode 6 is positioned on the upper portion of the right step 5, and the thickness of the drain electrode is larger than the sum of the thicknesses of the body region 3 and the polarization inversion layer 4; the source electrode 7 is positioned at the upper part of the left step 5, and the thickness of the source electrode is greater than that of the body region 3;
dielectric layers 8 are deposited on the upper part of the body region 3 and the left side and the upper part of the polarization inversion layer 4; a gate step 9 is etched on the left side of the dielectric layer 8, a modulation plate 10 and a tunneling gate 12 are sequentially deposited on the upper portion from right to left, and a gate 11 is located between the modulation plate 10 and the tunneling gate 12.
Preferably, the gate electrode 11 has a width c smaller than that of the modulation plate 10 and a width b of 6 to 70 nm.
Preferably, the drain electrode 6 has a work function of a metal lower than that of the metal used for depositing the gate electrode 11.
Preferably, the source electrode 7 is made of a metal having a work function higher than that of the metal used for depositing the gate electrode 11.
Preferably, the width of the modulation plate 10 overlapped with the polarization inversion layer 4 is smaller than the width f of the polarization inversion layer 4 and the width b of the modulation plate 10, and the work function of the metal used is higher than that of the metal used for depositing the gate electrode 11.
Preferably, the dielectric layer 8 is made of SiO2Or SiN or Al2O3Or HfO2Or TiO2And the thicknesses a of the areas of the upper part of the body area 3, the left side of the polarization inversion layer 4 and the upper part of the polarization inversion layer 4 are equal, the areas among the body area 3, the polarization inversion layer 4, the grid 11 and the modulation plate 10 are completely filled with the insulating dielectric material, and the thickness a is 1-20 nm.
Preferably, the gate step 9 has a depth e smaller than the thickness a of the dielectric layer 8 and a width d smaller than the width b of the modulator plate 10 and the width c of the gate 11.
Preferably, the tunneling gate 12 has the same width as the gate step 9, the lower portion of the tunneling gate is located above the gate step 9, the thickness of the tunneling gate is greater than the depth of the gate step 9, the work function of the metal used for depositing the gate 11 is less than or equal to the work function of the metal used for depositing the gate 11, and the tunneling gate 12, the modulation plate 10 and the gate 11 are electrically connected in sequence.
Second, the manufacturing method
The invention discloses a method for manufacturing a vertical power transistor of a source stepped field plate, which comprises the following steps:
A. extending a [0001] crystal orientation unintentionally doped GaN semiconductor material on a substrate 1 to form a buffer layer 2 with the thickness of 500-1000 nm;
B. extending a [0001] crystal orientation unintentionally doped InN semiconductor material on the buffer layer 2 to form a body region 3 with the thickness of 10-30 nm;
C. manufacturing a polarization inversion layer 4:
C1) epitaxy of [0001] over body 3]Unintentionally doped In of crystal orientationxGa1-xThe width f of the N semiconductor material is 10-100 nm, and the thickness h of the polarization inversion layer (4) and the In component x approximately satisfy the relation:
C2) in epitaxial at C1)xGa1-xManufacturing a mask on the N semiconductor material for the first time, etching the left side and the right side by using the mask to form a lower step 5, and stopping etching until the upper part of the buffer layer 2 is etched;
C3) in the upper part of the buffer layer 2 not covered by the body region 3xGa1-xMaking a mask on the N semiconductor material for the second time, and etching to remove In on the left side by using the maskxGa1-xN semiconductor material, forming a polarization inversion layer 4,
D. thirdly, a mask is manufactured on the lower steps 5 on the two sides and the upper part of the polarization inversion layer 4, and metal is deposited on the upper part of the lower step 5 on the right side by using the mask to form a drain electrode 6;
E. making a mask for the fourth time on the upper parts of the left lower step 5, the polarization inversion layer 4 and the drain electrode 6, and depositing metal on the upper part of the left lower step 5 by using the mask to form a source electrode 7;
F. manufacturing a dielectric layer 8:
F1) depositing an insulating dielectric material using a conformal coating process to cover the source 7, body 3, polarisation inversion layer 4 and drain 6;
F2) making a mask on the insulating medium material deposited in F1) for the fifth time, and etching and removing the insulating medium material on the left side and the right side by using the mask to form a medium layer 8, wherein the medium layer 8 covers part of the body region 3 and the polarization inversion layer 4, the thicknesses a of the medium layer 8 on the upper part of the body region 3 and the left side and the upper part of the polarization inversion layer 4 are equal, and the thickness a is 1-20 nm;
G. making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the sixth time, and etching the left side of the dielectric layer 8 by using the mask to form a gate step 9 with the etching depth smaller than the thickness of the dielectric layer 8 and the width smaller than the widths of the modulation plate 10 and the gate 11;
H. and manufacturing a mask on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the seventh time, and depositing metal on the upper part of the right side of the dielectric layer 8 by using the mask to form a modulation board 10, wherein the width b of the modulation board 10 is 6-70 nm. The overlapping width of the modulation board 10 and the polarization inversion layer 4 is smaller than the width of the polarization inversion layer 4 and the width of the modulation board 10, and the horizontal distance between the left side of the modulation board 10 and the left side of the polarization inversion layer 4 is the same as the thickness of the dielectric layer 8;
I. selecting metal with a metal work function larger than that of the drain electrode 6 and smaller than that of the source electrode 7 and the modulating plate 10, manufacturing masks on the source electrode 7, the body region 3, the dielectric layer 8, the modulating plate 10, the polarization inversion layer 4 and the drain electrode 6 for the eighth time, and depositing the metal on the upper part of the dielectric layer 8 between the left side of the modulating plate 10 and the right side of the gate step 9 by using the masks to form a gate electrode 11;
J. and selecting metal with the metal work function less than or equal to that of the grid 11, manufacturing a mask on the source electrode 7, the body region 3, the dielectric layer 8, the grid 11, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the ninth time, depositing the metal on the grid step 9 by using the mask to form a tunneling grid 12 with the thickness greater than the depth of the grid step 9, realizing the electrical connection among the tunneling grid 12, the modulation plate 10 and the grid 11, and finishing the manufacture of the device.
Compared with the traditional tunneling field effect transistor based on the physically doped III group nitride, the device has the following advantages:
1. and polarization doping is adopted, so that the influence of random doping fluctuation is avoided.
The device of the invention utilizes In formed by a polarization inversion layer 4 and a body region 3 according to the polarization theoryxGa1-xN, InN, the electron doping of the drain electrode region realized by the heterojunction is combined with the hole doping of the source electrode region realized by the InN and GaN heterojunction formed by the body region 3 and the buffer layer 2, thereby realizing the polarization doping of the device, avoiding the random doping fluctuation influence existing in the traditional III-group nitride-based tunneling field effect transistor based on physical doping, and obviously reducing the manufacturing difficulty and cost of the device by ion injection and high-temperature annealing process required in the process of manufacturing the traditional III-group nitride-based tunneling field effect transistor based on physical doping.
2. According to the invention, the drain electrode 6 with the thickness equal to the sum of the thicknesses of the body region 3 and the polarization inversion layer 4 is utilized, so that the contact resistance of the drain electrode is effectively reduced, and the output current of the device is increased.
3. The invention obviously improves the modulation effect of the grid 11 on the channel energy band and the electric field of the device, increases the output current of the device, reduces the subthreshold swing of the device, effectively inhibits the reverse electric leakage of the device and improves the reliability of the device by utilizing the mode of sequentially depositing the modulation plate 10, the grid 11 and the tunneling grid 12 with the metal work function from large to small on the dielectric layer 8 from right to left.
The technical contents and effects of the present invention are further explained below with reference to the drawings and examples.
Drawings
FIG. 1 is a block diagram of a conventional physically doped group III nitride based tunneling field effect transistor;
FIG. 2 is a block diagram of a poled doped InN-based tunneling field effect transistor of the present invention;
FIG. 3 is a schematic flow chart of the present invention for fabricating a polarized doped InN-based tunneling field effect transistor;
FIG. 4 is a sub-flow diagram of the present invention for fabricating a polarization inversion layer;
FIG. 5 is a sub-flow diagram of the present invention for fabricating a dielectric layer;
FIG. 6 is a graph showing the electron concentration and hole concentration at equilibrium for a device according to the present invention;
FIG. 7 is a graph of polarization charge and hole concentration distribution along the left edge of the device at equilibrium for a simulation of the device of the present invention;
FIG. 8 is a plot of polarization charge, carrier concentration, at equilibrium along the right edge of the device, as simulated for a device of the present invention;
figure 9 is a graph comparing transfer characteristics simulated for a conventional physically doped group iii nitride based tunneling field effect transistor and a device of the present invention.
Detailed Description
Referring to fig. 2, the polarization doped InN-based tunneling field effect transistor of the present invention comprises, from bottom to top: substrate 1, buffer layer 2, bulk region 3, wherein: the substrate 1 can adopt sapphire or silicon carbide or GaN material; the buffer layer 2 is made of a [0001] crystal orientation unintentionally doped GaN semiconductor material, and the thickness of the buffer layer is 500-1000 nm; the body region 3 is made of an InN semiconductor material with a [0001] crystal orientation and unintentionally doped, and the thickness of the InN semiconductor material is 10-30 nm.
The right upper part of the body region 3 is provided with a polarization inversion layer 4, and the inversion layer 4 adopts [0001]]Unintentionally doped In of crystal orientationxGa1-xThe width f of the N semiconductor material is 10-100 nm, and the thickness h of the polarization inversion layer (4) and the In component x approximately satisfy the relation:
dielectric layers 8 are deposited on the upper part of the body region 3 and on the left and upper parts of the polarization inversion layer 4, the dielectric layers 8 being made of SiO2Or SiN or Al2O3Or HfO2Or TiO2The thickness a of the insulating medium material is 1-20 nm, and the thicknesses a of the regions which are positioned at the upper part of the body region 3, the left side of the polarization inversion layer 4 and the upper part of the body region are equal. A gate step 9 is etched on the left side of the dielectric layer 8, the depth e of the gate step is smaller than the thickness a of the dielectric layer 8, a modulation plate 10, a grid 11 and a tunneling gate 12 are sequentially deposited on the upper portion of the dielectric layer 8 from right to left, wherein: the width b of the modulation plate 10 is 15 nm-50 nm, and the work function of the modulation plate is higher than that of the metal of the grid 11; the width c of the metal gate 11 is smaller than the width b of the modulation plate 10; the width of the tunneling gate 12 is equal to the width d of the gate step 9 and is smaller than the width b of the modulation plate 10 and the width c of the gate 11, the thickness of the tunneling gate is larger than the depth of the gate step 9, and a metal with a work function smaller than or equal to that of the gate 11 is adopted; the width of the overlapping of the modulation board 10 and the polarization inversion layer 4 is smaller than the width f of the polarization inversion layer 4 and the width b of the modulation board 10; the tunneling gate 12 is electrically connected to the modulation panel 10 and the gate 11 in this order. The regions between the body region 3, the polarization inversion layer 4, the gate 11 and the modulation plate 10 are completely filled with the dielectric layer 8.
Lower steps 5 are etched on two sides of the body region 3, a drain electrode 6 is arranged on the upper portion of the right side of each step 5, the thickness of each drain electrode 6 is larger than the sum of the thicknesses of the body region 3 and the polarization inversion layer 4, and metal with the work function lower than that of the grid electrode 11 is adopted; the upper part of the left side of the step 5 is provided with a source electrode 7, the thickness of the source electrode is larger than that of the body region 3, and metal with the work function higher than that of metal of the grid electrode 11 is adopted.
Referring to fig. 3, the method for fabricating a polarization-doped InN-based tunneling field effect transistor according to the present invention provides the following three embodiments.
The first embodiment is as follows: and manufacturing the polarization doped InN-based tunneling field effect transistor with the polarization inversion layer thickness of 24 nm.
Step 1, a drift layer 2 is fabricated on a substrate 1, as shown in fig. 3 b.
Sapphire is used as a substrate 1, a metal organic chemical vapor deposition technology is used for extending [0001] crystal orientation unintentional doped GaN semiconductor material with the thickness of 1000nm on the substrate 1 to form a drift layer 2, wherein the process conditions adopted by the extension are as follows: the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, the gallium source flow is 100 mu mol/min, and the epitaxial time is 2 h.
Step 2. make body region 3, as shown in fig. 3 c.
Epitaxy of [0001] using molecular Beam epitaxy on buffer layer 2]The body region 3 with the thickness of 30nm is formed by the InN semiconductor material which is not intentionally doped with crystal orientation, wherein the process condition adopted by epitaxy is that the vacuum degree is less than or equal to 1.0 × 10- 10mbar, radio frequency power of 400W, and N as reactant2And high-purity indium source, and the epitaxial time is 30 min.
And 3, manufacturing a polarization inversion layer 4, as shown in figure 3 d.
Referring to fig. 4, the specific implementation of this step is as follows:
3.1) epitaxy [0001] on the bulk region 3 using molecular Beam epitaxy]Unintentionally doped In of crystal orientation0.95Ga0.05N semiconductor material, forming a layer of In with a thickness of 24nm0.95Ga0.05N layer, wherein the epitaxial process condition is that the vacuum degree is less than or equal to 1.0 × 10-10mbar, radio frequency power of 400W, and N as reactant2The ratio of In molecular flow to Ga molecular flow is controlled to be 19:1, and the epitaxial time is 24 min;
3.2) In epitaxial at 3.1)0.95Ga0.05Making a mask on the N semiconductor material for the first time, and using the mask to In0.95Ga0.05The left side and the right side of the N semiconductor material are etched by using a reactive ion etching technology to form a lower step 5, and the etching is stopped until the upper part of the buffer layer 2, wherein the etching adopts the following process conditions: cl2The flow is 15sccm, the pressure is 10mT, and the power is 100W;
3.3) on top of the buffer layer 2 not covered by the body region 3 and In0.95Ga0.05Making a mask on the N semiconductor material for the second time, and etching to remove In on the left side by using reactive ion etching technology through the mask0.95Ga0.05N semiconductor material, forming a polarization inversion layer 4 with the width of 100nm, wherein the etching adopts the following process conditions: cl2The flow rate was 15sccm, the pressure was 10mT, and the power was 100W.
Step 4, manufacturing the drain electrode 6, as shown in fig. 3 e.
Thirdly manufacturing a mask on the lower steps 5 at two sides and the upper part of the polarization inversion layer 4, depositing metal Al on the upper part of the lower step 5 at the right side by using an electron beam evaporation technology by using the mask to form the drain electrode 6, wherein the process conditions for depositing the metal are that a high-purity aluminum source is adopted, and the vacuum degree is less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Step 5, manufacturing a source electrode 7, as shown in fig. 3 f.
Making a mask for the fourth time on the upper parts of the left lower step 5, the polarization inversion layer 4 and the drain electrode 6, depositing metal Pt on the upper part of the left lower step 5 by using an electron beam evaporation technology by using the mask to form the source electrode 7, wherein the process conditions for depositing the metal are a high-purity platinum source and the vacuum degree is less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Step 6, a dielectric layer 8 is manufactured, as shown in fig. 3 g.
Referring to fig. 5, the specific implementation of this step is as follows:
6.1) depositing a layer of SiN insulating medium with a thickness of 20nm on the upper parts of the source 7, body 3, polarization inversion layer 4 and drain 6 using plasma enhanced chemical vapor deposition and conformal capping, wherein the process conditions for depositing the passivation layer are: the gas being NH3、N2And SiH4The gas flow rates are respectively 2.5sccm, 950sccm and 250sccm, the temperature is 300 ℃, the radio frequency power is 25W, the pressure is 950mTorr, and the deposition time is 20 min.
6.2) making a mask on the insulating medium material deposited in the step 6.1) for the fifth time, and etching and removing the left side by using a reactive ion etching technology by using the maskThe SiN insulating mediums on the side part and the right side part form a medium layer 8, the medium layer 8 covers part of the body region 3 and the polarization inversion layer 4, the thicknesses of the medium layer 8, which are positioned on the upper part of the body region 3 and on the left side and the upper part of the polarization inversion layer 4, are 20nm, and the etching process adopts the following technological conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And 7, manufacturing a gate step 9 as shown in fig. 3 h.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the sixth time, and etching the left side of the dielectric layer 8 by using a reactive ion etching technology by using the mask to form a gate step 9 with the etching depth of 10nm and the width of 10nm, wherein the etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And 8, manufacturing the modulation board 10 as shown in fig. 3 i.
A mask is manufactured on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the seventh time, the mask is utilized to deposit metal Pt on the upper part of the right side of the dielectric layer 8 by using an electron beam evaporation technology to form a modulation plate 10 with the width of 70nm, the width of the overlapping part of the modulation plate 10 and the polarization inversion layer 4 is 50nm, the horizontal distance between the left side of the modulation plate 10 and the left side of the polarization inversion layer 4 is 20nm, wherein the technological conditions adopted by metal deposition are that a high-purity platinum source is adopted, the vacuum degree is less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Step 9, manufacturing a grid 11, as shown in fig. 3 j.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the eighth time, and depositing metal Ni on the upper part of the dielectric layer 8 between the left side of the modulation plate 10 and the right side of the grid step 9 by using an electron beam evaporation technology by using the mask to form a grid electrode 11 with the width of 30nm, wherein the process conditions adopted by depositing the metal are that a high-purity nickel source is adopted, and the vacuum degree is less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Step 10, a tunneling gate 12 is fabricated, as shown in fig. 3 k.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the grid electrode 11, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the ninth time, depositing metal Ni on the grid step 9 by using an electron beam evaporation technology by using the mask to form a tunneling grid 12 with the width of 10nm, wherein the thickness of the tunneling grid 12 is more than 10nm, and the manufacturing of the device is finished, wherein the process conditions adopted by the deposited metal are that a high-purity nickel source is adopted, the vacuum degree is less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Example two: and manufacturing the polarization doped InN-based tunneling field effect transistor with the polarization inversion layer thickness of 10 nm.
Step one, a drift layer 2 is fabricated on a substrate 1, as shown in fig. 3 b.
Silicon carbide is used as a substrate 1, and a metal organic chemical vapor deposition technology is used on the substrate 1 to form a drift layer 2 by extending a [0001] crystal orientation unintentional doped GaN semiconductor material with the thickness of 750nm under the process conditions of 950 ℃, 40Torr pressure, 4000sccm hydrogen flow, 4000sccm ammonia flow, 100 mu mol/min gallium source flow and 1.5h epitaxial time.
Step two, the body region 3 is fabricated, as shown in fig. 3 c.
Applying molecular beam epitaxy technique on the buffer layer 2 under vacuum degree of 1.0 × 10 or less-10mbar, radio frequency power of 400W, and N as reactant2High-purity indium source, the epitaxial time is 20min, and the epitaxy is performed under the process condition of [0001]]The body region 3 is formed of an unintentionally doped InN semiconductor material of a crystal orientation and has a thickness of 20 nm.
And step three, manufacturing a polarization inversion layer 4, as shown in figure 3 d.
Referring to fig. 4, the specific implementation of this step is as follows:
3a) using molecular beam epitaxy technique on the body region 3, vacuum degree of less than or equal toAt 1.0 × 10-10mbar, radio frequency power of 400W, and N as reactant2High-purity indium source and high-purity gallium source, wherein the ratio of In molecular flow to Ga molecular flow is controlled to be 17:3, and the epitaxy time is 10min, and the epitaxy is performed for [0001 [ ]]Unintentionally doped In of crystal orientation0.85Ga0.15N semiconductor material, forming a layer of In with a thickness of 10nm0.85Ga0.15N layers;
3b) in epitaxial at 3a)0.85Ga0.15Making a mask on the N semiconductor material for the first time, and using the mask to In0.85Ga0.15The left and right sides of the N semiconductor material are etched in Cl by using a reactive ion etching technology2Etching to the upper part of the buffer layer 2 under the process conditions of the flow of 20sccm, the pressure of 10mT and the power of 150W, and stopping to form a lower step 5;
3c) in the upper part of the buffer layer 2 not covered by the body region 30.85Ga0.15Second forming a mask over the N semiconductor material, using the mask to form a second layer of Cl using a reactive ion etching technique2Etching to remove In on the left side under the process conditions of 15sccm flow, 10mT pressure and 70W power0.85Ga0.15N semiconductor material, forming a polarization inversion layer 4 having a width of 40 nm.
Step four, manufacturing the drain electrode 6, as shown in fig. 3 e.
The specific implementation of this step is the same as step 4 of the first embodiment.
Step five, manufacturing the source electrode 7, as shown in fig. 3 f.
The specific implementation of this step is the same as step 5 of the first embodiment.
Step six, a dielectric layer 8 is manufactured, as shown in fig. 3 g.
Referring to fig. 5, the specific implementation of this step is as follows:
6a) a plasma enhanced chemical vapor deposition technique and conformal capping process are used on top of the source 7, body 3, polarization inversion layer 4 and drain 6 to coat the NH3、N2And SiH4Depositing a layer of 10 nm-thick insulating layer under the process conditions of gas flow of 2.5sccm, 950sccm and 250sccm, 300 ℃ temperature, radio frequency power of 25W, pressure of 950mTorr and deposition time of 10minA rim dielectric SiN;
6b) fifth mask is made on the insulating dielectric material deposited in 6a), by means of which the CF is etched by reactive ion etching4The flow rate was 45sccm, O2Under the process conditions of 5sccm flow, 15mTorr pressure and 250W power, etching to remove the insulating medium SiN on the left side and the right side to form a dielectric layer 8, wherein the dielectric layer 8 covers part of the body region 3 and the polarization inversion layer 4, and the thicknesses of the dielectric layer 8 on the upper portion of the body region 3 and the left side and the upper portion of the polarization inversion layer 4 are 10 nm.
And step seven, manufacturing the gate step 9 as shown in fig. 3 h.
Making masks on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the sixth time, and using the masks to etch the CF on the left side of the dielectric layer 8 by using a reactive ion etching technology4The flow rate was 45sccm, O2And etching to form a gate step 9 with the etching depth of 5nm and the width of 5nm under the process conditions of the flow of 5sccm, the pressure of 15mTorr and the power of 250W.
And step eight, manufacturing the modulation board 10 as shown in fig. 3 i.
A mask is manufactured on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the seventh time, the mask is utilized to use the electron beam evaporation technology to perform electron beam evaporation on the upper part of the right side of the dielectric layer 8 to form a high-purity platinum source, and the vacuum degree is less than 1.8 × 10-3Pa, power of 200W, evaporation rate of less than
The width of the modulation board 10 overlapped with the polarization inversion layer 4 is 20nm, and the horizontal distance between the left side of the modulation board 10 and the left side of the polarization inversion layer 4 is 10 nm.
Step nine, a gate 11 is fabricated as shown in fig. 3 j.
Making masks on the source electrode 7, the body region 3, the dielectric layer 8, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the eighth time, and using the masks to perform electron beam evaporation on the upper part of the dielectric layer 8 between the left side of the modulation plate 10 and the right side of the gate step 9 to form a high-purity nickel source with the vacuum degree of less than 1.8 × 10-3Pa, power of 200W, evaporation rate of less than
Under the process conditions of (1), depositing metallic Ni to form a gate electrode 11 with a width of 10 nm.
Step ten, manufacturing the tunneling gate 12, as shown in fig. 3 k.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the grid electrode 11, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the ninth time, and using the mask to use an electron beam evaporation technology on the grid step 9 to form a high-purity nickel source with the vacuum degree less than 1.8 × 10-3Pa, power of 200W, evaporation rate of less than
Under the process conditions of (1), depositing metal Ni to form a tunneling gate 12 with the width of 5nm, wherein the thickness of the tunneling gate 12 is more than 5nm, and finishing the manufacture of the device. .
Example three: and manufacturing the polarization doped InN-based tunneling field effect transistor with the polarization inversion layer thickness of 1.2 nm.
Step a. a drift layer 2 is fabricated on a substrate 1, as shown in fig. 3 b.
A GaN material is adopted as a substrate 1, a metal organic chemical vapor deposition technology is used for extending a [0001] crystal orientation unintentionally doped GaN semiconductor material with the thickness of 500nm on the substrate 1 to form a drift layer 2, wherein the process conditions adopted by the extension are as follows: the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, the gallium source flow is 100 mu mol/min, and the epitaxial time is 1 h.
Step b. body region 3 is fabricated as in fig. 3 c.
Epitaxy of [0001] using molecular Beam epitaxy on buffer layer 2]The body region 3 with the thickness of 10nm is formed by the InN semiconductor material which is not intentionally doped with the crystal orientation, wherein the process condition adopted by the epitaxy is that the vacuum degree is less than or equal to 1.0 × 10- 10mbar, radio frequency power of 400W, and N as reactant2And high-purity indium source, and the epitaxial time is 10 min.
Step c. make the polarization inversion layer 4, as shown in fig. 3 d.
Referring to fig. 4, the specific implementation of this step is as follows:
C1) epitaxy of [0001] over body region 3 using molecular beam epitaxy]Unintentionally doped In of crystal orientation0.1Ga0.9N semiconductor material, forming a layer of In with a thickness of 1.2nm0.1Ga0.9N layer, wherein the epitaxial process condition is that the vacuum degree is less than or equal to 1.0 × 10-10mbar, radio frequency power of 400W, and N as reactant2The ratio of In molecular flow to Ga molecular flow is controlled to be 1:9, and the epitaxial time is 72 s;
C2) in epitaxial at C1)0.1Ga0.9Making a mask on the N semiconductor material for the first time, and using the mask to In0.1Ga0.9Etching the left side and the right side of the N semiconductor material by using a reactive ion etching technology to form a lower step 5, and stopping etching until the upper part of the buffer layer 2 is etched, wherein the etching process conditions are the same as the step 3.2) of the first embodiment.
C3) In the upper part of the buffer layer 2 not covered by the body region 30.1Ga0.9Making a mask on the N semiconductor material for the second time, and etching to remove In on the left side by using reactive ion etching technology through the mask0.1Ga0.9N semiconductor material, forming a polarization inversion layer 4 with the width of 10nm, wherein the etching adopts the same process conditions as the step 3.3) of the embodiment.
Step d, drain 6 is fabricated as shown in fig. 3 e.
The specific implementation of this step is the same as step 4 of the first embodiment.
Step e. source 7 is fabricated as in fig. 3 f.
The specific implementation of this step is the same as step 5 of the first embodiment.
Step f, a dielectric layer 8 is fabricated as shown in fig. 3 g.
Referring to fig. 5, the specific implementation of this step is as follows:
F1) and depositing a layer of insulating medium SiN with the thickness of 1nm on the upper parts of the source electrode 7, the body region 3, the polarization inversion layer 4 and the drain electrode 6 by using a plasma enhanced chemical vapor deposition technology and a conformal covering process, wherein the process conditions for depositing the passivation layer are as follows: NH (NH)3、N2And SiH4The gas flow is respectively 2.5sccm, 950sccm and 250sccm, the temperature is 300 ℃, the radio frequency power is 25W, the pressure is 950mTorr, and the deposition time is 1 min;
F2) and manufacturing a mask on the insulating medium material deposited in F1) for the fifth time, and etching and removing the insulating medium SiN at the left side and the right side by using a reactive ion etching technology by using the mask to form a dielectric layer 8, wherein the dielectric layer 8 covers part of the body region 3 and the polarization inversion layer 4, the thicknesses of the dielectric layer 8, which are positioned at the upper part of the body region 3 and at the left side and the upper part of the polarization inversion layer 4, are all 1nm, and the etching process conditions are the same as those in the step 6.2).
And G, manufacturing a gate step 9 as shown in fig. 3 h.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the sixth time, and etching the left side of the dielectric layer 8 by using a reactive ion etching technology by using the mask to form a gate step 9 with the etching depth of 0.5nm and the width of 1nm, wherein the etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
Step h. make the modulation board 10, as in fig. 3 i.
And manufacturing a mask on the source electrode 7, the body region 3, the dielectric layer 8, the polarization inversion layer 4 and the drain electrode 6 for the seventh time, depositing metal Pt on the upper part of the right side of the dielectric layer 8 by using an electron beam evaporation technology by using the mask to form a modulation plate 10 with the width of 6nm, wherein the width of the overlapping part of the modulation plate 10 and the polarization inversion layer 4 is 5nm, the horizontal distance between the left side of the modulation plate 10 and the left side of the polarization inversion layer 4 is 1nm, and the process condition for depositing the metal is the same as the step 8 of the first embodiment.
Step I produces the gate 11 as shown in fig. 3 j.
And manufacturing a mask on the source electrode 7, the body region 3, the dielectric layer 8, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the eighth time, and depositing metal Ni on the upper part of the dielectric layer 8 between the left side of the modulation plate 10 and the right side of the gate step 9 by using an electron beam evaporation technology by using the mask to form a gate 11 with the width of 3nm, wherein the process condition for depositing the metal is the same as the step 9 of the first embodiment.
Step j. fabricate the tunnel gate 12, as in fig. 3 k.
Making a mask on the source electrode 7, the body region 3, the dielectric layer 8, the grid electrode 11, the modulation plate 10, the polarization inversion layer 4 and the drain electrode 6 for the ninth time, and using the mask to use an electron beam evaporation technology on the grid step 9 to form a high-purity nickel source with the vacuum degree less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Depositing metal Ni under the process condition of (1) to form a tunneling grid 12 with the width of 1nm, wherein the thickness of the tunneling grid 12 is more than 0.5nm, and the tunneling grid 12 is electrically connected with a modulation plate 10 and a grid 11 in sequence to finish the manufacture of the device.
The effects of the present invention can be further illustrated by the following simulations.
Simulation 1 shows the results of simulation of electron concentration and hole concentration distributions of the device of the present invention in an equilibrium state, as shown in fig. 6, where fig. 6(a) shows an electron concentration distribution and fig. 6(b) shows a hole concentration distribution. As can be seen from fig. 6, the device of the present invention can form a very high hole concentration in the source region and a moderate electron concentration in the drain region by using the polarization doping effect.
Simulation 2, the device of the present invention is simulated in terms of polarization charge and hole concentration distribution along the left edge of the device in an equilibrium state, and the result is shown in fig. 7. As can be seen from fig. 7, there is a high concentration of polarized negative charges at the interface between the body region and the buffer layer of the device, and the polarized negative charges induce a high concentration of holes in the body region 3. This indicates that the hole concentration required for the source region of the device can be formed using the polarization effect.
Simulation 4, the transfer characteristics of a conventional physically doped group iii nitride based tunneling field effect transistor and the device of the present invention were simulated, and the results are shown in fig. 9. Fig. 9 shows that the leakage of the device of the present invention is significantly less than that of the conventional device in the off state, indicating that the off-state characteristics of the device of the present invention are better than those of the conventional physically doped group iii nitride based tunneling field effect transistor; and the slope of the forward current-voltage characteristic curve of the device is obviously larger than that of the traditional tunneling field effect transistor based on the physically doped III family nitride base under the conducting state, which shows that the subthreshold swing of the device is superior to that of the traditional tunneling field effect transistor based on the physically doped III family nitride base.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (10)
1. A polarization doped InN-based tunneling field effect transistor, comprising: body region (3), drain (6), source (7), gate (11), characterized in that:
a buffer layer (2) and a substrate (1) are sequentially arranged below the body region (3), and the buffer layer (2) is made of an unintentionally doped GaN semiconductor material with a [0001] crystal orientation;
the right upper part of the body region (3) is deposited with a polarization inversion layer (4) using [0001]]Unintentionally doped In of crystal orientationxGa1-xThe N semiconductor material has a width f of 10-100 nm, and the thickness h of the polarization inversion layer (4) and the In component x satisfy the following relation:
lower steps (5) are etched on two sides of the body region (3), the drain electrode (6) is positioned on the upper portion of the lower step (5) on the right side, and the thickness of the drain electrode is larger than the sum of the thicknesses of the body region (3) and the polarization inversion layer (4); the source electrode (7) is positioned at the upper part of the lower step (5) at the left side, and the thickness of the source electrode is greater than that of the body region (3);
dielectric layers (8) are deposited on the upper part of the body region (3) and the left side and the upper part of the polarization inversion layer (4); a grid step (9) is etched on the left side of the dielectric layer (8), a modulation plate (10) and a tunneling grid (12) are sequentially deposited on the upper portion from right to left, and a grid (11) is located between the modulation plate (10) and the tunneling grid (12).
2. The tunneling field effect transistor according to claim 1, wherein the gate (11) has a width c smaller than the width b of the modulation plate (10), and the width b is 6-70 nm.
3. A tunneling field-effect transistor according to claim 1, characterized in that said drain (6) has a work function of the metal used lower than that of the metal used for depositing the gate (11).
4. A tunneling field-effect transistor according to claim 1, characterized in that said source (7) has a work function with metal higher than the one used for depositing the gate (11).
5. The tunneling field effect transistor according to claim 1, wherein the width of the modulation plate (10) overlapping the polarization inversion layer (4) is smaller than the width f of the polarization inversion layer (4) and the width b of the modulation plate (10), and the work function of the metal used is higher than the work function of the metal used for depositing the gate electrode (11).
6. The tunneling field effect transistor according to claim 1, wherein the dielectric layer (8) is made of SiO2Or SiN or Al2O3Or HfO2Or TiO2And the thicknesses a of the areas of the upper part of the body area (3), the left side of the polarization inversion layer (4) and the upper part of the polarization inversion layer (4) are equal, the areas among the body area (3), the polarization inversion layer (4), the grid (11) and the modulation plate (10) are completely filled with the insulating dielectric material, and the thickness a is 1-20 nm.
7. A tunneling field effect transistor according to claim 1, characterized in that the gate step (9) has a depth e smaller than the thickness a of the dielectric layer (8) and a width d smaller than the width b of the modulator plate (10) and the width c of the gate (11).
8. The tunneling field effect transistor according to claim 1, wherein the tunneling gate (12) has the same width as the gate step (9), the lower portion is located above the gate step (9) and has a thickness greater than the depth of the gate step (9), the work function of the metal used is less than or equal to that of the metal used for depositing the gate (11), and the tunneling gate (12), the modulator plate (10) and the gate (11) are electrically connected in sequence.
9. The tunneling field effect transistor of claim 1, wherein:
the substrate (1) is made of sapphire, silicon carbide and GaN materials;
the body region (3) adopts an InN semiconductor material with the [0001] crystal orientation and is not intentionally doped.
10. A method for manufacturing a polarization-doped InN-based tunneling field effect transistor is characterized by comprising the following steps:
A. extending a [0001] crystal orientation unintentionally doped GaN semiconductor material on a substrate (1) to form a buffer layer (2) with the thickness of 500-1000 nm;
B. extending a [0001] crystal orientation unintentionally doped InN semiconductor material on the buffer layer (2) to form a body region (3) with the thickness of 10-30 nm;
C. manufacturing a polarization inversion layer (4):
C1) epitaxy of [0001] over the body region (3)]Unintentionally doped In of crystal orientationxGa1-xN semiconductor material, the InxGa1-xThe width f of the N semiconductor material is 10-100 nm, and the thickness h of the polarization inversion layer (4) and the In component x satisfy the relation:
C2) in epitaxial at C1)xGa1-xManufacturing a mask on the N semiconductor material for the first time, etching the left side and the right side by using the mask to form a lower step (5), and etching until the upper part of the buffer layer (2) stops;
C3) in and on the buffer layer (2) not covered by the body region (3)xGa1-xMaking a mask on the N semiconductor material for the second time, and etching to remove In on the left side by using the maskxGa1-xN semiconductor material forming a polarization inversion layer (4);
D. thirdly, a mask is manufactured on the upper portions of the lower steps (5) on the two sides and the polarization inversion layer (4), and metal is deposited on the upper portion of the lower step (5) on the right side by using the mask to form a drain electrode (6);
E. manufacturing a mask for the fourth time on the upper parts of the left lower step (5), the polarization inversion layer (4) and the drain electrode (6), and depositing metal on the upper part of the left lower step (5) by using the mask to form a source electrode (7);
F. manufacturing a dielectric layer (8):
F1) depositing an insulating dielectric material using a conformal capping process to cap the source (7), body (3), polarisation inversion layer (4) and drain (6);
F2) making a mask on the insulating medium material deposited in F1) for the fifth time, removing the insulating medium material on the left side and the right side by etching by using the mask to form a medium layer (8), wherein the medium layer (8) covers part of the body region (3) and the polarization inversion layer (4), the thicknesses a of the areas, which are positioned on the upper part of the body region (3), on the left side and on the upper part of the polarization inversion layer (4), are equal, and the thickness a is 1-20 nm;
G. making a mask on the source electrode (7), the body region (3), the dielectric layer (8), the polarization inversion layer (4) and the drain electrode (6) for the sixth time, and etching the left side of the dielectric layer (8) by using the mask to form a gate step (9) with the etching depth smaller than the thickness of the dielectric layer (8);
H. manufacturing a mask on the source electrode (7), the body region (3), the dielectric layer (8), the polarization inversion layer (4) and the drain electrode (6) for the seventh time, and depositing metal on the upper part of the right side of the dielectric layer (8) by using the mask to form a modulation plate (10), wherein the width b of the modulation plate (10) is 6-70 nm; the overlapping width of the modulation plate (10) and the polarization inversion layer (4) is smaller than the width of the polarization inversion layer (4) and the width of the modulation plate (10), and the horizontal distance between the left side of the modulation plate (10) and the left side of the polarization inversion layer (4) is the same as the thickness of the dielectric layer (8);
I. selecting a metal with a metal work function larger than that of the drain electrode (6) and smaller than that of the source electrode (7) and the modulation plate (10); manufacturing masks on the source electrode (7), the body region (3), the dielectric layer (8), the modulation plate (10), the polarization inversion layer (4) and the drain electrode (6) for the eighth time, depositing selected metal on the upper part of the dielectric layer (8) between the left side of the modulation plate (10) and the right side of the gate step (9) by using the masks to form a gate (11), wherein the width of the gate step (9) is smaller than that of the modulation plate (10) and the gate (11);
J. and selecting metal with the metal work function less than or equal to that of the grid (11), manufacturing a mask on the source electrode (7), the body region (3), the dielectric layer (8), the grid (11), the modulation plate (10), the polarization inversion layer (4) and the drain electrode (6) for the ninth time, depositing the selected metal on the grid step (9) by using the mask to form a tunneling grid (12) with the thickness larger than the depth of the grid step (9), realizing the electrical connection among the tunneling grid (12), the modulation plate (10) and the grid (11), and finishing the manufacture of the device.
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| CN201910095373.4A CN110148626B (en) | 2019-01-31 | 2019-01-31 | Polarization doped InN-based tunneling field effect transistor and manufacturing method thereof |
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