CN109411350B - Preparation method of GaN-based p-type gate structure - Google Patents

Preparation method of GaN-based p-type gate structure Download PDF

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CN109411350B
CN109411350B CN201811190170.5A CN201811190170A CN109411350B CN 109411350 B CN109411350 B CN 109411350B CN 201811190170 A CN201811190170 A CN 201811190170A CN 109411350 B CN109411350 B CN 109411350B
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徐哲
周阳
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Institute of Electronic Engineering of CAEP
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract

本发明提供一种GaN基p型栅结构的制备方法，其步骤包括：在氮化镓基材料表面涂敷光刻胶并光刻待刻蚀区域图形；采用干法刻蚀以光刻胶为掩膜，刻蚀暴露区域的GaN cap层和~90%厚度的p型栅层，去除剩余光刻胶；对处理后的氮化镓基材料进行氧化处理；将氮化镓基材料置于腐蚀性溶液中进行腐蚀，得到GaN基p型栅结构。该方法采用干法和湿法混合刻蚀，完成GaN基p型栅结构的制备；其中的湿法腐蚀解决了干法刻蚀引起的表面损伤问题，其自停止特性保证了刻蚀深度的均匀性；其中的干法刻蚀将湿法腐蚀需要刻蚀的厚度明显缩小，可大大减小单纯采用湿法腐蚀所需氧化和腐蚀时间，不仅提高了效率，更减小了侧向腐蚀效应，保证了工艺可控性。

Figure 201811190170

The present invention provides a method for preparing a GaN-based p-type gate structure, which comprises the following steps: coating a photoresist on the surface of a gallium nitride-based material and photoetching a pattern of a region to be etched; using dry etching to use the photoresist as a Mask, etch the GaN cap layer in the exposed area and the p-type gate layer with a thickness of ~90%, and remove the remaining photoresist; oxidize the treated GaN-based material; place the GaN-based material in the etching process Etched in a neutral solution to obtain a GaN-based p-type gate structure. The method adopts dry and wet mixed etching to complete the preparation of GaN-based p-type gate structure; the wet etching solves the problem of surface damage caused by dry etching, and its self-stop characteristic ensures uniform etching depth Among them, dry etching significantly reduces the thickness of wet etching, which can greatly reduce the oxidation and etching time required for wet etching, which not only improves the efficiency, but also reduces the lateral corrosion effect. Process controllability is guaranteed.

Figure 201811190170

Description

Preparation method of GaN-based p-type gate structure
Technical Field
The invention relates to the technical field of semiconductors of gallium nitride (GaN) based materials and devices, in particular to a preparation method of a GaN-based p-type gate structure.
Background
Devices based on AlGaN/GaN, InGaN/GaN, InAlGa/GaN, etc. are collectively referred to as gallium nitride-based devices, such as AlGaN/GaN Heterojunction Field Effect Transistors (HFETs), Heterojunction Bipolar Transistors (HBTs), etc. Gallium nitride-based devices have the advantages of strong breakdown field, high electron mobility, high saturation velocity, etc., and are considered to be strong competitors of next-generation power switching devices, and recently, they are favored by researchers.
However, the heterojunction structure in the material system has strong spontaneous polarization and piezoelectric polarization effects, and the GaN-based heterojunction field effect transistor based on the material system is a depletion-mode device, i.e., the threshold voltage of the GaN-based heterojunction field effect transistor is negative. In practical power conversion application, an enhanced device is more favored, and on one hand, the enhanced device can reduce the design complexity of a driving circuit; on the other hand, the enhanced device can avoid the risk of malfunction. At present, the technologies for implementing enhancement devices mainly include a fluorine ion implantation technology, a trench gate technology, a p-type gate technology, and the like. Among them, the p-type gate technology is the most mature and the most adopted technology in the commercial GaN products at present. However, at present, the p-type gate structure is still prepared by adopting a dry etching technology based on Inductive Coupling (ICP) or Reactive Ion Etching (RIE), on one hand, dry etching is easy to damage the GaN surface, which causes device performance degradation; on the other hand, the dry etching has high control difficulty of etching rate and large inconsistency of etching depth, so that the consistency of the characteristics of devices in a chip or between chips is poor, and the yield of GaN products is reduced. On the other hand, the wet etching technology for the p-type gate structure is not mature, and meanwhile, a lateral etching phenomenon is inevitably introduced in the wet etching process, so that the process controllability of the device is influenced.
Disclosure of Invention
The invention aims to provide a preparation method of a GaN-based p-type gate structure, which is based on a customized GaN epitaxial structure and provides a mixed etching technology combining a dry method and a wet method to finish the preparation of the p-type gate structure, wherein the etching of 90 +/-5% of the thickness of a p-type gate layer is finished through the dry etching, and the etching of the p-type gate layer with the residual thickness is finished through the wet etching, so that the preparation of the p-type gate structure is finished.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a preparation method of a GaN-based p-type gate structure, which comprises the following steps:
1) coating photoresist on the surface of the gallium nitride-based material, and photoetching a pattern of a region to be etched; gallium nitride based material is customization epitaxial wafer structure, customization epitaxial wafer structure includes from bottom to top: 1) an epitaxial Substrate; 2) a high resistance GaN buffer layer (GaN buffer); 3) a GaN channel layer; 4) a barrier layer; 5) a GaN cut-off layer; 6) a p-type gate layer; 7) a GaN cap layer (GaN cap);
2) etching the GaN cap layer of the area to be etched on the surface of the gallium nitride-based material and the corresponding p-type gate layer with the thickness of 90 +/-5% below the GaN cap layer by adopting a dry etching technology and taking the photoresist as a mask, and then removing the residual photoresist;
3) oxidizing the gallium nitride-based material processed in the step 2), namely oxidizing the p-type gate layer with the residual thickness after etching;
4) and putting the oxidized gallium nitride-based material into a corrosive solution for corrosion, namely, corroding the oxidized p-type gate layer to obtain the GaN-based p-type gate structure.
Further, the epitaxial substrate includes, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide substrate.
Further, the high-resistance GaN buffer layer includes, but is not limited to, a carbon-doped or iron-doped GaN layer.
Further, the barrier layer includes, but is not limited to, AlGaN, InAlN, InGaN.
Furthermore, the GaN cut-off layer is made of GaN materials and has the thickness of 2-5 nm.
Further, the p-type gate layer includes, but is not limited to, p-AlGaN, p-InAlN, and p-AlN.
Further, the thickness of the GaN capping layer is 2-5 nm.
Furthermore, the photoresist can be made of AZ5214 and the like; the photoetching adopts modes of contact photoetching and the like.
Further, the dry etching technique in step 2) includes, but is not limited to: RIE (Reactive Ion Etching) processing; and (2) ICP (Inductively coupled plasma etching).
Further, the temperature for oxidation treatment in the step 3) is 590-670 ℃, and the time is 10-20 min; the oxidation treatment is preferably carried out in a tubular annealing furnace in an oxygen atmosphere.
Further, the corrosive solution is an alkaline solution, such as a potassium hydroxide solution or a sodium hydroxide solution: the temperature is 50-90 ℃, and the corrosion time is 10-20 min.
Furthermore, the oxidation temperature of the p-type gate layer with the remaining thickness of 10% +/-5% is lower than that of the GaN stop layer below the p-type gate layer, only the p-type gate layer can be oxidized at a certain oxidation temperature, the oxidized p-type gate layer is easily corroded by alkaline solution such as KOH and the like, and meanwhile, the alkaline solution has no influence on the GaN stop layer, so that the p-type gate layer in a specific area can be selectively corroded, the p-type gate layer has self-stop characteristic, and the preparation of the GaN-based p-type gate structure is completed.
Through comparison, if the p-type gate structure is prepared by simply adopting the traditional dry etching technology, the p-type gate layer is completely (namely 100% +/-5%) removed in the step 2), but the over-etching and under-etching phenomena of the p-type gate layer can be caused due to the uneven dry etching depth (100% +/-5%), and the two-dimensional electron gas of the device is reduced due to the over-etching and the under-etching, so that the characteristic degradation of the device is caused; on the other hand, the surface of the etched material is damaged by adopting dry etching, and the dynamic characteristic of the device is seriously degraded due to the surface damage. In the step 2), the p-type gate layer with the thickness of 90 +/-5% is removed by adopting dry etching, and the p-type gate layer with the residual thickness is removed by adopting an automatic stop wet etching technology, so that the uniformity of etching is ensured, and the problems of over-etching, under-etching and surface damage caused by pure dry etching are solved.
Further, in the steps 3) and 4), only the removal of the remaining p-type gate layer is needed, if the self-stop wet etching technology is simply adopted to remove all the p-type gate layer in the step 2) instead of removing the p-type gate layer with the thickness of 90% +/-5%, because the thickness of the p-type gate layer is large (usually 100 nm), the removal of the p-type gate layer in a specific area can be completed by adopting longer oxidation time (> 120 min) and corrosion time (> 120 min) in the steps 3) and 4), and the lateral corrosion effect in the corrosion process is greatly increased due to the long-time corrosion, so that the process controllability is greatly reduced. And removing the p-type gate layer with the thickness of 90 +/-5% by dry etching in the step 2), and controlling the oxidation and corrosion time of the p-type gate layer with the residual thickness in the steps 3) and 4) within 20min, so that the lateral corrosion effect in the corrosion process is greatly reduced, and the process controllability is increased.
The invention has the following beneficial effects:
(1) compared with the traditional dry etching technology, the mixed etching technology combining the dry etching and the wet etching is adopted, the wet etching in the method solves the problem of surface damage caused by the dry etching, and on the other hand, the uniformity of etching depth is ensured because the wet etching has the self-stopping characteristic;
(2) compared with the traditional self-stopping wet etching technology, the dry etching technology is introduced to reduce the thickness to be etched in the wet etching to about 10 percent, so that the oxidation and etching time required by the wet etching can be greatly reduced, the efficiency is improved, more importantly, the lateral etching effect caused by overlong wet etching time is reduced, and the process controllability is ensured.
Drawings
Fig. 1 is a schematic view of a customized gan epitaxial structure in an embodiment of the invention.
FIG. 2 is a schematic view of the structure of a GaN-based p-type gate prepared by the present invention.
Fig. 3 is a schematic diagram of the over-etching and under-etching phenomena caused by the pure dry etching to remove the p-type gate layer.
Fig. 4 is a schematic diagram of the surface damage phenomenon caused by the pure dry etching to remove the p-type gate layer.
FIG. 5 is a schematic diagram of a lateral etching phenomenon caused by a wet etching process to remove the p-type gate layer.
FIG. 6 is a flow chart of the steps for fabricating a GaN-based p-type gate structure according to the present invention.
FIG. 7 is a diagram showing the structure of the p-AlGaN gate layer after dry etching in the embodiment, and also showing the structure of the p-AlGaN layer in the region to be etched by the wet etching.
FIG. 8 is a diagram of a structure of a GaN-based p-type gate fabricated based on a p-AlGaN gate layer in the example.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments and accompanying drawings.
A method for fabricating a GaN-based p-type gate structure, as shown in fig. 6, comprises the steps of:
1) coating photoresist on the surface of the gallium nitride-based material, and photoetching a pattern of a region to be etched; gallium nitride based material is customization epitaxial wafer structure, customization epitaxial wafer structure includes from bottom to top: the GaN-based light-emitting diode comprises an epitaxial substrate, a channel layer, a barrier layer, a GaN cut-off layer, a p-type gate layer and a GaN cap layer;
2) as shown in fig. 2, a dry etching technique is adopted, the photoresist is used as a mask, the GaN cap layer of the area to be etched on the surface of the gallium nitride-based material and the corresponding p-type gate layer with the thickness of 90% ± 5% below the GaN cap layer are etched, and then the residual photoresist is removed;
3) oxidizing the gallium nitride-based material processed in the step 2), namely oxidizing the p-type gate layer with the residual thickness after etching;
4) and putting the oxidized gallium nitride-based material into a corrosive solution for corrosion, namely, corroding the oxidized p-type gate layer to obtain the GaN-based p-type gate structure.
Further, the epitaxial substrate includes, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide substrate.
Further, the high-resistance GaN buffer layer includes, but is not limited to, a carbon-doped or iron-doped GaN layer.
Further, the barrier layer includes, but is not limited to, AlGaN, InAlN, InGaN.
Furthermore, the GaN cut-off layer is made of GaN materials and has the thickness of 2-5 nm.
Further, the p-type gate layer includes, but is not limited to, p-AlGaN, p-InAlN, and p-AlN.
Further, the thickness of the GaN capping layer is 2-5 nm.
Furthermore, the photoresist can be made of AZ5214 and the like; the photoetching adopts modes of contact photoetching and the like.
Further, the dry etching technique in step 2) includes, but is not limited to: RIE (Reactive Ion Etching) processing; and (2) ICP (Inductively coupled plasma etching).
Further, the temperature for oxidation treatment in the step 3) is 590-670 ℃, and the time is 10-20 min; the oxidation treatment is preferably carried out in a tubular annealing furnace in an oxygen atmosphere.
Further, the corrosive solution is an alkaline solution, such as a potassium hydroxide solution or a sodium hydroxide solution: the temperature is 50-90 ℃, and the corrosion time is 10-20 min.
Further, the oxidation temperature of the p-type gate layer with the remaining thickness of 10% ± 5% is lower than that of the GaN stop layer thereunder.
Through comparison, if the p-type gate structure is prepared by simply adopting the traditional dry etching technology, the p-type gate layer is completely (namely 100% +/-5%) removed in the step 2), and the over-etching and under-etching phenomena of the p-type gate layer can be caused due to the uneven dry etching depth (100% +/-5%), and as shown in fig. 3, the two-dimensional electron gas of the device can be reduced due to the over-etching and the under-etching, so that the characteristic degradation of the device can be caused; on the other hand, the surface of the etched material is damaged by adopting the dry etching method, as shown in fig. 4, and the dynamic characteristic of the device is seriously degraded due to the surface damage. In the step 2), the p-type gate layer with the thickness of 90 +/-5% is removed by adopting dry etching, and the p-type gate layer with the residual thickness is removed by adopting an automatic stop wet etching technology, so that the uniformity of etching is ensured, and the problems of over-etching, under-etching and surface damage caused by pure dry etching are solved.
Further, in the steps 3) and 4), only the removal of the remaining p-type gate layer is needed, if the self-stop wet etching technology is simply adopted to complete the removal of all the p-type gate layers in the step 2), but not to remove the p-type gate layers with the thickness of 90% ± 5%, because the thickness of the p-type gate layers is large (usually 100 nm), the removal of the p-type gate layers in a specific area in the steps 3) and 4) needs to be completed by adopting longer oxidation time (> 120 min) and etching time (> 120 min), and the lateral etching effect in the etching process is greatly increased by the long-time etching, as shown in fig. 5, so that the process controllability is greatly reduced. And removing the p-type gate layer with the thickness of 90 +/-5% by dry etching in the step 2), and controlling the oxidation and corrosion time of the p-type gate layer with the residual thickness in the steps 3) and 4) within 20min, so that the lateral corrosion effect in the corrosion process is greatly reduced, and the process controllability is increased.
The method will be specifically described below by taking GaN cap/p-AlGaN/GaN/AlGaN/GaN/Sapphire material as an example. The self-stop etching process comprises the following steps:
1) and coating photoresist on the surface of the GaN-based material, and photoetching a pattern of an etching area to be etched.
The layout adopted in the embodiment is an etching layout, and the photoresist adopted is AZ 5214; and photoetching by adopting a contact photoetching method.
2) And removing the GaN cap layer of the region to be etched and the p-AlGaN layer with the thickness of 90 percent.
The purpose of the step is to remove the partial GaN cap layer and the p-AlGaN layer to be etched, so that the subsequent oxidation and corrosion time is conveniently reduced, and the GaN cap layer in the non-etching area cannot be etched due to the protection of the photoresist. This step is performed by etching using an RIE (reactive ion etching) method.
3) The remaining photoresist is removed. And removing the photoresist by an organic cleaning method, wherein the solvent is organic solvents such as acetone, isopropanol and the like.
As shown in fig. 7.
4) And (3) placing the gallium nitride-based material obtained in the step 3) in a rapid annealing furnace in a pure oxygen environment for oxidation treatment.
The purpose of steps 1) -3) is to protect the regions not to be oxidized with a GaN cap layer before the wafer is oxidized, and the regions to be oxidized are exposed, and the oxidation is performed in this step. The temperature of the oxidation was set at 645 deg.C for 15 min.
5) And soaking the oxidized gallium nitride-based material in a potassium hydroxide solution for corrosion for 15 min.
In the step 5), the temperature of the potassium hydroxide solution is constant at 70 ℃, and the corrosion time is 15 min.
Fig. 8 is a structural diagram of a GaN-based p-type gate structure prepared based on a p-AlGaN material.
The p-type gate layer in the above embodiment is made of p-AlGaN material, and in other embodiments, p-InAlN, p-AlN, etc. may be used.
In the above embodiment, the temperature can be adjusted within 590-670 ℃ for 10-20min when the oxidation treatment is performed by the tubular annealing furnace.
In the above embodiment, the temperature can be adjusted within the range of 50-90 ℃ for 10-20min when the etching is performed by using the potassium hydroxide solution.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.

Claims (12)

1. A preparation method of a GaN-based p-type gate structure comprises the following steps:
1) coating photoresist on the surface of the gallium nitride-based material, and photoetching a pattern of a region to be etched; gallium nitride based material is customization epitaxial wafer structure, customization epitaxial wafer structure includes from bottom to top: the GaN-based high-resistance buffer memory comprises an epitaxial substrate, a high-resistance GaN buffer layer, a GaN channel layer, a barrier layer, a GaN cut-off layer, a p-type gate layer and a GaN cap layer;
2) etching the GaN cap layer of the area to be etched on the surface of the gallium nitride-based material and the corresponding p-type gate layer with the thickness of 90 +/-5% below the GaN cap layer by adopting a dry etching technology and taking the photoresist as a mask, and then removing the residual photoresist;
3) oxidizing the gallium nitride-based material processed in the step 2), namely oxidizing the p-type gate layer with the residual thickness after etching;
4) and putting the oxidized gallium nitride-based material into a corrosive solution for corrosion, namely, corroding the oxidized p-type gate layer to obtain the GaN-based p-type gate structure.
2. The method of claim 1, wherein the epitaxial substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate.
3. The method of claim 1, wherein the high-resistance GaN buffer layer is a carbon-doped or iron-doped GaN layer.
4. The method of claim 1, wherein the barrier layer is made of any one of AlGaN, InAlN, and InGaN.
5. The method of claim 1, wherein the GaN stop layer is a GaN material and has a thickness of 2-5 nm.
6. The method of claim 1, wherein the p-type gate layer is made of any one of p-AlGaN, p-InAlN, and p-AlN.
7. The method of claim 1, wherein the GaN cap layer has a thickness of 2-5 nm.
8. The method of claim 1, wherein in step 1) the photoresist is AZ5214 material; the lithography adopts contact lithography.
9. The method for fabricating a GaN-based p-type gate structure according to claim 1, wherein the etching method for removing the GaN cap layer and the p-type gate layer on the outermost surface in the step 2) employs RIE process or ICP process.
10. The method as claimed in claim 1, wherein the temperature of the oxidation treatment in step 3) is 590-670 ℃ for 10-20 min.
11. The method according to claim 1, wherein in step 3), the oxidizing treatment is performed in a tubular annealing furnace in an atmosphere of oxygen.
12. The method of claim 1, wherein the etching solution in step 4) is potassium hydroxide solution or sodium hydroxide solution, and the etching time is 10-20 min.
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