CN112542384A - Manufacturing method of gallium nitride enhanced device - Google Patents

Manufacturing method of gallium nitride enhanced device Download PDF

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CN112542384A
CN112542384A CN202011425598.0A CN202011425598A CN112542384A CN 112542384 A CN112542384 A CN 112542384A CN 202011425598 A CN202011425598 A CN 202011425598A CN 112542384 A CN112542384 A CN 112542384A
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layer
etching
gan
aln
algan
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CN112542384B (en
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王祥骏
彭立仪
邱昭玮
邱显钦
敖金平
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Ningbo Rhenium Micro Semiconductor Co ltd
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Ningbo Rhenium Micro Semiconductor Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure

Abstract

The invention provides a manufacturing method of a gallium nitride enhanced device, which adopts a combined etching technology combining dry etching and wet etching, has low destructiveness on the surface of an AlGaN/GaN shielding layer, and can accurately stop when etching is close to the AlGaN/GaN shielding layer. The method is characterized in that an AlN etching stop layer is arranged below a p-GaN layer, and then the p-GaN layer is removed by matching with composite etching. When the AlN etching stop layer is oxidized, the surface layer material is oxidized to form Al2O3The etching selection ratio is improved, the etching uniformity can be improved, and the stability of the device is further improved. In addition, compared with the traditional dry etching, the composite etching technology can effectively reduce the surface roughness of the gallium nitride enhanced device and remove the surface damage, and improves the characteristics of the turn-on resistance and breakdown voltage of the device.

Description

Manufacturing method of gallium nitride enhanced device
Technical Field
The invention relates to the technical field of semiconductor photoelectric devices, in particular to a manufacturing method of a gallium nitride enhancement device.
Background
Generally, most of the conventional power devices are mainly made of Silicon (Si), mainly because Si is a material with a large amount on earth, and is cheap and mature in technical development compared with other materials; however, due to the physical characteristics of the materials and the large leakage loss of the substrate, the materials cannot be applied to high power and high frequency circuits, so that the energy conversion efficiency of the silicon-based devices is limited, and the development center of gravity is gradually shifted to Wide bandgap (Wide bandgap) semiconductor materials.
Gallium nitride has the following advantages over silicon: such as a wider band gap (Eg), a higher breakdown field, electron mobility, electron saturation velocity, thermal conductivity, etc. The above advantages are mainly attributed to the unique polarization effect of gan, and the formation of a triangular potential well at the heterojunction between gan and algan can induce a two-dimensional electron gas (2DEG) channel with high electron mobility, which is helpful for the performance of the fet.
However, because of the primitive nature of gallium nitride materials, gallium nitride-based devices are typically depletion mode devices. If it is used as a power switch device, the design complexity in circuit application is increased to achieve low power consumption. And the new material process has more requirements for the traditional silicon process, so as to realize a device with high stability. Therefore, for gan devices, enhancement and controllability, operability and repeatability are required to facilitate industrial production.
In view of this, the invention is particularly proposed.
Disclosure of Invention
The invention aims to provide a manufacturing method of a gallium nitride enhancement type device, which can effectively improve the stability of the device and the uniformity of an etching process and is more beneficial to industrial production.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention relates to a method for manufacturing a gallium nitride enhancement device, which comprises the following steps:
1) growing an AlN nucleating layer, an AlN/GaN buffer layer and an AlGaN/GaN shielding layer on the surface of the substrate in sequence;
2) sequentially growing an AlN etching stop layer and a p-GaN layer on the surface of the AlGaN/GaN shielding layer by an epitaxial technology, wherein the AlN nucleating layer, the AlN/GaN buffer layer, the AlGaN/GaN shielding layer, the AlN etching stop layer and the p-GaN layer form an epitaxial layer;
3) defining a grid region and a non-grid region on the surface of the epitaxial layer, and taking the non-grid region as an etching region;
4) removing the p-GaN layer in the non-grid region by adopting composite etching;
5) depositing a metal layer on the surface of the p-GaN layer of the grid region and preparing grid metal;
6) and depositing a metal layer on the surface of the AlGaN/GaN shielding layer and preparing source metal and drain metal.
Further, the AlN nucleation layer and the AlN/GaN buffer layer in step 1) are selectively prepared, i.e., the AlN nucleation layer and/or the AlN/GaN buffer layer may not be grown.
Further, the p-GaN layer in the step 2) forms a gate region after etching, and the gate region is a main layer of the enhancement type device. The AlN layer is an etching stop layer and used for enhancing the stability of the gallium nitride enhancement type device, and the AlGaN or GaN layer is used as a shielding layer to control the formed 2 DEG.
Further, step 3) defines the grid region and the non-grid region through a yellow light lithography process, and comprises the steps of gluing, exposing, developing, drying, etching, stripping and detecting. The method mainly aims to reserve an AlN etching stop layer and a p-GaN layer in a grid electrode area, and eliminate 2DEG channel electrons through the p-GaN layer to realize a gallium nitride enhancement type device.
Further, the composite etching in the step 4) is performed on the p-GaN layer and the AlN etching stop layer in the non-gate region, and the photoresist in the gate region is etched to remove the excess photoresist after the composite etching is completed.
The composite etching comprises dry etching and wet etching. Since the gallium nitride material has noThe method directly carries out wet etching, so the invention firstly oxidizes the surface of the p-GaN layer into Ga by dry etching2O3The oxidized surface is then removed by wet etching. The acid solution used in the wet etching process is a hydrochloric acid solution, a hydrofluoric acid solution or a BOE etching solution (a buffered oxide etching solution formed by mixing 49% of hydrofluoric acid and water or ammonium fluoride and water), and the concentration of the acid solution can be adjusted to keep a certain etching rate. An alkaline etching solution, such as a mixed solution containing hydrogen peroxide and potassium hydroxide, cannot be used because the alkaline etching solution damages the AlGaN/GaN shield layer. If hydrochloric acid solution is selected, the reaction equation of the hydrochloric acid solution and the oxide layer is shown as the formula (1):
Ga2O3+6HCl=2GaCl3+3H2O (1)
the above process of performing the primary dry etching and the wet etching is referred to as performing the primary composite etching, which is referred to as 1cycle for short. The thickness of the gallium nitride corroded by 1cycle is 2-6 nm, and if the gallium nitride with the thickness of 60nm needs to be corroded, 5-30 cycles are expected to be needed.
In an embodiment of the invention, in the step 4), an inductively coupled plasma spectrometer (ICP machine) or a Reactive Ion Etching (RIE) technology is used for the first stage dry etching oxidation step, and O is introduced into the etching equipment2Or N2And performing a GaN oxidation process by using O gas. The etching ICP power is 20-40W, the cavity pressure is 50-70mTorr, the gas flow is 20-40sccm, and the etching time is 120-170 s. In the process, the surface of the p-GaN layer is oxidized into Ga2O3The thickness of the oxide layer is about 4 nm; the second stage is a wet etching process, in which an acid solution reacts with the oxide layer on the surface of the p-GaN layer to remove the oxide layer for about 120 seconds. The compound etching is carried out for 15 times, and the etching depth which can be achieved is about 60 nm.
And after the etching of the p-GaN layer is finished, the etching AlN etching stop layer is etched by adopting a combined type of dry etching and wet etching. In the dry etching stage O2Or N2Formation of Al from O gas and AlN2O3However, Al2O3Is a stable interface oxide layer with a higher etching rate in a wet etching process using an acidic solutionSlow, thus avoiding the etching of the AlGaN/GaN shield layer during wet etching.
Further, step 5) defines a gate region by contact lithography, mainly by patterning the p-GaN layer. And then sequentially depositing Ni/Au on the p-GaN layer by electron beam evaporation, stripping the photoresist and the metal by a lift-off process, and only keeping the Ni/Au layer on the p-GaN layer as the grid metal.
Further, step 6) defines a source/drain contact hole pattern by a contact lithography technique. Then Ti/Al/Ni/Au is deposited on the AlGaN/GaN shielding layer in sequence through electron beam evaporation, photoresist and metal are stripped through lift-off process, and then the metal is annealed at 875 ℃ for 30 seconds by utilizing rapid thermal annealing process to form source metal and drain metal and ohmic contact between the metal and the AlGaN/GaN shielding layer.
Drawings
Fig. 1 is a diagram of an epitaxial layer structure of a gan enhancement device of the present invention.
FIG. 2 is a structural diagram of an epitaxial layer of a gate structure formed by compound etching in a non-gate region according to the present invention.
Fig. 3 shows a gate metal structure of a gan enhancement mode device of the present invention.
Fig. 4 shows a source-drain metal structure of the gan enhancement device of the present invention.
Where 1 is an AlGaN/GaN shield layer, 2 is an AlN etch stop layer, 3 is a p-GaN layer, 4 is a gate metal, and 5 is a source metal and a drain metal.
FIG. 5 is a graph showing the etching rate of the p-GaN layer and the AlN etching stop layer during the composite etching in the embodiment of the invention.
FIG. 6 is an atomic force microscope image of a sample reflecting surface roughness in an example of the invention.
FIG. 7 is a graph showing the output characteristics of an enhancement device according to an embodiment of the present invention.
FIG. 8 is a breakdown voltage characteristic of an enhancement mode device according to an embodiment of the invention.
Detailed Description
According to the manufacturing method of the gallium nitride enhanced device, the combined type etching technology combining dry etching and wet etching is adopted, the destructiveness on the surface of the AlGaN/GaN shielding layer is low, and the gallium nitride enhanced device can be accurately stopped when etching is close to the AlGaN/GaN shielding layer. The principle of the method is as follows: and arranging an AlN etching stop layer below the p-GaN layer, and then removing the p-GaN layer by matching with the composite etching. When the AlN etching stop layer is oxidized, the surface layer material is oxidized to form Al2O3The etching selection ratio is improved, the etching uniformity can be improved, and the stability of the device is further improved. In addition, compared with the traditional dry etching, the composite etching technology can effectively reduce the surface roughness of the gallium nitride enhanced device and remove the surface damage, and can improve the characteristics of the turn-on resistance and breakdown voltage of the device.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.
The figure is a description of the process for gallium nitride enhancement devices:
fig. 1 is a view showing the structure of an epitaxial layer of the gallium nitride enhancement device of the present embodiment, which is grown by Metal Organic Chemical Vapor Deposition (MOCVD) on a low resistivity 6-inch silicon-based (111) p-type substrate. For high breakdown voltage considerations, a 4 μm thick AlN nucleation layer and AlN buffer layer were first grown on the silicon substrate. Then, an AlGaN shield layer denoted by 1 was grown to a thickness of 12nm and made of Al0.17Ga0.83N; mark 2 is an AlN etching stop layer with a thickness of about 1 nm; denoted as p-GaN layer with a thickness of 60nm and a Mg doping concentration of 3e19 cm-3. And growing an AlN nucleating layer, an AlN buffer layer, an AlGaN shielding layer 1, an AlN etching stop layer 2 and a p-GaN layer 3 in sequence to finish the epitaxial structure.
FIG. 2 is a structural diagram of an epitaxial layer for forming a gate structure after performing a hybrid etching process on a non-gate region. The specific process comprises coating a photoresist layer on the surface of the p-GaN layer 3 of the epitaxial structure shown in FIG. 1, transferring the etching pattern to the surface of the photoresist layer by exposure and development, and removing the photoresist outside the gate region. Then, a gate region and a non-gate region are defined on the surface of the p-GaN layer 3 by photolithography. The gate region and the non-gate region may also be referred to as an etched region and a non-etched region, wherein the gate region is a non-etched region corresponding to the AlN etch stop layer 2 and the p-GaN layer 3 in fig. 2 and 3, and the non-gate region is an etched region corresponding to the portions of the AlN etch stop layer 2 and the p-GaN layer 3 removed in fig. 2 and 3.
After the gate region and the non-gate region are defined, the p-GaN layer 3 in the non-gate region is removed by hybrid etching. In the first stage, N is introduced through dry etching process2And oxidizing the surface of the p-GaN layer 3 by O gas, wherein the etching ICP power is 30W, the cavity pressure is 60mTorr, the gas flow is 20-40sccm, and the etching time is 150 s. The GaN is oxidized to obtain Ga2O3About 4nm thick; second stage removing Ga by wet etching process2O3And oxide, wherein the process is carried out by using HCl solution, the volume ratio of HCl to water in the HCl solution is 10:1, and the wet etching time is about 120 seconds. The p-GaN layer 3 with the thickness of about 4nm is removed through the two steps, and 15 times of composite etching process is needed according to the thickness of the p-GaN layer 3 of 60 nm. After the p-GaN layer 3 is etched, the AlN etching stop layer 2 is etched by adopting dry etching and wet etching. In the dry etching stage O2Or N2Formation of Al from O gas and AlN2O3However, Al2O3Is a stable interface oxide and is difficult to remove by HCl wet etching. It is still possible to leave a portion of the AlN etch stop layer 2 in the non-gate regions of fig. 2-4.
Fig. 5 reflects the etch rates of the p-GaN layer 3 and the AlN etch stop layer 2. Wherein the abscissa is the number of times of the compound etching and the ordinate is the etching depth. It can be seen that at the stage of etching the p-GaN layer 3, the etching depth and the number of times of the composite etching are almost linear, and when the 15 th composite etching is performed, the p-GaN layer 3 in the non-gate region has been completely etched. The etching depth is almost unchanged with the increase of the times of the compound etching, which shows that the AlN etching stop layer 2 is difficult to remove by etching, thereby protecting the AlGaN shielding layer 1.
FIG. 3 shows the gate metal process of the GaN enhancement device of this embodiment, in which Ni/Au is deposited as the gate metal on the surface of the p-GaN layer 3 in the gate region by electron beam evaporation. Denoted 4 is the gate metal, with a Ni layer thickness of 25nm and an Au layer thickness of 120 nm.
FIG. 4 shows the drain/source metal process of the GaN enhancement device of this embodiment, in which multiple Ti/Al/Ni/Au layers are evaporated on the surface of the AlGaN shielding layer 1 by electron beams to serve as the source and drain metals. The source and drain metals are denoted 5, where the Ti layer is 30nm thick, the Al layer is 125nm thick, the Ni layer is 50nm thick, and the Au layer is 200nm thick. And then rapidly thermally annealed at 750 deg.c for 20 minutes to form an ohmic contact.
FIG. 6 is a perspective view of the surface roughness of the device through an atomic force microscope, and it can be observed that FIG. a is the device obtained by the composite etching process, and the average surface roughness is 0.273 nm; and the figure b shows the device obtained by the dry etching process, the average surface roughness of which is 0.401nm, which shows that the composite etching can effectively reduce the surface roughness.
Fig. 7 is an output characteristic curve of the resulting enhancement mode device, where the abscissa of the left graph of fig. a is the gate voltage (Vgs) and the ordinate is the drain current (Id); the abscissa of the right graph of the graph a is the channel voltage (Vds), and the ordinate is the channel current (Ids). Graph b is a statistic of the channel resistance of 30 devices versus different etch techniques. As can be seen from fig. 7, the threshold voltage of the device in this embodiment is about 1.7V, the channel resistance is about 14.6 Ω · mm, and it can be observed that the device stability can be improved by the composite etching.
Fig. 8 is a breakdown voltage characteristic curve of the resulting enhancement mode device, with gate-source voltage (Vds) on the abscissa and drain current (Id) on the left ordinate. It can be observed that the breakdown voltage of the device obtained by the composite etching is 423V, and the breakdown voltage obtained by the dry etching process is 352V, which shows that the composite etching can reduce the surface damage and improve the breakdown voltage characteristic of the device.
The gallium nitride-based material in the above embodiment is p-GaN/AlN/AlGaN, and in other embodiments, gallium nitride-based materials such as p-GaN/AlN/InAlN, p-AlGaN/AlN/AlGaN, etc. may also be used.
In the embodiment of FIG. 2, N is2O oxidizing gas O may also be used in other embodiments2The oxidizing material, the HCl ratio in the wet etching process can be adjusted, and the acidic solution can also be BOE (buffer oxide etch) or HF solution.
In the embodiment of FIG. 3, the thickness of the gate metal 4Ni/Au (50/100nm) can be changed as appropriate, and Pt/Au, TiN, etc. can be used; the method of depositing the gate metal 4 may be sputtering or the like, in addition to electron beam evaporation.
In the above example, the thickness of the deposited source and drain metals 5Ti/Al/Ni/Au (30nm/125nm/50nm/200nm) may be changed as appropriate, and the metal may be Ti/Al/Ti/Au, Ti/Al/Ti/TiN, or the like. The annealing temperature and time may also be appropriately adjusted.
The gallium nitride enhancement device obtained by the composite etching of the invention is taken as an embodiment. The gallium nitride enhancement type device obtained by the conventional dry etching is used as a comparative example 1, an AlN etching stop layer is not prepared in the epitaxial layer preparation process, only dry etching is carried out in the etching process, wet etching is not carried out, and the other preparation processes are the same as the embodiment. The gallium nitride enhancement device obtained by the composite etching of the invention without preparing the AlN etching stop layer was used as comparative example 2. A conventional dry etch was used, but the AlN etch stop layer was prepared to yield an enhancement mode device of gallium nitride as comparative example 3. The results of the performance tests of the above devices are shown in table 1.
TABLE 1
Figure BDA0002824698220000071
Figure BDA0002824698220000081
The larger the on/off current difference (Ion/Ioff), the better, and the smaller the Subthreshold current (s.s), the better, indicating that the surface defects of the device are less. The smaller the on-resistance value (Ron) is, the better the Breakdown voltage value (Breakdown voltage) is.
The data in table 1 show that the addition of the AlN etch stop layer can improve the etch uniformity, so the etch uniformity of the devices of example 1 and comparative example 3 is better, and the etch uniformity of comparative example 1 is significantly reduced compared to example 1. The composite etch can improve device performance as demonstrated by higher on/off current difference, lower subthreshold current, lower on-resistance and higher breakdown voltage between example 1 and comparative example 2. In summary, the gan enhancement mode device of embodiment 1 has the best etching uniformity and device performance.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (10)

1. A method of fabricating a gallium nitride enhancement device, comprising the steps of:
1) growing an AlN nucleating layer, an AlN/GaN buffer layer and an AlGaN/GaN shielding layer on the surface of the substrate in sequence;
2) sequentially growing an AlN etching stop layer and a p-GaN layer on the surface of the AlGaN/GaN shielding layer by an epitaxial technology, wherein the AlN nucleating layer, the AlN/GaN buffer layer, the AlGaN/GaN shielding layer, the AlN etching stop layer and the p-GaN layer form an epitaxial layer;
3) defining a grid region and a non-grid region on the surface of the epitaxial layer, and taking the non-grid region as an etching region;
4) removing the p-GaN layer in the non-grid region by adopting composite etching;
5) depositing a metal layer on the surface of the p-GaN layer of the grid region and preparing grid metal;
6) and depositing a metal layer on the surface of the AlGaN/GaN shielding layer and preparing source metal and drain metal.
2. The method of claim 1, wherein step 3) defines the gate region and the non-gate region by photolithography.
3. The method of claim 1, wherein the composite etching of step 4) comprises dry etching and wet etching.
4. The method of claim 3, wherein the dry etching is by N2O or O2Oxidizing the surface of the p-GaN layer into Ga by gas2O3
5. The method as claimed in claim 4, wherein the etching ICP power is 20-40W, the chamber pressure is 50-70mTorr, the gas flow is 20-40sccm, and the etching time is 120-.
6. The method of claim 3, wherein the wet etching comprises etching Ga from the surface of the p-GaN layer by an acidic solution2O3And (6) corrosion.
7. The method of claim 6, wherein the acidic solution is a hydrochloric acid solution, a hydrofluoric acid solution, or a BOE etching solution.
8. The method of claim 1, wherein the photoresist on the surface of the p-GaN layer in the gate region is removed after the composite etching in step 4) is completed.
9. The method of claim 1, wherein the gate metal of step 5) is a Ni/Au layer.
10. The method of claim 1, wherein the source metal and drain metal of step 6) are Ti/Al/Ni/Au layers and form ohmic contact with the AlGaN/GaN shield layer.
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Cited By (1)

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CN116613065A (en) * 2023-04-28 2023-08-18 深圳智慧脑科技有限公司 Enhanced gallium nitride HEMT device and manufacturing method

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