CN111370470B - Gallium nitride MIS grid-control mixed channel power field effect transistor and manufacturing method thereof - Google Patents

Gallium nitride MIS grid-control mixed channel power field effect transistor and manufacturing method thereof Download PDF

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CN111370470B
CN111370470B CN202010169775.7A CN202010169775A CN111370470B CN 111370470 B CN111370470 B CN 111370470B CN 202010169775 A CN202010169775 A CN 202010169775A CN 111370470 B CN111370470 B CN 111370470B
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gallium nitride
layer
channel
gate
vertical channel
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CN111370470A (en
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周琦
杨秀
黄芃
魏鹏程
陈匡黎
李翔宇
王景海
韩晓琦
陈万军
张波
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University of Electronic Science and Technology of China
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Abstract

The invention relates to the technical field of semiconductor devices, in particular to a gallium nitride MIS gate control mixed channel power field effect transistor and a manufacturing method thereof. The invention adopts a mixed channel technology combining a planar two-position electron planar channel and a quasi-vertical U-shaped gallium nitride material channel, and improves the conduction characteristic of a device by respectively utilizing the quick switching characteristic of two-dimensional electron gas and the high-current characteristic of a gallium nitride material; meanwhile, on the hetero-epitaxial gallium nitride substrate, depletion voltage resistance and electric field modulation under the device turn-off state are realized by introducing the P-type gallium nitride modulation region, and the breakdown voltage of the device is improved. The invention fully utilizes the advantages of the bulk material property of the gallium nitride material and the two-dimensional electron gas generated by the polarization effect of the III-V group semiconductor material, improves the conduction performance of the gallium nitride device, and provides an excellent solution for realizing the gallium nitride power field effect device with high current, high voltage resistance and rapid switching property.

Description

Gallium nitride MIS grid-control mixed channel power field effect transistor and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a gallium nitride metal oxide semiconductor mixed channel power field effect transistor and a manufacturing method thereof.
Background
As a representative of the third generation wide bandgap semiconductor, gallium nitride (GaN) has many excellent characteristics: high critical breakdown field (-3.5 x 10)6V/cm), high electron mobility (2000 cm)2V.s), high two-dimensional electron gas (2DEG) concentration (-1013cm-2) And good high temperature working capability, etc. AlGaN/GaN heterojunction based High Electron Mobility Transistors (HEMTs) (or heterojunction field effect transistors HFETs, modulation doped field effect transistors MODFETs, hereinafter referred to as HEMT devices) have been used in the semiconductor field, especially in the radio frequency/microwave field of wireless communication, satellite communication, etc. In addition, the power device based on the wide bandgap GaN material has the characteristics of high reverse blocking voltage, low forward on resistance, high working frequency, high efficiency and the like, and can meet the requirements of a power electronic system on higher power, higher frequency, smaller volume, lower power consumption and worse working environment of a semiconductor device.
GaN power field effect transistor products, typically HFETs, have been produced, however, the breakdown voltage has not yet reached the desired level. Since the breakdown voltage rises with the area of the device, the improvement of the breakdown voltage of the device is based on the sacrifice of the current density of the device. And as the length of the drift region of the HFET rises, the on-resistance of the device is accelerated due to the parasitic parameters and defects of the drift region of the device, and the performance of the device is seriously influenced. In view of the above, the academic and industrial fields propose a solution to the vertical GaN device. However, GaN vertical devices also have limitations in achieving advanced through-voltage high current density GaN-based power devices. This limits the commercialization of GaN vertical devices due to the extremely high cost of materials required to fabricate vertical GaN power devices and the limited epitaxial thickness. Meanwhile, the mobility of the GaN bulk material is only about 800cm2The channel resistance is increased and the switching frequency is reduced compared with the planar GaN HFET deviceTo be improved. Therefore, the design of the bulk material GaN power device with higher switching frequency and thinner drift region has important practical significance for the application of the GaN semiconductor device in the power field.
Disclosure of Invention
Aiming at the problems existing in the vertical power field effect transistor made of the traditional gallium nitride material and the planar gallium nitride HFET (high frequency field effect transistor), the invention provides a novel gallium nitride MIS (metal-insulator-semiconductor) grid-control mixed channel power field effect transistor which has the advantages of good in-vivo electric field distribution, high breakdown voltage, low channel resistance, large current tolerance, high switching speed and good switching-off characteristics.
In order to achieve the purpose, the invention adopts the following technical scheme:
a gallium nitride MIS grid-control mixed channel power field effect transistor is disclosed, as shown in figure 1, comprising a heterogeneous substrate 1 containing a stress modulation structure, a transverse gallium nitride epitaxial layer 2 arranged on the upper surface of the heterogeneous substrate 1, a vertical channel layer 3 and a P-type gallium nitride electric field modulation region 4 which are arranged on the upper surface of the transverse gallium nitride epitaxial layer 2, a gallium nitride buffer layer 5 positioned on the vertical channel layer 3 and the P-type gallium nitride electric field modulation region 4, and an aluminum gallium nitride barrier layer 6 positioned on the gallium nitride buffer layer 5, wherein the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6 form a heterojunction barrier layer, and a passivation layer 11 covers the upper surface of the aluminum gallium nitride barrier layer 6; the P-type gallium nitride electric field modulation region 4 is positioned in the vertical channel layer 3, namely the vertical channel layer 3 is arranged on two sides of the P-type gallium nitride electric field modulation region 4, and the heterojunction barrier layer can generate two-dimensional electron gas; the metal electrodes comprise a source electrode 9, a drain electrode 10, a vertical channel grid electrode 81 and a plane channel grid electrode 82, wherein the drain electrode 10 is positioned on one side of an upper layer of the transistor, the vertical channel grid electrode 81 is positioned on the other side of the upper layer of the transistor, the source electrode 9 and the plane channel grid electrode 82 are positioned between the drain electrode 10 and the vertical channel grid electrode 81, the plane channel grid electrode 82 is positioned on one end close to the drain electrode 10, and the source electrode 9 is positioned between the plane channel grid electrode 82 and the vertical channel grid electrode 81; the upper part of the drain electrode 10 extends to the direction close to the plane channel gate 82 and covers part of the passivation layer 11, the middle part of the drain electrode 10 vertically extends downwards along the side surfaces of the passivation layer 11, the aluminum gallium nitride barrier layer 6 and the gallium nitride buffer layer 5, and the bottom part of the drain electrode 10 extends to the direction far away from the plane channel gate 82 and covers part of the upper surface of the vertical channel layer 3; the planar channel gate 82 and the source 9 are both of a trench structure, wherein the bottom of the source 9 extends to be in contact with the upper surface of the P-type gallium nitride electric field modulation region 4, the bottom of the planar channel gate 82 extends to the upper layer of the gallium nitride buffer layer 5, the planar channel gate 82 is isolated from the passivation layer 11, the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6 through gate dielectric layers, and the upper parts of the planar channel gate 82 and the source 9 extend towards two sides along the surface of the passivation layer 11; the upper part of the vertical channel gate 81 extends to one side close to the source electrode 9 along the surface of the passivation layer 11, the middle part of the vertical channel gate 81 vertically extends to the upper part of the gallium nitride buffer layer 5 along the side surfaces of the passivation layer 11 and the aluminum gallium nitride barrier layer 6 and extends to one side far away from the source electrode 9, and the vertical channel gate 81 is isolated from the passivation layer 11, the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6 through gate dielectric layers; the gate dielectric layers 7 of the gate electrodes 81 and 82 extend towards the passivation layer 11 material, and the electrode metals of the gate electrodes 81 and 82 extend towards the passivation layer 11 for a shorter distance than the gate dielectric layers 7.
Further, the vertical channel layer 3 is made of gallium nitride, and the aluminum component of the aluminum gallium nitride barrier layer 6 can be selected from 0 to 1.
Further, the gallium element in the aluminum gallium nitride barrier layer 6 can be replaced by one of gallium, indium or gallium indium compound.
Further, the gate dielectric layer 7 is one or a combination of more of silicon dioxide, silicon nitride, aluminum oxide, magnesium oxide and hafnium oxide, and the thickness thereof may be 1-100 nm.
Further, the metal material used for the gates 81 and 82 includes any one or any combination of nickel, gold, iridium, platinum, palladium, molybdenum, cesium, beryllium, tungsten, titanium nitride, tantalum, and tantalum nitride.
Furthermore, the vertical current channel formed by the vertical channel layer 3 and the planar current channel formed by the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6 are simultaneously current channels of the device and are controlled to be turned on or turned off along with the gate voltage.
Furthermore, the P-type gallium nitride electric field modulation layer plays a role in modulating electric fields of the planar channel and the vertical channel in depletion and opening states.
The manufacturing method of the novel gallium nitride MIS grid-control mixed channel power field effect transistor is characterized by comprising the following steps of:
the first step is as follows: sequentially epitaxially growing a transverse gallium nitride epitaxial layer 2 and a vertical channel layer 3 on a substrate 1;
the second step is that: and (3) secondarily extending a P-type gallium nitride material in the etched groove in the vertical channel layer 3 by adopting a secondary extension technology to form a P-type gallium nitride electric field modulation region 4, and secondarily flattening: the scheme of combining the chemical mechanical polishing technology and the digital etching is adopted, the characteristics of high planarization speed and low cost of the chemical mechanical polishing are utilized, and the characteristic of low damage of the digital etching to the semiconductor material is utilized;
the third step: adopting a secondary epitaxy technology to grow a gallium nitride buffer layer 5 and an aluminum gallium nitride barrier layer 6 again, and depositing a passivation layer 11;
the fourth step: and (3) adopting a groove etching technology to etch grooves needed by the vertical channel grid 81 and the plane channel grid 82, wherein the step only needs one-time photoetching: the aluminum gallium nitride barrier layer 6 needs to be completely etched to ensure that the transverse two-dimensional electron gas channel can be completely exhausted;
the fifth step: the required gate dielectric 7 is deposited by using photolithography and chemical vapor deposition. After depositing the gate dielectric, carrying out high-temperature rapid thermal annealing at 400-500 ℃ for 10-15 min;
and a sixth step: adopting a groove etching technology to etch grooves required by the source electrode 9 and the drain electrode 10, and completely etching the gallium nitride buffer layer 5, the aluminum gallium nitride barrier layer 6 and the passivation layer 11;
the seventh step: in the grooves of the source electrode and the drain electrode, on the upper surfaces of the vertical channel layer 3 and the P-type aluminum gallium nitride 4, ohmic metals required by the source electrode 9 and the drain electrode 10 are deposited on the side walls of the grooves of the gallium nitride buffer layer 5, the aluminum gallium nitride barrier layer 6 and the passivation layer 11 (a two-dimensional electronic gas channel formed by the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6), and high-temperature rapid thermal annealing is carried out in a pure nitrogen atmosphere to respectively finish the preparation of the source electrode 9 and the drain electrode 10;
eighth step: after the photolithography technique is adopted, schottky metal is deposited in the vertical channel gate groove and the horizontal channel gate groove, the preparation of the electrode in the vertical channel gate 81 and the horizontal channel gate 82 is completed, and the vertical channel gate 81 and the horizontal channel gate 82 form a schottky metal/insulating medium/semiconductor MIS gating structure.
The invention combines a horizontal two-dimensional electron gas channel and a vertical body material channel, utilizes the regulation and control function of a metal-insulating medium-semiconductor gate structure on threshold voltage, utilizes the depletion function of introducing a P-type gallium nitride electric field modulation layer 4 on a vertical channel and a gallium nitride buffer layer and a double-gate structure which is subjected to single etching and introduces Schottky metal to realize the depletion on the horizontal/vertical channel, realizes the electron accumulation effect of horizontal channel electrons on the gallium nitride buffer layer and the vertical channel on the interface of the vertical channel layer and the gallium nitride buffer layer by changing the gate voltage, realizes the effective on-off control on a gate control channel, forms an MIS structure and realizes an enhanced device; according to the invention, the two-dimensional electron gas channel of the device in the horizontal direction is introduced, so that the current flows in the starting state of the device and the switching speed of the device is higher; the invention realizes the improvement of the current tolerance of the device by introducing the vertical channel and solves the problem of insufficient current density of the gallium nitride power device; the invention utilizes the structure of symmetrical double vertical channels, and realizes higher device withstand voltage through a U-shaped current path under the condition of fixing the epitaxial thickness of the vertical channels; the invention realizes the modulation of the electric field of the device in the off state by introducing the P-type gallium nitride electric field modulation layer 4, forms a space charge area with a vertical current layer material, changes the direction of the electric field of the device, and simultaneously realizes the improvement of the withstand voltage of the device by utilizing the modulation of the horizontal channel electric field peak; the invention realizes the alleviation of the electric field peak at the sharp corner of the P-type gallium nitride electric field modulation layer by introducing the transverse gallium nitride epitaxial layer 2 with higher doping concentration. A
The invention has the advantages of high reverse voltage resistance, high on-current, enhanced threshold voltage, rapid turn-on and turn-off, high current tolerance and the like, and the selected substrate and the manufacturing process are compatible with the traditional gallium nitride heterojunction HEMT device.
Drawings
FIG. 1 is a schematic diagram of the structure of a GaN MIS gated hybrid channel power field effect transistor of the present invention;
FIG. 2 is a schematic structural diagram of a GaN MIS gate-controlled hybrid channel power field effect transistor according to the present invention after a lateral GaN epitaxial layer 2 and a vertical channel layer 3 are formed on the upper surface of the substrate;
FIG. 3 is a schematic diagram of a structure of a P-type GaN electric field modulation layer 4 with a groove required in the process flow of the GaN MIS gate-controlled hybrid channel power field effect transistor of the present invention;
FIG. 4 is a schematic structural diagram of a GaN MIS gate-controlled hybrid channel power field effect transistor after regrowth of a P-type GaN electric field modulation layer in the process flow of the present invention;
FIG. 5 is a schematic view of the planar GaN buffer layer, GaN barrier layer and passivation layer after epitaxial-deposition in the process flow of the GaN MIS gated hybrid channel power FET of the present invention;
FIG. 6 is a schematic structural diagram of a GaN MIS gate-controlled hybrid channel power field effect transistor after formation of a recess required for a gate by etching in a process flow of the invention;
FIG. 7 is a schematic structural diagram of a GaN MIS gated hybrid channel power FET after a dielectric layer is grown in a recess of a gate electrode in the process flow of the present invention;
FIG. 8 is a schematic structural diagram of a GaN MIS gate-controlled hybrid channel power field effect transistor after formation of grooves required for source and drain etching in the process flow of the present invention;
FIG. 9 is a schematic diagram of a structure formed by depositing ohmic metal for a source and a drain in a recess in a process flow of the GaN MIS gated hybrid channel power FET of the present invention;
FIG. 10 is a schematic diagram of a process flow for forming a GaN MIS gated hybrid channel power FET with a gate Schottky metal deposited in a recess in accordance with the present invention;
FIG. 11 is a schematic diagram of a conventional quasi-vertical GaN MIS gated power field effect transistor;
FIG. 12 is a schematic diagram of a conventional vertical GaN MIS gated power field effect transistor;
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
the invention provides a high-performance gallium nitride MIS gate-controlled power field effect transistor, which is different from the traditional vertical/quasi-vertical gallium nitride MIS gate-controlled power field effect transistor, and introduces a mixed channel structure and a U-shaped current path, namely a bulk current path from top to bottom through a transverse gallium nitride layer and then from bottom to top and a plane current path from a drain electrode to a source electrode; compared with the traditional vertical/quasi-vertical gallium nitride MIS grid-controlled power field effect transistor, the vertical current channel is repeatedly utilized by the current path of the device through the U-shaped channel, the length of the drift region of the device is equivalently prolonged, the breakdown voltage of the device is improved, the current density of partial devices is reduced, meanwhile, the switching speed of the device and the current density of the device are improved through the two-dimensional electron gas plane channel formed by the gallium nitride buffer layer on the surface and the aluminum gallium nitride barrier layer, and the breakdown voltage and the total current density of the device are macroscopically improved. In accordance with basic semiconductor principles, a major technical problem with planar gan devices, such as HFETs, having a low breakdown voltage is that the electric field is concentrated at the gate drain, leading to premature breakdown of the device. Therefore, the field plate technology, the back potential barrier technology and other technologies are used for modulating the electric field intensity of the grid drain terminal of the device, and for the high-performance gallium nitride MIS grid-controlled power field effect transistor provided by the invention, the electric field distribution of the horizontal channel grid side and the electric field distribution of the vertical channel of the device are modulated simultaneously by introducing the P-type gallium nitride electric field modulation layer, so that the electric field uniformity of the vertical channel and the plane channel in the turn-off state is realized, and the breakdown voltage of the device is improved.
As shown in fig. 1, the gan MIS gate-controlled hybrid channel power fet of the present invention includes a hetero-substrate 1 (silicon-based substrate) with a stress modulation structure, a lateral gan epitaxial layer 2 disposed on the upper surface of the substrate 1, a vertical channel layer 3 and a P-type gan electric field modulation region 4 disposed on the upper surface of the epitaxial layer 2 and based on gan material, and a hetero-junction gan barrier layer (a gan buffer layer 5 and an algan barrier layer 6) disposed on the vertical channel layer 3 and the P-type gan electric field modulation region 4, wherein a passivation layer 11 is disposed on the algan barrier layer 6, and the hetero-junction barrier layer can generate two-dimensional electron gas; the metal electrode comprises a vertical channel grid 81, a plane channel grid 82, a source electrode 9 and a drain electrode 10, a grid dielectric layer 7 exists under the grid 81 and the grid 82, wherein the source electrode 9 and the drain electrode 10 are in ohmic contact, the grid 81 and the grid 82 are in Schottky contact, and the source electrode 9 and the drain electrode 10 are connected with the side wall of the groove; the P-type gallium nitride electric field modulation region needs to cover and exceed the gate plane channel 82; the gate dielectric layers 7 of the gate electrodes 81 and 82 extend towards the material of the passivation layer 11, and the distance that the electrode metal of the gate electrodes 81 and 82 extends towards the passivation layer 11 is shorter than that of the gate dielectric layers 7; the gallium element of the aluminum gallium nitride barrier layer 6 may be replaced by one of gallium, indium or gallium indium compound.
The working principle of the invention is as follows:
because the P-type gallium nitride electric field modulation layer and the Schottky gate metal have depletion effects on the gallium nitride buffer layer and the vertical channel layer, the heterojunction formed by the gallium nitride buffer layer and the aluminum gallium nitride barrier layer is over-etched, the vertical gate control channel and the planar channel of the device are depleted at the moment, the channel is pinched off, and the device is in a turn-off state. When the grid voltage rises, the relative position of the Fermi level rises, and an electron accumulation effect occurs in a side wall formed by the vertical channel grid electrode groove, a space charge area formed between the vertical channel grid electrode groove and the P-type gallium nitride electric field modulation layer and a gallium nitride buffer layer contacted with the side wall and the groove bottom of the planar channel grid electrode groove, so that a device channel is opened. When the device is in an off state, the channel of the device begins to be depleted along with the rise of the drain voltage, on one hand, for the vertical channel of the device, the rise of the drain voltage causes the space charge region formed between the P-type gallium nitride electric field modulation layer and the vertical channel to expand, the direction of the electric field is modulated from the vertical direction into the electric field with a horizontal component, and under the condition of the same drift region thickness (the thickness of the vertical channel layer), the vertical channel of the device can obtain higher breakdown voltage due to the change of the direction of the electric field; on the other hand, for the planar channel, as the drain voltage rises, the P-type gallium nitride electric field modulation region generates depletion effect on the two-dimensional electron gas channel to form channel depletion effect, the horizontal channel generates a space charge region, the electric field distribution tends to be uniform, and the breakdown voltage of the horizontal two-dimensional electron gas channel of the device rises. Therefore, the breakdown voltage of the horizontal channel and the breakdown voltage of the vertical channel of the device can be simultaneously improved by introducing the P-type gallium nitride electric field modulation region, and the performance of the device is improved.
Example (b):
fig. 2 to 10 are schematic diagrams of steps of a manufacturing process of a gallium nitride MIS gate-controlled hybrid channel power field effect transistor of the present invention, and the process flow is as follows:
(1) utilizing a metal organic compound chemical vapor deposition technology, sequentially epitaxially growing a transverse gallium nitride epitaxial layer 2 and a vertical channel layer 3 on the upper layer of a substrate 1, as shown in FIG. 2;
(2) and (3) secondarily extending a P-type gallium nitride material in the etched groove in the vertical channel layer 3 by adopting a secondary extension technology to form a P-type gallium nitride electric field modulation region 4, and secondarily flattening: the scheme of combining the chemical mechanical polishing technology and the digital etching is adopted, the characteristics of high planarization speed and low cost of the chemical mechanical polishing are utilized, and the characteristic of low damage of the digital etching to the semiconductor material is utilized, as shown in figure 3;
(3) adopting a secondary epitaxial technology to grow a gallium nitride buffer layer 5 and an aluminum gallium nitride barrier layer 6 again, and depositing a passivation layer 11 by using a PECVD technology, as shown in FIG. 4;
(4) and (3) adopting a groove etching technology, masking and etching grooves needed by the vertical channel grid 81 and the plane channel grid 82, wherein the step only needs one-time photoetching: the gan barrier layer 6 needs to be completely etched to ensure that the transverse two-dimensional electron gas channel can be completely exhausted, as shown in fig. 5;
(5) the required gate dielectric 7 is deposited by using photolithography and chemical vapor deposition. After depositing a gate dielectric, performing high-temperature rapid thermal annealing at 400-500 ℃ for 10-15 min, masking and etching the region not covered by the gate dielectric, exposing the passivation layer, and reducing the thickness of the passivation layer, as shown in FIG. 6;
(6) adopting a groove etching technology to etch grooves required by the source electrode 9 and the drain electrode 10, and completely etching the gallium nitride buffer layer 5, the aluminum gallium nitride barrier layer 6 and the passivation layer 11 as shown in FIG. 7;
(7) in the grooves of the source electrode and the drain electrode, on the upper surfaces of the vertical channel layer 3 and the P-type aluminum gallium nitride 4, ohmic metals required by the source electrode 9 and the drain electrode 10 are deposited on the side walls of the grooves of the gallium nitride buffer layer 5, the aluminum gallium nitride barrier layer 6 and the passivation layer 11 (a two-dimensional electron gas channel is formed by the gallium nitride buffer layer 5 and the aluminum gallium nitride barrier layer 6), the photoetching technology is adopted, and high-temperature rapid thermal annealing is carried out in a pure nitrogen atmosphere, so that the preparation of the source electrode 9 and the drain electrode 10 is respectively completed, as shown in fig. 8;
(8) by using the photolithography technique and the metal deposition technique, schottky metal is deposited in the vertical trench gate recess and the horizontal trench gate recess, and the preparation of the electrodes in the vertical trench gate 81 and the horizontal trench gate 82 is completed, so that the vertical trench gate 81 and the horizontal trench gate 82 form a schottky metal/insulating dielectric/semiconductor MIS gate control structure, as shown in fig. 9.

Claims (5)

1. The gallium nitride MIS grid-control mixed channel power field effect transistor comprises a heterogeneous substrate (1) with a stress modulation structure, a transverse gallium nitride epitaxial layer (2) arranged on the upper surface of the heterogeneous substrate (1), a vertical channel layer (3) arranged on the upper surface of the transverse gallium nitride epitaxial layer (2), a P-type gallium nitride electric field modulation region (4), a gallium nitride buffer layer (5) positioned on the vertical channel layer (3) and the P-type gallium nitride electric field modulation region (4) and an aluminum gallium nitride barrier layer (6) positioned on the gallium nitride buffer layer (5), wherein the gallium nitride buffer layer (5) and the aluminum gallium nitride barrier layer (6) form a heterojunction barrier layer, and a passivation layer (11) covers the upper surface of the aluminum gallium nitride barrier layer (6); the P-type gallium nitride electric field modulation region (4) is positioned in the vertical channel layer (3), namely the vertical channel layer (3) is arranged on two sides of the P-type gallium nitride electric field modulation region (4); the transistor is characterized by further comprising a source electrode (9), a drain electrode (10), a vertical channel grid electrode (81) and a plane channel grid electrode (82), wherein the drain electrode (10) is located on one side of an upper layer of the transistor, the vertical channel grid electrode (81) is located on the other side of the upper layer of the transistor, the source electrode (9) and the plane channel grid electrode (82) are located between the drain electrode (10) and the vertical channel grid electrode (81), the plane channel grid electrode (82) is located at one end close to the drain electrode (10), and the source electrode (9) is located between the plane channel grid electrode (82) and the vertical channel grid electrode (81); the upper part of the drain electrode (10) extends to the direction close to the plane channel gate (82) and covers a part of the passivation layer (11), the middle part of the drain electrode (10) vertically extends downwards along the side surfaces of the passivation layer (11), the aluminum gallium nitride barrier layer (6) and the gallium nitride buffer layer (5), and the bottom part of the drain electrode (10) extends to the direction far away from the plane channel gate (82) and covers a part of the upper surface of the vertical channel layer (3); the planar channel grid (82) and the source electrode (9) are both of a groove structure, wherein the bottom of the source electrode (9) extends to be in contact with the upper surface of the P-type gallium nitride electric field modulation region (4), the bottom of the planar channel grid (82) extends to the upper layer of the gallium nitride buffer layer (5), the planar channel grid (82) is isolated from the passivation layer (11), the gallium nitride buffer layer (5) and the aluminum gallium nitride barrier layer (6) through grid dielectric layers, and the upper parts of the planar channel grid (82) and the source electrode (9) extend towards two sides along the surface of the passivation layer (11); the upper part of the vertical channel gate (81) extends to one side close to the source electrode (9) along the surface of the passivation layer (11), the middle part of the vertical channel gate (81) vertically extends to the upper part of the gallium nitride buffer layer (5) downwards along the side faces of the passivation layer (11) and the aluminum gallium nitride barrier layer (6) and extends to one side far away from the source electrode (9), and the vertical channel gate (81) is isolated from the passivation layer (11), the gallium nitride buffer layer (5) and the aluminum gallium nitride barrier layer (6) through gate dielectric layers.
2. The gan MIS gated hybrid channel power fet as claimed in claim 1, wherein the gate dielectric layer (7) is made of one or more of silicon dioxide, silicon nitride, aluminum oxide, magnesium oxide and hafnium oxide, and has a thickness of 1-100 nm.
3. The gan MIS gated hybrid channel power fet as claimed in claim 2, wherein the vertical channel layer (3) forms a vertical current channel that is used as a current channel of the device simultaneously with the planar current channel formed by the gan buffer layer (5) and the gan barrier layer (6) and is controlled to turn on or off with the gate voltage.
4. The GaN MIS gated hybrid channel power FET of claim 3, wherein the P-type GaN electric field modulation region (4) modulates both the planar channel and the vertical channel electric fields in depletion and on states.
5. The manufacturing method of the gallium nitride MIS grid-control mixed channel power field effect transistor is characterized by comprising the following steps of:
the first step is as follows: sequentially epitaxially growing a transverse gallium nitride epitaxial layer (2) and a vertical channel layer (3) on the upper layer of the substrate (1);
the second step is that: and (2) secondarily extending a P-type gallium nitride material in an etched groove in the vertical channel layer (3) by adopting a secondary extension technology to form a P-type gallium nitride electric field modulation region (4), and secondarily flattening: the scheme of combining the chemical mechanical polishing technology and the digital etching is adopted, the characteristics of high planarization speed and low cost of the chemical mechanical polishing are utilized, and the characteristic of low damage of the digital etching to the semiconductor material is utilized;
the third step: regrowing a gallium nitride buffer layer (5) and an aluminum gallium nitride barrier layer (6) by adopting a secondary epitaxial technology, and depositing a passivation layer (11);
the fourth step: and (2) adopting a groove etching technology to etch grooves required by the vertical channel grid (81) and the plane channel grid (82), wherein the step only needs one-time photoetching: the aluminum gallium nitride barrier layer (6) needs to be completely etched to ensure that the transverse two-dimensional electron gas channel can be completely exhausted;
the fifth step: depositing a required gate dielectric (7) by adopting a photoetching technology and a chemical vapor deposition technology; after depositing the gate dielectric, carrying out high-temperature rapid thermal annealing at 400-500 ℃ for 10-15 min;
and a sixth step: adopting a groove etching technology to etch grooves required by the source electrode (9) and the drain electrode (10), and completely etching the gallium nitride buffer layer (5), the aluminum gallium nitride barrier layer (6) and the passivation layer (11);
the seventh step: in the grooves of the source electrode and the drain electrode, on the upper surfaces of the vertical channel layer (3) and the P-type aluminum gallium nitride (4), ohmic metal required by the source electrode (9) and the drain electrode (10) is deposited on the side walls of the grooves of the gallium nitride buffer layer (5), the aluminum gallium nitride barrier layer (6) and the passivation layer (11), the photoetching technology is adopted, and high-temperature rapid thermal annealing is carried out in a pure nitrogen atmosphere, so that the preparation of the source electrode (9) and the drain electrode (10) is respectively completed;
eighth step: and (3) depositing Schottky metal in the vertical channel gate groove and the horizontal channel gate groove by adopting a photoetching technology to finish the preparation of the electrode vertical channel gate (81) and the plane channel gate (82), so that the vertical channel gate (81) and the plane channel gate (82) form a Schottky metal/insulating medium/semiconductor MIS gate control structure.
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CN110310981A (en) * 2019-07-08 2019-10-08 电子科技大学 The enhanced composite potential barrier layer gallium nitride radical heterojunction field effect pipe in nitrogen face

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