CN117219676A - Enhancement mode HEMT device of heterogeneous pn junction grid - Google Patents
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- CN117219676A CN117219676A CN202311025609.XA CN202311025609A CN117219676A CN 117219676 A CN117219676 A CN 117219676A CN 202311025609 A CN202311025609 A CN 202311025609A CN 117219676 A CN117219676 A CN 117219676A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 82
- 230000004888 barrier function Effects 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 125000005842 heteroatom Chemical group 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 18
- 229910002704 AlGaN Inorganic materials 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 description 10
- 230000006872 improvement Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Abstract
The invention discloses an enhanced HEMT device of a heterogeneous pn junction grid, which comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially laminated on the substrate; the gate electrode includes a p-type semiconductor layer and an n-type semiconductor layer sequentially stacked on the barrier layer, the p-type semiconductor layer and the n-type semiconductor layer forming a hetero pn junction. According to the invention, the heterogeneous pn junction grid electrode is formed, so that the voltage resistance of the grid electrode is improved, and the grid leakage current is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an enhanced HEMT device with a heterogeneous pn junction grid electrode.
Background
AlGaN/GaN High Electron Mobility Transistor (HEMT) has wide application prospect in the application aspect of switching devices due to the characteristics of low cost, high frequency, high efficiency, high temperature resistance, miniaturization and the like. Conventional GaN HEMTs are depletion mode devices, and in practical power switching system applications, it is particularly important to use enhancement mode devices in order to meet the needs of safety and simplified circuit design. In the preparation scheme of realizing the enhanced GaN HEMT device by using a groove etching technology, a fluorine ion implantation technology, a P-GaN (P-AlGaN) gate, a co-source co-gate and the like, the GaN HEMT device based on the P-GaN gate is the best choice for realizing commercialization.
The conventional P-GaN gate HEMT extends P-GaN on the AlGaN barrier layer, the lattice constant of the AlGaN material is larger than that of the GaN material, the crystal quality of the material is easily deteriorated due to large lattice mismatch, defects induced by strain are increased, and the surface and interface quality of the AIGaN are reduced, so that the performance of the device is affected.
In addition, the gate structure of a conventional P-GaN gate HEMT forms a schottky contact from metal and P-GaN, including a schottky diode formed of metal/P-GaN. When a forward voltage is applied to the metal gate, the schottky diode is in a reverse cut-off state and vertical gate leakage is limited by the schottky diode. However, the turn-on voltage of the schottky contact is low, and when the forward voltage applied to the gate is greater than a threshold, the schottky diode turns on, and the gate leakage increases significantly. Gate leakage can increase switching losses, affect conversion efficiency, and even lead to breakdown of the gate of the device, which is disadvantageous in high voltage applications.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the enhanced HEMT device with the heterogeneous pn junction grid electrode, and the grid electrode voltage resistance of the device is good.
The invention also aims to provide a preparation method of the enhanced HEMT device with the heterogeneous pn junction grid electrode, which is simple in process.
In order to achieve the technical effects, the invention provides an enhanced HEMT device with a heterogeneous pn junction grid, which comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially laminated on the substrate, a drain electrode, a grid electrode and a source electrode are arranged on the barrier layer, and the drain electrode, the source electrode and the barrier layer form ohmic contact;
the gate electrode includes a p-type semiconductor layer and an n-type semiconductor layer sequentially stacked on the barrier layer, the p-type semiconductor layer and the n-type semiconductor layer forming a hetero pn junction.
As an improvement of the above technical scheme, the p-type semiconductor layer comprises p-Al sequentially laminated on the barrier layer a Ga 1-a N layer, p-In b Al c Ga 1-b-c The N layer and the p-GaN layer, wherein the value range of a is 0.05-0.2, the value range of b is 0.001-0.01, and the value range of c is 0.01-0.1.
As an improvement of the technical proposal, the n-type semiconductor layer is a Si layer, a GaN layer, a ZnO layer or a Ta 2 O 5 Layer of SnO 2 Layer, tiO 2 Layer, cdO layer, in 2 O 3 One or more of a layer, an ITO layer, an AZO layer, an FTO layer and an ATO layer.
As an improvement of the technical scheme, the thickness of the p-type semiconductor layer is 40-150nm; the thickness of the n-type semiconductor layer is 5-500nm.
As an improvement of the above technical scheme, the p-Al a Ga 1-a The thickness of the N layer is smaller than that of the p-GaN layer; the p-In b Al c Ga 1-b-c The thickness of the N layer is less than the thickness of the p-GaN layer.
As an improvement of the above technical scheme, the p-Al a Ga 1-a The thickness of the N layer is 1-20nm; the p-In b Al c Ga 1-b-c The thickness of the N layer is 1-20nm; the thickness of the p-GaN layer is 30-120nm.
As an improvement of the above technical scheme, the p-Al a Ga 1-a The doping concentration of the N layer is less than that of the p-In b Al c Ga 1-b-c The doping concentration of the N layer is less than that of the p-GaN layer.
As an improvement of the above technical scheme, the p-Al a Ga 1-a The doping concentration of the N layer is 1 multiplied by 10 14 -1×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-In b Al c Ga 1-b-c The doping concentration of the N layer is 1 multiplied by 10 14 -1×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the p-GaN layer is 1 multiplied by 10 16 -5×10 19 cm -3 。
As an improvement of the technical proposal, the substrate is selected from Si substrate, gaN substrate, siC substrate and Al 2 O 3 One of the substrates;
the buffer layer is made of AlGaN and/or GaN;
the channel layer is made of GaN;
the barrier layer is made of AlGaN and/or InAlGaN.
In addition, the invention also provides a preparation method of the enhanced HEMT device with the heterogeneous pn junction grid electrode, which comprises the following steps:
(1) Providing a substrate, and sequentially epitaxially growing a buffer layer, a channel layer, a barrier layer, a p-type semiconductor layer and an n-type semiconductor layer on the substrate, wherein the p-type semiconductor layer and the n-type semiconductor layer form a pn heterojunction layer;
(2) Etching and removing the p-type semiconductor layer and the n-type semiconductor layer of the non-gate region to expose the barrier layer;
(3) And depositing metal on the barrier layer to enable the metal and the barrier layer to form ohmic contact, so as to obtain the drain electrode and the source electrode.
The embodiment of the invention has the following beneficial effects:
1. the invention provides an enhanced HEMT device with a heterogeneous pn junction grid, which is formed by depositing a layer of n-type semiconductor material on the top of p-type semiconductor material and forming the heterogeneous pn junction grid. When the gate is forward biased, the pn junction is reverse biased, and the reverse biased pn junction can be maintained at a higher voltage than the schottky junction at the same peak electric field. Compared with a Schottky junction, the pn junction can also reduce the hole injected from the gate metal and Mg diffusion from the p-type semiconductor layer to the channel layer, so that higher breakdown voltage is realized; the n-type semiconductor layer is adopted to replace the metal gate electrode, so that a gold-free gate process is realized, the process is simple, and the repeatability is high.
2. The p-type semiconductor layer of the present invention comprises p-Al a Ga 1-a N layer, p-In b Al c Ga 1-b-c The N layer and the p-GaN layer reduce lattice mismatch between the barrier layer and the GaN layer in the grid electrode by growing the p-type semiconductor layer with a specific structure, reduce current collapse probability, reduce grid leakage current and further improve device reliability.
Drawings
Fig. 1 is a schematic structural diagram of an enhancement HEMT device of a hetero-pn junction gate of embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a p-type semiconductor layer of an enhancement HEMT device of a hetero-pn junction gate of embodiment 1 of the present invention;
fig. 3 is a comparative graph of gate leakage current for example 1 of the present invention and comparative example 1;
fig. 4 is a comparative graph of the forward gate breakdown voltages of inventive example 1 and comparative example 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
As shown in fig. 1 and fig. 2, the embodiment of the invention provides an enhanced HEMT device with low gate leakage, which comprises a substrate 1, a buffer layer 2, a channel layer 3 and a barrier layer 4 which are sequentially stacked on the substrate 1, wherein a drain electrode 5, a gate electrode 6 and a source electrode 7 are arranged on the barrier layer 4, and the drain electrode 5 and the source electrode 7 form ohmic contact with the barrier layer 4; the gate electrode 6 includes a p-type semiconductor layer 61 and an n-type semiconductor layer 62 sequentially stacked on the barrier layer 4, the p-type semiconductor layer 61 and the n-type semiconductor layer 62 forming a hetero pn junction.
The conventional metal gate forms a Schottky junction with the barrier layer, and after long-time surface contact, metal diffuses into the barrier layer, seriously affecting the reliability of the device, and is formed by the Schottky junctionThe low breakdown voltage of the gate contact limits the gate voltage application range of the device. The invention takes the pn junction as the grid electrode, can increase the breakdown voltage V of the grid electrode g The HEMT device has larger gate voltage swing, and the p-type semiconductor layer contacted with the barrier layer can deplete 2DEG, so that the threshold voltage of the device is improved. Meanwhile, the p-type semiconductor material and the n-type semiconductor material can form a heterogeneous pn junction diode, when the device is in a conducting state, the diode consumes a certain voltage drop, so that the voltage reaching the channel layer is reduced, and therefore, the device can be conducted only by needing a higher grid voltage, and the threshold voltage of the device is further improved. In addition, the invention adopts the n-type semiconductor layer to replace the metal gate electrode, thereby realizing a gold-free gate structure, having simple structure and high repeatability.
Preferably, the p-type semiconductor layer 61 includes p-Al sequentially laminated a Ga 1-a N layer 61a, p-In b Al c Ga 1-b-c An N layer 61b and a p-GaN layer 61c, wherein a has a value ranging from 0.05 to 0.2, b has a value ranging from 0.001 to 0.01, and c has a value ranging from 0.01 to 0.1.
The barrier layer of the conventional p-GaN gate HEMT is in direct contact with the p-GaN layer, so that larger lattice mismatch exists, and the p-type semiconductor layer 61 provided by the invention can further improve the quality of combination between the barrier layer 4 and the p-GaN layer 61 c. By introducing p-Al between the barrier layer 4 and the p-GaN layer 61c a Ga 1-a N layer 61a having a buffer effect and capable of being more preferably formed on p-Al a Ga 1-a Growth of p-In on N layer 61a b Al c Ga 1-b-c N layer 61b by controlling p-Al a Ga 1-a The Al component in the N layer 61a can enhance p-Al a Ga 1-a Buffer action of the N layer 61 a; at the same time at p-Al a Ga 1-a Introducing p-In between the N layer 61a and the p-GaN layer 61c b Al c Ga 1-b-c N layer 61b, avoid p-Al a Ga 1-a The direct contact of the N layer 61a and the p-GaN layer 61c effectively reduces lattice mismatch caused by excessive difference of Al components, reduces dislocation density of a hetero interface, and In addition, the introduction of In components can improve interface flatness, improve crystal quality and component uniformity of an epitaxial layer on the interface, and control the p-type semiconductor device by controlling the p-type semiconductor deviceIn b Al c Ga 1-b-c In component and Al component In N layer 61b, further enhancing p-Al a Ga 1-a The bonding quality of the N layer 61a and the p-GaN layer 61 c.
The n-type semiconductor layer 62 is a Si layer, a GaN layer, a ZnO layer, or Ta 2 O 5 Layer of SnO 2 Layer, tiO 2 Layer, cdO layer, in 2 O 3 One or more of the layer, the ITO layer, the AZO layer, the FTO layer and the ATO layer can avoid the electrical instability of the n-type semiconductor layer under mechanical deformation by limiting the material of the n-type semiconductor layer. The thickness of the p-type semiconductor layer 61 is 40-150nm, and the thickness of the n-type semiconductor layer 62 is 5-500nm.
Preferably, the p-Al a Ga 1-a The doping concentration of the N layer 61a < the p-In b Al c Ga 1-b-c The doping concentration of the N layer 61b < the doping concentration of the p-GaN layer 61 c. By providing the p-type semiconductor layer 61 with graded doping concentration, the doping concentration of the p-GaN layer 61c can be further increased, the 2DEG in the channel can be depleted, and the gate breakdown voltage can be increased on the basis of ensuring lattice matching of the barrier layer 4 and the p-type semiconductor layer 61. Preferably, the p-Al a Ga 1-a The doping concentration of the N layer 61a is 1×10 14 -1×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-In b Al c Ga 1-b-c The doping concentration of the N layer 61b is 1×10 14 -1×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-GaN layer 61c has a doping concentration of 1×10 16 -5×10 19 cm -3 。
p-Al a Ga 1-a N layer 61a and p-In b Al c Ga 1-b-c The thickness of the N layer 61b is smaller than the thickness of the p-GaN layer 61c, ensuring that sufficient carriers can be injected into the channel layer 3, preferably, the p-Al a Ga 1-a The thickness of the N layer 61a is 1-20nm; the p-In b Al c Ga 1-b-c The thickness of the N layer 61b is 1-20nm; the thickness of the p-GaN layer 61c is 30-120nm.
In addition, the substrate 1 is selected from Si substrate, gaN substrate, siC substrate, al 2 O 3 One of the substrates, the kind of the substrate 1 is not limited thereto. Which is a kind ofThe Si substrate has the advantages of relatively low price, excellent heat and electric conductivity, mature device processing technology and the like, is widely applied to GaN-based enhanced HEMT devices, meets the requirement of saving cost, and is beneficial to the growth of subsequent materials.
The buffer layer 2 is made of AlGaN and/or GaN for alleviating the problems of lattice mismatch and thermal expansion coefficient mismatch of the substrate 1 and the channel layer 3.
The channel layer 3 is made of GaN, and the material forming the channel layer 3 and the state of the channel layer 3 as a mobile charge carrier path may affect the carrier mobility or leakage current of the transistor.
The barrier layer 4 is made of AlGaN and/or InAlGaN.
Correspondingly, the embodiment of the invention also provides a preparation method of the enhanced HEMT device of the heterogeneous pn junction grid, which is used for preparing the enhanced HEMT device of the heterogeneous pn junction grid and comprises the following steps:
(1) Providing a substrate 1, and sequentially epitaxially growing a buffer layer 2, a channel layer 3, a barrier layer 4, a p-type semiconductor layer 51 and an n-type semiconductor layer 52 on the substrate 1, wherein the p-type semiconductor layer 51 and the n-type semiconductor layer 52 form a pn heterojunction layer;
(2) Etching the p-type semiconductor layer 51 and the n-type semiconductor layer 52 of the non-gate region to remove, exposing the barrier layer 4;
(3) A metal is deposited on the barrier layer 4 to form an ohmic contact with the barrier layer and to obtain a drain 5 and a source 7.
The invention is further illustrated by the following specific examples.
Example 1
The enhanced HEMT device comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially laminated on the substrate; the gate electrode includes a p-type semiconductor layer and an n-type semiconductor layer sequentially stacked on the barrier layer, the p-type semiconductor layer and the n-type semiconductor layer forming a hetero pn junction.
The substrate is a Si substrate.
The buffer layer is made of GaN.
The channel layer is made of GaN.
The barrier layer is made of AlGaN.
The p-type semiconductor layer is a p-GaN layer with a doping concentration of 5×10 19 cm -3 The thickness was 80nm.
The n-type semiconductor layer is an ITO layer with a thickness of 200nm.
The preparation method comprises the following steps:
(1) Sequentially epitaxially growing a buffer layer, a channel layer, a barrier layer, a p-type semiconductor layer and an n-type semiconductor layer on a substrate, wherein the p-type semiconductor layer and the n-type semiconductor layer form a pn heterojunction layer;
(2) Etching and removing the p-type semiconductor layer and the n-type semiconductor layer of the non-gate region to expose the barrier layer;
(3) And depositing metal on the barrier layer to enable the metal and the barrier layer to form ohmic contact, so as to obtain the drain electrode and the source electrode.
Comparative example 1
An enhanced HEMT device comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially laminated on the substrate, wherein a drain electrode and a source electrode are arranged on the barrier layer, and the drain electrode and the source electrode form ohmic contact with the barrier layer; the gate electrode is disposed on the p-type semiconductor layer.
The substrate is a Si substrate.
The buffer layer is made of GaN.
The channel layer is made of GaN.
The barrier layer is made of AlGaN.
The p-type semiconductor layer is p-GaN layer with thickness of 100nm and doping concentration of 5×10 19 cm -3 。
The preparation method comprises the following steps:
(1) Sequentially epitaxially growing a buffer layer, a channel layer, a barrier layer and a p-type semiconductor layer on a substrate;
(2) Etching and removing the p-type semiconductor layer of the non-gate region to expose the barrier layer;
(3) And depositing metal on the barrier layer, enabling the metal and the barrier layer to form ohmic contact to obtain a drain electrode and a source electrode, and depositing metal Ni/Au (50/150 nm) on the p-type semiconductor layer to obtain a gate electrode.
Performance testing
Performance tests were performed on the enhanced HEMT devices of example 1 and comparative example 1, and the results are shown in fig. 3 and 4.
As can be seen from fig. 3 and fig. 4, by introducing the heterogeneous pn junction, the gate breakdown voltage of the HEMT device is obviously improved, and the gate leakage current is also greatly reduced.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The enhanced HEMT device of the heterogeneous pn junction grid is characterized by comprising a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially laminated on the substrate, a drain electrode, a grid electrode and a source electrode are arranged on the barrier layer, and the drain electrode, the source electrode and the barrier layer form ohmic contact;
the gate electrode includes a p-type semiconductor layer and an n-type semiconductor layer sequentially stacked on the barrier layer, the p-type semiconductor layer and the n-type semiconductor layer forming a hetero pn junction.
2. The enhancement mode HEMT device of claim 1, wherein said p-type semiconductor layer comprises p-Al sequentially laminated on said barrier layer a Ga 1-a N layer, p-In b Al c Ga 1-b-c The N layer and the p-GaN layer, wherein the value range of a is 0.05-0.2, the value range of b is 0.001-0.01, and the value range of c is 0.01-0.1.
3. The enhancement HEMT device of claim 1, wherein said n-type semiconductor layer is a Si layer, a GaN layer, a ZnO layer, a Ta 2 O 5 Layer of SnO 2 Layer, tiO 2 Layer, cdO layer, in 2 O 3 One or more of a layer, an ITO layer, an AZO layer, an FTO layer and an ATO layer.
4. The enhancement mode HEMT device of claim 1, wherein said p-type semiconductor layer has a thickness of 40-150nm; the thickness of the n-type semiconductor layer is 5-500nm.
5. The enhancement mode HEMT device of claim 2, wherein the p-Al a Ga 1-a The thickness of the N layer is smaller than that of the p-GaN layer; the p-In b Al c Ga 1-b-c The thickness of the N layer is less than the thickness of the p-GaN layer.
6. The enhancement mode HEMT device of claim 5, wherein said p-Al a Ga 1-a The thickness of the N layer is 1-20nm; the p-In b Al c Ga 1-b-c The thickness of the N layer is 1-20nm; the thickness of the p-GaN layer is 30-120nm.
7. The enhancement mode HEMT device of claim 2, wherein the p-Al a Ga 1-a The doping concentration of the N layer is less than that of the p-In b Al c Ga 1-b-c The doping concentration of the N layer is less than that of the p-GaN layer.
8. The enhancement mode HEMT device of claim 7, wherein the p-Al a Ga 1-a The doping concentration of the N layer is 1 multiplied by 10 14 -1×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-In b Al c Ga 1-b-c The doping concentration of the N layer is 1 multiplied by 10 14 -1×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the p-GaN layer is 1 multiplied by 10 16 -5×10 19 cm -3 。
9. The enhancement mode HEMT device of claim 1, wherein said substrate is selected from the group consisting of Si substrate, gaN substrate, siC substrate, al 2 O 3 One of the substrates;
the buffer layer is made of AlGaN and/or GaN;
the channel layer is made of GaN;
the barrier layer is made of AlGaN and/or InAlGaN.
10. A method for preparing an enhanced HEMT device of a hetero-pn junction gate, for preparing an enhanced HEMT device of a hetero-pn junction gate as claimed in any one of claims 1-9, comprising the steps of:
(1) Providing a substrate, and sequentially epitaxially growing a buffer layer, a channel layer, a barrier layer, a p-type semiconductor layer and an n-type semiconductor layer on the substrate, wherein the p-type semiconductor layer and the n-type semiconductor layer form a pn heterojunction layer;
(2) Etching and removing the p-type semiconductor layer and the n-type semiconductor layer of the non-gate region to expose the barrier layer;
(3) And depositing metal on the barrier layer to enable the metal and the barrier layer to form ohmic contact, so as to obtain the drain electrode and the source electrode.
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| CN117429677B (en) * | 2023-12-19 | 2024-03-05 | 浙江名瑞智能装备科技股份有限公司 | Vacuum packaging device and method for soft battery |
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