JP5208439B2 - Nitride semiconductor device - Google Patents

Description

  The present invention relates to a nitride semiconductor device using a nitride semiconductor as an active layer, and in particular, a semiconductor device such as a high electron mobility transistor (HEMT) or a field effect transistor (FET). The present invention relates to a normally-off type field effect transistor having a control electrode in Schottky contact and applied to a switching device such as an inverter or a converter.

  FIG. 6 shows a cross-sectional view of a conventional semiconductor device made of a group III-V nitride semiconductor. The semiconductor device shown in FIG. 6 has a so-called HEMT structure. On a substrate 101 made of a sapphire substrate, a buffer layer 102 made of gallium nitride (GaN), a channel layer 103 made of gallium nitride, and non-doped aluminum gallium nitride. A Schottky layer 104 made of (AlGaN) is sequentially stacked, and a two-dimensional electron gas layer made of a potential well and having a very high electron mobility is formed in the vicinity of the heterojunction interface made up of the channel layer 103 and the Schottky layer 104. Is formed. A recess 104a is formed in the Schottky layer 104, and a gate electrode 108 (control electrode) that makes a Schottky contact is formed in the recess 104a. In the semiconductor device having such a structure, the carrier (two-dimensional electron gas) flowing between the source electrode 107a and the drain electrode 107b is controlled by controlling the voltage applied to the gate electrode. Moreover, the pinch-off voltage is made shallow by providing the recessed part 104a. That is, when the control voltage applied to the gate electrode 108 is 0 V, the carrier is not present in the channel immediately below the gate electrode 108, and the carrier is present in the channel other than directly below the gate electrode 108. Yes.

FIG. 7 shows a cross-sectional view of another conventional semiconductor device made of a group III-V nitride semiconductor. In the semiconductor device shown in FIG. 7, a p-type gallium nitride layer 105 doped with a p-type impurity is formed on the Schottky layer 104 instead of the recess 104 a described in FIG. 6, and a gate electrode is formed on the p-type gallium nitride layer 105. 108 is formed. In the semiconductor device having such a structure, by using a built-in potential formed between the p-type gallium nitride layer 105 and the Schottky layer 104 made of non-doped aluminum gallium nitride, the pinch-off voltage is made shallow and normally off. It is a mold (for example, Non-Patent Document 1).
X.Hu, G.Simin, J.Yang, M.AsifKhan, R.GaskaandM.S.Shur, `` Enhancement mode AlGaN / GaN HFET with selectively grown pn junction gate '', ELECTRONICSLETTERS, Vol.36, No.8, 2000 , P753-754

In the conventional nitride semiconductor device in which the recess 104a is formed in the Schottky layer 104 shown in FIG. 6 and the gate electrode 108 is formed in the recess 104a, the recess 104a is formed by dry etching the Schottky layer 104. Damage to the surface. That is, the surface of the Schottky layer 104 with which the gate electrode 108 is in Schottky contact is damaged. As a result, there is a problem that the height of the Schottky barrier is reduced and it is difficult to realize a completely normally-off operation.

  Further, in the structure including the p-type gallium nitride layer 105 on the Schottky layer 104 shown in FIG. 7, it is difficult to dope the gallium nitride layer with a high concentration of p-type impurities, and the activation rate is low. The p-type gallium nitride layer 105 having a concentration could not be formed, and a good pn junction could not be formed. As a result, the built-in potential is reduced, and there is a problem that a completely normally-off operation cannot be realized.

  An object of the present invention is to provide a nitride semiconductor device capable of realizing a completely normally-off operation.

To achieve the above object, the invention according to claim 1 is a group consisting of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and a group consisting of nitrogen, phosphorus and arsenic stacked on a substrate. A first nitride semiconductor layer composed of a group III-V nitride semiconductor layer composed of a group V element containing at least nitrogen, and the layer III-V stacked on the first nitride semiconductor layer. A first nitride semiconductor layer made of a group nitride semiconductor layer, the second nitride semiconductor layer not containing aluminum, and the III-V group nitride semiconductor layer stacked on the second nitride semiconductor layer. In the nitride semiconductor device in which the third nitride semiconductor layer having a lower deposition temperature than the group III-V nitride semiconductor layer 2 and not including aluminum having a microcrystalline structure is sequentially stacked, the third nitride Shown on the semiconductor layer When the control voltage applied to the control electrode is 0 V, carriers do not exist in the channel formed of the first nitride semiconductor layer immediately below the control electrode, and the control electrode applied to the contact electrode is other than directly below the control electrode. A carrier is present in the channel.

The invention according to claim 2 includes a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium stacked on the substrate, and at least nitrogen of the group consisting of nitrogen, phosphorus and arsenic. A first nitride semiconductor layer composed of a group III-V nitride semiconductor layer composed of a group V element, and the group III-V nitride semiconductor layer stacked on the first nitride semiconductor layer. A first nitride semiconductor layer comprising: a second nitride semiconductor layer not containing aluminum; and the group III-V nitride semiconductor layer stacked on the second nitride semiconductor layer; In a nitride semiconductor device in which a third nitride semiconductor layer having a microcrystalline structure and containing no aluminum is sequentially stacked, a part of the first nitride semiconductor layer is formed in a concave shape. Lack, at least the The second nitride semiconductor layer and the third nitride semiconductor layer are sequentially stacked on the first nitride semiconductor layer exposed in the portion, and the Schottky layer is formed on the third nitride semiconductor layer on the recess. When the control voltage applied to the control electrode is 0 V, carriers do not exist in the channel formed of the first nitride semiconductor layer immediately below the control electrode, and the control electrodes other than directly below the control electrode are provided. The carrier is present in the channel.

  The invention according to claim 3 is the nitride semiconductor device according to claim 1 or 2, wherein an energy gap of the first nitride semiconductor layer is provided between the substrate and the first nitride semiconductor layer. A fourth nitride semiconductor layer comprising the group III-V nitride semiconductor layer having a smaller energy gap, and when the control voltage applied to the control electrode is 0 V, the fourth nitride semiconductor layer immediately below the control electrode; There is no carrier formed between the nitride semiconductor layer and the first nitride semiconductor layer, and carriers exist in the channel other than directly below the control electrode.

  According to a fourth aspect of the present invention, in the nitride semiconductor device according to any one of the first to third aspects, the control electrode that is in Schottky contact with the third nitride semiconductor layer, and the first nitride semiconductor layer A channel having a source electrode and a drain electrode that are in ohmic contact, and a channel formed of the first nitride semiconductor layer or a channel formed between the fourth nitride semiconductor layer and the first nitride semiconductor layer Is controlled by a voltage applied to the control electrode.

The invention according to claim 5 is the nitride semiconductor device according to any one of claims 1 to 3, wherein the control electrode that is in Schottky contact with the third nitride semiconductor layer and the third nitride semiconductor layer are provided. A channel having a source electrode and a drain electrode that are in ohmic contact, and a channel formed of the first nitride semiconductor layer or a channel formed between the fourth nitride semiconductor layer and the first nitride semiconductor layer Is controlled by a voltage applied to the control electrode.

  A nitride semiconductor device according to the present invention includes a structure in which a control electrode is brought into contact with a highly insulating third nitride semiconductor layer that does not contain at least aluminum and has an epitaxial growth temperature set lower than a normal temperature and has a microcrystalline structure. By doing so, the height of the Schottky barrier formed between the control electrode and the nitride semiconductor layer can be made higher than that of the contact with the conventional nitride semiconductor layer. In addition, since the third nitride semiconductor layer and the second nitride semiconductor layer having high insulating properties are stacked, the effects of spontaneous polarization and piezo polarization compared to the case of only the third nitride semiconductor layer. The height of the Schottky barrier is increased by adopting a structure in which the control electrode is in contact with the third nitride semiconductor layer.

  As a result, when the control electrode of the present invention is a gate electrode such as an FET or HEMT and a control voltage is applied so that the potential difference between the source and gate electrodes is 0 V, no carrier exists in the channel immediately below the gate electrode, Provided a nitride semiconductor device capable of forming a structure in which carriers exist in the channel between the gate and source electrodes, and between the gate and drain electrodes, which are regions other than directly under the gate electrode, and realizing a normally-off operation It becomes possible to do.

  Since the control electrode of the present invention is provided on a nitride semiconductor layer having a highly crystalline microcrystalline structure, leakage current can be reduced. When the control electrode of the present invention is a gate electrode such as an FET or HEMT, the gate leakage current is reduced. Further, by suppressing collision ionization in the channel, a high breakdown voltage can be realized. In addition, since a nitride semiconductor layer having a highly insulating microcrystalline structure is provided between the gate and drain electrodes, it is possible to suppress or trap electrons trapped in the surface level between the gate and drain electrodes. By reducing the level density, the current collapse phenomenon is suppressed and the high frequency characteristics are improved.

According to the present invention, an ohmic electrode is formed on a nitride semiconductor layer having a microcrystalline structure after film formation that does not include aluminum and is not subjected to processing such as implantation of impurity ions. A semiconductor device having an ohmic electrode with low contact resistivity (10 ⁻⁶ Ω · cm ² ) can be obtained because the metal constituting the ohmic electrode penetrates into the crystal grain boundary.

  Hereinafter, the nitride semiconductor device of the present invention will be described in detail.

  First, the nitride semiconductor device of the present invention will be described in detail by taking a HEMT as a group III-V nitride semiconductor device as an example. FIG. 1 shows a first embodiment of the present invention. As shown in FIG. 1, a substrate 11 made of silicon carbide (SiC) has an energy gap smaller than that of a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm and a Schottky layer 14 to be described later. A channel layer 13 made of non-doped gallium nitride (GaN) with a thickness of 3 μm, a Schottky layer 14 made of non-doped aluminum gallium nitride (AlGaN) with a thickness of 15 nm forming a two-dimensional electron gas layer serving as a carrier at the interface with the channel layer 13, A cap layer 15 made of non-doped gallium nitride (GaN) having a thickness of 10 nm and a low-temperature growth cap layer 16 made of non-doped gallium nitride (GaN) having a microcrystalline structure having a thickness of 10 nm are stacked. A gate electrode 18 made of a nickel (Ni) / gold (Au) laminate or the like is formed on the low temperature growth cap layer 16, and Schottky contact is made between the Schottky layer 14, the cap layer 15, and the low temperature growth cap layer 16. Is forming. Further, a part of the low-temperature growth cap layer 16 and the cap layer 15 is removed, and the source electrode 17a made of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) that is in ohmic contact with the Schottky layer 14 and the drain An electrode 17b is formed.

The low temperature growth cap layer 16 having a microcrystalline structure is formed at a temperature lower by about 600 ° C. than the film formation temperature of the cap layer 15 by MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxial) method or the like. Thus, a highly insulating semiconductor layer is formed. The low-temperature growth cap layer 16 of the first embodiment shown in FIG. 1 is formed by MOCVD at 500 ° C., and has a sheet resistance of 10 ¹¹ Ω / □ or higher. The semiconductor layers other than the low-temperature growth cap layer 16 such as the channel layer 13 and the Schottky layer 14 are epitaxially grown at a deposition temperature of 1130 ° C.

  2A and 2B show the HEMT of the above-described conventional example and the drain current-voltage characteristics of the present invention, respectively. The drain sweep voltage was 0V to 20V, and the gate voltage was changed in steps 1V from 0V to + 3V and from -2V to + 2V. As apparent from FIG. 2B, it was confirmed that the nitride semiconductor device of the present invention was operating in a normally-off type. It was also confirmed that the current collapse was significantly suppressed in the nitride semiconductor device of the present invention as compared with the conventional example by the pulse IV characteristics in which the gate voltage was applied with a measurement period of 10 ms and a pulse width of 300 μsec. . Thus, it has been confirmed that the present invention can provide a nitride semiconductor device having excellent characteristics.

In addition, the low temperature growth cap layer 16 has excellent insulation characteristics, and the combination with the cap layer 15 increases the Schottky barrier, so it is confirmed that the gate current (gate leakage current) is reduced by 5 digits or more. It was done. As the gate leakage current is reduced, collision ionization in the channel can be suppressed, and as a result, the off breakdown voltage is improved from the conventional 100V to 180V. It has been reported that the off breakdown voltage of a nitride semiconductor HEMT is not due to thermal runaway but due to impact ionization and is largely governed by the tunnel current flowing into the channel from the Schottky electrode (International Conference on Nitride Semiconductor, Nara, 2003, Tu-P2.067).

  FIG. 3 shows a cross-sectional view of a HEMT that is a group III-V nitride semiconductor device according to a second embodiment of the present invention. As in the first embodiment shown in FIG. 1, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm, and a non-doped gallium nitride (GaN) having a thickness of 3 μm. A Schottky layer 14 made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 15 nm, and a non-doped gallium nitride having a thickness of 10 nm (which forms a two-dimensional electron gas layer serving as a carrier at the interface with the channel layer 13. A cap layer 15 made of GaN) and a low temperature growth cap layer 16 made of non-doped gallium nitride (GaN) having a microcrystalline structure with a thickness of 10 nm are stacked. On the low temperature growth cap layer 16, a source electrode 17a and a drain electrode 17b (ohmic electrode) made of a laminate of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) are formed. The ohmic contact is formed on the Schottky layer 14. In this embodiment, the low temperature growth cap layer 16 and the cap layer 15 in which ohmic contact is formed are not subjected to special processing such as impurity ion implantation or etching after the film formation, and the microcrystalline structure after the film formation is maintained as it is. This is the difference from the first embodiment. A gate electrode 18 made of a nickel (Ni) / gold (Au) laminate or the like is formed on the low temperature growth cap layer 16, and a Schottky junction is formed between the Schottky layer 14, the cap layer 15, and the low temperature growth cap layer 16. Is forming.

Since the low temperature growth cap layer 16 on which the ohmic electrode is formed has a microcrystalline structure, the metal constituting the ohmic electrode penetrates into the crystal grain boundary, and the contact resistivity is low (10 ⁻⁶ Ω · cm ^2). Stand) Ohmic electrodes can be obtained. Thus, since the source electrode 17a and the drain electrode 17b can be formed without removing a part of the low temperature growth cap layer 16 and the cap layer 15, a planar structure is obtained and the yield and reliability of the manufacturing process are improved.

  It was confirmed that the nitride semiconductor device of this example also operates normally-off as described in Example 1. It was also confirmed that current collapse was significantly suppressed.

  FIG. 4 shows a cross-sectional view of a HEMT that is a group III-V nitride semiconductor device according to a third embodiment of the present invention. As in the first embodiment shown in FIG. 1, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm, and a non-doped gallium nitride (GaN) having a thickness of 3 μm. And a Schottky layer 14 made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 15 nm, which forms a two-dimensional electron gas layer serving as a carrier at the interface between the channel layer 13 and the channel layer 13.

Thereafter, after depositing a protective film (not shown) made of a silicon oxide film (SiO ₂ ) or the like, a part thereof is opened by photolithography, hydrofluoric acid based wet etching or the like, and a thickness of 10 nm is formed on the Schottky layer 14 in the opening. The cap layer 15 made of non-doped gallium nitride (GaN) is selectively grown. After removing the protective film, a low-temperature growth cap layer 16 made of non-doped gallium nitride (GaN) having a microcrystalline structure with a thickness of 10 nm is laminated over the entire surface.

  On the low temperature growth cap layer 16, a source electrode 17a and a drain electrode 17b (ohmic electrode) made of a laminate of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) are formed. At least an ohmic contact is formed on the Schottky layer 14. If the electrode material is diffused, ohmic contact is formed up to the channel layer 13. A gate electrode 18 made of a nickel (Ni) / gold (Au) laminate or the like is formed on the low temperature growth cap layer 16 on the selectively grown cap layer 15, and the Schottky layer 14, the cap layer 15, and the low temperature growth cap are formed. A Schottky junction is formed with the layer 16.

  This embodiment is different from the second embodiment described above in that the cap layer 15 is provided only directly under the gate electrode 18 and the Schottky barrier is increased.

  FIG. 5 shows a cross-sectional view of a HEMT that is a group III-V nitride semiconductor device according to a fourth embodiment of the present invention. As in the first embodiment shown in FIG. 1, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm, and a non-doped gallium nitride (GaN) having a thickness of 3 μm. And a Schottky layer 14 made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 25 nm, which forms a two-dimensional electron gas layer serving as a carrier at the interface between the channel layer 13 and the channel layer 13.

Thereafter, after depositing a protective film (not shown) made of a silicon oxide film (SiO ₂ ) or the like, a part thereof is opened by photolithography, hydrofluoric acid-based wet etching or the like, and the Schottky layer 14 in the opening portion is made of chlorine-based gas. The dry etching is used to etch 10 nm in a concave shape, and a cap layer 15 made of non-doped gallium nitride (GaN) having a thickness of 10 nm is selectively grown in the concave portion. After removing the protective film, a low-temperature growth cap layer 16 made of non-doped gallium nitride (GaN) having a microcrystalline structure with a thickness of 10 nm is laminated over the entire surface.

  On the low temperature growth cap layer 16, a source electrode 17a and a drain electrode 17b (ohmic electrode) made of a laminate of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) are formed. The ohmic contact is formed on the Schottky layer 14. A gate electrode 18 made of a nickel (Ni) / gold (Au) laminate or the like is formed on the low temperature growth cap layer 16 on the selectively grown cap layer 15, and the Schottky layer 14, the cap layer 15, and the low temperature growth cap are formed. A Schottky junction is formed with the layer 16.

  In this embodiment, the cap layer 15 is selectively grown by etching in a concave shape only directly below the gate electrode 18, the Schottky barrier is increased, and a Schottky layer having a thickness of 25 nm other than directly below the gate electrode is used as compared to immediately below the gate electrode. The difference from the second embodiment is that the two-dimensional electron gas existing at the interface between the Schottky layer 14 and the channel layer 13 is increased.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be variously modified. For example, the type of control electrode, the thickness of the Schottky layer or carrier supply layer, and the impurity concentration are appropriately selected and set so that carriers do not exist in channels directly under the control electrode and carriers exist in channels other than directly under the control electrode. can do.

  In addition to the HEMT structure described in the embodiment, a nitride semiconductor having a HEMT structure having a so-called carrier supply layer, or a nitride semiconductor layer to which an impurity is added is used as an active layer (channel layer), and the above-described layer is formed as described above. It can be set as the FET structure of the structure in which the cap layer 15 and the low-temperature growth cap layer 16 were formed. The nitride semiconductor layer is not limited to the GaN / AlGaN system, and the second nitride semiconductor layer (corresponding to the cap layer 15 in the above embodiment) is made of GaN, InN or a mixed crystal compound thereof. It can be comprised by the layer which contains and does not contain aluminum. The first nitride semiconductor layer (corresponding to the channel layer 13 in the above embodiment) can be formed of a layer containing GaN, InN, AlN, or a mixed crystal semiconductor thereof and containing at least aluminum. A sapphire substrate may be used instead of the silicon carbide (SiC) substrate used in the examples. In that case, it is preferable to use gallium nitride (GaN) as the buffer layer 12. A silicon (Si) substrate may be used instead of the silicon carbide (SiC) substrate.

  The composition of the electrode that is in ohmic contact with the first nitride semiconductor layer or the third nitride semiconductor layer may be appropriately selected according to the type of the nitride semiconductor layer to be used.

  Although the third nitride semiconductor layer has been described as having a microcrystalline structure, this is an aggregate of microcrystalline grains or a rearranged structure thereof. The growth temperature, the atmospheric gas composition during growth, the growth of the substrate to be grown. The size and arrangement of crystal grains vary depending on the type and the like, and can be obtained by controlling the growth temperature within a range where desired Schottky characteristics, insulation characteristics, and the like can be obtained. If the growth temperature of the third nitride semiconductor layer is set to a temperature lower by about 600 ° C. than the growth temperature of the first nitride semiconductor layer, it is suitable for forming a control electrode of HEMT or FET.

1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention. It is a figure which shows the drain current-voltage characteristic of the conventional nitride semiconductor device and the nitride semiconductor device of a 1st Example. It is sectional drawing of the nitride semiconductor device which is the 2nd Example of this invention. It is sectional drawing of the nitride semiconductor device which is the 3rd Example of this invention. It is sectional drawing of the nitride semiconductor device which is the 4th Example of this invention. It is sectional drawing of this kind of conventional nitride semiconductor device. It is sectional drawing of another conventional nitride semiconductor device of this kind.

Explanation of symbols

11, 101; substrate, 12, 102; buffer layer, 13, 103; channel layer,
14, 104; Schottky layer, 104a; recess, 15, 105; cap layer,
16; low temperature growth cap layer, 17a, 107a; source electrode,
17b, 107b; drain electrode, 18, 108; gate electrode

Claims (5)

A group III element composed of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic stacked on the substrate. A first nitride semiconductor layer made of a -V group nitride semiconductor layer, and a III-V group nitride semiconductor layer laminated on the first nitride semiconductor layer, and containing no aluminum. A nitride semiconductor layer and the group III-V nitride semiconductor layer stacked on the second nitride semiconductor layer, and the film formation temperature is higher than that of the first and second group III-V nitride semiconductor layers. In a nitride semiconductor device in which a third nitride semiconductor layer that is low and does not contain aluminum having a microcrystalline structure is sequentially stacked,
A control electrode that is in Schottky contact with the third nitride semiconductor layer is provided, and when a control voltage applied to the control electrode is 0 V, carriers exist in a channel formed of the first nitride semiconductor layer immediately below the control electrode And a carrier exists in the channel other than immediately below the control electrode. A group III element composed of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic stacked on the substrate. A first nitride semiconductor layer made of a group V nitride semiconductor layer, and a second nitride made of the group III-V nitride semiconductor layer laminated on the first nitride semiconductor layer and containing no aluminum And a group III-V nitride semiconductor layer stacked on the second nitride semiconductor layer, and has a lower deposition temperature than the first and second group III-V nitride semiconductor layers. In the nitride semiconductor device in which the third nitride semiconductor layer not containing aluminum having a microcrystalline structure is sequentially stacked,
The second nitride semiconductor layer and the third nitride semiconductor layer are formed on at least the first nitride semiconductor layer that is partially concaved and is exposed in the recess. Are sequentially stacked, and have a control electrode that is in Schottky contact with the third nitride semiconductor layer on the recess, and when the control voltage applied to the control electrode is 0 V, the first nitride just below the control electrode A nitride semiconductor device, wherein no carrier exists in a channel formed of a semiconductor layer, and carriers exist in the channel other than directly below the control electrode. The nitride semiconductor device according to claim 1 or 2,
A fourth nitride composed of the III-V nitride semiconductor layer having an energy gap smaller than that of the first nitride semiconductor layer between the substrate and the first nitride semiconductor layer; When a control voltage applied to the control electrode is 0 V, there is no carrier formed between the fourth nitride semiconductor layer and the first nitride semiconductor layer immediately below the control electrode. First, the nitride semiconductor device is characterized in that carriers exist in the channel other than immediately below the control electrode. The nitride semiconductor device according to any one of claims 1 to 3,
A channel comprising the first nitride semiconductor layer, the control electrode being in Schottky contact with the third nitride semiconductor layer, and a source electrode and a drain electrode being in ohmic contact with the first nitride semiconductor layer, Alternatively, the nitride semiconductor device is characterized in that a current flowing through a channel formed between the fourth nitride semiconductor layer and the first nitride semiconductor layer is controlled by a voltage applied to the control electrode. The nitride semiconductor device according to any one of claims 1 to 3,
A channel comprising the first nitride semiconductor layer, the control electrode being in Schottky contact with the third nitride semiconductor layer, and a source electrode and a drain electrode being in ohmic contact with the third nitride semiconductor layer, Alternatively, the nitride semiconductor device is characterized in that a current flowing through a channel formed between the fourth nitride semiconductor layer and the first nitride semiconductor layer is controlled by a voltage applied to the control electrode .

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