KR102080744B1 - Nitride semiconductor and method thereof - Google Patents

Abstract

The present specification provides a nitride-based HFET device having a superlattice layer doped with a p-type dopant and a method of manufacturing the same.
To this end, the semiconductor device according to the embodiment includes a buffer layer; A superlattice layer formed on the buffer layer; A GaN layer formed on the superlattice layer; An AlGaN layer formed on the GaN layer; And a source electrode, a drain electrode, and a gate electrode formed on a portion of the AlGaN layer, wherein the superlattice layer may be doped with a p-type dopant.

Description

Nitride semiconductor device and method for manufacturing same

The present specification relates to a nitride-based HFET device having a superlattice layer doped with a p-type dopant, and a method of manufacturing the same.

Nitride semiconductors have been focused on high critical electric fields, low on-resistance, high temperature, and high frequency operating characteristics compared to silicon, and have been previously studied as materials for next generation semiconductor devices.

In recent years, high output power devices are mainly mainstream, MOSFETs and IGBTs, and GaN-based devices such as HEMTs, HFETs, and MOSFETs have been studied.

In the case of HEMT, the high electron mobility is used for communication devices having high frequency characteristics.

HEMT is also used in power semiconductors and communication devices having high frequency characteristics. Recently, the development of hybrid / fuel cell vehicles is underway, and a variety of companies are launching hybrid vehicles. Voltage booster converters that connect motors and generators in hybrid vehicles and semiconductor switches in inverters require reliable operation at high temperatures due to heat generated by the engine. GaN enables reliable high temperature operation due to its wide bandgap, making it suitable for next-generation semiconductor switches in hybrid vehicles.

Among them, Japan's Furukawa Electric announced AlGaN / GaN high-electron-mobility transistor (HEMT) discrete, which has a high breakdown voltage of 750 V and low on-resistance of 6.3 mΩ-cm2. , Si superjunction MOSFETs and SiC MESFETs have excellent characteristics. Also announced GaN discrete has stable switching operation even at high temperature of 225 ℃.

1 is an exemplary view showing a general structure of a heterojunction field effect transistor (HFET).

Referring to FIG. 1, a typical HFET may switch 2DEG current flowing from a drain electrode to a source electrode through a schottky gate electrode.

The general HFET 10 includes a substrate (not shown), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 formed on the first GaN layer, and a second GaN formed on the AlGaN layer. The layer 13 may include a gate electrode 14, a source electrode 15, and a drain electrode 16 formed on the second GaN layer.

In the case of a general HFET device, the quality of the schottky characteristic using the gate operation can greatly affect the switch characteristics of the device.

Therefore, there is a need for a technique that reduces the leakage current of the HFET and maximizes the breakdown voltage.

An object of the present disclosure is to provide a semiconductor device having a superlattice layer doped with a p-type dopant and exhibiting reduced leakage current characteristics and breakdown voltage characteristics and a method of manufacturing the same.

A semiconductor device according to the present disclosure for achieving the above object, the buffer layer; A superlattice layer formed on the buffer layer; A GaN layer formed on the superlattice layer; An AlGaN layer formed on the GaN layer; And a source electrode, a drain electrode, and a gate electrode formed on a portion of the AlGaN layer, wherein the superlattice layer may be doped with a p-type dopant.

As an example related to the present specification, the buffer layer may be formed of at least one of AlN and AlGaN.

As an example related to the present specification, the buffer layer may include AIN, and the buffer layer may include a first AIN layer grown at low temperature; And a second AIN layer formed on the first AIN layer and grown at a high temperature.

As an example related to the present specification, the buffer layer may be made of AlGaN, and the buffer layer may be one in which a composition of Al is gradually reduced in a stacking direction.

As an example related to the present specification, the superlattice layer may be formed by stacking a plurality of superlattice thin film layers in which two different thin film layers are stacked.

As an example related to the present specification, the superlattice thin film layer may be at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN.

As an example related to the present specification, the thicknesses of the two different thin film layers may be 1 nm to 100 nm.

As an example related to the present specification, the superlattice layer may include 3 to 500 superlattice thin film layers.

As an example related to the present specification, the p-type dopant may be at least one of Mg, C, and Fe.

As an example related to the present specification, the concentration of the p-type dopant may be 1e ¹⁶ / cm ₃ ~ 5e ²⁰ / cm ₃ .

As an example related to the present specification, the concentration of the p-type dopant may be gradually reduced in the stacking direction of the superlattice layer.

As an example related to the present specification, the GaN layer may have a thickness of about 0.1 μm to about 7 μm.

As an example related to the present specification, the GaN layer may be doped with at least one dopant of Mg, C, and Fe, and the at least one dopant concentration may be 1e ¹⁶ / cm ₃ to 5e ²⁰ / cm ₃ . .

As an example related to the present specification, the thickness of the AlGaN layer may be 2 nm to 100 nm.

As an example related to the present specification, the semiconductor device may further include a GaN cap layer formed on the AlGaN layer.

As an example related to the present specification, the thickness of the GaN cap layer may be 2 nm to 10 nm.

As an example related to the present specification, the buffer layer may be formed on a substrate.

As an example related to the present specification, the substrate may be formed of at least one of Si, SiC, Sapphire, and GaN.

As an example related to the present specification, the semiconductor device may further include an oxide layer formed on a portion of the AlGaN layer, the source electrode, the drain electrode, and the gate electrode.

As an example related to the present specification, the oxide layer may be formed of at least one of SiO ₂ , Si ₃ N ₄ , HfO ₂ , Al ₂ O ₃ , ZnO, and Ga ₂ O ₃ .

As an example related to the present specification, the thickness of the oxide layer may be 2 nm to 200 nm.

Method for manufacturing a semiconductor device according to the present specification for achieving the above objects,

Forming a buffer layer on the substrate; Forming a superlattice layer on the buffer layer; Forming a GaN layer on the superlattice layer; Forming an AlGaN layer on the GaN layer; And forming a source electrode, a drain electrode, and a gate electrode on a portion of the AlGaN layer, wherein the superlattice layer may be doped with a p-type dopant.

As an example related to the present specification, the buffer layer, the superlattice layer, the GaN layer, and the AlGaN layer may include an organic metal vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), and a helide vapor deposition method (HVPE). It may be formed based on at least one of plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

As an example related to the present specification, the p-type dopant may be Fe, and the superlattice layer may be doped with the p-type dopant based on a Cp ₂ Fe source.

According to one embodiment disclosed herein, a semiconductor device having a superlattice layer doped with a p-type dopant exhibits reduced leakage current characteristics and breakdown voltage characteristics, and a method of manufacturing the same.

In particular, according to the semiconductor device disclosed herein, in order to minimize leakage current increase and decrease in breakdown voltage, it has a superlattice structure of AlN / GaN, and has a superlattice layer doped with a p-type dopant, thereby providing a vertical and lateral structure. Additional benefits to reduce leakage current and, in particular, when using Fe as a p-type dopant, improve crystallinity by GaN slow growth through Fe doping to prevent degradation of AlN / GaN interface and film quality This can be.

1 is an exemplary view showing a general structure of a heterojunction field effect transistor (HFET).
2 is an exemplary view illustrating a structure of a semiconductor device according to an exemplary embodiment disclosed herein.
3 is a graph showing a doping profile of Fe dopant according to one embodiment disclosed herein.
4 is a graph showing a doping profile of Fe dopant according to another embodiment disclosed herein.
5 is a flowchart illustrating a method of manufacturing a semiconductor device according to one embodiment disclosed herein.
6A to 6F are exemplary views illustrating a method of manufacturing a semiconductor device according to an embodiment disclosed in the present specification.

The technique disclosed herein can be applied to a heterojunction field effect transistor and a method of manufacturing the same. However, the technology disclosed in the present specification is not limited thereto, and may be applied to all nitride-based semiconductor devices and a method of manufacturing the same, to which the technical spirit of the technology may be applied.

It is to be noted that the technical terms used herein are merely used to describe particular embodiments, and are not intended to limit the spirit of the technology disclosed herein. In addition, the technical terms used herein should be interpreted as meanings generally understood by those skilled in the art to which the technology disclosed herein belongs, unless defined otherwise in this specification. It should not be interpreted in a comprehensive sense, or in an overly reduced sense. In addition, when the technical terms used herein are incorrect technical terms that do not accurately express the spirit of the technology disclosed herein, it will be replaced with technical terms that can be understood correctly by those skilled in the art. In addition, the general terms used herein should be interpreted as defined in the dictionary, or according to the context before and after, and should not be interpreted in an excessively reduced sense.

Also, the singular forms used herein include the plural forms unless the context clearly indicates otherwise. In this specification, terms such as “consisting of” or “comprising” should not be construed as necessarily including all of the various components or steps described in the specification, and some of the components or some steps It should be construed that it may not be included or may further include additional components or steps.

In addition, terms including ordinal numbers, such as first and second, as used herein may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments disclosed herein will be described in detail with reference to the accompanying drawings, and the same or similar components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

In addition, in describing the technology disclosed herein, if it is determined that the detailed description of the related known technology may obscure the gist of the technology disclosed herein, the detailed description thereof will be omitted. In addition, it is to be noted that the accompanying drawings are only for easily understanding the spirit of the technology disclosed in this specification, and the spirit of the technology should not be construed as being limited by the accompanying drawings.

In nitride semiconductor elements In the buffer layer  Description of

In a nitride semiconductor power device having a heterojunction structure, there may be various methods to reduce leakage current from the epi thin film.

In particular, there may be a method of growing at least one buffer layer between the substrate and the GaN layer to reduce the leakage current.

In addition, in order to efficiently reduce leakage current through the buffer layer, not only the semi-insulating function of the GaN channel should be strengthened, but also the crystal defects of the buffer layer for growing it are minimized and the semi-insulating characteristics are also increased to increase the device active area. The vertical and lateral leakage currents coming from may need to be minimized.

In particular, this is a necessary part of the operation of the high-power device.

The technique disclosed herein proposes an effective epi structure that reduces the leakage current of the buffer layer for GaN growth.

According to one embodiment disclosed herein, there may be three kinds of buffer layers for growing GaN on a substrate (eg, Si substrate). For example, the buffer layer may be formed of AlN, AlGaN, and a superlattice structure.

Firstly, AlN buffers can be used in combination with low and high temperatures. That is, the lower portion of the AIN buffer may be formed by low temperature growth, and the upper portion of the AIN buffer may be formed by high temperature growth.

Secondly, a continuous graded or step graded buffer having a high Al composition in the lower layer of the AlGaN buffer and a low Al composition in the upper layer may be used.

Finally, the buffer layer may have a superlattice buffer structure.

The superlattice buffer structure may be a structure in which two different thin film layers (or ultra thin film layers) are stacked.

For example, a combination of AlN / GaN, AlGaN / GaN, and AlN / AlGaN may be used for the type of superlattice buffer structure.

Therefore, when the buffer layer has a superlattice buffer structure (or a superlattice layer), the buffer layer (or superlattice layer) having the superlattice structure may be formed by alternately stacking two different thin film layers. have.

Among the three buffers, the superlattice structure may exhibit the lowest characteristic in terms of leakage current, and among them, the AlN / GaN combination may exhibit the lowest characteristic in terms of leakage current.

According to one embodiment disclosed herein, the three types of buffer layers may be used as a single buffer layer, but may be combined with each other and provided in one semiconductor device.

Therefore, the heterojunction nitride-based semiconductor device according to the embodiment disclosed in the present specification includes at least one buffer layer formed on a substrate, a GaN layer formed on the at least one buffer layer, and a role of an active layer formed on the GaN layer. It may include an AlGaN layer and a source electrode, a drain electrode and a gate electrode formed on a portion of the AlGaN layer.

In general, the substrate may be Si, SiC, Sapphire, GaN substrate and the like.

For example, when the substrate is a Si substrate, when the GaN layer is grown (or deposited or deposited) directly on the Si substrate, the crystallinity of the GaN layer is inferior due to the lattice constant difference between Si and GaN, and the lattice defects and the like. Due to this, there may be a problem in that the leakage current increases and the breakdown voltage characteristics decrease.

Therefore, as described above, instead of growing the GaN layer directly on the Si substrate, by growing at least one buffer layer in the middle, the crystallinity of the GaN layer can be increased, and leakage current characteristics and breakdown voltage characteristics can be improved. have.

According to one embodiment disclosed herein, the at least one buffer layer may be composed of two buffer layers, a lower buffer layer and an upper buffer layer.

The lower buffer layer may be a buffer layer (or AIN buffer layer) made of AIN or a buffer layer (or AlGaN buffer layer) made of AlGaN.

The upper buffer layer may be a superlattice layer having a superlattice structure (or a superlattice buffer structure).

The semiconductor device according to the exemplary embodiment includes a lower buffer layer and an upper buffer layer, which can more effectively prevent crystallinity degradation, leakage current increase, and breakdown voltage characteristic degradation caused by the lattice constant difference between the substrate and the GaN layer. There may be an advantage.

Hereinafter, a structure of a semiconductor device according to an exemplary embodiment disclosed herein will be described with reference to FIGS. 2 to 4.

Work disclosed herein Example  Description of semiconductor devices according to

A semiconductor device according to an embodiment disclosed in the present specification includes a buffer layer, a superlattice layer formed on the buffer layer, a GaN layer formed on the superlattice layer, an AlGaN layer formed on the GaN layer, and the AlGaN layer. It may include a source electrode, a drain electrode and a gate electrode formed on a portion of the region.

According to an embodiment, the superlattice layer may be doped with a p-type dopant.

In addition, according to an embodiment, the buffer layer may be formed of at least one of AlN and AlGaN.

According to an embodiment, the buffer layer is made of AIN, and the buffer layer includes a first AIN layer grown at a low temperature and a second AIN layer formed on the first AIN layer and grown at a high temperature. It may be.

In addition, according to an embodiment, the buffer layer may be made of AlGaN, and the buffer layer may be one in which a composition of Al is gradually reduced in a stacking direction.

According to an embodiment, the superlattice layer may be formed by stacking a plurality of superlattice thin film layers in which two different thin film layers are stacked.

According to an embodiment, the superlattice thin film layer may be at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN.

In addition, according to an embodiment, the thickness of each of the two different thin film layers may be 1 nm to 100 nm.

In addition, according to an embodiment, the superlattice layer may include 3 to 500 superlattice thin film layers.

In addition, according to one embodiment, the p-type dopant may be at least one of Mg, C and Fe.

In addition, according to an embodiment, the concentration of the p-type dopant may be 1e16 / cm 3 to 5e20 / cm 3.

In addition, according to an embodiment, the concentration of the p-type dopant may be gradually reduced in the stacking direction of the superlattice layer.

In addition, according to one embodiment, the GaN layer may have a thickness of 0.1 μm to 7 μm.

According to an embodiment, the GaN layer may be doped with at least one dopant of Mg, C, and Fe, and the at least one dopant concentration may be 1e16 / cm 3 to 5e20 / cm 3.

In addition, according to one embodiment, the thickness of the AlGaN layer may be 2nm ~ 100nm.

In addition, according to an embodiment, the semiconductor device may further include a GaN cap layer formed on the AlGaN layer.

In addition, according to one embodiment, the thickness of the GaN cap layer may be 2nm ~ 10nm.

In addition, according to an embodiment, the buffer layer may be formed on a substrate.

In addition, according to one embodiment, the substrate may be made of at least one of Si, SiC, Sapphire and GaN.

In addition, according to an embodiment, the semiconductor device may further include an oxide layer formed on a portion of the AlGaN layer, the source electrode, the drain electrode, and the gate electrode.

In addition, according to an embodiment, the oxide layer may be formed of at least one of SiO 2, Si 3 N 4, HfO 2, Al 2 O 3, ZnO, and Ga 2 O 3.

In addition, according to an embodiment, the thickness of the oxide layer may be 2 nm to 200 nm.

2 is an exemplary view illustrating a structure of a semiconductor device according to an exemplary embodiment disclosed herein.

Referring to FIG. 2, the semiconductor device D100 according to the exemplary embodiment disclosed herein may include a buffer layer 100, a superlattice layer 200, a GaN layer 300, an AlGaN layer 400, and a source electrode 600. The gate electrode 700 and the drain electrode 800 may be included.

In addition, the semiconductor device D100 may further include a GaN layer cap layer 500 as shown in FIG. 2.

In addition, the semiconductor device D100 may further include an oxide layer 900 to prevent surface leakage current as shown in FIG. 2.

The semiconductor device D100 according to an exemplary embodiment of the present disclosure performs a switching operation of a 2DEG current flowing from the drain electrode 800 to the source electrode 600 through a schottky gate electrode 700. can do.

Here, the buffer layer 100 may be formed on a substrate (not shown).

According to an embodiment, the substrate may be n-type, p-type, or made of various kinds of materials. For example, the substrate may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, and a Si substrate. In addition, it will be apparent to those skilled in the art that various kinds of substrates may be applied to the semiconductor devices disclosed herein.

In addition, the substrate may be removed after fabrication of the semiconductor device D100. Therefore, the final structure of the semiconductor device D100 may be a structure without the substrate.

The buffer layer 100 may be made of various materials. For example, the buffer layer 100 may be formed of at least one of AlN and AlGaN.

According to an embodiment, when the buffer layer 100 is made of AIN, the buffer layer 100 may be grown under various conditions. For example, the buffer layer 100 may include a first AIN layer grown at a low temperature and a second AIN layer formed on the first AIN layer and grown at a high temperature.

According to another embodiment, when the buffer layer 100 is made of AlGaN, the composition ratio of Al may change the stacking direction. For example, the buffer layer 100 may be made of AlGaN in which the composition of Al gradually decreases in the stacking direction.

That is, the Al composition of the AlGaN layer may be represented by Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1). For example, the composition of Al may be continuous and gradually decreasing. In addition, for example, the composition of Al may be gradually reduced stepwise (or stepwise).

The change in Al composition may be similar to the Fe doping concentration profile disclosed in FIGS. 3 to 4.

In addition, it will be apparent to those skilled in the art that the buffer layer 100 may be formed based on various materials, composition ratios, and growth conditions.

The buffer layer 100 may be formed in various ways (or methods). For example, the buffer layer 100 may be formed through a method of selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), and helide vapor deposition (HVPE). It may be formed based on at least one of). However, considering the crystallinity of the buffer layer 100, it may be common to use the MOCVD method for manufacturing the device.

The superlattice layer 200 may be formed by stacking a plurality of superlattice thin film layers 210 in which two different thin film layers 201 and 202 are stacked.

In other words, the superlattice layer 200 may be formed by alternately stacking two different thin film layers 201, 202, or ultra thin layers.

The superlattice thin film layer 210 may be made of various materials. For example, the superlattice thin film layer 210 may be at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. That is, it may mean that each of the two different thin film layers 201 and 202 is formed of at least one combination of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. In addition, it is apparent to those skilled in the art that the superlattice thin film layer 210 may be made of various materials.

According to an embodiment, the Al composition of AlGaN may be represented by Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1), and the composition of Al may change according to the stacking direction. For example, the Al composition of AlGaN may be similar to the composition change of Al of the AlGaN buffer layer described above (see also FIGS. 3 to 4).

According to an embodiment, the thicknesses of the two different thin film layers 201 and 202 may be 1 nm to 100 nm. In particular, the thicknesses of the two different thin film layers 201 and 202 may be 5 nm to 35 nm.

In addition, according to an embodiment, the superlattice layer 200 may include 3 to 500 superlattice thin film layers 210. In other words, the superlattice layer 200 may be provided with two different thin film layers 201 and 202 of 3 to 500 pairs. In another meaning, the superlattice layer 200 may be formed by alternately stacking two different thin film layers 201 and 202 5 to 999 times.

The superlattice layer 200 may be formed in various ways (or methods). For example, the superlattice layer 200 may be formed through a method for selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), and helide vapor phase growth It may be formed based on at least one of (HVPE). However, considering the crystallinity of the superlattice layer 200, it may be common to use the MOCVD method for manufacturing the device.

According to one embodiment disclosed herein, the superlattice buffer structure (or superlattice layer, 200) may be formed by doping a specific dopant.

According to one embodiment, the specific dopant may be a p-type dopant. For example, the p-type dopant may be at least one of Mg, C, and Fe.

The p-type dopant may be doped into the superlattice layer 200 in various ways (or methods).

For example, when the superlattice layer 200 has an AlN / GaN superlattice structure and the p-type dopant is C, growth of GaN to carbon doping the superlattice layer 200 is performed. The p-type dopant may be doped into the superlattice layer 200 by increasing the speed to form (or doping) a high carbon content in the TMGa source itself inside the GaN crystal.

Further, for example, if the superlattice layer 200 has an AlN / GaN superlattice structure and the p-type dopant is Fe, intentionally Fe doping using (or based on) a Cp2Fe source. By creating a new trap, a superlattice buffer structure can be formed that does not deteriorate the quality of the thin film and can also have a semi-insulating effect.

When the p-type dopant is Fe, the GaN growth rate of AlN / GaN may be lowered as much as possible to improve the crystallinity of the interface. In other words, when Fe (iron) doping is used, a new trap by Fe dopant is formed while maintaining high-quality crystallinity due to the slow growth of GaN, resulting in semi-insulating effect and reducing leakage current more efficiently. It may have an advantage.

According to one embodiment disclosed herein, the concentration of the p-type dopant may be 1e ¹⁶ / cm ³ ~ 5e ²⁰ / cm ³ . In particular, the concentration of the p-type dopant may be 3e ¹⁷ / cm ³ ~ 1e ²⁰ / cm ³ .

In addition, according to an embodiment, the concentration of the p-type dopant may be gradually reduced in the stacking direction of the superlattice layer 200. For example, the concentration of the p-type dopant may be continuous and gradually decreasing. Also, for example, the concentration of the p-type dopant may be gradually reduced stepwise.

In other words, the p-type dopant may be doped based on a doping profile indicating an amount of doping with respect to the p-type dopant in the stacking direction of the superlattice layer 200.

Here, the doping profile may be a doping profile in which the doping amount of the p-type dopant is reduced to a specific slope in a stacking direction from a specific position of the superlattice layer.

The doping profile may be a doping profile in which the doping amount of the p-type dopant decreases stepwise (or stepwise) in a stacking direction from a specific position of the superlattice layer.

In addition, according to one embodiment, the doping amount of the p-type dopant may be to be less than the minimum doping amount from the top of the superlattice layer 200 to a specific depth.

The specific depth may be 2 nm to 50 nm. The minimum doping amount may be 1e ¹⁶ / cm ³ to 1e ¹⁷ / cm ³ .

3 is a graph showing a doping profile of Fe dopant according to one embodiment disclosed herein.

3 shows the case where the p-type dopant is Fe.

Referring to FIG. 3, a doping profile for the Fe doping concentration in the superlattice layer 200 may be confirmed.

The Fe doping concentration may be continuously and gradually decreased from the second point P2 to the first point P1 in the superlattice layer 200.

According to an embodiment, the Fe doping concentration at the second point P2 may be 5e ²⁰ / cm ³ .

According to an embodiment, the Fe doping concentration at the first point P1 may be 1e ¹⁶ / cm ³ .

In addition, according to one embodiment, from the top of the superlattice layer 200 to a specific depth Δl may be less than the minimum doping amount. For example, the specific depth Δl may be 2 nm to 50 nm, and FIG. 3 illustrates a case in which the specific depth Δl is 50 nm.

4 is a graph showing a doping profile of Fe dopant according to another embodiment disclosed herein.

4 shows the case where the p-type dopant is Fe.

Referring to FIG. 4, a doping profile for the Fe doping concentration in the superlattice layer 200 may be confirmed.

The Fe doping concentration may be gradually reduced stepwise from the sixth point in the superlattice layer 200 to the third point (P6 ~ P3).

As in FIG. 3, the Fe doping concentration at the sixth point P6 may be 5e ²⁰ / cm ³ , and the Fe doping concentration at the third point may be 1e ¹⁶ / cm ³ .

In addition, from the top of the superlattice layer 200 to a specific depth Δl may be less than the minimum doping amount. For example, the specific depth Δl may be 2 nm to 50 nm, and FIG. 4 illustrates a case in which the specific depth Δl is 50 nm.

Referring back to FIG. 2, the GaN layer 300 may have a thickness of 0.1 μm to 7 μm. In particular, the thickness of the GaN layer 300 may be 1um ~ 3um.

The GaN layer 300 may be formed in various ways (or methods). For example, the GaN layer 300 may be formed by a method of selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE) and helide vapor deposition ( HVPE) may be formed based on at least one. However, considering the crystallinity of the GaN (300), it may be common to use the MOCVD method for manufacturing the device.

In example embodiments, the semiconductor device D100 has a high resistance to exhibit semi-insulating properties of a GaN channel formed by implanting at least one of C, Fe, and Mg dopants onto the GaN layer 300. It may further include a GaN layer (not shown). Here, the concentration of the at least one dopant may be at least one of Mg, C and Fe. In addition, the concentration of the at least one dopant may be 1e ¹⁶ / cm ³ ~ 5e ²⁰ / cm ³ . In particular, the concentration of the at least one dopant may be 3e ¹⁷ / cm ³ ~ 1e ²⁰ / cm ³ .

The AlGaN layer 400 may be formed on the GaN layer 300. The AlGaN layer 400 may serve as an active layer.

According to one embodiment, the thickness of the AlGaN layer 400, 2nm ~ 100nm, in particular, the thickness of the AlGaN layer 400 may be 10nm ~ 30nm.

The AlGaN layer 400 may be formed of various materials and compositions. For example, the AlGaN layer 120 may be made of Al _x Ga _{1 - x} N. In addition, it is apparent to those skilled in the art that the AlGaN layer 120 may be formed by various materials or composition ratios.

The AlGaN layer 400 may be formed in various ways (or methods). For example, the AlGaN layer 400 may be formed through a method of selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), and helide vapor deposition ( HVPE) may be formed based on at least one. However, considering the crystallinity of the AlGaN layer 400, it may be common to use the MOCVD method for manufacturing the device.

The GaN cap layer 500 may be formed on the AlGaN layer 400, and may be formed by thinly growing GaN.

According to one embodiment, the thickness of the GaN cap layer 500 may be in the range of 0nm to 100nm, in particular, 2nm ~ 10nm. The GaN cap layer 500 may serve to prevent surface leakage current.

The gate electrode 700, the source electrode 600, and the drain electrode 800 may be formed on a portion of the AlGaN layer 400. In addition, when the semiconductor device D100 further includes the GaN cap layer 500, the semiconductor device D100 may be formed on a portion of the GaN cap layer 500.

As described above, a 2DEG current flowing from the drain electrode 800 to the source electrode 600 may be generated through the control of the schottky gate electrode 700.

In addition, according to an embodiment, the semiconductor device D100 may be formed on an oxide layer formed on a portion of the AlGaN layer 400, the source electrode 600, the drain electrode 800, and the gate electrode 700. The layer 900 may further include.

In addition, when the semiconductor device D100 further includes the GaN cap layer 500, the oxide layer 900 may be formed on a portion of the GaN cap layer 500.

The oxide layer 900 may serve to reduce surface leakage current.

Here, the oxide layer 900 may be formed between the source electrode 600 or the drain electrode 800 and the gate electrode 700.

The oxide layer 900 may be formed of various materials or composition ratios. For example, the oxide layer 900 may be formed of at least one of SiO 2, Si _x N _y (eg, Si 3 N 4), HfO 2, Al 2 O 3, ZnO, and Ga 2 O 3.

According to one embodiment, the thickness of the oxide layer 900 is in the range of 2nm to 200nm, in particular may be 2nm to 100nm.

In addition, the oxide layer 900 may be formed in various ways. For example, the oxide layer 900 may be formed by organometallic vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), or helide vapor deposition. (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and at least one of atomic layer deposition (ALD).

Work disclosed herein Example  Description of manufacturing method of semiconductor device according to

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may be implemented by some or a combination of the structures or steps included in the above-described embodiments, or may be implemented by a combination of the embodiments, which are disclosed herein In order to clearly express a method of manufacturing a semiconductor device according to an exemplary embodiment, overlapping portions may be omitted.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a buffer layer on a substrate, forming a superlattice layer on the buffer layer, and forming a GaN layer on the superlattice layer. The method may include forming an AlGaN layer on the GaN layer, and forming a source electrode, a drain electrode, and a gate electrode on a portion of the AlGaN layer.

The superlattice layer may be doped with a p-type dopant.

In example embodiments, the buffer layer, the superlattice layer, the GaN layer, and the AlGaN layer may include an organometallic vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), a helide vapor deposition method (HVPE), and a PECVD layer. It may be formed based on at least one of plasma-enhanced chemical vapor deposition (SPE), sputtering, and atomic layer deposition (ALD).

According to an embodiment, the p-type dopant may be Fe, and the superlattice layer may be doped with the p-type dopant based on a Cp 2 Fe source.

5 is a flowchart illustrating a method of manufacturing a semiconductor device according to one embodiment disclosed herein.

Referring to FIG. 5, a method of manufacturing a semiconductor device according to an embodiment disclosed herein may be performed in the following steps.

First, a buffer layer may be formed on a substrate (S110).

Next, a superlattice layer doped with a p-type dopant may be formed on the buffer layer (S120).

Next, a GaN layer may be formed on the superlattice layer (S130).

Next, an AlGaN layer may be formed on the GaN layer (S140).

Next, a source electrode, a drain electrode, and a gate electrode may be formed on a portion of the AlGaN layer (S150).

6A to 6F are exemplary views illustrating a method of manufacturing a semiconductor device according to an embodiment disclosed in the present specification.

6A to 6F, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure may sequentially include a buffer layer 100, a superlattice layer 200 doped with a p-type dopant, a GaN layer 300, and AlGaN. Forming the layer 400 and the GaN cap layer 500.

In addition, the method of manufacturing a semiconductor device according to the exemplary embodiment disclosed herein may further include forming a source electrode, a drain electrode, and a gate electrode on a portion of the GaN layer 500.

In addition, according to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include an oxide film on a portion of the GaN cap layer 500, the source electrode 600, the drain electrode 800, and the gate electrode 700. The method may further include forming the layer 900.

6A to 6G, the detailed process sequence will be described in detail. First, the buffer layer 100 may be formed (or grown) on the substrate (not shown) with the MOCVD thin film growth equipment (FIG. 6A).

The substrate may be n-type or p-type, and the type of substrate may be Si, SiC, Sapphire, GaN substrate, or the like.

AlN and AlGaN layers may be used as the buffer layer 100, and when the AlN buffer layer is used, the buffer layer 100 may have a complex structure of a combination of low temperature AlN and high temperature AlN. That is, AlN buffer can be used in combination of low temperature and high temperature. That is, the lower portion of the AIN buffer may be formed by low temperature growth, and the upper portion of the AIN buffer may be formed by high temperature growth (see the first and second AIN layers described above).

In addition, when the AlGaN buffer layer is used as the buffer layer 100, a continuous graded or stepped graded buffer may be used from the layer having a high Al composition to the layer having a low Al composition in the upper layer. That is, the Al composition of AlGaN may be expressed as Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1), and the composition of Al is continuous, gradually reduced, or stepwise (or stepwise). May be reduced (see also FIGS. 3-4 together).

Next, the superlattice layer 200 may be formed on the buffer layer 100 (FIG. 6B).

Specifically, the superlattice layer 200 may be formed by stacking the superlattice thin film layer 210 in which two different thin film layers 201 and 202 are stacked a specific number of times. In other words, the superlattice layer 200 may be formed by alternately stacking two different thin film layers 201, 202, or ultra thin layers. For example, the specific number may be 3 to 500.

The superlattice thin film layer 210 may be made of various materials. For example, the superlattice thin film layer 210 may be at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. That is, it may mean that each of the two different thin film layers 201 and 202 is formed of at least one combination of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. In addition, it is apparent to those skilled in the art that the superlattice thin film layer 210 may be made of various materials.

According to an embodiment, the Al composition of AlGaN may be represented by Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1), and the composition of Al may change according to the stacking direction. For example, the Al composition of AlGaN may be similar to the composition change of Al of the AlGaN buffer layer described above (see also FIGS. 3 to 4).

According to an embodiment, the thicknesses of the two different thin film layers 201 and 202 may be 1 nm to 100 nm. In particular, the thicknesses of the two different thin film layers 201 and 202 may be 5 nm to 35 nm.

The superlattice layer 200 may be formed in various ways (or methods). For example, the superlattice layer 200 may be formed through a method for selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), and helide vapor phase growth It may be formed based on at least one of (HVPE). However, considering the crystallinity of the superlattice layer 200, it may be common to use the MOCVD method for manufacturing the device.

According to one embodiment disclosed herein, the superlattice buffer structure (or superlattice layer, 200) may be formed by doping a specific dopant.

According to one embodiment, the specific dopant may be a p-type dopant. For example, the p-type dopant may be at least one of Mg, C, and Fe.

The p-type dopant may be doped into the superlattice layer 200 in various ways (or methods).

For example, when the superlattice layer 200 has an AlN / GaN superlattice structure and the p-type dopant is C, growth of GaN to carbon doping the superlattice layer 200 is performed. The p-type dopant may be doped into the superlattice layer 200 by increasing the speed to form (or doping) a high carbon content in the TMGa source itself inside the GaN crystal.

Further, for example, if the superlattice layer 200 has an AlN / GaN superlattice structure and the p-type dopant is Fe, intentionally Fe doping using (or based on) a Cp2Fe source. By creating a new trap, a superlattice buffer structure can be formed that does not deteriorate the quality of the thin film and can also have a semi-insulating effect.

When the p-type dopant is Fe, the GaN growth rate of AlN / GaN may be lowered as much as possible to improve the crystallinity of the interface. In other words, when Fe (iron) doping is used, a new trap by Fe dopant is formed while maintaining high-quality crystallinity due to the slow growth of GaN, resulting in semi-insulating effect and reducing leakage current more efficiently. It may have an advantage.

According to one embodiment disclosed herein, the concentration of the p-type dopant may be 1e ¹⁶ / cm ³ ~ 5e ²⁰ / cm ³ . In particular, the concentration of the p-type dopant may be 3e ¹⁷ / cm ³ ~ 1e ²⁰ / cm ³ .

In addition, according to an embodiment, the concentration of the p-type dopant may be gradually reduced in the stacking direction of the superlattice layer 200. For example, the concentration of the p-type dopant may be continuous and gradually decreasing. Also, for example, the concentration of the p-type dopant may be gradually reduced stepwise.

In other words, the p-type dopant may be doped based on a doping profile indicating an amount of doping with respect to the p-type dopant in the stacking direction of the superlattice layer 200 (see FIGS. 3 to 4). .

Here, the doping profile may be a doping profile in which the doping amount of the p-type dopant is reduced to a specific slope in a stacking direction from a specific position of the superlattice layer.

The doping profile may be a doping profile in which the doping amount of the p-type dopant decreases stepwise (or stepwise) in a stacking direction from a specific position of the superlattice layer.

In addition, according to one embodiment, the doping amount of the p-type dopant may be to be less than the minimum doping amount from the top of the superlattice layer 200 to a specific depth.

The specific depth may be 2 nm to 50 nm. The minimum doping amount may be 1e ¹⁶ / cm ³ to 1e ¹⁷ / cm ³ .

Next, a GaN layer 300 may be formed on the superlattice layer 200 (FIG. 6C).

GaN constituting the GaN layer 300 may be generally manufactured by an organometallic gas phase growth method called MOCVD.

In this case, the GaN layer 300 may be formed by epi growth by synthesizing Ga ₃ , NH ₃ , which is a raw material of Ga, and NH ₃ , which is a raw material of N, in a reactor.

According to one embodiment, the thickness of the GaN layer 300 may be 1 ~ 10um. In particular, the thickness of the GaN layer 300 may be 0.1um ~ 7um.

As described above, a high-resistance GaN layer (or high-resistivity GaN) is added to the GaN layer 300 to prevent leakage current (semi-insulating properties) using C, Fe, or Mg dopants. You can grow.

The concentration of C, Fe or Mg dopant may be 1e ¹⁶ / cm ³ to 5e ²⁰ / cm ³ . In particular, the concentration of the C, Fe or Mg dopant (dopant) may be 3e ¹⁷ / cm ³ ~ 1e ²⁰ / cm ³ .

Next, after the GaN layer 300 is grown, an AlGaN layer 400 which is an active layer may be grown (FIG. 6D).

According to one embodiment, the thickness of the AlGaN layer 400 may be in the range of 2nm to 100nm, in particular, 10nm to 30nm.

In addition, after the active layer is grown, a GaN cap layer 500 may be grown to prevent surface leakage current (FIG. 6E).

According to an embodiment, the GaN cap layer 500 may be in a range of 0 nm to 100 nm, particularly, 2 nm to 10 nm.

Next, the gate electrode 700, the source electrode 600, and the drain electrode 800 may be formed on a portion of the GaN cap layer 500 (FIG. 6E).

Next, an oxide layer 900 may be formed on the GaN cap layer 500, the gate electrode 700, the source electrode 600, and the drain electrode 800 (FIG. 6F).

The oxide layer 900 may serve to reduce surface leakage current.

Here, the oxide layer 900 may be formed between the source electrode 600 or the drain electrode 800 and the gate electrode 700.

The oxide layer 900 may be formed of various materials or composition ratios. For example, the oxide layer 900 may be formed of at least one of SiO 2, Si _x N _y (eg, Si 3 N 4), HfO 2, Al 2 O 3, ZnO, and Ga 2 O 3.

According to one embodiment, the thickness of the oxide layer 900 is in the range of 2nm to 200nm, in particular, may be 2nm ~ 100nm.

In addition, the oxide layer 900 may be formed by various methods. For example, the oxide layer 170 may be formed by organometallic vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), or helide vapor deposition. (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and at least one of atomic layer deposition (ALD).

As described above, according to one embodiment disclosed herein, a semiconductor device having a superlattice layer doped with a p-type dopant exhibiting reduced leakage current characteristics and breakdown voltage characteristics and a method of manufacturing the same are provided.

In particular, according to the semiconductor device disclosed herein, in order to minimize leakage current increase and decrease in breakdown voltage, it has a superlattice structure of AlN / GaN, and has a superlattice layer doped with a p-type dopant, thereby providing a vertical and lateral structure. Additional benefits to reduce leakage current and, in particular, when using Fe as a p-type dopant, improve crystallinity by GaN slow growth through Fe doping to prevent degradation of AlN / GaN interface and film quality This can be. In other words, when Fe (iron) doping is used, it produces semi-insulating effect and reduces leakage current more efficiently by forming new trap by Fe dopant while maintaining high quality crystallinity due to the slow growth of GaN. It can have an advantage.

The scope of the present invention is not limited to the embodiments disclosed herein, and the present invention can be modified, changed, or improved in various forms within the scope of the spirit and claims of the present invention.

D100: semiconductor device 100: buffer layer
200: superlattice layer 300: GaN layer
400: AlGaN layer 500: GaN cap layer
600: source electrode 700: gate electrode
800: drain electrode 900: oxide film layer

Claims (24)

Buffer layer;
A superlattice layer formed on the buffer layer;
A GaN layer formed on the superlattice layer;
An AlGaN layer formed on the GaN layer; And
A source electrode, a drain electrode, and a gate electrode formed on a portion of the AlGaN layer,
The superlattice layer is doped with a p-type dopant,
The concentration of the p-type dopant is gradually reduced in the stacking direction of the superlattice layer. The method of claim 1, wherein the buffer layer,
A semiconductor device comprising at least one of AlN and AlGaN. The method of claim 2, wherein the buffer layer,
Made of AIN,
The buffer layer,
A first AIN layer grown at low temperature; And
And a second AIN layer formed on the first AIN layer and grown at a high temperature. The method of claim 2, wherein the buffer layer,
Made of AlGaN,
The buffer layer,
A semiconductor device in which the composition of Al is gradually reduced in the stacking direction. The method of claim 1, wherein the superlattice layer,
2. A semiconductor device in which a plurality of superlattice thin film layers in which two different thin film layers are stacked are stacked. The method of claim 5, wherein the superlattice thin film layer,
At least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. The thickness of each of the two different thin film layers,
1 nm to 100 nm semiconductor device. The method of claim 5, wherein the superlattice layer,
Semiconductor device comprising 3 to 500 superlattice thin film layer. The method of claim 1, wherein the p-type dopant,
At least one of Mg, C and Fe. The method of claim 1, wherein the concentration of the p-type dopant,
A semiconductor device having 1E16 / cm³ to 5E20 / cm³. delete The method of claim 1, wherein the thickness of the GaN layer,
A semiconductor device of 0.1 μm to 7 μm. The method of claim 1, wherein the GaN layer,
Doped with at least one dopant of Mg, C and Fe,
The at least one dopant concentration is,
A semiconductor device having 1E16 / cm³ to 5E20 / cm³. The method of claim 1, wherein the thickness of the AlGaN layer,
2nm to 100nm semiconductor device. The method of claim 1,
And a GaN cap layer formed on the AlGaN layer. The method of claim 15, wherein the thickness of the GaN cap layer,
A semiconductor device of 2 nm to 10 nm. The method of claim 1, wherein the buffer layer,
The semiconductor device is formed on a substrate. The method of claim 17, wherein the substrate,
A semiconductor device comprising at least one of Si, SiC, Sapphire and GaN. The method of claim 1,
And an oxide layer formed on a portion of the AlGaN layer, the source electrode, the drain electrode, and the gate electrode. The method of claim 19, wherein the oxide film layer,
A semiconductor device comprising at least one of SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZnO, and Ga ₂ O ₃ . The method of claim 19, wherein the thickness of the oxide film layer,
2 nm to 200 nm. delete delete delete

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