CN103094281A

CN103094281A - 5 voltages complementary metal-oxide-semiconductor transistor (CMOS) component structure and manufacturing method thereof

Info

Publication number: CN103094281A
Application number: CN2011103485918A
Authority: CN
Inventors: 刘冬华; 钱文生; 胡君; 段文婷; 石晶
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-07
Filing date: 2011-11-07
Publication date: 2013-05-08
Anticipated expiration: 2031-11-07
Also published as: CN103094281B

Abstract

The invention discloses a 5 voltage complementary metal-oxide-semiconductor transistor (CMOS) component structure. The 5 voltage CMOS component structure comprises the steps that a P trap (N trap) is formed on a silicon substrate and, the P trap (N trap) and a shallow groove is separated from the shallow groove, a gate oxide is formed on the P trap (N trap), gate polysilicon is formed on the gate oxide, and separating side walls are formed on two sides of the gate oxide and two sides of the gate polysilicon. Connecting metal wires are leaded out from a contacting hole of the P trap (N trap), wherein the thickness of the gate oxide is unevenly distributed. The invention also discloses a manufacturing method of the 5 voltage CMOS component structure. By using the facts that the thickness of the border position is larger than that of the middle position and the non-uniform-thickness gate oxide can increase the breakdown voltage of a circuit, the 5 voltage CMOS component structure and the manufacturing method of the 5 voltage CMOS component structure have the advantage of improving the voltage withstanding stability of the circuit.

Description

A kind of 5V cmos device structure and manufacture method thereof

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to a kind of 5V cmos device structure.The invention still further relates to a kind of manufacture method of 5V cmos device structure.

Background technology

The 5V device has been widely used in circuit design.5v voltage is a kind of input and output voltage that extensively adopts at present, to the demand widely that has of 5v device, is all to adopt them to design imput output circuit usually in present circuit reality.For 5v cmos device, the key parameters such as its threshold voltage, drive current and cut-off current, everybody relatively pays close attention to.But in the circuit application of reality, the puncture voltage of mosfet is also very important important parameter.The method of the monitoring mosfet puncture voltage that industry is general is as follows: substrate, source and grounded-grid, and drain terminal adds bias voltage, (100nA/um usually), just think that this voltage is puncture voltage when the electric current of drain terminal reaches a certain standard.When the length long enough of raceway groove, puncture or occur in gate oxide, or occurring between the pn knot of source leakage-substrate.When the puncture voltage of reality test 5v device, we can see that the drain terminal electric current when puncturing equates with the electric current that substrate monitors, so we can puncturing of decision device be to cause because the pn between the leakage-substrate of source binds up one's hair to give birth to puncture.But the puncture voltage of pn knot is leaked in the puncture voltage of comparator device and source, and common device electric breakdown strength forces down than the breakdown potential that the pn knot is leaked in the source.

As shown in Figure 1 and Figure 2, a kind of traditional 5V MOSFET device architecture breakdown potential occurs in the position 10 under gate edge of being in of drain terminal.Industry is in order to improve the withstand voltage of device, and there is diverse ways in different companies, ties engineering (Junction Engineering) but mostly concentrate on.Such as adopting codope drain terminal (Double Doped Drain); And for example the extension by drain terminal extend to increase withstand voltage, such as the LDMOS structure.Through scrutinizing punch-through and the mechanism of 5v device, by semiconductor technology and device simulation instrument, we find, when device punctures, its breakdown potential occurs in the position under gate edge of being in of drain terminal, rather than the metallurgical junction position of leaking pn circle, our source that it has been generally acknowledged that.This phenomenon has been given us enlightenment: can not tie by pn the raising that technologic change realizes device electric breakdown strength.

Summary of the invention

The technical problem to be solved in the present invention is to provide the puncture voltage that a kind of 5V cmos device structure can improve circuit, can increase the withstand voltage stability of circuit.For this reason, the present invention also provides the manufacture method of planting 5V cmos device structure.

For solving the problems of the technologies described above, 5V cmos device structure of the present invention comprises:

Be formed with on silicon substrate P trap (or N trap) and shallow trench isolation from, be formed with gate oxide on described P trap (or N trap), be formed with gate polysilicon on described gate oxide, isolation side walls is formed on gate oxide and gate polysilicon both sides, and described gate polysilicon and P trap (or N trap) are drawn the connection metal line by contact hole; Wherein, described gate oxide thickness non-uniform Distribution.

The thickness of described gate oxide edge is greater than the thickness of middle part.

The thickness of described gate oxide middle part is 10 nanometer to 20 nanometers.

The width of described gate oxide edge is 1 nanometer to 10 nanometer.

5V cmos device structure making process of the present invention comprises:

(1) make on P type substrate shallow trench isolation from, make the P trap;

(2) growth gate oxide, the growth gate polysilicon;

(3) carry out the gate polysilicon etching;

(4) carry out the hydrofluoric acid wet etching;

(5) carrying out gate polysilicon reoxidizes;

(6) etching is made isolation side walls;

(7) P trap and gate polysilicon are drawn the connection metal line by contact hole.

Further improve, during implementation step (1), make the N trap on P type substrate.

Further improve, during implementation step (2), the growth gate oxide thickness is 10 nanometer to 20 nanometers.

Further improve, during implementation step (4), to the middle part etching, the etching width is 1 nanometer to 10 nanometer to the hydrofluoric acid wet etching by position, gate oxide both sides of the edge.

5V cmos device structure of the present invention utilizes the gate oxide of thickness non-uniform Distribution can improve the puncture voltage of circuit, can increase the withstand voltage stability of circuit.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is a kind of schematic diagram of traditional 5V cmos device structure.

Fig. 2 is the strong and weak emulation schematic diagram of the carrier impact of traditional 5V cmos device structure devices when puncturing.

The schematic diagram of Fig. 3 5V cmos device of the present invention structure.

Fig. 4 is the partial enlarged drawing of gate oxide in Fig. 2 (4).

Fig. 5 is the electric-field intensity distribution contrast schematic diagram of drain terminal under identical bias voltage of 5V cmos device structure of the present invention and traditional 5V CMOS

Fig. 6 is the flow chart of 5V cmos device structure of the present invention manufacturing side.

Fig. 7 is the schematic diagram one of the present invention side of manufacturing, and it shows the device architecture that forms behind implementation step (1), (2).

Fig. 8 is the schematic diagram two of the present invention side of manufacturing, and it shows the device architecture that forms behind implementation step (3), (4).

Fig. 9 is the schematic diagram three of the present invention side of manufacturing, and it shows the device architecture that forms after implementation step (5).

Description of reference numerals

The 1st, P type substrate 2 are shallow trench isolations from

The 3rd, P trap/N trap 4 is gate oxides

4.1 be that gate oxide middle part 4.2 is gate oxide edges

The 5th, gate polysilicon

The 6th, isolation side walls 7 is sources/leakage of MOSFET

The 8th, contact hole 9 is metal wires

The 10th, the electric field concentrated area

A is the Electric Field Distribution curve of 5V cmos device of the present invention

B is the Electric Field Distribution curve of traditional 5V cmos device

C is the gate oxide marginal position.

Embodiment

As shown in Figure 3, Figure 4,5V cmos device structure of the present invention comprises:

Be formed with P trap (or N trap) 1 and shallow trench isolation on silicon substrate from 2, be formed with gate oxide 4 on described P trap (or N trap) 1, be formed with gate polysilicon 5 on described gate oxide 4, isolation side walls 6 is formed on gate oxide 4 and gate polysilicon 5 both sides, and described gate polysilicon 5 and P trap (or N trap) 1 drawn connection metal line 9 by contact hole 8; Wherein, described gate oxidation 4 layer thickness non-uniform Distribution have gate oxide middle part 4.1 and gate oxide edge 4.2, and the thickness of gate oxide edge 4.2 is greater than the thickness of gate oxide middle part 4.1.5V cmos device structure of the present invention, it punctures and still occurs in 10 position, but under identical drain terminal bias voltage, electric field strength weakens.

As shown in Figure 6, the manufacture method of 5V cmos device structure of the present invention comprises:

(1) as shown in Figure 7, make shallow trench isolation from 2 on P type substrate 1, make P trap 3;

(2) growth gate oxide 4, growth gate polysilicon 5;

(3) as shown in Figure 8, carry out the gate polysilicon etching;

(4) carry out the hydrofluoric acid wet etching, edge 4.2 etchings of gate oxide 4 are removed, keep gate oxide middle part 4.1;

(5) as shown in Figure 9,4.2 carry out gate polysilicon and reoxidize in the gate oxide edge, and oxide layer edge 4.2 is filled up grid oxygen again, and the thickness that makes oxide layer edge 4.2 is greater than the thickness of gate oxide middle part 4.1;

(6) etching is made isolation side walls 6;

(7) P trap 2 and gate polysilicon 5 are drawn connection metal line 9 by contact hole 8, form as scheming device as shown in Figure 3.

Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. 5V cmos device structure, comprise: be formed with on silicon substrate P trap and shallow trench isolation from, be formed with gate oxide on described P trap, be formed with gate polysilicon on described gate oxide, isolation side walls is formed on gate oxide and gate polysilicon both sides, and described gate polysilicon and P trap are drawn the connection metal line by contact hole; It is characterized in that: described gate oxide thickness non-uniform Distribution.

2. 5V cmos device structure is characterized in that: be formed with on silicon substrate N trap and shallow trench isolation from.

3. 5V cmos device structure as claimed in claim 1 or 2 is characterized in that: the thickness of described gate oxide edge is greater than the thickness of middle part.

4. 5V cmos device structure as claimed in claim 3 is characterized in that: the thickness of described gate oxide middle part is 10 nanometer to 20 nanometers.

5. 5V cmos device structure as claimed in claim 3 is characterized in that: the width of described gate oxide edge is 1 nanometer to 10 nanometer.

6. the manufacture method of a 5V cmos device structure comprises:

(1) make on P type substrate shallow trench isolation from, make the P trap;

(2) growth gate oxide, the growth gate polysilicon;

(3) carry out the gate polysilicon etching;

(4) carry out the hydrofluoric acid wet etching;

(5) carrying out gate polysilicon reoxidizes;

(6) etching is made isolation side walls;

7. manufacture method as claimed in claim 6, is characterized in that: during implementation step (1), make the N trap on P type substrate.

8. manufacture method as claimed in claim 6 is characterized in that: during implementation step (2), the growth gate oxide thickness is 10 nanometer to 20 nanometers.

9. manufacture method as claimed in claim 8, it is characterized in that: during implementation step (4), to the middle part etching, the etching width is 1 nanometer to 10 nanometer to the hydrofluoric acid wet etching by position, gate oxide both sides of the edge.