CN103531592A - Tri-gate control type no-junction transistor with high mobility and low source/drain resistance - Google Patents
Tri-gate control type no-junction transistor with high mobility and low source/drain resistance Download PDFInfo
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- CN103531592A CN103531592A CN201310519069.0A CN201310519069A CN103531592A CN 103531592 A CN103531592 A CN 103531592A CN 201310519069 A CN201310519069 A CN 201310519069A CN 103531592 A CN103531592 A CN 103531592A
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Abstract
The invention relates to a tri-gate control type no-junction transistor with high mobility and low source/drain resistance. With the adoption of three gate electrodes of a source control gate electrode, a channel control gate electrode and a drain control gate electrode which are mutually and independently controlled, a device can guarantee high mobility in a channel with low dosage concentration, device stability decrease caused by a high dosage concentration random scattering enhancement effect is avoided, and at the same time, lower source/drain resistance can be obtained through independent control effects of the source control gate electrode and the drain control gate electrode, so that the contradiction between increase, caused by over low dosage concentration of an ordinary no-junction transistor channel, of source/drain resistance and decrease, caused by over high dosage concentration, of the device mobility and the stability is effectively solved, and the tri-gate control type no-junction transistor is suitable for popularization and application.
Description
Technical field
The invention belongs to very lagre scale integrated circuit (VLSIC) and manufacture field, be specifically related to a kind of three grid control types that are applicable to the low source of the high mobility ohmic leakage that superelevation integrated level integrated circuit manufactures without junction transistors structure.
Background technology
Elementary cell MOSFETs transistor constantly the reducing along with size of integrated circuit, the concentration difference that need to realize a plurality of orders of magnitude in the distance of several nanometers forms extremely steep source electrode and drain electrode PN junction, and such concentration gradient has high requirement for doping and Technology for Heating Processing.By the field-effect transistor without knot of making on SOI wafer, can effectively address the above problem, without junction transistors, adopt how sub-conducting, the source region of device, drain region and channel region have identical high-dopant concentration, utilization is done to obtain enough thin features by silicon thin film, take N-type device as example, when grid is during in reverse biased, because silicon thin film is very thin, the electronics of channel region is easy to depleted under the effect of grid electric field, thereby realizes the blocking state of device.Along with the increase of grid bias, many sons of channel region exhaust releasing, and in interface, form electron accumulation to realize the unlatching of device.Yet the raceway groove of this high-dopant concentration can cause the mobility of device obviously to decline, and impurity random scatter meeting causes the reliability of device to be had a strong impact on.For improving mobility and the reliability without junction device, just need to reduce the doping content of silicon thin film, yet the reduction of doping content can affect with the increase of source ohmic leakage the opening feature of device.Therefore, for solving above-mentioned contradiction, need design have high mobility and low source ohmic leakage without junction transistors.
Summary of the invention
Goal of the invention
For solving without the contradictory relation existing between the ohmic leakage of junction transistors mobility source, the invention provides three grid control types of the low source of a kind of high mobility ohmic leakage without the structure of junction transistors.
Technical scheme
The present invention is achieved through the following technical solutions:
Three grid control types of low source ohmic leakage, without a junction transistors, comprise the silicon substrate of SOI wafer, and the silicon substrate top of SOI wafer is the insulating barrier of SOI wafer; It is characterized in that: the insulating barrier top of SOI wafer is monocrystalline silicon thin film, and monocrystalline silicon thin film top is gate insulator, between adjacent monocrystalline silicon thin film, by insulating medium layer, isolates; The gate insulator top of each top, monocrystalline silicon thin film middle part is provided with successively source control gate electrode, raceway groove control gate electrode, leaks control gate electrode, and the top of gate insulator is provided with to be controlled source gate electrode, raceway groove control gate electrode and leak the insulating medium layer that control gate electrode is isolated from each other; By etching technics, etch away each top position, monocrystalline silicon thin film two ends corresponding gate insulator and insulating medium layer, and in the through hole etching away, inject metal and generate respectively source electrode and drain electrode.
Source control gate electrode, raceway groove control gate electrode and these three electrodes of leakage control gate electrode are the gate electrode of controlling independent of one another.
Monocrystalline silicon thin film is the silicon thin film of high mobility low doping concentration.
Gate insulator is insulating material dielectric layer or the silicon dioxide layer with high-k.
Advantage and effect
Tool of the present invention has the following advantages and beneficial effect:
Because the present invention adopts source control gate electrode, raceway groove control gate electrode and leaks three gate electrodes of controlling independent of one another such as control gate electrode, make the raceway groove of device under low doping concentration, when guaranteeing high mobility, the independent control action that still can be controlled gate electrode and be leaked control gate electrode by source obtains lower source ohmic leakage, thus efficiently solve common without junction transistors channel doping concentration too low can band source ohmic leakage increase and affect this problem of the opening feature of device.
Accompanying drawing explanation
Fig. 1 is the two-dimensional structure schematic diagram that three grid control types of the low source of high mobility of the present invention ohmic leakage form on SOI substrate without junction transistors;
Fig. 2 to Fig. 6 be three grid control types of the low source of high mobility of the present invention ohmic leakage without the process chart of the construction unit of junction transistors and the preparation method's of array thereof a instantiation,
Fig. 2 is step 1 schematic diagram,
Fig. 3 is step 2 schematic diagram,
Fig. 4 is step 3 schematic diagram,
Fig. 5 is step 4 schematic diagram,
Fig. 6 is step 5 schematic diagram.
Reference numeral is said:
1, source electrode; 2, source control gate electrode; 3, raceway groove control gate electrode; 4, leak control gate electrode; 5, drain electrode; 6, insulating medium layer; 7, gate insulator; 8, monocrystalline silicon thin film; 9, the insulating barrier of SOI wafer; 10, the silicon substrate of SOI wafer.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described further:
The invention provides three grid control types of the low source of a kind of high mobility ohmic leakage without junction transistors, the acting in conjunction of controlling gate electrode 2, raceway groove control gate electrode 3 and leaking control gate electrode 4 these three gate electrodes of controlling independent of one another by source, under the condition of low doping concentration, realize high mobility, low source ohmic leakage without junction transistors.Take N-type as example, when device is worked, make source control gate electrode 2 and leak control gate electrode 4 keeping constant high potential, make the two ends of monocrystalline silicon thin film 8 corresponding to below form electron accumulation, so just effectively reduced source ohmic leakage; And the working control gate electrode that raceway groove control gate electrode 3 is device, when the raceway groove blocking-up during in electronegative potential of raceway groove control gate electrode 3, device is in off state, and when raceway groove control gate electrode 3 is during in high potential, raceway groove is opened, and device is in opening.The high-performance three grid control types that have high mobility, low source ohmic leakage by above-mentioned embodiment realization are without junction transistors.
For reaching device function of the present invention, three grid control types of the low source of this high mobility ohmic leakage proposed by the invention are without junction transistors, and its core texture is characterized as:
1. for making device there is high mobility, the monocrystalline silicon thin film that monocrystalline silicon thin film 8 is low doping concentration; For the control ability of enhancing source control gate electrode 2, raceway groove control gate electrode 3 and 4 pairs of monocrystalline silicon thin films 8 of leakage control gate electrode, gate insulator 7 can be the insulating material dielectric layer with high-k, but can be also silicon dioxide layer.
2. source control gate electrode 2, raceway groove control gate electrode 3 and leakage control gate electrode 4 these three electrodes are the gate electrode of controlling independent of one another, wherein source control gate electrode 2 and leakage control gate electrode 4 keep constant high potential when device is worked, and make the two ends of monocrystalline silicon thin film 8 corresponding to below form electron accumulation with reduction source ohmic leakage; And the working control gate electrode that raceway groove control gate electrode 3 is device, when raceway groove control gate electrode 3 is during in electronegative potential, it is depleted under the effect of electric field force that monocrystalline silicon thin film 8 is positioned at the electronics of below part of raceway groove control gate electrode 3, thereby make raceway groove blocking-up, device is in off state, and when raceway groove control gate electrode 3 is during in high potential, the below part that monocrystalline silicon thin film 8 is positioned at raceway groove control gate electrode 3 accumulates electronics under the effect of electric field force, thereby raceway groove is opened, and device is in opening.
Below in conjunction with accompanying drawing, the present invention is described further:
The two-dimensional structure schematic diagram forming on SOI substrate without junction transistors as three grid control types of Fig. 1-the Figure 6 shows that low source of high mobility proposed by the invention ohmic leakage.The silicon substrate 10 that specifically comprises SOI wafer; Silicon substrate 10 tops of SOI wafer are the insulating barrier 9 of SOI wafer; Insulating barrier 9 tops of SOI wafer are monocrystalline silicon thin film 8, and monocrystalline silicon thin film 8 tops are gate insulator 7; Between adjacent monocrystalline silicon thin film 8, by insulating medium layer 6, isolate; Gate insulator 7 tops of each monocrystalline silicon thin film 8 top, middle part are provided with successively source control gate electrode 2, raceway groove control gate electrode 3, leak control gate electrode 4, and the top of gate insulator 7 is provided with to be controlled source gate electrode 2, raceway groove control gate electrode 3 and leak the insulating medium layer 6 that control gate electrode 4 is isolated from each other; By etching technics, etch away each monocrystalline silicon thin film 8 top position, two ends corresponding gate insulator 7 and insulating medium layer 6, and in the through hole etching away, inject metal and generate respectively source electrode 1 and drain electrode 5.
For making device have high mobility, the doping content of monocrystalline silicon thin film 8 is set to lower than 10
17cm
-3; For the control ability that the charge carrier in enhancing source control gate electrode 2, raceway groove control gate electrode 3 and 4 pairs of monocrystalline silicon thin films 8 of leakage control gate electrode distributes, gate insulator 7 can be the insulating material dielectric layer with high-k, can be also common earth silicon material.
Source control gate electrode 2, raceway groove control gate electrode 3 and leakage control gate electrode 4 these three electrodes are the gate electrode of controlling independent of one another, with N-type, be doped to example, wherein source control gate electrode 2 and leakage control gate electrode 4 are applied in high voltage when device is worked, and the two ends formation concentration that monocrystalline silicon thin film 8 corresponding to order below contacts with drain electrode with source electrode is higher than 10
20cm
-3electron accumulation, so just can significantly reduce near the source ohmic leakage that monocrystalline silicon thin film self brings source electrode or drain electrode, and the working control gate electrode that raceway groove control gate electrode 3 is device, when raceway groove control gate electrode 3 is during in electronegative potential, the free electron of monocrystalline silicon thin film 8 mid portions is drained and exhausts, free electron can be blocked by raceway groove control gate electrode 3 by free-pouring raceway groove, device is just in off state like this, the voltage applying along with raceway groove control gate electrode 3 constantly increases, the spent condition of the free electron of monocrystalline silicon thin film 8 mid portions is disengaged gradually like this, and then also can form electron accumulation at the mid portion of monocrystalline silicon thin film 8, raceway groove is opened, and make device in opening.Because source control gate electrode 2 and leakage control gate electrode 4 all keep high potential state in whole process, therefore the two ends of monocrystalline silicon thin film 8 are all the time in electron accumulation state, when guaranteeing the good characteristic of device channel high mobility under low doping concentration, effectively reduce source ohmic leakage.
Three grid control types of the low source of this high mobility ohmic leakage proposed by the invention are as follows without the unit of junction transistors and the concrete manufacturing technology steps of array:
Step 1, provide a SOI wafer, the below of SOI wafer is the silicon substrate 10 of SOI wafer, SOI wafer top is monocrystalline silicon thin film 8, between the two, be the insulating barrier 9 of SOI wafer, by techniques such as Implantation, photoetching, etchings, on the insulating barrier 9 of provided SOI wafer, form a series of rectangular-shaped doping contents as shown in Figure 2 lower than 10
17cm
-3the isolated island array of monocrystalline silicon thin film 8;
Step 2, as shown in Figure 3 forms insulating medium layer 6 by techniques such as deposit, etchings between the isolated island array of monocrystalline silicon thin film 8, as isolation between device cell, uses;
Step 3, as shown in Figure 4, is oxidized the upper surface of monocrystalline silicon thin film 8, or deposit has the dielectric of high-k, in order to generate gate insulator 7;
Claims (4)
1. three grid control types of the low source of high mobility ohmic leakage, without a junction transistors, comprise the silicon substrate (10) of SOI wafer, and the silicon substrate of SOI wafer (10) top is the insulating barrier (9) of SOI wafer; It is characterized in that: the insulating barrier of SOI wafer (9) top is monocrystalline silicon thin film (8), monocrystalline silicon thin film (8) top is gate insulator (7), between adjacent monocrystalline silicon thin film (8), by insulating medium layer (6), isolates; Gate insulator (7) top of top, each monocrystalline silicon thin film (8) middle part is provided with successively source control gate electrode (2), raceway groove control gate electrode (3), leaks control gate electrode (4), and the top of gate insulator (7) is provided with to be controlled source gate electrode (2), raceway groove control gate electrode (3) and leaks the insulating medium layer (6) that control gate electrode (4) is isolated from each other; By etching technics, etch away gate insulator (7) corresponding to each monocrystalline silicon thin film (8) top position, two ends and insulating medium layer (6), and in the through hole etching away, inject metal and generate respectively source electrode (1) and drain electrode (5).
2. three grid control types of the low source of high mobility according to claim 1 ohmic leakage, without junction transistors, is characterized in that: source control gate electrode (2), raceway groove control gate electrode (3) and these three electrodes of leakage control gate electrode (4) are the gate electrode of controlling independent of one another.
3. three grid control types of the low source of high mobility according to claim 1 ohmic leakage, without junction transistors, is characterized in that: monocrystalline silicon thin film (8) is the silicon thin film of high mobility low doping concentration.
4. three grid control types of the low source of high mobility according to claim 1 ohmic leakage, without junction transistors, is characterized in that: gate insulator (7) is insulating material dielectric layer or the silicon dioxide layer with high-k.
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| CN201310519069.0A CN103531592B (en) | 2013-10-29 | 2013-10-29 | Three gate control type nodeless mesh body pipes of high mobility low source and drain resistance |
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| CN103531592B CN103531592B (en) | 2016-11-23 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538443A (en) * | 2014-12-08 | 2015-04-22 | 沈阳工业大学 | High performance SOI non-junction transistor of non-monolithic substrate insulation layer thickness |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
| CN113471213A (en) * | 2021-07-02 | 2021-10-01 | 上海集成电路材料研究院有限公司 | Multi-gate MOS device based on embedded cavity SOI substrate and preparation method thereof |
| WO2022006021A1 (en) * | 2020-07-02 | 2022-01-06 | Micron Technology, Inc. | Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6051470A (en) * | 1999-01-15 | 2000-04-18 | Advanced Micro Devices, Inc. | Dual-gate MOSFET with channel potential engineering |
| KR100282454B1 (en) * | 1999-03-19 | 2001-02-15 | 김영환 | Structure of a field effect transistor and method of fabrication thereof |
| CN102237407A (en) * | 2010-04-29 | 2011-11-09 | 上海宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN103268889B (en) * | 2013-05-23 | 2016-06-01 | 清华大学 | A kind of without the horizontal tunneling field-effect transistor of knot type |
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2013
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Non-Patent Citations (1)
| Title |
|---|
| WU MEILE等: ""Simulation study on short channel double-gate junctionless field-effect transistors"", 《JOURNAL OF SEMICONDUCTORS》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538443A (en) * | 2014-12-08 | 2015-04-22 | 沈阳工业大学 | High performance SOI non-junction transistor of non-monolithic substrate insulation layer thickness |
| CN104538443B (en) * | 2014-12-08 | 2018-02-16 | 沈阳工业大学 | The high-performance SOI nodeless mesh body pipes of non-single insulated substrate thickness degree |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
| CN107068734B (en) * | 2017-01-24 | 2020-04-14 | 北京大学深圳研究生院 | Junction-free field effect transistor |
| WO2022006021A1 (en) * | 2020-07-02 | 2022-01-06 | Micron Technology, Inc. | Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies |
| US11430888B2 (en) | 2020-07-02 | 2022-08-30 | Micron Technology, Inc. | Integrated assemblies having transistors configured for high-voltage applications |
| US12027621B2 (en) | 2020-07-02 | 2024-07-02 | Micron Technology, Inc. | Method of forming integrated assemblies having transistors configured for high-voltage applications |
| CN113471213A (en) * | 2021-07-02 | 2021-10-01 | 上海集成电路材料研究院有限公司 | Multi-gate MOS device based on embedded cavity SOI substrate and preparation method thereof |
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