CN104299903A - Method for manufacturing trench MOSFET - Google Patents
Method for manufacturing trench MOSFET Download PDFInfo
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- CN104299903A CN104299903A CN201310297866.9A CN201310297866A CN104299903A CN 104299903 A CN104299903 A CN 104299903A CN 201310297866 A CN201310297866 A CN 201310297866A CN 104299903 A CN104299903 A CN 104299903A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000011248 coating agent Substances 0.000 claims description 43
- 238000000576 coating method Methods 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 150000002500 ions Chemical class 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000001459 lithography Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract description 15
- 239000012528 membrane Substances 0.000 abstract 2
- 238000004904 shortening Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- QVGXLLKOCUKJST-NJFSPNSNSA-N oxygen-18 atom Chemical compound [18O] QVGXLLKOCUKJST-NJFSPNSNSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention discloses a method for manufacturing a trench MOSFET. When conducting hard mask trench photo-etching and etching on a hard mask, the width of a formed hard mask trench in a gate region is 1.5 times larger than the width of a hard mask trench in a source region; the thickness of a deposited dielectric membrane under metal is smaller than half of the width of the hard mask trench in the gate region and is larger than half of the width of the hard mask trench in the source region; and a polysilicon etching back is full etching. The method for manufacturing a trench MOSFET in the present invention naturally form a gate contact with a proper width above the polysilicon in the trench in the gate region after full etching the polysilicon through matching the width of the hard mask trench in the gate region with the thickness of the dielectric membrane under metal, such that self-alignment is realized for etching the gate contact and polysilicon photo-etching is eliminated to only three layers of photo-etching at minimum, thereby shortening the process flow and reducing process cost.
Description
Technical field
The present invention relates to semiconductor technology, particularly the manufacture method of a kind of trench gate mosfet (mos field effect transistor).
Background technology
Trench gate mosfet (Trench MOSFET) is as a kind of novel vertical structure device, at the vertical double diffused metal-oxide semiconductor field effect transistor of VDMOS() basis on the Novel MOS tube that grows up, the advantage such as have little, the low gate-drain charge density of conducting resistance, saturation voltage is low, switching speed is fast, gully density is high, chip size is little is the main flow of mesolow (20V ~ 300V) metal-oxide-semiconductor development.
In trench gate mosfet device, namely reduction cell size improves integration density and effectively can reduce conducting resistance, and especially low-voltage device is more obvious.
Traditional trench gate mosfet as shown in Figure 1, comprise the drift region 102 of silicon substrate 100, setting drain region 101 on a semiconductor substrate, formation on drain region 101, the channel region 103 that drift region 102 is formed, the source region 104 that channel region 103 is formed, grid structure comprises the grid oxygen 106 be formed on trenched side-wall and the grid polycrystalline silicon 105 being filled with groove.For N-type trench gate mosfet, drain region adopts highly doped N-type silicon substrate, and epitaxial growth thereon has lightly doped N-type drift region 102, and channel region 103 can be injected with the doping of P type, and source region 104 can be injected with N-type doping.
The manufacture method of traditional high-density, trench gate MOSFET, comprises the following steps:
1) form drain region 11 on a silicon substrate, drain region 11 is formed drift region 12, drift region 12 is carried out hard mask (Hard mask) 13 deposits, hard mask structure can be silica 1 31+ silicon nitride 132;
2) on hard mask 13, carry out hard mask trench lithography, etching removes the hard mask at hard mask groove place, forms source region hard mask groove and the hard mask groove in grid region;
3) on silicon chip, carry out channel region Doped ions autoregistration inject and advance (drive-in), the drift region 12 at source region hard mask groove and grid region hard mask groove place forms channel region (body) 14, as shown in Figure 2;
4) at grown above silicon side wall oxide-film, then etch side wall oxide-film, in source region, the side of the hard mask at hard mask groove and hard mask groove place, grid region forms groove side wall (spacer) 15, as shown in Figure 3;
5) top, drift region 12 between etching removal groove side wall and channel region 14, form source region groove 16 and grid region groove 17, as shown in Figure 4;
6) in grown above silicon sacrificial oxidation film, etching removes sacrificial oxidation film;
7) grid oxygen 18 is formed at the trench wall of source region groove and grid region groove;
8) depositing polysilicon 19 on silicon chip;
9) polysilicon photoetching, etching is carried out, retain polysilicon 19, the polysilicon 19 in the groove of grid region and the polysilicon 19 above the groove of grid region in the groove of source region, remove other polysilicons, the polysilicon 19 above the groove of grid region covers the groove side wall of groove both sides, grid region, as shown in Figure 5;
10) the groove side wall of groove both sides, source region is removed;
11) carry out source region Doped ions autoregistration to inject, anneal, as shown in Figure 6;
12) deielectric-coating (ILD) 20 under depositing metal on silicon chip, as shown in Figure 7;
13) under carrying out metal, deielectric-coating returns etching, remove deielectric-coating under the metal on the polysilicon under the metal on the hard mask of groove both sides, source region above deielectric-coating and grid region groove, deielectric-coating under metal between the hard mask of reservation groove both sides, source region, deielectric-coating under metal on the hard mask of the polysilicon both sides above the groove of reservation grid region, as shown in Figure 8;
14) grid region is protected by photoresist, carry out the hard mask Self-aligned etching in source contact hole, remove the hard mask at source region place, retain the hard mask between grid region and grid region homologous region;
15) carrying out subsequent technique (as grown at the enterprising row metal layer 21 of silicon chip, photoetching, etching etc.), forming source electrode and grid, as shown in Figure 9.
The manufacture method of traditional high-density, trench gate MOSFET, subsistence level carries out groove (trench), polysilicon (poly), contact hole (contact), metal level (metal) four layer photoetching, wherein polysilicon layer photoetching is used for defining grid polycrystalline silicon exit, complex process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of trench gate mosfet, and minimum needs carry out groove, contact hole, metal level three layer photoetching, and technique is simple.
For solving the problems of the technologies described above, the manufacture method of trench gate mosfet provided by the invention, it comprises the following steps:
One. form drain region on a silicon substrate, drain region forms drift region, drift region is carried out hard mask deposit;
Two. on hard mask, carry out hard mask trench lithography, etching removes the hard mask at hard mask groove place, forms source region hard mask groove and the hard mask groove in grid region;
The width of grid region hard mask groove is greater than 1.5 times of the width of the hard mask groove in source region;
Three. on silicon chip, carry out channel region Doped ions autoregistration inject and advance, the drift region at source region hard mask groove and grid region hard mask groove place forms channel region;
Four. at grown above silicon side wall oxide-film, then etch side wall oxide-film, in source region, the side of the hard mask at hard mask groove and hard mask groove place, grid region forms groove side wall;
Five. the top, drift region between etching removal groove side wall and channel region, form source region groove and grid region groove;
Six. form grid oxygen at the trench wall of source region groove and grid region groove;
Seven. depositing polysilicon on silicon chip;
Eight. carry out polysilicon and return etching comprehensively, retain the polysilicon in the groove of source region and the polysilicon in the groove of grid region, remove other polysilicon;
Nine. remove the groove side wall of groove both sides, source region, the groove side wall of groove both sides, grid region;
Ten. carry out source region Doped ions autoregistration and inject, anneal;
11. deielectric-coating under depositing metal on silicon chip, under metal, the thickness of deielectric-coating is less than the half of the width of the hard mask groove in grid region, and is greater than the half of the width of the hard mask groove in source region;
12. that carries out deielectric-coating under metal returns etching comprehensively, removes deielectric-coating under the metal on hard mask, and deielectric-coating under removing the metal of the top of the polysilicon in the groove of grid region, thus forms gate contact hole above polysilicon in the groove of grid region;
13. grid region is protected by photoresist, carries out the hard mask Self-aligned etching in source contact hole, remove the hard mask at source region place, retain the hard mask between grid region and grid region homologous region;
14. carry out post-order process, form source electrode and grid.
Preferably, after step 5, before step 6, in grown above silicon sacrificial oxidation film, then etching removes sacrificial oxidation film.
Preferably, described hard mask, lower floor is silicon dioxide, and upper strata is silicon nitride.
Preferably, the width of the hard mask groove in source region is 0.5um, and the width of the hard mask groove in grid region is 1.0um, and under metal, the thickness of deielectric-coating is 0.4um.
Preferably, the width of the hard mask groove in source region is 0.5um, and the width of the hard mask groove in grid region is 1.2um, and under metal, the thickness of deielectric-coating is 0.4um.
Preferably, drain region is N+ doping, and drift region is N-doping, and channel region Doped ions is P type, and source region Doped ions is N+.
The manufacture method of trench gate mosfet of the present invention, hard mask trench lithography is being carried out to hard mask, during etching, the width of the grid region hard mask groove formed is greater than 1.5 times of the width of the hard mask groove in source region, under the metal of deposit, the thickness of deielectric-coating is less than the half of the width of grid region hard mask groove and is greater than the half of the width of the hard mask groove in source region, and polysilicon returns etching for etching comprehensively, so under metal after deielectric-coating deposit, the structure of well shape can be formed in the hard mask groove in grid region, thus can by etching returning of deielectric-coating under metal comprehensively, remove deielectric-coating under the metal on hard mask, and deielectric-coating under removing the metal of the top of the polysilicon in the groove of grid region, gate contact hole is formed above polysilicon in the groove of grid region.Trench gate mosfet manufacture method of the present invention, match with the thickness of deielectric-coating under metal by making the width of the hard mask groove in grid region, after polysilicon is etched comprehensively, the gate contact hole of self-assembling formation proper width above polysilicon in the groove of grid region, gate contact hole is etched and realizes autoregistration, eliminate polysilicon photoetching, minimum needs carry out groove (trench), contact hole (contact), metal level (metal) three layer photoetching, save one deck photoetching process, thus shortened process, reduce process costs.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the present invention, below the accompanying drawing that will use required for the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is traditional trench gate mosfet structural representation;
Fig. 2 is that the manufacture method channel region Doped ions autoregistration of traditional high-density, trench gate MOSFET is injected and sectional schematic diagram after advancing;
Fig. 3 is the rear sectional schematic diagram of manufacture method channel side stela erosion of traditional high-density, trench gate MOSFET;
Fig. 4 is sectional schematic diagram after the manufacture method source region groove of traditional high-density, trench gate MOSFET and grid region etching groove;
Fig. 5 is that the manufacture method polysilicon of traditional high-density, trench gate MOSFET returns sectional schematic diagram after etching;
Fig. 6 is the rear sectional schematic diagram of manufacture method source region Doped ions autoregistration injection of traditional high-density, trench gate MOSFET;
Fig. 7 is sectional schematic diagram after deielectric-coating deposit under the manufacture method metal of traditional high-density, trench gate MOSFET;
Fig. 8 is that under the manufacture method metal of traditional high-density, trench gate MOSFET, deielectric-coating returns sectional schematic diagram after etching;
Fig. 9 is the rear sectional schematic diagram of manufacture method metal level etching of traditional high-density, trench gate MOSFET;
Figure 10 is that the manufacture method one embodiment channel region Doped ions autoregistration of trench gate mosfet of the present invention is injected and sectional schematic diagram after advancing;
Figure 11 is sectional schematic diagram after the manufacture method one embodiment channel side stela erosion of trench gate mosfet of the present invention;
Figure 12 is sectional schematic diagram after the manufacture method one embodiment source region groove of trench gate mosfet of the present invention and grid region etching groove;
Figure 13 is that the manufacture method one embodiment polysilicon of trench gate mosfet of the present invention returns the rear sectional schematic diagram of etching;
Figure 14 is sectional schematic diagram after the manufacture method one embodiment source region Doped ions autoregistration of trench gate mosfet of the present invention is injected;
Figure 15 is sectional schematic diagram after deielectric-coating deposit under the manufacture method one embodiment metal of trench gate mosfet of the present invention;
Figure 16 is that under the manufacture method one embodiment metal of trench gate mosfet of the present invention, deielectric-coating returns the rear sectional schematic diagram of etching;
Figure 17 is sectional schematic diagram after the manufacture method one embodiment source contact hole etching of trench gate mosfet of the present invention;
Figure 18 is sectional schematic diagram after the manufacture method one embodiment metal level etching of trench gate mosfet of the present invention.
Embodiment
Below in conjunction with accompanying drawing, carry out clear, complete description to the technical scheme in the present invention, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belong to the scope of protection of the invention.
Embodiment one
The manufacture method of trench gate mosfet of the present invention, comprises the following steps:
One. form drain region 11 on a silicon substrate, drain region 11 is formed drift region 12, drift region 12 is carried out hard mask (Hard mask) 13 deposits;
Two. on hard mask 13, carry out hard mask trench lithography, etching removes the hard mask at groove place, forms source region hard mask groove and the hard mask groove in grid region; The width of grid region hard mask groove is greater than 1.5 times of the width of the hard mask groove in source region;
Three. on silicon chip, carry out channel region Doped ions autoregistration inject and advance (drive-in), the drift region 12 at source region hard mask groove and grid region hard mask groove place forms channel region (body) 14, as shown in Figure 10;
Four. at grown above silicon side wall oxide-film, then etch side wall oxide-film, in source region, the side of the hard mask at hard mask groove and hard mask groove place, grid region forms groove side wall (spacer) 15, as shown in figure 11;
Five. the top, drift region 12 between etching removal groove side wall and channel region 14, form source region groove 16 and grid region groove 17, as shown in figure 12;
Six. form grid oxygen 18 at the trench wall of source region groove and grid region groove;
Seven. depositing polysilicon 19 on silicon chip;
Eight. carry out polysilicon 19 and return etching comprehensively, the polysilicon 19 in the groove of reservation source region, the polysilicon 19 in the groove of grid region, remove other polysilicon, as shown in figure 13;
Nine. remove the groove side wall of groove both sides, source region, the groove side wall of groove both sides, grid region;
Ten. carry out source region Doped ions autoregistration and inject, anneal, as shown in figure 14;
11. deielectric-coating (ILD) 20 under depositing metal on silicon chip, under metal, the thickness of deielectric-coating 20 is less than the half of the width of the hard mask groove in grid region, and is greater than the half of the width of the hard mask groove in source region, as shown in figure 15;
12. under carrying out metal, the comprehensive of deielectric-coating returns etching 20, remove deielectric-coating under the metal on hard mask, and deielectric-coating under removing the metal of the top of the polysilicon in the groove of grid region, thus form gate contact hole above polysilicon in the groove of grid region, as shown in figure 16;
13. grid region is protected by photoresist, carries out the hard mask Self-aligned etching in source contact hole, remove the hard mask at source region place, retain the hard mask between grid region and grid region homologous region, as shown in figure 17;
14. carrying out post-order process (as grown at the enterprising row metal layer 21 of silicon chip, photoetching, etching etc.), forming source electrode and grid, as shown in figure 18.
The manufacture method of the trench gate mosfet of embodiment one, hard mask trench lithography is being carried out to hard mask, during etching, the width of the grid region hard mask groove formed is greater than 1.5 times of the width of the hard mask groove in source region, under the metal of deposit, the thickness of deielectric-coating is less than the half of the width of grid region hard mask groove and is greater than the half of the width of the hard mask groove in source region, and polysilicon returns etching for etching comprehensively, so under metal after deielectric-coating deposit, the structure of well shape can be formed in the hard mask groove in grid region, thus can by etching returning of deielectric-coating under metal comprehensively, remove deielectric-coating under the metal on hard mask, and deielectric-coating under removing the metal of the top of the polysilicon in the groove of grid region, gate contact hole is formed above polysilicon in the groove of grid region.Trench gate mosfet manufacture method of the present invention, match with the thickness of deielectric-coating under metal by making the width of the hard mask groove in grid region, after polysilicon is etched comprehensively, the gate contact hole of self-assembling formation proper width above polysilicon in the groove of grid region, gate contact hole is etched and realizes autoregistration, eliminate polysilicon photoetching, minimum needs carry out groove (trench), contact hole (contact), metal level (metal) three layer photoetching, save one deck photoetching process, thus shortened process, reduce process costs.
Embodiment two
Based on the manufacture method of the trench gate mosfet of embodiment one, can after step 5, before step 6, in grown above silicon sacrificial oxidation film, then etching removes sacrificial oxidation film, thus makes the trench wall of source region groove and grid region groove more level and smooth.
Embodiment three
Based on the manufacture method of the trench gate mosfet of embodiment two, described hard mask, lower floor is silica 1 31, and upper strata is silicon nitride 132;
Preferably, the width a=0.5um of the hard mask groove in source region, the width c=1.0um of the hard mask groove in grid region, under metal, the thickness of deielectric-coating ILD is b=d=0.4um, at the width e=c-d*2=0.2um in the gate contact hole that step 12 is finally formed.
Preferably, the width a=0.5um of the hard mask groove in source region, the width c=1.2um of the hard mask groove in grid region, under metal, the thickness of deielectric-coating ILD is b=d=0.4um, at the width e=c-d*2=0.4um in the gate contact hole that step 12 is finally formed.
Preferably, drain region 11 is N+ doping, and drift region 12 is N-doping, and channel region Doped ions is P type, and source region Doped ions is N+.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (6)
1. a manufacture method for trench gate mosfet, is characterized in that, comprises the following steps:
One. form drain region on a silicon substrate, drain region forms drift region, drift region is carried out hard mask deposit;
Two. on hard mask, carry out hard mask trench lithography, etching removes the hard mask at hard mask groove place, forms source region hard mask groove and the hard mask groove in grid region;
The width of grid region hard mask groove is greater than 1.5 times of the width of the hard mask groove in source region;
Three. on silicon chip, carry out channel region Doped ions autoregistration inject and advance, the drift region at source region hard mask groove and grid region hard mask groove place forms channel region;
Four. at grown above silicon side wall oxide-film, then etch side wall oxide-film, in source region, the side of the hard mask at hard mask groove and hard mask groove place, grid region forms groove side wall;
Five. the top, drift region between etching removal groove side wall and channel region, form source region groove and grid region groove;
Six. form grid oxygen at the trench wall of source region groove and grid region groove;
Seven. depositing polysilicon on silicon chip;
Eight. carry out polysilicon and return etching comprehensively, retain the polysilicon in the groove of source region and the polysilicon in the groove of grid region, remove other polysilicon;
Nine. remove the groove side wall of groove both sides, source region, the groove side wall of groove both sides, grid region;
Ten. carry out source region Doped ions autoregistration and inject, anneal;
11. deielectric-coating under depositing metal on silicon chip, under metal, the thickness of deielectric-coating is less than the half of the width of the hard mask groove in grid region, and is greater than the half of the width of the hard mask groove in source region;
12. that carries out deielectric-coating under metal returns etching comprehensively, removes deielectric-coating under the metal on hard mask, and deielectric-coating under removing the metal of the top of the polysilicon in the groove of grid region, thus forms gate contact hole above polysilicon in the groove of grid region;
13. grid region is protected by photoresist, carries out the hard mask Self-aligned etching in source contact hole, remove the hard mask at source region place, retain the hard mask between grid region and grid region homologous region;
14. carry out post-order process, form source electrode and grid.
2. the manufacture method of trench gate mosfet according to claim 1, is characterized in that,
After step 5, before step 6, in grown above silicon sacrificial oxidation film, then etching removes sacrificial oxidation film.
3. the manufacture method of trench gate mosfet according to claim 1, is characterized in that,
Described hard mask, lower floor is silicon dioxide, and upper strata is silicon nitride.
4. the manufacture method of trench gate mosfet according to claim 1, is characterized in that,
The width of the hard mask groove in source region is 0.5um, and the width of the hard mask groove in grid region is 1.0um, and under metal, the thickness of deielectric-coating is 0.4um.
5. the manufacture method of trench gate mosfet according to claim 1, is characterized in that,
The width of the hard mask groove in source region is 0.5um, and the width of the hard mask groove in grid region is 1.2um, and under metal, the thickness of deielectric-coating is 0.4um.
6. the manufacture method of trench gate mosfet according to claim 1, is characterized in that,
Drain region is N+ doping, and drift region is N-doping, and channel region Doped ions is P type, and source region Doped ions is N+.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105932061A (en) * | 2016-04-28 | 2016-09-07 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN108695392A (en) * | 2017-03-30 | 2018-10-23 | 艾普凌科有限公司 | Semiconductor device and its manufacturing method |
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| US20100291744A1 (en) * | 2009-01-29 | 2010-11-18 | Alpha And Omega Semiconductor Incorporated | High density trench mosfet with single mask pre-defined gate and contact trenches |
| CN102017103A (en) * | 2006-01-05 | 2011-04-13 | 飞兆半导体公司 | Power device utilizing chemical mechanical planarization |
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| CN102017103A (en) * | 2006-01-05 | 2011-04-13 | 飞兆半导体公司 | Power device utilizing chemical mechanical planarization |
| US20120058615A1 (en) * | 2006-01-05 | 2012-03-08 | Bruce Douglas Marchant | Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization |
| US20100291744A1 (en) * | 2009-01-29 | 2010-11-18 | Alpha And Omega Semiconductor Incorporated | High density trench mosfet with single mask pre-defined gate and contact trenches |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105932061A (en) * | 2016-04-28 | 2016-09-07 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN108695392A (en) * | 2017-03-30 | 2018-10-23 | 艾普凌科有限公司 | Semiconductor device and its manufacturing method |
| CN108695392B (en) * | 2017-03-30 | 2023-10-03 | 艾普凌科有限公司 | Semiconductor device and method for manufacturing the same |
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