CN104299903B - The manufacture method of trench gate mosfet - Google Patents
The manufacture method of trench gate mosfet Download PDFInfo
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- CN104299903B CN104299903B CN201310297866.9A CN201310297866A CN104299903B CN 104299903 B CN104299903 B CN 104299903B CN 201310297866 A CN201310297866 A CN 201310297866A CN 104299903 B CN104299903 B CN 104299903B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 239000011248 coating agent Substances 0.000 claims abstract description 44
- 238000000576 coating method Methods 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000001459 lithography Methods 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 150000002500 ions Chemical class 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- QVGXLLKOCUKJST-NJFSPNSNSA-N oxygen-18 atom Chemical compound [18O] QVGXLLKOCUKJST-NJFSPNSNSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of manufacture method of trench gate mosfet, when hard mask trench lithography, etching is carried out to hard mask, 1.5 times of the width of the hard mask groove in grid region of formation more than the width of the hard mask groove of source region, the thickness of deielectric-coating is less than the half and the half of the width more than the hard mask groove of source region of the width of the hard mask groove in grid region under the metal of deposit, and polysilicon is etched back to be to etch comprehensively.Trench gate mosfet manufacture method of the invention, matched with the thickness of deielectric-coating under metal by making the width of the hard mask groove in grid region, after etched to polysilicon comprehensively, the gate contact hole of the top self-assembling formation proper width of the polysilicon in the groove of grid region, etch gate contact hole and realize autoregistration, eliminate polysilicon photoetching, it is minimum to only need to carry out three layers of photoetching, so as to shorten technological process, process costs are reduced.
Description
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of trench gate mosfet (metal oxide semiconductor field-effect
Transistor) manufacture method.
Background technology
Trench gate mosfet (Trench MOSFET), as a kind of novel vertical structure device, is (vertical double in VDMOS
Diffusion Metal-Oxide Semiconductor field-effect transistor) on the basis of the Novel MOS tube that grows up, with conducting resistance it is small,
The advantages of low gate-drain charge density, saturation voltage are low, switching speed is fast, gully density is high, chip size is small, is mesolow (20V
~300V) metal-oxide-semiconductor development main flow.
In trench gate mosfet device, it is to improve integration density can effectively reduce conducting resistance to reduce unit size,
Especially low-voltage device becomes apparent.
Traditional trench gate mosfet is as shown in figure 1, including silicon substrate 100, setting drain region on a semiconductor substrate
101st, the drift region 102 formed on drain region 101, the channel region 103 formed on drift region 102 is formed on channel region 103
Source region 104, grid structure include the grid oxygen 106 being formed on trenched side-wall and the grid polycrystalline silicon 105 for being filled with groove.With
As a example by N-type trench gate mosfet, drain region uses highly doped N-type silicon substrate, and epitaxial growth thereon has the N-type being lightly doped to float
Area 102 is moved, channel region 103 can be injected with p-type doping, and source region 104 can be injected with n-type doping.
The manufacture method of traditional high-density, trench gate MOSFET, comprises the following steps：
1) drain region 11 being formed on a silicon substrate, drift region 12 being formed on drain region 11, hard mask is carried out on drift region 12
(Hard mask) 13 is deposited, and hard mask structure can be silica 1 31+ silicon nitrides 132；
2) hard mask trench lithography is carried out on hard mask 13, the hard mask at the hard mask groove of etching removal forms source
The hard mask groove of the hard mask groove in area and grid region；
3) carry out channel region Doped ions autoregistration on silicon chip to inject and advance (drive-in), in the hard mask ditch of source region
Channel region (body) 14 is formed on drift region 12 at the hard mask groove of groove and grid region, as shown in Figure 2；
4) in grown above silicon side wall oxide-film, side wall oxide-film is then etched, it is hard in the hard mask groove of source region and grid region
The side of the hard mask at mask groove forms groove side wall (spacer) 15, as shown in Figure 3；
5) top of drift region 12 between etching removal groove side wall and channel region 14, form source region groove 16 and grid region groove
17, as shown in Figure 4；
6) in grown above silicon sacrificial oxidation film, etching removal sacrificial oxidation film；
7) trench wall in source region groove and grid region groove forms grid oxygen 18；
8) depositing polysilicon 19 on silicon chip；
9) carry out polysilicon photoetching, etching, retain source region groove in polysilicon 19, the polysilicon 19 in the groove of grid region and
Polysilicon 19 above the groove of grid region, removes other polysilicons, the covering of the polysilicon 19 grid region groove both sides above the groove of grid region
Groove side wall, as shown in Figure 5；
10) the groove side wall of removal source region groove both sides；
11) source region Doped ions autoregistration injection, annealing are carried out, as shown in Figure 6；
12) deielectric-coating (ILD) 20 under depositing metal on silicon chip, as shown in Figure 7；
13) deielectric-coating is etched back under entering row metal, under the metal on the hard mask of removal source region groove both sides deielectric-coating and
Deielectric-coating under the metal on polysilicon above the groove of grid region, retains medium under the metal between the hard mask of source region groove both sides
Film, retains deielectric-coating under the metal on the hard mask of the polysilicon both sides above the groove of grid region, as shown in Figure 8；
14) grid region is protected by photoresist, carries out the hard mask Self-aligned etching in source contact hole, it is hard at removal source region
Mask, retains the hard mask between grid region and grid region homologous region；
15) subsequent technique (such as in 21 growth of the enterprising row metal layer of silicon chip, photoetching, etching) is carried out, source electrode and grid are formed
Pole, as shown in Figure 9.
The manufacture method of traditional high-density, trench gate MOSFET, subsistence level carries out groove (trench), polysilicon
(poly), contact hole (contact), four layers of photoetching of metal level (metal), wherein polysilicon layer photoetching are used to define gate polycrystalline
Silicon exit, complex process.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of trench gate mosfet, minimum to only need to carry out
Groove, contact hole, three layers of photoetching of metal level, process is simple.
In order to solve the above technical problems, the manufacture method of the trench gate mosfet that the present invention is provided, it is comprised the following steps：
One, forms drain region on a silicon substrate, and drift region is formed on drain region, and hard mask deposit is carried out on drift region；
Two, carry out hard mask trench lithography on hard mask, and the hard mask at the hard mask groove of etching removal forms source region
Hard mask groove and the hard mask groove in grid region；
1.5 times of the width of the hard mask groove in grid region more than the width of the hard mask groove of source region；
Three, carry out channel region Doped ions autoregistration on silicon chip and inject and advance, in the hard mask groove of source region and grid region
Channel region is formed on drift region at hard mask groove；
Then four, etch side wall oxide-film in grown above silicon side wall oxide-film, hard in the hard mask groove of source region and grid region
The side of the hard mask at mask groove forms groove side wall；
Drift region top and channel region between five, etching removal groove side walls, form source region groove and grid region groove；
Six, form grid oxygen in the trench wall of source region groove and grid region groove；
Seven, depositing polysilicons on silicon chip；
Eight, carry out polysilicon and are etched back to comprehensively, retain the polysilicon in source region groove and the polysilicon in the groove of grid region, go
Except other polysilicons；
Groove side wall, the groove side wall of grid region groove both sides of nine, removal source region grooves both sides；
Ten, carry out source region Doped ions autoregistration injection, annealing；
11, deielectric-coating under deposit metal on silicon chip, the thickness of deielectric-coating is less than under the metal above hard mask
The half of the width of the hard mask groove in grid region, and the width more than the hard mask groove of source region half；
The comprehensive of deielectric-coating is etched back under 12, enter row metal, removes deielectric-coating under the metal on hard mask, and remove grid
Deielectric-coating under the metal of the top of the polysilicon in area's groove, connects so as to the top of the polysilicon in the groove of grid region forms grid
Contact hole；
13, protect grid region by photoresist, the hard mask Self-aligned etching in source contact hole are carried out, at removal source region
Hard mask, retains the hard mask between grid region and grid region homologous region；
14, carry out post-order process, form source electrode and grid.
Preferably, after step 5, before step 6, in grown above silicon sacrificial oxidation film, then etching removal is sacrificial
Domestic animal oxide-film.
Preferably, the hard mask, lower floor is silica, and upper strata is silicon nitride.
Preferably, the width of the hard mask groove of source region is 0.5um, the width of the hard mask groove in grid region is 1.0um, positioned at hard
The thickness of deielectric-coating is 0.4um under metal above mask.
Preferably, the width of the hard mask groove of source region is 0.5um, the width of the hard mask groove in grid region is 1.2um, positioned at hard
The thickness of deielectric-coating is 0.4um under metal above mask.
Preferably, drain region is adulterated for N+, drift region is adulterated for N-, and channel region Doped ions are p-type, and source region Doped ions are
N+ types.
The manufacture method of trench gate mosfet of the invention, when hard mask trench lithography, etching is carried out to hard mask, shape
Into the hard mask groove in grid region 1.5 times of width of width more than the hard mask groove of source region, deposit positioned at hard mask top
Metal under deielectric-coating thickness less than the hard mask groove in grid region width half and more than the width of the hard mask groove of source region
The half of degree, and polysilicon is etched back to be etching comprehensively, so under the metal after deielectric-coating deposit, in the hard mask groove in grid region
The structure of well shape can be formed, such that it is able to be etched back to by the comprehensive of deielectric-coating under metal, is removed under the metal on hard mask
Deielectric-coating under deielectric-coating, and the metal of the top for removing polysilicon in the groove of grid region, polysilicon in the groove of grid region it is upper
It is square into gate contact hole.Trench gate mosfet manufacture method of the invention, by making the width of the hard mask groove in grid region with gold
The thickness of subordinate's deielectric-coating matches, and after etched to polysilicon comprehensively, the top of the polysilicon in the groove of grid region is certainly
The gate contact hole of proper width is so formed, gate contact hole is etched and is realized autoregistration, eliminate polysilicon photoetching, minimum
Need to carry out groove (trench), contact hole (contact), three layers of photoetching of metal level (metal), save one layer of photoetching work
Skill, so as to shorten technological process, reduces process costs.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, simple is made to the accompanying drawing used required for the present invention below
Introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill people
For member, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is traditional trench gate mosfet structural representation；
Fig. 2 is that the manufacture method channel region Doped ions autoregistration of traditional high-density, trench gate MOSFET is injected and advanced
Sectional schematic diagram afterwards；
Fig. 3 be traditional high-density, trench gate MOSFET manufacture method channel side stela erosion after sectional schematic diagram；
Fig. 4 be traditional high-density, trench gate MOSFET manufacture method source region groove and grid region etching groove after section show
It is intended to；
Fig. 5 is that the manufacture method polysilicon of traditional high-density, trench gate MOSFET is etched back to rear sectional schematic diagram；
Fig. 6 be traditional high-density, trench gate MOSFET the autoregistration of manufacture method source region Doped ions injection after section show
It is intended to；
Fig. 7 be traditional high-density, trench gate MOSFET manufacture method metal under deielectric-coating deposit after sectional schematic diagram；
Fig. 8 be traditional high-density, trench gate MOSFET manufacture method metal under deielectric-coating be etched back to rear section and illustrate
Figure；
Fig. 9 be traditional high-density, trench gate MOSFET manufacture method metal level etching after sectional schematic diagram；
Figure 10 is the embodiment channel region Doped ions autoregistration of manufacture method one injection of trench gate mosfet of the invention
And the sectional schematic diagram after advancing；
Figure 11 be trench gate mosfet of the invention the embodiment channel side stela of manufacture method one erosion after sectional schematic diagram；
After Figure 12 is the embodiment source region groove of manufacture method one and grid region etching groove of trench gate mosfet of the invention
Sectional schematic diagram；
Figure 13 is that the embodiment polysilicon of manufacture method one of trench gate mosfet of the invention is etched back to rear sectional schematic diagram；
Figure 14 be trench gate mosfet of the invention the embodiment source region Doped ions autoregistration of manufacture method one injection after
Sectional schematic diagram；
Figure 15 be trench gate mosfet of the invention the embodiment metal of manufacture method one under deielectric-coating deposit after section show
It is intended to；
Figure 16 be trench gate mosfet of the invention the embodiment metal of manufacture method one under deielectric-coating be etched back to rear section
Schematic diagram；
Figure 17 be trench gate mosfet of the invention the embodiment source contact hole of manufacture method one etching after section illustrate
Figure；
Figure 18 be trench gate mosfet of the invention the embodiment metal level of manufacture method one etching after sectional schematic diagram.
Specific embodiment
Below in conjunction with accompanying drawing, clear, complete description is carried out to the technical scheme in the present invention, it is clear that described
Embodiment is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is general
All other embodiment that logical technical staff is obtained on the premise of creative work is not made, belongs to protection of the present invention
Scope.
Embodiment one
The manufacture method of trench gate mosfet of the invention, comprises the following steps：
One, forms drain region 11 on a silicon substrate, and drift region 12 is formed on drain region 11, and hard mask is carried out on drift region 12
(Hard mask) 13 is deposited；
Two, carry out hard mask trench lithography on hard mask 13, and the hard mask at etching removal groove forms source region and covers firmly
The hard mask groove of film groove and grid region；1.5 times of the width of the hard mask groove in grid region more than the width of the hard mask groove of source region；
Three, carry out channel region Doped ions autoregistration on silicon chip and inject and advance (drive-in), in the hard mask of source region
Channel region (body) 14 is formed on drift region 12 at the hard mask groove of groove and grid region, as shown in Figure 10；
Then four, etch side wall oxide-film in grown above silicon side wall oxide-film, hard in the hard mask groove of source region and grid region
The side of the hard mask at mask groove forms groove side wall (spacer) 15, as shown in figure 11；
The top of drift region 12 and channel region 14 between five, etching removal groove side walls, form source region groove 16 and grid region ditch
Groove 17, as shown in figure 12；
Six, form grid oxygen 18 in the trench wall of source region groove and grid region groove；
Seven, depositing polysilicon 19 on silicon chip；
Eight, carry out polysilicon 19 and are etched back to comprehensively, retain polysilicon 19, the polysilicon in the groove of grid region in source region groove
19, other polysilicons are removed, as shown in figure 13；
Groove side wall, the groove side wall of grid region groove both sides of nine, removal source region grooves both sides；
Ten, carry out source region Doped ions autoregistration injection, annealing, as shown in figure 14；
11, deielectric-coating (ILD) 20, the deielectric-coating 20 under the metal above hard mask under deposit metal on silicon chip
Thickness less than the hard mask groove in grid region width half, and the width more than the hard mask groove of source region half, such as Figure 15
It is shown；
The comprehensive of deielectric-coating is etched back to 20 under 12, enter row metal, removes deielectric-coating under the metal on hard mask, and remove
Deielectric-coating under the metal of the top of the polysilicon in the groove of grid region, so as to the top of the polysilicon in the groove of grid region forms grid
Contact hole, as shown in figure 16；
13, protect grid region by photoresist, the hard mask Self-aligned etching in source contact hole are carried out, at removal source region
Hard mask, retains the hard mask between grid region and grid region homologous region, as shown in figure 17；
14, carry out post-order process (such as in 21 growth of silicon chip enterprising row metal layer, photoetching, etching), formation source electrode and
Grid, as shown in figure 18.
The manufacture method of the trench gate mosfet of embodiment one, when hard mask trench lithography, etching is carried out to hard mask,
The width of the hard mask groove in grid region of formation more than 1.5 times of width of the hard mask groove of source region, deposit on hard mask
The thickness of deielectric-coating is less than the half of the width of the hard mask groove in grid region and more than the hard mask groove of source region under the metal of side
The half of width, and polysilicon is etched back to be etching comprehensively, so under the metal after deielectric-coating deposit, in the hard mask groove in grid region
The interior structure that can form well shape, such that it is able to be etched back to by the comprehensive of deielectric-coating under metal, removes the metal on hard mask
Deielectric-coating under lower deielectric-coating, and the metal of the top for removing polysilicon in the groove of grid region, polysilicon in the groove of grid region
Top forms gate contact hole.Trench gate mosfet manufacture method of the invention, by making the width of the hard mask groove in grid region same
The thickness of deielectric-coating matches under metal, after etched to polysilicon comprehensively, the top of the polysilicon in the groove of grid region
The gate contact hole of self-assembling formation proper width, etches gate contact hole and realizes autoregistration, eliminates polysilicon photoetching, minimum
Only need to carry out groove (trench), contact hole (contact), three layers of photoetching of metal level (metal), save one layer of photoetching work
Skill, so as to shorten technological process, reduces process costs.
Embodiment two
The manufacture method of the trench gate mosfet based on embodiment one, can be after step 5, before step 6, in silicon
Sacrificial oxidation film is grown on piece, then etching removal sacrificial oxidation film, so that the trench wall of source region groove and grid region groove
More smooth.
Embodiment three
The manufacture method of the trench gate mosfet based on embodiment two, the hard mask, lower floor is silica 1 31, on
Layer is silicon nitride 132；
Preferably, the width a=0.5um of the hard mask groove of source region, the width c=1.0um of the hard mask groove in grid region, are located at
The thickness of deielectric-coating ILD is b=d=0.4um under metal above hard mask, in the gate contact hole that step 12 is ultimately formed
Width e=c-d*2=0.2um.
Preferably, the width a=0.5um of the hard mask groove of source region, the width c=1.2um of the hard mask groove in grid region, are located at
The thickness of deielectric-coating ILD is b=d=0.4um under metal above hard mask, in the gate contact hole that step 12 is ultimately formed
Width e=c-d*2=0.4um.
Preferably, drain region 11 be N+ doping, drift region 12 be N- doping, channel region Doped ions be p-type, source region adulterate from
Son is N+ types.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (6)
1. a kind of manufacture method of trench gate mosfet, it is characterised in that comprise the following steps：
One, forms drain region on a silicon substrate, and drift region is formed on drain region, and hard mask deposit is carried out on drift region；
Two, carry out hard mask trench lithography on hard mask, and the hard mask at the hard mask groove of etching removal forms source region and covers firmly
The hard mask groove of film groove and grid region；
1.5 times of the width of the hard mask groove in grid region more than the width of the hard mask groove of source region；
Three, carry out channel region Doped ions autoregistration on silicon chip and inject and advance, and are covered firmly in the hard mask groove of source region and grid region
Channel region is formed on drift region at film groove；
Then four, etch side wall oxide-film, in the hard mask groove of source region and the hard mask in grid region in grown above silicon side wall oxide-film
The side of the hard mask at groove forms groove side wall；
Drift region top and channel region between five, etching removal groove side walls, form source region groove and grid region groove；
Six, form grid oxygen in the trench wall of source region groove and grid region groove；
Seven, depositing polysilicons on silicon chip；
Eight, carry out polysilicon and are etched back to comprehensively, retain the polysilicon in source region groove and the polysilicon in the groove of grid region, remove it
Its polysilicon；
Groove side wall, the groove side wall of grid region groove both sides of nine, removal source region grooves both sides；
Ten, carry out source region Doped ions autoregistration injection, annealing；
11, deielectric-coating under deposit metal on silicon chip, the thickness of deielectric-coating is less than grid region under the metal above hard mask
The half of the half of the width of mask groove, and the width more than the hard mask groove of source region firmly；
The comprehensive of deielectric-coating is etched back under 12, enter row metal, removes deielectric-coating under the metal on hard mask, and remove grid region ditch
Deielectric-coating under the metal of the top of the polysilicon in groove, so as to the top of the polysilicon in the groove of grid region forms gate contact
Hole；
13, protect grid region by photoresist, carry out the hard mask Self-aligned etching in source contact hole, covering firmly at removal source region
Film, retains the hard mask between grid region and grid region homologous region；
14, carry out post-order process, form source electrode and grid.
2. the manufacture method of trench gate mosfet according to claim 1, it is characterised in that
After step 5, before step 6, in grown above silicon sacrificial oxidation film, removal sacrificial oxidation film is then etched.
3. the manufacture method of trench gate mosfet according to claim 1, it is characterised in that
The hard mask, lower floor is silica, and upper strata is silicon nitride.
4. the manufacture method of trench gate mosfet according to claim 1, it is characterised in that
The width of the hard mask groove of source region is 0.5um, and the width of the hard mask groove in grid region is 1.0um, above hard mask
The thickness of deielectric-coating is 0.4um under metal.
5. the manufacture method of trench gate mosfet according to claim 1, it is characterised in that
The width of the hard mask groove of source region is 0.5um, and the width of the hard mask groove in grid region is 1.2um, above hard mask
The thickness of deielectric-coating is 0.4um under metal.
6. the manufacture method of trench gate mosfet according to claim 1, it is characterised in that
Drain region is adulterated for N+, and drift region is adulterated for N-, and channel region Doped ions are p-type, and source region Doped ions are N+ types.
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