CN109244094A - Pixel unit and its manufacturing method, imaging sensor and imaging device - Google Patents
Pixel unit and its manufacturing method, imaging sensor and imaging device Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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Abstract
This disclosure relates to pixel unit and its manufacturing method, imaging sensor and imaging device.A kind of pixel unit, comprising: photosensitive element；The transistor being electrically connected with photosensitive element, transistor have channel formation region；The charge storage cell being electrically connected with transistor, wherein channel formation region includes the first part adjacent with charge storage cell and the second part adjacent with photosensitive element；And gate structure, it include: the gate insulating layer on channel formation region, the first grid being separated from each other and second grid on gate insulating layer, first grid is corresponding with the first part of channel formation region, second grid is corresponding with the second part of channel formation region, and the inter-gate insulating layer between first grid and second grid is wherein, when transistor is turned off, the potential height of first part is lower than the potential height of second part.
Description
Technical field
This disclosure relates to pixel unit and its manufacturing method, imaging sensor and imaging device.
Background technique
In recent years, cmos image sensor is rapidly developed.But it in the prior art, is being turned off in transmission transistor
When, a part of the signal charge as caused by the photosensitive element of such as photodiode can flow back into photosensitive element, cause
The image lag issues of next cycle.
Therefore, it is necessary to improved pixel unit and its manufacturing methods, imaging sensor and imaging device.
Summary of the invention
According to one aspect of the disclosure, a kind of pixel unit is provided, comprising: photosensitive element；With the photosensitive element
The transistor of electrical connection, the transistor have channel formation region；Charge storage cell electrically connected to the transistor is used
In the charge from photosensitive element that reception is transmitted by the transistor, wherein the channel formation region includes and the electricity
The adjacent first part of charge storing element and the second part adjacent with the photosensitive element；And gate structure, packet
It includes: the gate insulating layer on the channel formation region, the first grid being separated from each other on gate insulating layer and
Two grids, first grid is corresponding with the first part of the channel formation region, second grid and the second of the channel formation region
Part is corresponding, and the inter-gate insulating layer between the first grid and the second grid, wherein in the crystal
The potential height of the first part is lower than the potential height of the second part when pipe is turned off.
In some embodiments, the gate insulating layer includes: in the first part of the channel formation region and described
First part between one grid, and second between the second part and the second grid of the channel formation region
Part, wherein the thickness of the first part of the gate insulating layer is different from the thickness of the second part of the gate insulating layer.
In some embodiments, the channel formation region further include: between the first part and second part
Three parts, wherein the Part III is configured as: when the transistor is turned off, the potential height of the Part III exists
Between the first part and the potential height of second part.
In some embodiments, one in the first grid and second grid is included in the first grid and
The part of another side in two grids and in the part on another.
In some embodiments, one in the first grid and second grid setting is in the first grid and the
Another side in two grids.
In some embodiments, it is exhausted to be set to larger than the grid for the thickness of the first part of the gate insulating layer
The thickness of the second part of edge layer.
In some embodiments, the conduction type of the first part is identical as the conduction type of the second part, and
And the impurity concentration of the first part is lower than the impurity concentration of the second part.
In some embodiments, the photosensitive element is photodiode；The charge storage cell is floating diffusion
Area.
In some embodiments, the pixel unit further include: semiconductor substrate, the photosensitive element, the channel shape
It is formed at area and the charge storage cell in the semiconductor substrate, wherein the both ends of the channel formation region are distinguished
It is engaged with a part of a part of the photosensitive element and the charge storage cell.
On the other hand according to the disclosure, a kind of pixel unit is additionally provided, comprising: photosensitive element；With the photosensitive element
The transistor of electrical connection, the transistor have channel formation region；Charge storage cell electrically connected to the transistor is used
In the charge from photosensitive element that reception is transmitted by the transistor, wherein the channel formation region includes and the electricity
The adjacent first part of charge storing element and the second part adjacent with the photosensitive element；And gate structure, packet
It includes: the gate insulating layer on the channel formation region, first grid and second grid on gate insulating layer, the
One grid is corresponding with the first part of the channel formation region, and second grid is corresponding with the second part of the channel formation region,
And the inter-gate insulating layer between the first grid and the second grid, wherein when the transistor is turned off
The potential height of the first part is lower than the potential height of the second part, and wherein, first grid and second gate
Pole is integrated, and the first grid is configured as than the second grid far from the channel formation region.
On the other hand according to the disclosure, a kind of imaging sensor is additionally provided, including the picture according to any embodiment
Plain unit.
On the other hand according to the disclosure, a kind of imaging device is additionally provided, including such as the figure as described according to any embodiment
As sensor.
On the other hand according to the disclosure, a kind of method for manufacturing pixel unit is additionally provided, comprising: provide semiconductor lining
Bottom；The first insulation material layer is formed on the semiconductor substrate；The first grid is formed on first insulation material layer
Pole material layer；By the first grid material layer pattern, to form first grid middle layer；The second insulation material layer is formed,
Second insulation material layer at least covers the first grid middle layer；Is formed on second insulation material layer
Two gate material layers, the second grid material layer include at least the side of the first grid middle layer part and
Part on the first grid middle layer；Carry out patterned process so that the first grid is intermediate, described the
Two gate material layers and the respective a part of second insulation material layer are retained, the first grid middle layer and described
The retained part of second grid material layer respectively as transistor to be formed first grid and second grid, described the
In the part between the first grid and the second grid as the crystalline substance in the retained part of two insulation material layers
The inter-gate insulating layer of body pipe.
In some embodiments, the patterned process also makes: a part of first insulation material layer is protected
It stays, gate insulating film of the retained part of first insulation material layer as the transistor.
In some embodiments, the method also includes: before the patterned process, in second grid material layer
On formed the protected material bed of material；Wherein the patterned process is kept as a part of the protected material bed of material
The protective layer of the grid of the transistor.
In some embodiments, the gate insulating layer includes: in the first part of the channel formation region and described
First part between one grid, and second between the second part and the second grid of the channel formation region
Part, wherein the thickness of the first part of the gate insulating layer is different from the thickness of the second part of the gate insulating layer.
In some embodiments, one in the first grid and second grid is included in the first grid and
The part of another side in two grids and in the part on another.
In some embodiments, one in the first grid and second grid setting is in the first grid and the
Another side in two grids.
In some embodiments, the method also includes: formed photosensitive element；And charge storage cell is formed,
In, the both ends of the channel formation region one with a part of the photosensitive element and the charge storage cell respectively
Tap is closed, and wherein, the channel formation region may include the first part adjacent with the charge storage cell and with
The adjacent second part of the photosensitive element.
In some embodiments, the method also includes: in the aimed semiconductor region of the substrate introduce have with
The impurity of the second opposite conduction type of first conduction type, so that at least two doped regions are formed, described at least two
Doped region includes the first doped region and the second doped region, and the impurity concentration of first doped region is lower than the second doped region
Impurity concentration, wherein at least part that the channel formation region includes first doped region and the second doped region are extremely
Few a part.
In some embodiments, it introduces in the aimed semiconductor region with opposite with first conduction type
The impurity of the second conduction type also make: form third doped region, the impurity concentration of the third doped region is described first
Between the impurity concentration of doped region and the impurity concentration of the second doped region.
On the other hand according to the disclosure, a kind of operating method for pixel unit is additionally provided, it is characterised in that: institute
Stating pixel unit is the pixel unit according to any embodiment, which comprises to the first grid and second gate
Pole applies first voltage and second voltage respectively, so that the potential of the second part is high when the transistor is turned off
Degree is higher than the potential height of the first part.
In some embodiments, the first voltage is set to less than the second voltage.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and
Its advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and is used for together with the description
Explain the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Figure 1A shows the schematic sectional view of the pixel unit according to an embodiment of the present disclosure；
Figure 1B and 1C shows transmission transistor and channel shape in the pixel unit according to another embodiment of the disclosure
It is distributed at the doped region of area part；
Fig. 2A and Fig. 2 B shows the schematic sectional view of the pixel unit according to the disclosure other embodiments；
Fig. 3 A and 3B respectively illustrate the schematic sectional view of the pixel unit according to disclosure other embodiment；
Fig. 4,4A, 4B and 4C show the example flow of the manufacturing method of the pixel unit according to an embodiment of the present disclosure
Figure；
Some steps of the manufacturing process of the pixel unit according to an embodiment of the present disclosure are shown respectively in Fig. 5 A-5G
Schematic sectional view；
Fig. 6,6A and 6B show the example flow of the manufacturing method of the pixel unit according to the disclosure another embodiment
Figure；
Fig. 7 A-7H shows showing for some steps of the manufacturing process of the pixel unit according to an embodiment of the present disclosure
Meaning property sectional view；
Fig. 8 shows the schematic block diagram of the imaging device according to the embodiment of the present disclosure；
Fig. 9 A is shown according to the prior art, and the transmission transistor in pixel unit is conducting (ON) in the case where
The signal of potential level illustrates；
Fig. 9 B is shown according to the prior art, and the transmission transistor in pixel unit is at shutdown (OFF) in the ideal case
In the case of potential level signal diagram；
Fig. 9 C shows electricity of the transmission transistor in pixel unit according to prior art at shutdown (OFF)
The signal of gesture level illustrates；
Fig. 9 D shows the transmission transistor in pixel unit according to prior art at shutdown (OFF) due to returning
Excessive (spill-back) causes the signal of picture delay (lag) to illustrate；
Fig. 9 E shows electricity of the transmission transistor in the pixel unit according to the embodiment of the present disclosure at shutdown (OFF)
The signal of gesture level illustrates；
Fig. 9 F promotes in the case where shutdown (OFF) according to the transmission transistor in the pixel unit of the embodiment of the present disclosure
Signal electrode flows to the signal diagram of memory element (FD).
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiment explained below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms therefore once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc.
Deng.
Specific embodiment
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that unless in addition specific
Illustrate, unlimited this public affairs of system of component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments
The range opened.In addition, technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail,
But in the appropriate case, the technology, method and apparatus should be considered as authorizing part of specification.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that use in this way
Word be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can with
It is operated in those of shown by this or other description other different orientations of orientation.
Any implementation of this exemplary description be not necessarily to be interpreted it is more preferred than other implementations or
It is advantageous.Moreover, the disclosure not by given in above-mentioned technical field, background technique, summary of the invention or specific embodiment go out
Theory that is any stated or being implied is limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As made at this
, unless explicitly stated otherwise, " connection " means an element/node/feature and another element/node/feature in electricity
On, it is directly connected (or direct communication) mechanically, in logic or in other ways.Similarly, unless in addition specifically
Bright, " coupling " means that an element/node/feature can be with another element/node/feature in a manner of direct or is indirect
Mechanically, link electrically, in logic or in other ways to allow to interact, even if the two features may be not
It is directly connected to be also such.That is, " coupling " is intended to encompass the direct connection and in succession of element or other feature
Knot, including the use of the connection of one or more intermediary elements.
In addition, middle certain term of use can also be described below, and thus not just to the purpose of reference
Intended limitation.For example, unless clearly indicated by the context, otherwise it is related to the word " first ", " second " and other of structure or element
Such number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " provides certain from broadly by covering all modes for obtaining object
Object " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object
Deng.
It is not to this public affairs it should also be understood that being merely illustrative below to the description of at least one exemplary embodiment
It opens and its application or any restrictions used.
Figure 1A shows the schematic sectional view of the pixel unit according to an embodiment of the present disclosure.As shown in Figure 1A, pixel
Unit 10 includes: photosensitive element 103, and the transistor 105 being electrically connected with photosensitive element 103 is (as indicated by the dotted ellipse in figure
) and charge storage cell electrically connected to the transistor 107.
Photosensitive element 103 can be any component that can convert light to electricity, for example, light emitting diode etc..Charge
Memory element 107 can be used for receiving the charge from photosensitive element transmitted by transistor 105.In some embodiments
In, charge storage cell 107 can be floating diffusion region (FD) or capacitor etc..It also shows in Fig. 1 and to be formed in the substrate
Isolation (PDI) 109 between light-emitting component or pixel.
A part of transistor 105, for example, channel formation region 110, source area, drain region etc., can be formed in and partly lead
In body substrate 101.Transistor 105 can also include the gate structure 120 being formed on substrate 101 (later will specifically
It is bright).
Incidentally, term " semiconductor substrate " used herein above, refers to the substrate with semiconductor layer.Cause
This, substrate 101 shown in figure can indicate the substrate formed completely by semiconductor material or part of it (for example, in substrate
The well region of middle formation), or the semiconductor layer or part of it that can also indicate substrate in the semiconductor layer (for example, form
Well region).
As shown in Figure 1A, a part of photosensitive element 103, charge storage cell 107 and transistor 105 is (for example, ditch
Road formation area, source area, drain region etc.) it can be formed in semiconductor substrate 101.In some embodiments, photosensitive element
103 and charge storage cell 107 in each at least part can be used as source area or the drain region of transistor.Such as
In embodiment shown in Figure 1A, the both ends of channel formation region 110 can respectively with a part of the photosensitive element and institute
State a part engagement of charge storage cell.
In embodiment shown in figure 1A, channel formation region 110 is shown as including being formed at least in substrate 101
Two doped regions, such as doped region 111 and 113.One or more of described doped region can be by substrate 101
Target area introduces the conduction type impurity opposite with the conduction type of substrate and is formed.For example, for P type substrate (or
Well region) form N-type transistor in 101 in the case where, N-type impurity can be introduced to P type substrate (or well region) 101 to be formed
State doped region.
Although should be understood that in figure 1A, it is basic that the first doped region 111 and the second doped region 113 are shown as its lower surface
It flushes, however this is only exemplary.In other embodiments, the following table of the first doped region 111 and the second doped region 113
It face can be independent of one another.For example, the lower surface of first doped region 111 is than the second doped region in embodiment as shown in Figure 1B
113 lower surface is deeper, in other words, further from substrate surface.The other component of embodiment shown in Figure 1B can be with Figure 1A
Shown in corresponding component it is identical.
Therefore, as shown in the figure, the channel formation region 110 of transistor 105 may include and 107 phase of charge storage cell
Adjacent first part and the second part adjacent with photosensitive element 103.First part is corresponding with the first doped region, and second
Divide corresponding with the second doped region.In some embodiments, first part may include at least part of the first doped region, the
Two parts may include at least part of the second doped region.Therefore, the first part of channel region and second part can also be with
It is indicated with appended drawing reference 111 and 113.
In some embodiments, the channel formation region can also include more parts.For example, as shown in Figure 1B,
In substrate, other than the first doped region 111 and the second doped region 113, more doped regions can also be formed with, for example, the
Three doped regions 115.For third doped region between the first doped region 111 and the second doped region 113, impurity concentration can be
Between the impurity concentration of one doped region 111 and the impurity concentration of the second doped region 113.In this way, channel formation region can also wrap
Include the Part III 115 between the first part and second part.Part III 115 can be configured as in the crystalline substance
When body pipe is turned off, potential height is between the first part and the potential height of second part.Here, it should be appreciated that the greatest extent
Pipe doped region may undergo the doping of different-energy and/or various dose, but doped region shows identical conduction type.
Although should also be understood that in Fig. 1, the channel formation region 110 of transistor 105 is shown as by the first doped region 111
It is constituted with the second doped region 113, however the present disclosure is not limited thereto.For example, in other embodiments, channel formation region 110 can be with
At least part of at least part and the second doped region including the first doped region, as shown in Figure 1B.It is real shown in Figure 1B
It applies in example, a part of a part of the first doped region 111 and the second doped region 113 constitutes channel formation region 110 (as schemed
In dashed rectangle indicated by).In a still further embodiment, channel formation region 110 may include other part.
For example, in some embodiments, channel formation region 110 may be formed as beyond one or more of these doped regions, such as
Shown in Fig. 1 C.
In accordance with an embodiment of the present disclosure, for transistor 105 when being turned off, the potential height of the first part is lower than institute
State the potential height of second part.In this way, transistor can be made when being turned off, signal charge existing for channel portion (
That is, photoelectron) at least part can enter capacity cell (for example, in FD).It is existing so as to which reflux is alleviated or avoided
As image lag issues have been mitigated or eliminated.
It is further described below with reference to Fig. 9 A-9F.Fig. 9 A is shown according to the prior art, in pixel unit
The signal of potential level of transmission transistor in the case where conducting (ON) illustrates；Fig. 9 B is shown according to the prior art, resonable
The signal of potential level of the transmission transistor at shutdown (OFF) in the case of thinking in pixel unit illustrates.It needs exist for
Illustrate, in Fig. 9 A-9F, horizontal axis schematically shows some parts of position of pixel unit, and wherein FD indicates electricity
Charge storing element (for example, capacitor or floating diffusion region), TG indicate that transmission transistor, PD indicate that photosensitive element, PDI indicate
Isolation between photosensitive element or between pixel unit；The longitudinal axis indicates the corresponding potential level of each section.
As shown in Figure 9 A, in the prior art, in the case where (ON) is connected in transmission transistor TG, electricity corresponding with TG
Gesture level is lower than photosensitive element PD, so that the signal charge (for example, light induced electron) generated at photosensitive element PD is transferred to storage
Element FD.
As shown in Figure 9 B, in the prior art, in the ideal case, the case where transmission transistor TG turns off (OFF)
Under, photosensitive element PD and charge storage cell FD are isolated.Therefore, equally, high potential barrier is formed in transmission transistor TG,
To the flowing of disabling signal charge.
However, in practical applications, as shown in Figure 9 C, when transmission transistor TG turns off (OFF), in transmission transistor
There are still part signal charges in TG (for example, in its channel region).This part signal charge fails to be transferred to memory element
FD, and its all or part may return to photosensitive element PD.This phenomenon is referred to as Hui Yi, and (spill-back is also claimed
For reflux).This phenomenon may be partly due in transmission transistor TG the electricity between memory element FD and photosensitive element PD
Lotus access (channel) is preferably not that there may be the fluctuatings of potential, as shown in Figure 9 C, so that brilliant in transmission
In the case that body pipe TG is turned off, part signal charge " delay " is in transmission transistor TG (specifically, for example, its channel region
In), and its all or part may return to photosensitive element PD.The charge of Hui Yi returns to photosensitive element PD, such as Fig. 9 D institute
Show, will cause signal hysteresis when scanning (or imaging) next time, under the influence of single pass photogenerated charge when being imaged generation,
To influence image quality.
Fig. 9 E shows electricity of the transmission transistor in the pixel unit according to the embodiment of the present disclosure at shutdown (OFF)
The signal of gesture level illustrates；Fig. 9 F according to the transmission transistor in the pixel unit of the embodiment of the present disclosure shutdown (OFF) feelings
Signal electrode is promoted to flow to the signal diagram of memory element (FD) under condition.
As shown in fig. 9e, in accordance with an embodiment of the present disclosure, when transmission transistor turns off (OFF), the first part
The potential height of (for example, 111) is lower than the potential height of the second part (such as 113).In this way, as shown in fig. 9f, due to
The potential height of first part is lowered, so that the signal charge energy when transmission transistor is turned off, in transmission transistor TG
It is enough that charge storage cell FD is arrived by least partly " coming down in torrents ".In this way, " Hui Yi " that mitigates or eliminate signal charge is existing
As, and signal hysteresis caused by thus phenomenon is mitigated or eliminated, the generation of photogenerated charge when promoting scanning imagery next time,
To improve image quality.
Here, one ordinarily skilled in the art will readily appreciate that in actual manufacturing process, due to processing technology etc.
The error or difference that inevitably will cause surface rough overshoot, impurities concentration distribution, defect distribution, surface state etc., to make
It obtains potential level and small fluctuation occurs, as Fig. 9 D and 9F Wave curve schematically (is exaggerated to a certain extent
Ground) show.
Figure 1A is returned to, transistor 105 further includes gate structure 120.Gate structure 120 may include: in the channel shape
At the gate insulating layer 121 in area；And the grid 123 on the gate insulating layer.Gate insulating layer 121 can wrap
It includes: the first part on the first part 1101 of the channel formation region, and second in the channel formation region
Divide the second part on 1103.In some embodiments, the thickness of the first part of gate insulating layer is different from the grid
The thickness of the second part of pole insulating layer.In this way, the potential height of the first part can be made to further decrease.To,
Transistor can be made when being turned off, signal charge existing for channel portion (that is, photoelectron) can be entered more
Capacity cell (for example, in FD).So as to which backflow phenomenon is further alleviated or avoided, so that figure further be mitigated or eliminated
As lag issues.
Gate structure 120 can further include the spacer (spacer) 127 for grid.In some embodiments, grid
Structure 120 can further include the optional protective layer 129 on grid.In some embodiments, there are grid protection layers
In the case where 129, spacer 127 can be formed as into its top and be substantially flush substantially with the top of grid protection layer 129.And
In the case where grid protection layer 129 are not present, spacer 127 can be formed as to top of its top substantially with grid 129
End is substantially flush.
In addition, also showing the isolation (PDI) 109 between the light-emitting component formed in the substrate or pixel in Fig. 1.
Fig. 2A shows the schematic sectional view of the pixel unit according to the disclosure another embodiment.As shown in Figure 2 A, as
Plain unit 20 includes: photosensitive element 103；The transistor 105 being electrically connected with the photosensitive element, the transistor have channel
Form area 110；And the charge storage cell 107 being electrically connected with the transistor 105, pass through the transistor for receiving
The charge from photosensitive element of transmission.
The channel formation region 110 may include the first part 1101 adjacent with the charge storage cell and with
The adjacent second part 1103 of the photosensitive element.
Transistor 105 further includes gate structure 200.As shown in Figure 2 A, gate structure 200 may include being formed in channel
Gate insulating layer 201 on area.Gate structure 200 further include: corresponding with the first part 1101 of the channel formation region
First grid 203；Second grid 207 corresponding with the second part 1103 of the channel formation region, the second grid 207
It is separated from each other with the first grid 203；And the grid electrode insulation between the first grid and the second grid
Layer 205.The gate insulating layer 201 is between the channel formation region and the first grid and second grid.
Embodiment shown in A according to fig. 2 can be by first grid and second grid when transistor 105 turns off
Apply different voltage, comes so that the first part of channel formation region is different with the second part potential height.For example, such as
Shown in Fig. 2A, in transistor shutdown, voltage V1 is applied to first grid 203, and voltage V2 is applied to second grid 207.It can
So that voltage V1 is higher than voltage V2, so that the potential height of the first part 1101 of channel formation region is lower than described second
Divide 1103 potential height.
In some embodiments, correspondingly, gate insulating layer 201 may include: at first of the channel formation region
Divide the first part between the first grid, and second part and the second grid in the channel formation region
Between second part.In some embodiments, the thickness of the first part of the gate insulating layer can be configured as difference
In the thickness of the second part of the gate insulating layer.In this way, can further the part to channel formation region potential into
Row is adjusted.
In some embodiments, channel formation region 110 further includes the third between the first part and second part
The part of part or more.The Part III can be configured as: the Part III when the transistor is turned off
Potential height is between the first part and the potential height of second part.
In some embodiments, one in the first grid and second grid is included in the first grid and
The part of another side in two grids and in the part on another.As shown in Figure 2 A, second grid
207 include the part in the side of first grid 203 and the part on first grid 203.Here, it should be appreciated that the first grid
The configuration of pole and second grid can be interchanged.As shown in Figure 2 B, according to another embodiment of the present disclosure, first grid 203 wraps
Include the part in the side of second grid 207 and the part on second grid 207.Other component shown in Fig. 2 B and figure
Corresponding component shown in 2A can be identical, therefore is omitted and carries out repeated explanation to it.
Optionally, gate structure 200 can also include grid protection layer 209.Gate structure can also include spacer
211.In the example shown in Fig. 2A and 2B, the spacer of gate structure two sides can have different sizes.
Fig. 3 A shows the schematic sectional view of the pixel unit according to disclosure other embodiment.Shown in Fig. 3 A
Embodiment and embodiment shown in Fig. 2A and 2B are essentially identical, and the main distinction is the configuration of gate structure.Shown in Fig. 3 A
Other component can be identical with the corresponding component shown in figure such as Fig. 2A and 2B, therefore is omitted and carries out repeated explanation to it.
In the embodiment as shown in fig. 3 a, one in first grid 203 and second grid 207 can be set described
Another side in first grid and second grid.Inter-gate insulating layer 205 is arranged in first grid 203 and second gate
Between pole 207.
Fig. 3 B shows the schematic sectional view of the pixel unit according to disclosure other embodiment.Shown in Fig. 3 B
Embodiment and embodiment shown in Fig. 2A and 2B are essentially identical, and the main distinction is the configuration of gate structure.Shown in Fig. 3 B
Other component can be identical with the corresponding component shown in figure such as Fig. 2A and 2B, therefore is omitted and carries out repeated explanation to it.
In this embodiment, gate structure 200 may include: corresponding with the first part of the channel formation region
One grid 203；And second grid 207 corresponding with the second part of the channel formation region.As shown in Figure 3B, the first grid
Pole and second grid are integrated, and the first grid is configured as being formed than the second grid far from the channel
Area.Note that in the disclosure, under normal circumstances, first grid refers to the grid or grid adjacent with charge storage cell
Part, second grid refer to the part of the grid or grid adjacent with photosensitive element.
Gate insulating layer 201 is between the channel formation region and the first grid and second grid.Gate insulator
Layer 201 includes: the first part between the first part and the first grid of the channel formation region, and described
Second part between the second part of channel formation region and the second grid.As shown in the figure, the gate insulating layer
The thickness of first part is different from the thickness of the second part of the gate insulating layer.Specifically, the gate insulating layer
The thickness of first part can be set to the thickness of the second part greater than the gate insulating layer, as shown in Figure 3B.
According in some embodiments of the present disclosure, it is contemplated that the ditch that will be configured in embodiment as that shown in figs. 1A to 1 c
Road formation area is integrated to the scheme in the structure as described in Fig. 2A -2B and 3A-3B.Since such combination is for this field
It for those of ordinary skill, can be readily apparent that from the introduction of the upper surface of the disclosure, therefore no longer it is carried out in detail herein
Explanation.
Fig. 4,4A, 4B and 4C show the example flow of the manufacturing method of the pixel unit according to some embodiments of the disclosure
Figure.The schematic of some steps of the manufacturing process of the pixel unit according to some embodiments of the disclosure is shown respectively in Fig. 5 A-5G
Sectional view.It is illustrated below with reference to Fig. 4, Fig. 5 A-5G.
According to some embodiments of the present disclosure, a kind of method for manufacturing pixel unit is provided, may include following step
Suddenly.
In step S410, substrate 101 is provided.As shown in Figure 5A, the substrate has aimed semiconductor region 102, described
Aimed semiconductor region has the first conduction type, such as p-type.Can be optionally pre-formed in substrate 101 PDI every
From object 109.
In addition, in some embodiments, it is alternatively possible to be pre-formed at least one of photosensitive element 103 in the substrate
Point, as indicated by the dotted line frame in figure.
In step S420, introduce in the aimed semiconductor region 102 with opposite with first conduction type
The impurity of second conduction type (for example, N-type), to form at least two doped regions.As shown in Figure 5 B, described at least two
Doped region includes the first doped region 111 and the second doped region 113, and makes the impurity concentration of first doped region lower than the
The impurity concentration of two doped regions.Note that the conduction type of the first doped region 111 and the second doped region 113 is not miscellaneous here
The introducing of matter and change, but impurity concentration therein is changed.For example, be p-type in aimed semiconductor region, introducing
In the case that impurity is N-type, after introducing N-type impurity, the conduction type of the first doped region 111 and the second doped region 113 is still P
Type, but the concentration for being introduced into the leading impurity (p type impurity) of the doped region of N-type impurity reduces.
It in some embodiments, can be by processing step as shown in Figure 4 A come in the aimed semiconductor region
The impurity of the second conduction type (for example, N-type) is introduced in 102.
In step S451, the first mask is formed over the substrate, and first mask exposes the aimed semiconductor area
Domain with the surface of a corresponding part in first doped region and the second doped region.
In step S453, using first mask, to have second conductive-type opposite with first conduction type
The impurity pair of type is doped with one corresponding part.
For example, in some embodiments, the first mask can be set to expose the aimed semiconductor region with institute
State the surface of the corresponding part of the first doped region.Later, using first mask, to have and first conduction type
The impurity pair of the second opposite conduction type part corresponding with first doped region is doped.In this case
In some implementations, it is contemplated that part not corresponding for the second doped region is doped.In other words, the second doping
Area can keep impurity concentration identical with the target part of substrate.
In some embodiments, it introduces in the aimed semiconductor region with opposite with first conduction type
The impurity of the second conduction type can also include the following steps.
As shown in Figure 4 A, in step S455, first mask is removed.
In step S457, the second mask is formed over the substrate, and second mask exposes the aimed semiconductor area
Domain with the surface of another corresponding part in first doped region and the second doped region.
In step S459, using second mask, to have second conductive-type opposite with first conduction type
The impurity pair of type is doped with another described corresponding part.
In step S461, second mask is removed.
In some embodiments, it introduces in the aimed semiconductor region with opposite with first conduction type
The impurity of the second conduction type can also include the following steps.
As shown in Figure 4 C, in step S463, third mask is formed over the substrate, and the third mask has and institute
The corresponding first part of the first doped region and second part corresponding with second doped region are stated, the third mask
First part and second part have different thickness.
In step S465, using the third mask, to have second conductive-type opposite with first conduction type
The impurity of type mixes the part corresponding with first doped region and the second doped region in the aimed semiconductor region
It is miscellaneous.
In step S467, the third mask is removed.
Fig. 4 is returned to, the method also includes: in step S430, the grid for being used for transistor is formed in the substrate
Structure.
In some embodiments, the gate structure of transistor can be formed by processing step as shown in Figure 4 C.Such as
Shown in Fig. 4 C, in step S469, form gate stack in the substrate, the gate stack include gate insulating layer and
Grid on gate insulating layer.In step S471, it is formed in the spacer of the side of the gate stack.The grid
Structure can be gate structure described in any embodiment in the disclosure.
Fig. 5 C to 5G shows more specifical technical process.As shown in Figure 5 C, doped region is being formd as shown in Figure 5 B
Later, can be formed in substrate includes gate insulating material layer 501, the grid material on gate insulating material layer
The lamination of layer 503 and the optional protective layer 505 on gate material layers.
Later, as shown in Figure 5 D, it can use patterned mask (not shown) to pattern the lamination, to be formed
Gate stack.The gate stack may include gate insulating layer 121, grid 123 and optional protective layer 125.
Later, optionally, in some embodiments, it can use patterned mask (not shown) and form photosensitive element
103 (or part of it) are for example, by ion implanting etc., as shown in fig. 5e.In some instances, ion implanting can be passed through
Form the light emitting diode (PPD) of pinning.
As illustrated in figure 5f, spacer 127 is formed.
As depicted in fig. 5g, memory element 107 is formed, such as is formed by the ion implanting using patterned mask floating
Dynamic diffusion region.
It should be understood that the disclosure is not limited to this.In other embodiments, it is formed it should be noted that although in figure 5d
Gate stack is shown as one side and flushes substantially with the side of the second part 113 of channel formation region, the other side not with channel
Another side for the second part 113 for forming area flushes, however the disclosure is not limited to this.The position of gate stack and PD and FD
The relationship of setting can according to need to be arranged.
In some embodiments, it introduces in the aimed semiconductor region with opposite with first conduction type
The impurity of the second conduction type also make: form third doped region, the impurity concentration of the third doped region is described first
Between the impurity concentration of doped region and the impurity concentration of the second doped region.
Fig. 4 is returned to, the method can also include: to form photosensitive element；And form charge storage cell.The crystalline substance
The both ends of the channel formation region of body pipe can respectively with a part of the photosensitive element and the charge storage cell one
Part engages.The channel formation region may include first doped region at least part and second doped region
At least partially.
Fig. 6,6A-6B show the example flow diagram of the manufacturing method of the pixel unit according to the disclosure other embodiments；
Fig. 7 A-7H shows the schematic cross-sectional of some steps of the manufacturing process of the pixel unit according to some embodiments of the disclosure
Figure.It is illustrated below with reference to Fig. 6,6A-6B and Fig. 7 A-7H.
As shown in fig. 6, may include following step according to a kind of method of manufacture pixel unit of some embodiments of the disclosure
Suddenly.
In step S610, semiconductor substrate is provided.As shown in Figure 7 A, semiconductor substrate 101 can be provided.Semiconductor lining
The isolation structure 109 for separating photosensitive element or pixel can be pre-formed in bottom 101.It can be in semiconductor substrate 101
It is pre-formed at least part (equally indicating in fig. 7 with 103) of photosensitive element to be formed.
In step S620, the first insulation material layer is formed on the semiconductor substrate.As shown in Figure 7 B, it is partly leading
The first insulation material layer 701 is formed on body substrate 101.In step S603, is formed on first insulation material layer
One gate material layers 703, as shown in Figure 7 B.
In step S640, the first grid material layer 703 is patterned, to form first grid middle layer 705, such as
Shown in Fig. 7 C.
It in step S650, is formed the second insulation material layer (707), described in second insulation material layer 707 at least covers
First grid middle layer 705, as seen in figure 7 c.
In step S660, second grid material layer 709 is formed on second insulation material layer 707, such as Fig. 7 D institute
Show, the second grid material layer 709 is included at least in the part of the side of the first grid middle layer 705 and in institute
State the part on first grid middle layer 705.
Here, it is alternatively possible to form the protected material bed of material 711 on second grid material layer 709.
In step S670, patterned process is carried out, so that 705, the second grid material among the first grid
Layer 709 and the respective a part of second insulation material layer 707 are retained, as seen in figure 7e.The first grid middle layer
705 and the retained part of the second grid material layer 707 respectively as transistor to be formed first grid 203, the
Two grids 207.In the retained part of second insulation material layer in the first grid and the second grid it
Between inter-gate insulating layer 205 of the part as the transistor.
In some embodiments, the patterned process also makes: a part of quilt of first insulation material layer 701
Retain, as seen in figure 7e.The retained part of first insulation material layer 701 the first grid middle layer 705,
Under the retained part of the second grid material layer 709 and second insulation material layer 707.First insulation
The retained part of material layer 701 can be used as the gate insulating film 201 of transistor.
Here, in the case where foring the protected material bed of material 711, the patterned process also makes the protection materials
A part of layer 711 is kept as protective layer 209.
As seen in figure 7e, second grid 207 may include in the part of the side of the first grid 203 and in institute
State the part on first grid 203.
In some embodiments, the one or both in the first grid material layer and the second grid material layer
It can be the lamination for including conductive material layer and the cushioned material layer on conductive material layer.In this case, by institute
The retained part of each conductive material layer after patterned process is stated as corresponding grid.
In some embodiments, the part or complete of photosensitive element can alternatively after forming gate stack, be formed
Portion.For example, can be photosensitive to be formed by the ion implantation technology using patterned mask after forming gate stack
Some or all of element.
In some embodiments, the method also includes: in step S680, after the patterned process, between formation
Spacing body (spacer) 211, as shown in Figure 7 G.
In some embodiments, the method also includes: in step S690, form photosensitive element, as shown in Figure 7 F；With
And in step S695, charge storage cell is formed, as shown in fig. 7h.As shown in fig. 7h, the transistor can be configured
Are as follows: the both ends of its channel formation region a part with a part of the photosensitive element and the charge storage cell respectively
Engagement.The channel formation region may include the first part adjacent with the charge storage cell and with the photosensitive member
The adjacent second part of part.
Here, it will be appreciated that step shown in the flowchart not necessarily indicates its sequence being performed.According to different realities
Example is applied, certain steps may be performed in a differing order.
As previously described, according in some embodiments of the present disclosure, it is contemplated that will implement as shown in Figure 1A -1C
The channel formation region configured in example is integrated to the scheme in the structure as described in Fig. 2A -2B and 3A-3B.It can use above
At least two doped regions are formed in substrate 101 (as shown in Figure 7 A) with regard to similar approach shown in Fig. 4 A-4B.
In some embodiments, as shown in Figure 6A, in step S651, the first mask is formed over the substrate.Described
One mask expose the aimed semiconductor region with a corresponding part in first doped region and the second doped region
Surface.
In step S653, using first mask, to have second conductive-type opposite with first conduction type
The impurity pair of type is doped with one corresponding part.
For example, in some embodiments, the first mask can be set to expose the aimed semiconductor region with institute
State the surface of the corresponding part of the first doped region.Later, using first mask, to have and first conduction type
The impurity pair of the second opposite conduction type part corresponding with first doped region is doped.In this case
In some implementations, it is contemplated that part not corresponding for the second doped region is doped.In other words, the second doping
Area can keep impurity concentration identical with the target part of substrate.
In step S655, first mask is removed.
In some embodiments, the first doped region 111 and the second doped region 113 can so be formed.
And in further embodiments, it can also include further following steps.
In step S657, the second mask is formed over the substrate, and second mask exposes the aimed semiconductor area
Domain with the surface of another corresponding part in first doped region and the second doped region.
In step S659, using second mask, to have second conductive-type opposite with first conduction type
The impurity pair of type is doped with another described corresponding part.
In step S661, second mask is removed.In this way, the first doped region 111 can be formed in this way
With the second doped region 113.
In other some embodiments, doped region can also be formed by following method.
As shown in Figure 6B, in step S663, third mask is formed over the substrate, and the third mask has and institute
The corresponding first part of the first doped region and second part corresponding with second doped region are stated, the third mask
First part and second part have different thickness.
In step S665, using the third mask, to have second conductive-type opposite with first conduction type
The impurity of type mixes the part corresponding with first doped region and the second doped region in the aimed semiconductor region
It is miscellaneous.
In step S667, the third mask is removed.In this way, doped region can be formed in this way, such as
One doped region 111 and the second doped region 113.
According to some embodiments of the present disclosure, a kind of operating method for pixel unit is additionally provided, in the pixel
In unit, transmission transistor has isolated first grid and second grid.The described method includes: to the first grid and
Second grid applies first voltage V1 and second voltage V2 respectively, so that second described in when the transistor is turned off
The potential height divided is higher than the potential height of the first part.In some embodiments, the first voltage V1 can be by
It is set smaller than the second voltage V2.
According to some embodiments of the present disclosure, a kind of imaging sensor is additionally provided comprising according to any embodiment institute
The pixel unit stated.According to some embodiments of the present disclosure, a kind of imaging device is additionally provided comprising described image sensing
Device.Fig. 8 shows the schematic block diagram of the imaging device according to the embodiment of the present disclosure.
In accordance with an embodiment of the present disclosure, improved imaging sensor and its manufacturing method and imaging device can be provided.
In accordance with an embodiment of the present disclosure, it can also improve or solve the cross-interference issue of light, so as to improve image quality.According to this public affairs
The some embodiments opened, can also simplify the manufacturing process of imaging sensor, reduce cost.
It should be appreciated by those skilled in the art that description operates the boundary between (or step) only in the above-described embodiments
It is merely illustrative.Multiple operations can be combined into single operation, and single operation can be distributed in additional operation, and
Operation can be executed at least partially overlappingly in time.Moreover, alternative embodiment may include multiple realities of specific operation
Example, and can change operation order in other various embodiments.But other modifications, variations and alternatives are equally
It is possible.Therefore, the specification and drawings should be counted as illustrative and not restrictive.
Although being described in detail by some specific embodiments of the example to the disclosure, this field
It is to be understood by the skilled artisans that above example is merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is public herein
Each embodiment opened can in any combination, without departing from spirit and scope of the present disclosure.Those skilled in the art should also manage
Solution can carry out a variety of modifications to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is by appended power
Benefit requires to limit.
Claims (10)
1. a kind of pixel unit characterized by comprising
Photosensitive element；
The transistor being electrically connected with the photosensitive element, the transistor have channel formation region；
Charge storage cell electrically connected to the transistor comes from photosensitive element by what the transistor transmitted for receiving
Charge, wherein the channel formation region include the first part adjacent with the charge storage cell and with the photosensitive member
The adjacent second part of part；And
Gate structure comprising:
Gate insulating layer on the channel formation region,
The first grid being separated from each other and second grid on gate insulating layer, first grid and the channel formation region
First part is corresponding, and second grid is corresponding with the second part of the channel formation region, and
Inter-gate insulating layer between the first grid and the second grid,
Wherein, when the transistor is turned off, the potential height of the first part is high lower than the potential of the second part
Degree.
2. pixel unit as described in claim 1, which is characterized in that the gate insulating layer includes:
First part between the first part and the first grid of the channel formation region, and
Second part between the second part and the second grid of the channel formation region,
Wherein the thickness of the first part of the gate insulating layer is different from the thickness of the second part of the gate insulating layer.
3. pixel unit as described in claim 1, which is characterized in that the channel formation region further include:
Part III between the first part and second part,
Wherein the Part III is configured as: when the transistor is turned off, the potential height of the Part III is described
Between first part and the potential height of second part.
4. pixel unit as described in claim 1, which is characterized in that wherein:
One in the first grid and second grid includes another the side in the first grid and second grid
The part in face and in the part on another.
5. pixel unit as described in claim 1, which is characterized in that wherein:
One in the first grid and second grid another the side being arranged in the first grid and second grid
Face.
6. pixel unit as claimed in claim 2, which is characterized in that wherein:
The thickness of the first part of the gate insulating layer is set to larger than the thickness of the second part of the gate insulating layer.
7. pixel unit as described in claim 1, which is characterized in that wherein:
The conduction type of the first part is identical as the conduction type of the second part, and
The impurity concentration of the first part is lower than the impurity concentration of the second part.
8. pixel unit as described in claim 1, which is characterized in that wherein:
The photosensitive element is photodiode；
The charge storage cell is floating diffusion region.
9. pixel unit as described in claim 1, which is characterized in that further include:
Semiconductor substrate, the photosensitive element, the channel formation region and the charge storage cell, which are formed in, described partly leads
In body substrate,
Wherein the both ends of the channel formation region respectively with a part of the photosensitive element and the charge storage cell
A part engagement.
10. a kind of pixel unit characterized by comprising
Photosensitive element；
The transistor being electrically connected with the photosensitive element, the transistor have channel formation region；
Charge storage cell electrically connected to the transistor comes from photosensitive element by what the transistor transmitted for receiving
Charge, wherein the channel formation region include the first part adjacent with the charge storage cell and with the photosensitive member
The adjacent second part of part；And
Gate structure comprising:
Gate insulating layer on the channel formation region,
First grid and second grid on gate insulating layer, the first part pair of first grid and the channel formation region
It answers, second grid is corresponding with the second part of the channel formation region, and
Inter-gate insulating layer between the first grid and the second grid,
Wherein, when the transistor is turned off, the potential height of the first part is high lower than the potential of the second part
Degree, and
Wherein, first grid and second grid are integrated, and the first grid be configured as it is remoter than the second grid
From the channel formation region.
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| CN107221539A (en) * | 2016-03-22 | 2017-09-29 | 爱思开海力士有限公司 | Imaging sensor and the method for manufacturing it |
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| CN110620125A (en) * | 2019-09-23 | 2019-12-27 | 上海华力微电子有限公司 | Structure for reducing random telegraph noise in CMOS image sensor and forming method |
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