JP2010251534A - Photoelectric conversion element, image sensor, and method of manufacturing the photoelectric conversion element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein a capital investment is increased in forming a photoelectric conversion element having a PIN structure by using a CVD method, because three chambers are required to form individual layers in different chambers for avoiding the mixing of impurities into a P-layer and an N-layer, and to solve the problem, wherein black floating occurs due to interface-defect-induced charge generation caused by the contact between an I layer and a region other than semiconductor layers. <P>SOLUTION: An I-type semiconductor layer 208 is surrounded by an N<SP>+</SP>layer 210, obtained by a CVD method and a P<SP>+</SP>layer 207 formed by an ion implantation method. The I-type semiconductor layer 208 does not make contact with a region other than the semiconductor layers. Accordingly, interface-defect-induced charge generation can be suppressed. Formation of the P<SP>+</SP>layer 207 by using the ion implantation method allows a CVD apparatus equipped with two chambers to be used, thereby reduction in the capital investment becomes possible. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion element, an image sensor, and a method for manufacturing a photoelectric conversion element.

  Conventionally, crystalline silicon has been mainly used as a substrate for forming an image sensor, but recently, glass is used for the substrate, an amorphous silicon layer is used as a photoelectric conversion layer, and electrical processing between the photoelectric conversion layer is performed. In addition, image sensors using TFTs (thin film transistors) made of polysilicon or the like have been intensively studied.

  When a crystalline silicon substrate is used, the substrate diameter is about 30 cm in diameter, but using a glass substrate makes it possible to use a substrate with a side of nearly 3 m, and to obtain a large image sensor. Become. In addition, since the number of image sensors obtained from a single substrate is different, there is a difference in the number of acquisitions in addition to the value difference of the substrate itself, which is advantageous in terms of cost.

  In Patent Document 1, as a manufacturing method of an image sensor (referred to as a photoelectric conversion element), an impurity is added to a material containing a raw material to be a host (substrate) to an I layer (a layer containing almost no impurities), N-type layers and P-type layers are formed by diffusing, for example, phosphorus in the case of N-type and boron, for example in the case of P-type. Further, Patent Document 2 describes a structure in which a PIN structure is arranged in the horizontal direction.

JP 2007-258332 A Japanese Patent Laid-Open No. 2005-19638

  As shown in Patent Document 1, when impurity diffusion from a host is performed, it is necessary to add a large amount of phosphorus or boron to the host. Phosphorus and boron have the property of making the metal brittle, and there is a problem that the reliability of the metal in a region used as an electrode such as ITO (indium / tin / oxide) or tungsten directly connected to the host is lowered. . In addition, since these impurities are added to portions other than the semiconductor layer, the inside of the image sensor may be contaminated. In order to avoid this phenomenon, it may be considered to add an impurity only to a necessary portion. In this case, however, another problem that the number of manufacturing steps increases is caused. Further, the semiconductor layer is extremely sensitive to contamination, and even if the stacked host is removed for impurity diffusion, the properties of the semiconductor layer may be changed due to contamination by residual impurities.

  In addition, when the technique disclosed in Patent Document 2 is used, since the region that does not contribute to the photoelectric reaction is disposed adjacent to the photoelectric reaction region, the equivalent incident light amount is decreased, and the sensitivity is decreased due to the decrease in photoelectric conversion efficiency. For this reason, there is a problem that the image quality is deteriorated due to noise particularly when used in a low light quantity.

  As the photoelectric conversion layer, a photodiode having a PIN structure is typically used. However, when the PIN structure is formed by a CVD (chemical vapor deposition) method, a P layer or N layer is used. In order to avoid contamination of impurities in the layer, it is necessary to form a chamber (reaction chamber) separately. In this case, three chambers are required, and there is a problem that initial investment becomes large. Here, it is possible to suppress the increase in the number of chambers by switching the gas components and using the CVD method. However, since it becomes impossible to form a layer until the remaining amount of impurity components disappears, this time the throughput is increased. There is a problem of lowering.

  In addition, since the I layer is in direct contact with the element isolation layer, a leakage current due to an interface defect occurs. For this reason, there is a problem that the image quality is deteriorated due to noise particularly when used in a low light quantity.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. Note that the first conductivity type impurity amount represents the sum of the impurities indicating the first conductivity type, and the second conductivity type impurity amount represents the sum of the impurities indicating the second conductivity type. For example, when the first conductivity type is N-type, it is defined that the amount of N-type impurities is equal when the total amount of N-type impurities such as arsenic and phosphorus is equal. Similarly, for example, when the first conductivity type is P type, similarly, when the total amount of impurities indicating P type, such as boron and indium, is equal, the first conductivity type impurity amount is defined to be equal. The second conductivity type is defined as a conductivity type having a polarity opposite to that of the first conductivity type. Further, “light” is not limited to only visible light, and X-rays, electron beams, ultraviolet rays, infrared rays, and the like are also handled as light. The electron beam is assumed to be an electromagnetic wave having a very short wavelength.

  Application Example 1 A photoelectric conversion element according to this application example has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a first conductivity type impurity amount less than that of the first conductivity type semiconductor layer, and An I-type semiconductor layer having a smaller amount of second-conductivity-type impurities than the second-conductivity-type semiconductor layer, wherein the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer serve as the I-type semiconductor layer. And a junction region that is wrapped and directly joined to the first conductive semiconductor layer and the second conductive semiconductor layer.

  According to this, since the first conductive type semiconductor layer and the second conductive type semiconductor layer are directly joined, the I type semiconductor layer is surrounded by the first conductive type semiconductor layer and the second conductive type semiconductor layer. Will be. Therefore, the I-type semiconductor layer does not touch anything other than the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and can suppress charge generation due to interface defects. Therefore, it is possible to suppress the occurrence of leakage current due to interface defects that occurs when the I-type semiconductor layer is in contact with a place other than the semiconductor layer. Note that the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact with other substances, but both have a higher impurity concentration than the I type semiconductor layer, so that the interface defect is high. Filled with a layer having a carrier density. Therefore, it is possible to suppress the generation of charges due to interface defects.

  Application Example 2 In the photoelectric conversion element according to the application example, the first conductivity type semiconductor layer side including the junction region or the second conductivity type semiconductor layer side including the junction region may include the first conversion element. A region including a total impurity amount of the conductivity type impurity amount and the second conductivity type impurity amount is provided.

  According to the application example described above, the impurity concentration in the junction region where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined is the sum of the first conductivity type impurity amount and the second conductivity type impurity amount. High value. When the impurity concentration is high, the crystal structure is destroyed and a very high resistance region is formed. Therefore, the first conductive type semiconductor layer and the second conductive type semiconductor layer are insulated, and it is possible to suppress the occurrence of a leak current generated between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

  Application Example 3 An image sensor according to this application example is an image sensor including a photoelectric conversion element that converts an optical signal into an electric signal and outputs it in cooperation with an active element disposed on a substrate. The first conductivity type semiconductor layer, the second conductivity type semiconductor layer, the first conductivity type impurity amount is smaller than that of the first conductivity type semiconductor layer, and the second conductivity type impurity is less than that of the second conductivity type semiconductor layer. An I-type semiconductor layer having a small amount, wherein the first conductive semiconductor layer and the second conductive semiconductor layer surround the I-type semiconductor layer, and the first conductive semiconductor layer, A photoelectric conversion element including a junction region where the conductive semiconductor layer is directly joined is provided on the substrate.

  According to this, since the first conductive type semiconductor layer and the second conductive type semiconductor layer are directly joined, the I type semiconductor layer is surrounded by the first conductive type semiconductor layer and the second conductive type semiconductor layer. Will be. Therefore, the I-type semiconductor layer does not touch anything other than the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and can suppress charge generation due to interface defects. Accordingly, it is possible to suppress the occurrence of leakage current due to interface defects caused by contact of the I-type semiconductor layer with a place other than the semiconductor layer, and to provide an image sensor with particularly high definition of black display. It becomes possible. Note that the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact with other substances, but since the impurity concentration is higher than that of the I type semiconductor layer, the interface defect has a high carrier density. Filled with a layer having Therefore, it is possible to suppress the generation of charges due to interface defects.

  Application Example 4 In the image sensor according to the application example, the photoelectric conversion element is on the first conductivity type semiconductor layer side including the junction region, or on the second conductivity type semiconductor layer side including the junction region. A region including a sum of the first conductivity type impurity amount and the second conductivity type impurity amount is provided.

  According to the application example described above, the impurity concentration in the junction region where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined is the sum of the first conductivity type impurity amount and the second conductivity type impurity amount. High value. When the impurity concentration is high, the crystal structure is destroyed and a very high resistance region is formed. Therefore, an insulating region is formed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. For this reason, it is possible to suppress the occurrence of leakage current between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and it is possible to provide an image sensor with high definition of black display.

  Application Example 5 A method for manufacturing a photoelectric conversion element according to this application example includes a step of forming a first conductivity type semiconductor layer and a step of forming an I type semiconductor layer following the formation of the first conductivity type semiconductor layer. And patterning the first conductivity type semiconductor layer and the I type semiconductor layer; and implanting second conductivity type impurity ions to form a second conductivity type semiconductor layer; The first conductivity type impurity amount of the layer is less than that of the first conductivity type semiconductor layer, and the second conductivity type impurity amount of the I type semiconductor layer is less than that of the second conductivity type semiconductor layer. The type semiconductor layer and the second conductivity type semiconductor layer cooperate to wrap the I type semiconductor layer, and have a junction region where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined. It is characterized by.

  According to this, since the impurity concentration in the junction region where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined is the sum of the first conductivity type impurity amount and the second conductivity type impurity amount, a high value is obtained. It becomes. When the impurity concentration is high, the crystal structure is destroyed and a very high resistance region is formed. Therefore, the first conductive type semiconductor layer and the second conductive type semiconductor layer are insulated, and it is possible to suppress the occurrence of a leak current generated between the first conductive type semiconductor layer and the second conductive type semiconductor layer. In addition, since the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined, the I type semiconductor layer is surrounded by the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. It becomes. Therefore, the I-type semiconductor layer does not touch anything other than the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and can suppress charge generation due to interface defects. Therefore, it is possible to suppress the occurrence of leakage current due to interface defects that occurs when the I-type semiconductor layer is in contact with a place other than the semiconductor layer. Therefore, by using this manufacturing method, it is possible to provide a photoelectric conversion element in which deterioration in image quality due to leakage current is suppressed. Note that the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact with other substances, but since the impurity concentration is higher than that of the I type semiconductor layer, the interface defect has a high carrier density. Filled with a layer having Therefore, it is possible to suppress the generation of charges due to interface defects.

  Application Example 6 A method for manufacturing a photoelectric conversion element according to this application example includes a step of forming a first conductivity type semiconductor layer and a step of forming an I type semiconductor layer following the formation of the first conductivity type semiconductor layer. And a step of implanting second conductivity type impurity ions to form a second conductivity type semiconductor layer, wherein the first conductivity type impurity amount of the I type semiconductor layer is greater than that of the first conductivity type semiconductor layer. The amount of the second conductivity type impurity of the I-type semiconductor layer is smaller than that of the second conductivity type semiconductor layer.

  According to this, since the second conductivity type impurity ions are implanted into the junction region where the second conductivity type semiconductor layer is directly joined, the second conductivity type semiconductor layer can be formed by diverting the I type semiconductor layer. Thus, it is possible to shorten the semiconductor layer formation time for controlling the manufacturing process, and to provide a manufacturing method capable of producing a photoelectric conversion element with a short TAT (required time).

It is a schematic diagram which shows the wiring structure of the image sensor of this embodiment, (a) is a whole structure, (b) is an enlarged view of the photosensor with which an image sensor is provided. FIG. 3 is an enlarged cross-sectional view illustrating a schematic configuration of a photosensor included in the image sensor according to the present embodiment. (A), (b) is process sectional drawing for demonstrating the manufacturing process of the photosensor with which an image sensor is provided. Process sectional drawing for demonstrating the manufacturing process of the photosensor with which an image sensor is provided. Process sectional drawing for demonstrating the manufacturing process of the photosensor with which an image sensor is provided. Process sectional drawing for demonstrating the manufacturing process of the photosensor with which an image sensor is provided. Process sectional drawing for demonstrating the manufacturing process of an image sensor. Process sectional drawing for demonstrating the manufacturing process of an image sensor. Process sectional drawing for demonstrating the manufacturing process of an image sensor.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. Moreover, the same code | symbol is attached | subjected to the corresponding part.

(First Embodiment: Configuration of Image Sensor)
Hereinafter, the configuration of the image sensor will be described. FIG. 1 is a schematic diagram illustrating a wiring structure of an image sensor according to the present embodiment, where (a) is an overall configuration, and (b) is an enlarged view of a photosensor included in the image sensor. As shown in FIG. 1A, the image sensor 100 of the present embodiment is provided with scanning lines 3a and data lines 6a extending in a direction intersecting with the element region A. The scanning line 3 a is connected to the scanning line driving circuit 102, and the data line 6 a is connected to the data line driving circuit 101. The photo sensors 50 are formed corresponding to the vicinity of the intersections of the scanning lines 3a and the data lines 6a, and are arranged in a matrix in the element region A.

  As shown in FIG. 1B, a constant potential line 3b is provided in parallel with the scanning line 3a, and a constant potential line 12a is provided in parallel with the data line 6a. The constant potential line 3 b is connected to the scanning line driving circuit 102, and the constant potential line 12 a is connected to the data line driving circuit 101. In each photosensor 50, a photodiode 20 as a photoelectric conversion element and a storage capacitor 30 are electrically connected in series between the constant potential line 12a and the constant potential line 3b. Here, the storage capacitor 30 is preferably made of a light-transmitting substance. In this case, the storage capacitor 30 can be disposed below the photodiode 20. Further, a TFT (thin film transistor) 10 in which the gate electrode 10G (see FIG. 2) is connected to the scanning line 3a is formed, and the source 10S (see FIG. 2) of the TFT 10 is connected to the data line 6a and the drain. 10D (see FIG. 2) is electrically connected to a connection point between the photodiode 20 and the storage capacitor 30. In the present embodiment, the photosensor 50 is configured by the TFT 10, the photodiode 20, and the storage capacitor 30.

  FIG. 2 is an enlarged cross-sectional view illustrating a schematic configuration of a photosensor included in the image sensor according to the present embodiment. The photosensor 50 includes a substrate 250, a TFT 10, a photodiode 20 as a photoelectric conversion element, a first interlayer insulating layer 201, a second interlayer insulating layer 202, a planarizing layer 203, a capacitor insulating layer 204, an element isolation layer 205, an upper electrode. 206, a lower electrode 211, a capacitor electrode 213, a constant potential contact 214, a data line contact 215, a contact hole 201C, a contact hole 202C, a first contact 201W, a second contact 202W, and a storage capacitor 30.

  The TFT 10 includes a channel 10CH, an electric field relaxation portion 10LDD, a source 10S, a drain 10D, a gate insulating layer 10GI, and a gate electrode 10G.

  The channel 10CH has a function of controlling the current flowing through the TFT 10 and switching on and off between the source 10S and the drain 10D.

  The gate insulating layer 10GI and the gate electrode 10G have a function of inducing or eliminating carriers in the channel 10CH in cooperation.

  The electric field relaxation unit 10LDD has a function of relaxing the electric field strength applied between the source 10S and the channel 10CH, the drain 10D and the channel 10CH, and suppressing the deterioration of the TFT 10 due to hot carriers generated by the acceleration of carriers by the high electric field. have.

  The substrate 250 supports the structure in the upper layer. As the substrate 250, for example, glass is preferably used. Glass having a flat structure is currently available with a side of about 3 m, and is suitable because a large number of image sensors 100 can be manufactured at one time. A ceramic plate or the like may be used as the substrate.

  The first interlayer insulating layer 201, the second interlayer insulating layer 202, the contact hole 201C, the contact hole 202C, the first contact 201W, and the second contact 202W are formed for electrical wiring. In terms of structure, it is not possible to create a structure in which electrical wirings intersect with each other while maintaining independence on one interlayer insulating layer. Therefore, it is possible to perform complicated electrical wiring by using a multilayer interlayer insulating layer for separation of electrical wiring. Here, the conduction between the respective interlayer insulating layers is performed, for example, via the first contact 201W and the second contact 202W.

  The planarization layer 203 has a function of covering the TFT 10 and the surface that is uneven by the electric wiring and returning it to the flat surface. By flattening in this manner, the photodiode 20 can be formed in a region overlapping the TFT 10 and the substrate 250 in plan view, and the photosensor 50 having a small area and high photosensitivity can be obtained.

  The capacitor insulating layer 204 is formed to form the storage capacitor 30 in a region where the upper electrode 206 and the lower electrode 211 overlap with each other in the plan view of the substrate 250. By forming the storage capacitor 30, it is possible to store carriers generated in the photodiode 20 other than the photodiode 20, and to secure a large dynamic range for the optical signal.

  The upper electrode 206 and the lower electrode 211 cooperate to control the charge generated from the photodiode 20 and supply a bias voltage.

  The element isolation layer 205 is disposed between adjacent photodiodes 20 and has a function of avoiding crosstalk between the photodiodes 20.

  The constant potential contact 214 is electrically connected to the constant potential line 3b (see FIG. 1B) and has a function of providing a constant potential for accumulating charges in the storage capacitor 30.

  The data line contact 215 is electrically connected to the data line 6a (see FIG. 1B), receives a signal from the scanning line 3a (see FIG. 1A), and receives the signal from the photodiode 20 and the storage capacitor 30. The accumulated charge is output to the data line 6a.

The photodiode 20 includes an N ⁺ layer 210 as a first conductivity type semiconductor layer, an I type semiconductor layer 208, and a P ⁺ layer 207 as a second conductivity type semiconductor layer. The first conductivity type semiconductor layer may be P ⁺ and the second conductivity type semiconductor layer may be N ⁺ . In this case, it can be dealt with by changing the electrical wiring or the like, or changing the bias condition of the photodiode 20. N ⁺ and P ⁺ mean high concentration N-type and high concentration P-type (for example, about 1 × 10 ²⁰ cm ⁻³ or more), respectively. Here, the N-type impurity amount (first conductivity type impurity amount) of the I-type semiconductor layer 208 is smaller than that of the N ⁺ layer 210, and the P-type impurity amount (second conductivity type impurity amount) is smaller than that of the P ⁺ layer 207. . The depletion layer of the I-type semiconductor layer 208 functions as a photoelectric conversion unit. The impurity concentration in the I-type semiconductor layer 208 is low. Therefore, the elongation of the depletion layer is increased. Therefore, it is possible to increase the photoelectric conversion efficiency.

Further, at the boundary portion between the N ⁺ layer 210 and the P ⁺ layer 207, the impurity amount of the P ⁺ layer 207 (second conductivity type impurity amount) and the impurity amount of the N ⁺ layer 210 (first conductivity type impurity amount). The quantity has a value that is the sum of both. Therefore, the crystallinity at the boundary portion between the N ⁺ layer 210 and the P ⁺ layer 207 is remarkably lowered, and an extremely high resistance region is formed. Therefore, the dark current flowing between the N ⁺ layer 210 and the P ⁺ layer 207 can be reduced, and the black image quality can be improved.

The I-type semiconductor layer 208 constituting the photodiode 20 is covered with an N ⁺ layer 210 and a P ⁺ layer 207, and the I-type semiconductor layer 208 does not contact any region other than the semiconductor layer. Therefore, generation of charges due to interface defects can be suppressed. Although the N ⁺ layer 210 and the P ⁺ layer 207 come into contact with other substances, the N ⁺ layer 210 and the P ⁺ layer 207 have a high impurity concentration, so that the interface defect has a high carrier density. Since it is filled with a layer, it loses its ability to generate charge. Therefore, it is possible to suppress the generation of charges due to interface defects. Therefore, the dark current can be reduced and the black image quality can be improved.

(Second Embodiment: Manufacturing Method of Image Sensor)
Hereinafter, a method for manufacturing an image sensor including a photodiode as a photoelectric conversion element will be described with reference to FIGS. 3A, 3 </ b> B, 4, 5, and 6. 3A, 3 </ b> B, 4, 5, and 6 are process cross-sectional views for explaining a manufacturing process of a photosensor included in the image sensor.

  First, as step 1, a TFT 10 as an active element is formed on a substrate 250. As a method for forming the TFT 10, for example, an amorphous silicon layer having a thickness of about 70 nm is formed and crystallized by excimer laser annealing to be modified into a polysilicon layer. Next, patterning is performed leaving a region to be the TFT 10. Next, heat treatment is performed in an oxidizing atmosphere to form an oxide film, and then the gate insulating layer 10GI is formed by a CVD method or the like. Next, for example, after an aluminum alloy film or the like is formed, patterning is performed to form the gate electrode 10G. Next, for example, ion implantation is performed using the gate electrode 10G as a mask to form the electric field relaxation portion 10LDD. In this step, another mask may be used. Next, for example, a mask that covers the gate electrode 10G and overlaps the region where the electric field relaxation portion 10LDD is left in plan view in the substrate 250 is formed, ion implantation is performed, and the source 10S and the channel 10CH (below the gate electrode 10G Impurities do not enter and the channel 10CH remains), and the drain 10D is formed, whereby the TFT 10 is formed. A cross-sectional view after the steps up to here are shown in FIG.

  Next, as step 2, an electrical wiring portion is formed. Specifically, the first interlayer insulating layer 201 is formed using a CVD method or the like. Next, patterning is performed to open a region where the data line contact 215 and the first contact 201W are formed (the contact hole 201C corresponds to the first contact 201W) including the gate insulating layer 10GI. Next, the data line contact 215 and the first contact 201 </ b> W are formed by tungsten CVD, and are electrically connected to the source 10 </ b> S and the drain 10 </ b> D. Then, unnecessary portions of tungsten are removed by patterning.

  Here, instead of using tungsten for the wiring, the data line contact 215 and the first contact 201W may be etched and the wiring may be performed using another metal such as an aluminum alloy. Since the aluminum alloy has a resistivity about half that of tungsten, the time constant caused by the wiring can be reduced. In the subsequent processes, the same process can be applied to the filling of the contact portion. Next, the second interlayer insulating layer 202 is formed using a CVD method or the like. Next, patterning is performed to open a region where the constant potential contact 214 and the second contact 202W are to be formed (the contact hole 202C corresponds to the second contact 202W). Next, the constant potential contact 214 and the second contact 202W are formed by tungsten CVD, and are electrically connected to the drain 10D. Then, unnecessary portions of tungsten are removed by patterning. A cross-sectional view after the steps so far are shown in FIG.

  Next, as Step 3, a storage capacitor 30 and a region (see FIG. 2) to be the lower electrode 211 of the photodiode 20 as a photoelectric conversion element are formed. First, a planarization layer 203 is formed by forming a layer having a thickness of about 2 μm using acrylic and patterning. Next, a capacitor electrode 213 is formed by forming and patterning a layer thickness of about 100 nm using tungsten or the like. Next, a silicon nitride layer is deposited, and a region where the second contact 202W overlaps with the second electrode 202W in plan view on the substrate 250 is opened by forming a capacitor insulating layer 204. Next, the lower electrode 211 and the storage capacitor 30 are formed simultaneously by forming and patterning a layer thickness of about 100 nm using tungsten or the like. A cross-sectional view after the steps up to here are shown in FIG.

Next, as a step 4, a precursor of the photodiode 20 is formed. First, an N ⁺ layer 210 as a first conductivity type semiconductor layer is formed using a CVD method. Subsequently, for example, the reaction chamber of the CVD apparatus is changed to form the I-type semiconductor layer 208. This step may be performed by switching the forming gas without changing the reaction chamber. Next, it is taken out from the CVD apparatus and patterned to form a precursor of the photodiode 20. A cross-sectional view after the steps up to here are shown in FIG.

Next, as step 5, by using an ion implantation method, a plasma doping method, or the like, the P ⁺ layer 207 as the second conductivity type semiconductor layer is modified at the portion where the precursor of the photodiode 20 is exposed. A photodiode 20 as a photoelectric conversion element is formed. When performing the CVD method for forming the photodiode 20, it is sufficient to have two chambers, a chamber for forming the N ⁺ layer 210 and a chamber for forming the I-type semiconductor layer 208, with a short TAT (required time), and The photodiode 20 can be formed by a CVD apparatus having a two-chamber configuration. A cross-sectional view after the steps up to here are shown in FIG.

The I-type semiconductor layer 208 constituting the photodiode 20 is covered with an N ⁺ layer 210 and a P ⁺ layer 207, and the I-type semiconductor layer 208 does not contact any region other than the semiconductor layer. Therefore, generation of charges due to interface defects can be suppressed. Although the N ⁺ layer 210 and the P ⁺ layer 207 come into contact with other substances, the N ⁺ layer 210 and the P ⁺ layer 207 have a high impurity concentration, so that the interface defect has a high carrier density. Since it is filled with a layer, it loses its ability to generate charge. Therefore, it is possible to suppress the generation of charges due to interface defects. Accordingly, the dark current can be reduced and the black image quality can be improved.

Here, since the intentional impurity addition is not performed on the I-type semiconductor layer 208, the N-type impurity amount (first conductivity-type impurity amount) of the I-type semiconductor layer 208 is smaller than that of the N ⁺ layer 210, and P The type impurity amount (second conductivity type impurity amount) is smaller than that of the P ⁺ layer 207. Since the depletion layer of the I-type semiconductor layer 208 functions as a photoelectric conversion portion, the photoelectric conversion efficiency can be increased by using the I-type semiconductor layer 208 that has a low impurity concentration and easily extends. Note that less N-type impurities than the N ⁺ layer 210 may be added to the I-type semiconductor layer 208, or less P-type impurities than the P ⁺ layer 207 may be added.

Further, the region that was the N ⁺ layer 210 into which the P-type impurity was implanted has been converted into the P ⁺ layer 207. By using this manufacturing method, at the boundary portion between the N ⁺ layer 210 and the P ⁺ layer 207, the impurity amount of the P ⁺ layer 207 (second conductivity type impurity amount) and the impurity amount of the N ⁺ layer 210 (first conductivity type). Type impurity amount) has a value that is the sum of both. Therefore, the crystallinity at the boundary portion between the N ⁺ layer 210 and the P ⁺ layer 207 is remarkably lowered, and an extremely high resistance region is formed. Therefore, the dark current flowing between the N ⁺ layer 210 and the P ⁺ layer 207 can be reduced, and the black image quality can be improved. Note that the amount of P-type impurity implanted may be set so that the N ⁺ layer 210 retains the region that was the N ⁺ layer 210 into which the P-type impurity has been implanted.

  Next, as step 6, a silicon nitride layer is deposited to a thickness of about 500 nm and then patterned to form an element isolation layer 205. Then, after depositing an ITO (indium / tin / oxide) layer of about 50 nm to be a transparent electrode, patterning is performed to form the upper electrode 206, whereby the image sensor 100 shown in FIG. 2 is formed.

(Third Embodiment: Image Sensor Manufacturing Method with Another Configuration)
In the second embodiment described above, the manufacturing method for manufacturing the configuration in which the N ⁺ layer 210 and the P ⁺ layer 207 cooperate to wrap the I-type semiconductor layer 208 has been described. When the main purpose is to shorten the process of forming the PIN structure in the photodiode 20 as a neck, the image sensor 100a in which the photosensor 50a is integrated can be manufactured even by using the following process. Since this manufacturing method has many parts in common with the second embodiment described above, the description of the parts that are the same manufacturing process will be omitted. 7, 8, and 9 are process cross-sectional views for explaining the manufacturing process of the image sensor.

  First, steps 1 to 4 are performed. So far, the same process is used.

  Next, as step 5a, a silicon nitride layer is deposited to a thickness of about 500 nm and then patterned to form an element isolation layer 205. FIG. 7 shows the process up to this point.

Next, as a step 6a, an ion implantation method, a plasma doping method, or the like is used to modify the P ⁺ layer 207 as the second conductivity type semiconductor layer in the portion where the precursor of the photodiode 20a is exposed. A photodiode 20a as a photoelectric conversion element is formed. When performing the CVD method for forming the photodiode 20a, it is sufficient that there are two chambers, namely, a chamber for forming the N ⁺ layer 210 and a chamber for forming the I-type semiconductor layer 208, with a short TAT (required time), and The photodiode 20a can be formed by a CVD apparatus having a two-chamber configuration. A cross-sectional view after the steps up to here are shown in FIG.

  Next, an ITO layer serving as a transparent electrode is deposited to a thickness of about 50 nm, followed by patterning to form the upper electrode 206, thereby forming the image sensor 100a shown in FIG.

3a ... scanning line, 3b ... constant potential line, 6a ... data line, 10 ... TFT, 10CH ... channel, 10D ... drain, 10G ... gate electrode, 10GI ... gate insulating layer, 10LDD ... electric field relaxation part, 10S ... source, 12a Reference potential line, 20 ... Photodiode, 20a ... Photodiode, 30 ... Retention capacitance, 50 ... Photosensor, 50a ... Photosensor, 100 ... Image sensor, 100a ... Image sensor, 101 ... Data line driving circuit, 102 ... Scanning Line drive circuit 201 ... first interlayer insulating layer 201C ... contact hole 201W ... first contact 202 ... second interlayer insulating layer 202C ... contact hole 202W ... second contact 203 ... flattening layer 204 ... Capacitance insulating layer, 205 ... element isolation layer, 206 ... upper electrode, 207 ... second conductivity type P ⁺ layer as a conductor layer, 208 ... I-type semiconductor layer, 210 ... N ⁺ layer of the first conductivity type semiconductor layer, 211 ... lower electrode, 213 ... capacitor electrode, 214 ... constant potential contact, 215 ... data line contact 250 ... substrate.

Claims (6)

A first conductivity type semiconductor layer;
A second conductivity type semiconductor layer;
An I-type semiconductor layer having a first conductivity type impurity amount less than that of the first conductivity type semiconductor layer and a second conductivity type impurity amount being less than that of the second conductivity type semiconductor layer;
A junction region in which the first conductivity type semiconductor layer and the second conductivity type semiconductor layer enclose the I type semiconductor layer, and the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined. A photoelectric conversion element comprising:   2. The photoelectric conversion element according to claim 1, wherein the first conductivity type is provided on the first conductivity type semiconductor layer side including the directly bonded region or on the second conductivity type semiconductor layer side including the junction region. A photoelectric conversion element comprising a region including an impurity amount that is the sum of an impurity amount and the second conductivity type impurity amount. In cooperation with an active element arranged on a substrate, an image sensor including a photoelectric conversion element that converts an optical signal into an electric signal and outputs the electric signal,
A first conductivity type semiconductor layer;
A second conductivity type semiconductor layer;
An I-type semiconductor layer having a first conductivity type impurity amount less than that of the first conductivity type semiconductor layer and a second conductivity type impurity amount being less than that of the second conductivity type semiconductor layer;
A junction in which the first conductivity type semiconductor layer and the second conductivity type semiconductor layer surround the I type semiconductor layer, and the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined. An image sensor comprising a photoelectric conversion element having a region on the substrate.   4. The image sensor according to claim 3, wherein the photoelectric conversion element is arranged on the first conductive semiconductor layer side including the junction region, or on the second conductive semiconductor layer side including the junction region. An image sensor comprising a region including an impurity amount that is the sum of one conductivity type impurity amount and the second conductivity type impurity amount. Forming a first conductivity type semiconductor layer;
Forming an I-type semiconductor layer following the formation of the first conductive semiconductor layer;
Patterning the first conductive semiconductor layer and the I-type semiconductor layer;
Implanting second conductivity type impurity ions to form a second conductivity type semiconductor layer;
With
The first conductivity type impurity amount of the I type semiconductor layer is less than that of the first conductivity type semiconductor layer,
The second conductivity type impurity amount of the I type semiconductor layer is less than that of the second conductivity type semiconductor layer,
The first conductive semiconductor layer and the second conductive semiconductor layer cooperate to wrap the I type semiconductor layer,
A method for manufacturing a photoelectric conversion element, comprising: a junction region in which the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are directly joined. Forming a first conductivity type semiconductor layer;
Forming an I-type semiconductor layer following the formation of the first conductive semiconductor layer;
Implanting second conductivity type impurity ions to form a second conductivity type semiconductor layer;
With
The first conductivity type impurity amount of the I type semiconductor layer is less than that of the first conductivity type semiconductor layer,
The method for manufacturing a photoelectric conversion element, wherein the second conductivity type impurity amount of the I-type semiconductor layer is smaller than that of the second conductivity type semiconductor layer.

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