TWI478330B - Photoelectric conversion element and method for manufacturing same - Google Patents

Description

Photoelectric conversion element and method of manufacturing same

The present disclosure is directed to a photoelectric conversion element such as a PIN photodiode for, for example, a radiation imaging device and an optical touch sensor, and a method of fabricating the same.

The PIN photodiode system is used as a photoelectric conversion element in a radiation imaging device, an optical touch panel, or the like. The PIN (positive-essential-negative) photodiode has a structure in which a so-called i-type semiconductor layer is interposed between a p-type semiconductor layer and an n-type semiconductor layer, and extractable has an amount depending on the amount of incident light. One of the charge amounts of the signal charge.

It is desired that such a photodiode has further improved optical sensitivity and various proposals have been made in view of such expectations (refer to, for example, Japanese Patent Laid-Open Publication No. 2000-156522). This patent document discloses a photoelectric conversion device in which a semiconductor layer of a photoelectric transducer extends to a portion of a transistor and the extension portion serves as a light blocking layer to thereby ensure a high aperture ratio and improve pattern accuracy for improvement. Sensitivity.

However, in the above PIN photodiode, the i-type semiconductor layer is provided to extend from the inside of one of the holes formed in the interlayer insulating film to the top surface of the interlayer insulating film. Therefore, stress is applied to the i-type semiconductor layer (hierarchical of the side wall portion) due to the shape of the hole and a crack is generated. In particular, if the film thickness of the i-type semiconductor layer is increased to increase the optical sensitivity, the stress becomes larger. This crack has a problem of acting as a leak path and increasing dark current.

There is a need for a technique to provide a photoelectric conversion element capable of suppressing an increase in dark current due to a crack and a method of manufacturing the same.

According to an embodiment of the present disclosure, a photoelectric conversion element is provided, comprising: a first semiconductor layer configured to exhibit a first conductivity type and provided in a selected region above a substrate; a second semiconductor layer configured to exhibit a second conductivity type different from the first conductivity type and disposed opposite the first semiconductor layer; and a third semiconductor layer configured to Provided between the first semiconductor layer and the second semiconductor layer and exhibiting a substantially intrinsic conductivity type. The third semiconductor layer has at least one corner portion that does not contact the first semiconductor layer.

In accordance with another embodiment of the present disclosure, a method of fabricating a photoelectric conversion element is provided. The method includes forming a first semiconductor layer exhibiting a first conductivity type and forming a third semiconductor layer on the first semiconductor layer in a selected region above a substrate. The third semiconductor layer has at least one corner portion that does not contact the first semiconductor layer and exhibits a substantially intrinsic conductivity type, the method further comprising forming a second semiconductor layer exhibiting a second conductivity type on the third semiconductor layer.

According to the photoelectric conversion element and the method of manufacturing the photoelectric conversion element according to the embodiment of the present disclosure, if a crack is generated in the third semiconductor layer due to the influence of stress due to, for example, the shape of the third semiconductor layer, Since the third semiconductor layer has a corner portion, the crack tends to be generated such that its starting point (or end point) is the corner portion of the third semiconductor layer. Since the corner portion does not contact the first semiconductor layer, the crack generated is suppressed from acting as a leak path. Or, the generation of the crack itself is suppressed.

According to the photoelectric conversion element and the method of manufacturing the photoelectric conversion element according to the embodiment of the present disclosure, the third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer has a corner portion that does not contact the first semiconductor layer. Thus, for example, when a crack is generated in the third semiconductor layer, the crack can be suppressed from acting as a leak path. Alternatively, the occurrence of the crack itself can be suppressed. This can suppress an increase in dark current due to cracks.

Modes for carrying out the disclosure will be described below with reference to the drawings. The description sequence is as follows.

1. Embodiment (wherein the i-type semiconductor layer is formed such that it ranges from the inside of the contact hole to the top surface of the first interlayer insulating film)

2. Modifications of Examples 1 and 2 (where the contact holes are formed by two-step etching)

3. Modification Examples 3 and 4 (examples in which an i-type semiconductor layer is patterned in a contact hole)

4. Application examples (examples of photoelectric conversion devices and radiation imaging devices using photoelectric conversion elements)

<Example>

1 shows a schematic configuration of a photoelectric conversion element 10 in accordance with an embodiment of the present disclosure. The photoelectric conversion element 10 obtains one PIN (positive-essential-negative) photoelectric by interposing an undoped i-type semiconductor layer (essential semiconductor layer) between a p-type semiconductor layer and an n-type semiconductor layer. Diode.

[Complete Configuration of Photoelectric Conversion Element 10]

The photoelectric conversion element 10 has a p-type semiconductor layer 14 (first semiconductor layer) in a selected region above one of the substrates 11 made of, for example, glass, (the intermediate is an insulating film 13). A first interlayer insulating film 15A having one of contact holes 150A (through holes) opposite to the p-type semiconductor layer 14 is provided over the substrate 11 (specifically on the insulating film 13). An i-type semiconductor layer 16 (third semiconductor layer) is provided on the p-type semiconductor layer 14 in the contact hole 150A of the first interlayer insulating film 15A, and an n-type semiconductor layer 17 is formed on the i-type semiconductor layer 16 ( Second semiconductor layer). An upper electrode 18 is connected to the n-type semiconductor layer 17 via a contact hole 150B of a second interlayer insulating film 15B. 2 is a schematic plan view showing a formation region of the p-type semiconductor layer 14, the contact hole 150A, and the i-type semiconductor layer 16 (n-type semiconductor layer 17). Figure 1 is equivalent to a cross-sectional view taken along line A-A' in Figure 2. Figure 3 is an arrow cross-sectional view taken along line BB' of Figure 2.

For the present embodiment, a case where the p-type semiconductor layer 14 is provided on the substrate side (lower side) and the n-type semiconductor layer 17 is provided on the upper side will be described below. However, an opposite structure may be employed, that is, a case where an n-type semiconductor layer is provided on the lower side (substrate side) and a p-type semiconductor layer is provided on the upper side.

The insulating film 13 is obtained by stacking an insulating film such as the SiNx layer 13a and the SiO ₂ layer 13b. For example, if the photoelectric conversion element 10 is used in, for example, each pixel in an image forming apparatus, the insulating film 13 can be formed in the same layer as the gate insulating film in various types of transistors. The thickness of the SiNx layer 13a is, for example, 50 nm and the thickness of the SiO ₂ layer 13b is, for example, 10 nm to 120 nm.

The p-type semiconductor layer 14 is made of one p+ region and has a thickness of, for example, 40 nm to 50 nm by doping, for example, boron (B) with, for example, polycrystalline silicon/polysilicon or microcrystalline germanium. This p-type semiconductor layer 14 is also used, for example, as a lower electrode (anode) for reading a signal charge and is connected to the lower extraction interconnect 16h.

The first interlayer insulating film 15A is obtained by stacking insulating films (i.e., SiO ₂ layer 15A1, SiNx layer 15A2, and SiO ₂ layer 15A3). For example, if the photoelectric conversion element 10 is used in, for example, each pixel in an image forming apparatus, the first interlayer insulating film 15A can be formed in the same layer as one of the interlayer insulating films of various types of transistors. . The thickness of the SiO ₂ layer 15A1 is, for example, 150 nm. The thickness of the SiNx layer 15A2 is, for example, 300 nm. The thickness of the SiO ₂ layer 15A3 is, for example, 200 nm.

In this first interlayer insulating film 15A, a contact hole 150A is formed by etching. In the present embodiment, the contact hole 150A is formed by a one-step etching process. That is, the shape of one of the wall surfaces 15S1 of the contact hole 150A is a straight line shape in a section along a direction perpendicular to the surface of the substrate. In other words, the wall surface 15S1 is a flat surface of one of the cornerless ridges (convex portions). This wall surface 15S1 may be one of the inclined surfaces as shown in FIG. 1 or may be perpendicular to one surface of the substrate surface.

The i-type semiconductor layer is a semiconductor layer exhibiting a substantially intrinsic conductivity type, for example, an undoped intrinsic semiconductor layer, and is composed of, for example, non-crystalline silicon/amorphous silicon. The thickness of the i-type semiconductor layer 16 is, for example, 400 nm to 1000 nm. As this thickness becomes larger, the optical sensitivity can be increased to a greater extent. Details of the configuration of this i-type semiconductor layer 16 will be described later.

The n-type semiconductor layer 17 is composed of, for example, non-crystalline silicon/amorphous silicon and forms an n+ region. The thickness of the n-type semiconductor layer 17 is, for example, 10 nm to 50 nm.

The upper electrode 18 is for supplying one of the reference potentials of the photoelectric conversion and is formed of a transparent conductive film of, for example, indium tin oxide (ITO). This upper electrode 18 is connected to a power supply line (not shown). The second interlayer insulating film 15B is composed of, for example, SiO ₂ and has a thickness of, for example, 400 nm.

(Details of configuration of the i-type semiconductor layer 16)

In the present embodiment, the i-type semiconductor layer 16 is provided so as to extend from the inside of the contact hole 150A of the first interlayer insulating film 15A to the top surface of the first interlayer insulating film 15A (specifically, to the position p1). In other words, a portion of the i-type semiconductor layer 16 overlaps (superimposes) with the top surface of the first interlayer insulating film 15A. Further, the i-type semiconductor layer 16 has a stepped structure (16S1) depending on the level of the first interlayer insulating film 15A (the difference in height of the wall surface of the contact hole 150A). As described in more detail below, due to this stepped structure 16S1, stress occurs (stress is applied to) the i-type semiconductor layer 16 and promotes the generation of cracks.

This i-type semiconductor layer 16 is provided along the shape of the wall surface 15S1 of the contact hole 150A of the first interlayer insulating film 15A. That is, the surface (side surface) of the i-type semiconductor layer 16 on the side of the first interlayer insulating film 15A has a surface shape depending on the above-described shape of the wall surface 15S1 and is a flat surface in this embodiment.

Further, the i-type semiconductor layer 16 has a corner portion 16e of the p-type semiconductor layer 14 in a surface (the surface on the opposite side of the n-type semiconductor layer 17) on the side not contacting the substrate 11. This corner portion 16e is equivalent to a portion corresponding to the end edge on the side of the substrate 11 in the present embodiment, wherein the side surface of the i-type semiconductor layer 16 is a flat surface. This structure is equivalent to the structure in which the lower side opening of the contact hole 150A is formed so as to surround the outside of the formation region of the p-type semiconductor layer 14 in the direction along the substrate surface. That is, the width Da of the p-type semiconductor layer 14 is smaller than the width Db of the opening on the lower side of the contact hole 150A.

[Method of Manufacturing Photoelectric Conversion Element 10]

For example, the photoelectric conversion element 10 can be manufactured in the following manner. 4A to 8B are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element 10 in a hierarchical order.

First, as shown in FIG. 4A, an insulating film 13 is formed on the substrate 11 by depositing the SiNx layer 13a and the SiO ₂ layer 13b in this order by, for example, chemical vapor deposition (CVD). An amorphous germanium (α-Si) layer 14A is deposited on the formed insulating film 13 by, for example, CVD.

Next, as shown in FIG. 4B, a dehydrogenation annealing treatment is performed at, for example, a temperature of 400 ° C to 450 ° C. Subsequently, as shown in FIG. 4C, the ?-Si layer 14A is converted into polycrystalline germanium by, for example, excimer laser annealing (ELA) by irradiating the ?-Si layer 14A with, for example, laser light L having a wavelength of 308 nm. Thereby, a polycrystalline germanium (p-Si) layer 14B is formed on the insulating film 13.

Next, as shown in FIG. 5A, the formed p-Si layer 14B is doped with, for example, boron (B) ions by, for example, ion implantation. Thereby, the p-type semiconductor layer 14 is formed on the insulating film 13 to serve as a p+ region. Subsequently, as shown in FIG. 5B, the p-type semiconductor layer 14 is patterned by, for example, photolithography.

Next, as shown in FIG. 5C, the SiO ₂ layer 15A1, the SiNx layer 15A2, and the SiO ₂ layer 15A3 are deposited in this order over the entire surface of the substrate 11 by, for example, CVD, and the p-type semiconductor layer 14 is formed in the Above the substrate 11. This forms the first interlayer insulating film 15A.

Next, as shown in FIG. 6A, a contact hole 150A is formed in a region of the first interlayer insulating film 15A opposed to the p-type semiconductor layer 14 by, for example, photolithography. In this step, in the present embodiment, three layers of the first interlayer insulating film 15A, that is, the SiO ₂ layer 15A1 and the SiNx layer 15A2, are removed by a one-time (one-step) etching process (such as dry etching). SiO ₂ layer 15A3. Thereby, the contact hole 150A having the flat wall surface 15S1 is formed. At this time, the etching is performed such that the lower side opening of the contact hole 150A becomes larger than the p-type semiconductor layer 14 (around the outside of the p-type semiconductor layer 14). This allows the above-described corner portion 16e to be formed in the i-type semiconductor layer 16 to be formed in the next step.

Next, as shown in FIG. 6B, the i-type semiconductor layer 16 and the n-type semiconductor layer 17 are deposited in this order over the first interlayer insulating film 15A by, for example, CVD filling the contact holes 150A. Thereby, the stepped structure 16S1 depending on the height difference of the contact hole 150A is formed in the i-type semiconductor layer 16. The n-type semiconductor layer 17 is formed in accordance with the surface shape of the i-type semiconductor layer 16 having the first-order structure 16S1.

Next, as shown in FIG. 7A, the formed i-type semiconductor layer 16 and n-type semiconductor layer 17 are patterned into a predetermined shape by, for example, photolithography. At this time, the i-type semiconductor layer 16 and the n-type semiconductor layer 17 are patterned in such a manner as to overlap the first interlayer insulating film 15A in a range to a predetermined position p1 on the first interlayer insulating film 15A. In this patterning, the SiO ₂ layer 15A3 of the first interlayer insulating film 15A serves as an etch stop layer.

Next, as shown in FIG. 7B, a second interlayer insulating film 15B is deposited over the entire surface of the substrate 11 by, for example, CVD.

Next, as shown in FIG. 8A, a contact hole 150B is formed in a region of the second interlayer insulating film 15B opposed to the n-type semiconductor layer 17 by, for example, photolithography. Subsequently, as shown in FIG. 8B, the upper electrode 18 is deposited by, for example, sputtering and thereby the photoelectric conversion element 10 shown in Fig. 1 is completed.

[Operation and Effect of Photoelectric Conversion Element 10]

In the photoelectric conversion element 10, when a predetermined potential is applied from a power supply line (not shown) via the upper electrode 18, for example, light incident from the side of the upper electrode 18 is converted into a charge having a quantity depending on the amount of received light. The amount of signal charge (photoelectric conversion). The signal charge generated by this photoelectric conversion is extracted as the photocurrent from the side of the p-type semiconductor layer 14.

As described above, in this photoelectric conversion element 10, the i-type semiconductor layer 16 is provided so as to extend from the inside of the contact hole 150A to the top surface of the first interlayer insulating film 15A. Therefore, the i-type semiconductor layer 16 has a stepped structure 16S1 depending on the height difference of the wall surface 15S1 of the contact hole 150A. If the i-type semiconductor layer 16 has this first-order structure 16S1, stress is applied to the i-type semiconductor layer 16 and a crack (slit) is easily generated on, for example, the edge portion of the stepped structure 16S1. As described above, in order to increase the optical sensitivity, the film thickness of the i-type semiconductor layer 16 is preferably increased. However, as the film thickness increases, the height difference of the wall surface 15S1 becomes larger (the height difference of the stepped structure 16S1 becomes larger) and thus a crack is more likely to be generated.

The influence of the above crack in the photoelectric conversion element (photoelectric conversion element 100) according to a comparative example will be described below. 9 is a schematic plan view showing a region in which a p-type semiconductor layer 104, a contact hole 109A, and an i-type semiconductor layer 106 (n-type semiconductor layer 107) in the photoelectric conversion element 100 are formed. Figure 10A is a cross-sectional view taken along line A-A' of Figure 9. Figure 10B is an arrow cross-sectional view taken along line BB'. The photoelectric conversion element 100 has a p-type semiconductor layer 104 (the intermediate is an insulating film 103) in a selected region above the substrate 101, and a contact hole 109A having a surface opposite to the p-type semiconductor layer 104 is provided on the p-type semiconductor layer 104. One of the first interlayer insulating films 105A. The i-type semiconductor layer 106 and the n-type semiconductor layer 107 are provided in a region corresponding to the contact hole 109A, and the i-type semiconductor layer 106 has a layer 106S on the top surface thereof.

In the photoelectric conversion element 100 of the above comparative example, a crack X as shown in Fig. 11A is generated due to the stress attributed to the layer 106S. The generated crack X reaches the p-type semiconductor layer 104. Therefore, the crack X acts as a leak path and generates a dark current.

In contrast, in the present embodiment, as shown in FIG. 11B, the i-type semiconductor layer 16 has a corner portion 16e. Therefore, the crack X is generated such that its starting point (end point) is the corner portion 16e. Therefore, since the corner portion 16e does not contact the p-type semiconductor layer 14, even when the crack X due to the step structure 16S1 is generated, the crack X is introduced to the corner portion 16e separated from the p-type semiconductor layer 14, thereby suppressing Crack X acts as a leak path. Fig. 12 is an image obtained by photographing the actually generated crack X.

As described above, in the present embodiment, in the PIN photodiode structure having the i-type semiconductor layer 16 between the p-type semiconductor layer 14 and the n-type semiconductor layer 17, the i-type semiconductor layer 16 has no contact with the p-type semiconductor. The corner portion 16e of the layer 14. Due to this feature, for example, in the case where the i-type semiconductor layer 16 has the stepped structure 16S1 depending on the shape of the contact hole 150A, even when cracks are generated due to the stepped structure 16S1, cracks can be suppressed as one Leak path. This can suppress an increase in dark current due to cracks.

Modified examples of the photoelectric conversion elements of the above embodiments (modification examples 1 to 4) will be described in detail below. In the following description, the same constituent elements as those in the photoelectric conversion element 10 according to the above embodiment are given the same element symbols and the description thereof is omitted accordingly.

<Modification Examples 1 and 2>

Fig. 13 shows a sectional configuration of a photoelectric conversion element according to one modification example 1. Fig. 14 shows a sectional configuration of a photoelectric conversion element according to Modification Example 2. The photoelectric conversion elements of the modified examples 1 and 2 are similar to the photoelectric conversion element 10 of the above-described embodiment, having a p-type conductive layer 14 over the substrate 11 (the intermediate is an insulating layer 13) and a first interlayer insulating film 15C. An i-type semiconductor layer 16 is provided in a contact hole 150C. On the i-type semiconductor layer 16, an n-type semiconductor layer 17 is provided in accordance with the surface shape of the i-type semiconductor layer 16. In this configuration, the i-type semiconductor layer 16 has a corner portion that does not contact the p-type semiconductor layer 14. For the sake of simplicity, the pictorial representation of the second interlayer insulating film 15B and the upper electrode 18 is omitted.

In the modification examples 1 and 2, the contact hole 150C of the first interlayer insulating film 15C was formed by a two-step etching process. Specifically, one of the wall surfaces 15S2 of the contact hole 150C is shaped to have a step shape of a plurality of (two in these examples) sections in a section along a direction perpendicular to the surface of the substrate. In other words, the wall surface 15S2 is an uneven surface having one corner (convex). This first interlayer insulating film 15C is obtained by stacking an insulating film such as a SiO ₂ layer and a SiNx layer, similarly to the first interlayer insulating film 15A in the above embodiment.

Similar to the above embodiment, the i-type semiconductor layer 16 is provided so as to extend from the inside of the contact hole 150C of the first interlayer insulating film 15C to the top surface of the first interlayer insulating film 15C. Further, the i-type semiconductor layer 16 is provided along the shape of the wall surface 15S2 of the contact hole 150C and thus has a stepped structure (16S2) depending on the shape of the wall surface 15S2.

That is, in the modification examples 1 and 2, the i-type semiconductor layer 16 has a plurality of corner portions 16e1 and 16e2 associated with the wall surface shape (step shape) of the contact hole 150C. The corner portion 16e1 is equivalent to a portion corresponding to the end edge on the side of the substrate 11 and the corner portion 16e2 is a convex portion that protrudes toward the first interlayer insulating film 15C of the side surface of the i-type semiconductor layer 16. Further, it is preferable that at least one step portion of each step portion of the step shape is larger than a step portion closest to the substrate. In these examples, the stepped shape has two stepped portions s1 and s2 arranged in the order of the stepped portions s1 and s2 on the substrate side, and the stepped portion s2 is larger than the stepped portion s1. Due to this feature, the crack X is more likely to be led to the corner portion 16e2 which is further separated from the p-type semiconductor layer 14.

As in the modification example 1 (Fig. 13), the above-mentioned corner portions 16e1 and 16e2 can be formed such that only the corner portion 16e2 does not contact the p-type semiconductor layer 14 and the corner portion 16e1 contacts the p-type semiconductor layer 14. That is, the formation region of the p-type semiconductor layer 14 is larger than the lower side opening of the contact hole 150C.

Alternatively, as in the modification example 2 (Fig. 14), the corner portions 16e1 and 16e2 may not be in contact with the p-type semiconductor layer 14. That is, the formation region of the p-type semiconductor layer 14 may be smaller than the lower side opening of the contact hole 150C.

For example, the above photoelectric conversion element can be manufactured in the following manner. In the following description, the structure of the modification example 1 is taken as an example. 15A to 15C are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element according to Modification Example 1.

First, a p-type semiconductor layer 14 (the intermediate is an insulating film 13) is formed in a selected region above the substrate 11 similarly to the photoelectric conversion element of the above embodiment. Subsequently, as shown in FIG. 15A, a first interlayer insulating film is formed on the insulating film 13 by, for example, CVD, for example, SiO ₂ layer 15C1, SiNx layer 15C2, and SiO ₂ layer 15C3 are deposited in this order. 15C. For example, the film deposition is performed such that the total film thickness of the SiNx layer 15C2 and the SiO ₂ layer 15C3 is set larger than the film thickness of the SiO ₂ layer 15C1 such that the step portion s2 can become larger than the substrate side in the subsequent step. Stepped portion s1. In these layers, the SiO ₂ layer 15C3 serves as an etch stop layer in the subsequent step of patterning the i-type semiconductor layer 16 and the n-type semiconductor layer 17.

Next, as shown in FIG. 15B, the upper two insulating films (the SiO ₂ layer 15C3 and the SiNx layer 15C2) in the formed first interlayer insulating film 15C are subjected to dry etching. Next, as shown in Fig. 15C, the lowermost insulating film of the formed first interlayer insulating film 15C (SiO ₂ layer 15C1) is subjected to dry etching. Thereby, the contact hole 150C is formed. That is, in the present modification example, the contact hole 150C having the wall surface 15S2 having the above-described stepped shape is formed by the two-step etching process as described above.

Subsequently, similarly to the above embodiment, the i-type semiconductor layer 16 and the n-type semiconductor layer 17 (specifically, the second interlayer insulating film 15B and the upper electrode 18) are formed to thereby complete the photoelectric conversion element shown in FIG.

The i-type semiconductor layer 16 may have a plurality of corner portions 16e1 and 16e2 of the modified examples 1 and 2 as described above. Similar to the above embodiment, if at least one corner portion thereof does not contact the p-type semiconductor layer 14, even when a crack is generated in the i-type semiconductor layer 16, the crack may be introduced to the p-type semiconductor layer 14 Separate corners and suppress the occurrence of leak paths. Therefore, an advantageous effect equivalent to the above embodiment can be achieved. Further, the crack may be introduced to a corner portion which is separated from the p-type semiconductor layer 14 in a plurality of corner portions. This can effectively suppress the influence of cracks.

<Modification Examples 3 and 4>

Fig. 16 shows a sectional configuration of a photoelectric conversion element according to Modification Example 3. Fig. 17 shows a sectional configuration of a photoelectric conversion element according to Modification Example 4. Similarly to the photoelectric conversion element 10 of the above embodiment, the photoelectric conversion elements of the modification examples 3 and 4 have the p-type semiconductor layer 14 above the substrate 11, and have a contact hole 150A in the first interlayer insulating film 15A. The i-type semiconductor layer 24 has an n-type semiconductor layer 25 on the i-type semiconductor layer 24. Further, the wall surface 15S1 of the contact hole 150A is a flat surface.

However, unlike the above-described embodiments (and the modification examples 1 and 2), in the modification examples 3 and 4, the i-type semiconductor layer 24 is disposed in the contact hole 150A so as to be separated from the wall surface 15S1 thereof. That is, the i-type semiconductor layer 24 has a shape that does not depend on the shape of the wall surface 15S1 of the contact hole 150A, that is, the shape of the stepless structure. An n-type semiconductor layer 25 is provided on this i-type semiconductor layer 24 in accordance with the surface shape of the i-type semiconductor layer 24. Further, a protective film 26 composed of, for example, SiO _{2 is} formed so as to cover the side surfaces of the i-type semiconductor layer 24 and the n-type semiconductor layer 25. The functions and constituent materials of the i-type semiconductor layer 24 and the n-type semiconductor layer 25 are the same as those of the i-type semiconductor layer 16 and the n-type semiconductor layer 17.

In the modification examples 3 and 4, the formation regions of the p-type semiconductor layer 14 are not particularly limited. For example, as in the modification example 3, the p-type semiconductor layer 14 may be smaller than the formation region of the i-type semiconductor 24 in the surface of the substrate (FIG. 16). In this case, the i-type semiconductor layer 24 has a corner portion 24e that does not contact the p-type semiconductor layer 14.

Alternatively, as in the modification example 4, the p-type semiconductor layer 14 may be larger than the formation region of the i-type semiconductor 24 in the surface of the substrate (Fig. 17). In this case, the i-type semiconductor layer 24 does not contact the corner portion 24e of the p-type semiconductor layer 14. However, since no crack is generated, there is no problem.

For example, the above photoelectric conversion element can be manufactured in the following manner. In the following description, the structure of the modification example 3 is taken as an example. 18A to 18C are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element according to Modification Example 3.

First, similarly to the photoelectric conversion element of the above embodiment, a p-type semiconductor layer 14 is formed in a selected region above the substrate 11 (the intermediate is an insulating film 13), and then a first interlayer insulating film 15A is deposited and a contact hole is formed. 150A. Subsequently, as shown in FIG. 18A, the i-type semiconductor layer 24 and the n-type semiconductor layer 25 are deposited over the first interlayer insulating film 15A in this order by, for example, a DVD in which the contact holes 150A are filled. Next, as shown in FIG. 18B, the formed i-type semiconductor layer 24 and n-type semiconductor are formed by, for example, photolithography in which the i-type semiconductor layer 24 is separated from the wall surface 15S1 of the contact hole 150A. Layer 25 is patterned. Next, as shown in FIG. 18C, a protective film 26 is formed over the entire surface of the substrate 11. This protective film 26 is formed to fill the gap between the wall surface 15S1 and the i-type semiconductor layer 24.

Subsequently, a contact hole is formed in a region of the protective film 26 opposed to the n-type semiconductor layer 25. Finally, the upper electrode 18 is formed similarly to the above embodiment and thereby the photoelectric conversion element shown in Fig. 16 is completed.

As in the modification examples 3 and 4 described above, the i-type semiconductor layer 24 can be provided in the contact hole 150A to be separated from the wall surface 15S1. Due to this feature, the i-type semiconductor layer 24 does not have a stepped structure as described above and thus can suppress a crack from occurring itself. Therefore, a leak path can be suppressed and an advantageous effect almost equivalent to the above embodiment can be achieved.

An application example of a photoelectric conversion device 2 (radiation imaging device 1) as one of the photoelectric conversion elements described in the above embodiment and modification examples 1 to 4 will be described below. However, the application example of the above photoelectric conversion element is not limited to this radiation imaging device and the photoelectric conversion element can also be applied to, for example, an optical touch sensor (touch panel). As an example, the following description will be made with the photoelectric conversion element 10 described in the above embodiment as a representative of the above several photoelectric conversion elements.

[Configuration of photoelectric conversion device 2]

Fig. 19 shows a system configuration of the photoelectric conversion device 2 in the radiation imaging device 1 according to the application example. The radiation imaging apparatus 1 (Fig. 20) is obtained by providing a wavelength converter 40 on the photoelectric conversion device 2. It performs wavelength conversion of radiation represented by α rays, β rays, γ rays, and X rays and reads information based on the radiation.

The wavelength converter 40 performs the wavelength conversion of the above-described radiation to the sensitivity region of the photoelectric conversion device 2. Wavelength converter 40 converts radiation, such as X-rays, into, for example, a fluorescent body (eg, a scintillator) of visible light. Specifically, it is obtained by forming, for example, a fluorescent film of one of CsI, NaI or CaF2 on the top surface of one of the planarizing films formed of an organic planarizing film or, for example, a spin-on glass material. One of the components.

The photoelectric conversion device 2 has a pixel unit 112 on a substrate 11. A peripheral circuit portion (driving portion) composed of, for example, a column of scanning units (vertical drivers) 113, a horizontal selector 114, a row of scanning units (horizontal drivers) 115, and a system controller 116 is provided around the pixel unit 112.

In the pixel unit 112, a unit pixel 20 (hereinafter, simply referred to as a "pixel") each having a photo-electric transducer that generates photocharges having a charge amount depending on the amount of incident light and internally accumulating photocharges is two-dimensionally configured as a matrix. The photoelectric transducer included in this unit pixel 20 is equivalent to the photoelectric conversion element 10 and the like of the above embodiment. In the unit pixel 20, for example, two interconnections (specifically, a column selection line and a reset control line) are provided for each pixel column as one of the pixel drive lines 117 which will be described later.

In the pixel unit 112, for the matrix pixel arrangement, the pixel driving lines 117 are provided for each pixel column along the column direction (the arrangement direction of the pixels on the pixel columns) and along the row direction (the arrangement direction of the pixels on the pixel rows) is Each pixel row provides a vertical signal line 118. The pixel drive line 117 transmits a drive signal for reading out signals from the pixels. In Figure 19, pixel drive lines 117 are shown as one interconnect per column. However, the number of pixel drive lines 117 of each column is not limited to one. One of the ends of each of the pixel drive lines 117 is connected to an output terminal of the column scanning unit 113 corresponding to one of the columns.

Column scan unit 113 is configured to have a shift register, a bit address decoder, etc. and to drive, for example, one of the respective pixels of pixel unit 112 on a column by column basis. The signals output from the respective unit pixels on the pixel columns selectively scanned by the column scanning unit 113 are supplied to the horizontal selector 114 via the respective vertical signal lines 118. The horizontal selector 114 is configured to have one of the amplifiers, a horizontal selection switch, and the like provided for each of the vertical signal lines 118.

Row scan unit 115 is configured to have a shift register, a bit address decoder, etc. and scan and sequentially drive respective horizontal select switches of horizontal selector 114. By this selective scanning of the row scanning unit 115, the signals of the respective pixels transmitted via the respective vertical signal lines 118 are sequentially outputted to a horizontal signal line 119 and transmitted to the outside of the substrate 11 via the horizontal signal line 119.

The circuit portion composed of the column scanning unit 113, the horizontal selector 114, the row scanning unit 115, and the horizontal signal line 119 is configured by using one or both of the circuits formed on the substrate 11 and one of the external control ICs. Alternatively, the circuit portion may be formed on another substrate that is connected to the substrate 11 by a cable or the like.

The system controller 116 receives a data given from the outside of the substrate 11, a data of a command operation mode, and the like, and outputs information of external information of the photoelectric conversion device 2 and the like. In addition, the system controller 116 has a timing generator that generates various types of timing signals and controls the column-containing scanning unit 113, the horizontal selector 114, based on various types of timing signals generated by the timing generator. The driving of the peripheral circuit portion of the row scanning unit 115 and the like.

(Configuration of unit pixel 20)

In the unit pixel 20, a pixel transistor such as a reset transistor, a read transistor, and a column selection transistor is provided together with the photoelectric conversion element 10. These pixel transistors are each, for example, an N-channel field effect transistor and use a germanium-based semiconductor such as microcrystalline germanium or polysilicon. Alternatively, an oxide semiconductor such as indium gallium zinc oxide (InGaZnO) or zinc oxide (ZnO) may be used.

FIG. 21 shows a cross-sectional structure of this unit pixel 20. As shown in FIG. 21, in the unit pixel 20, a photoelectric transducer 20A as one of the photoelectric conversion elements 10 and a transistor portion 20B composed of a readout transistor or the like are formed over the same substrate 11. Further, the insulating film 13, the first interlayer insulating film 15A, and the second interlayer insulating film 15B are also used as a common layer shared by the photoelectric transducer 20A and the transistor portion 20B.

The transistor portion 20B has a structure between the substrate 11 and the insulating film 13 (gate insulating film), for example, titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W) or chromium (Cr). One of the gate electrodes 12 is formed. On the insulating film 13, a semiconductor layer 19 including, for example, a p+ region, an i region, and an n+ region is formed. Further, lightly doped drain electrodes (LDD) 19a and 19b are provided in the semiconductor layer 19 to reduce leakage current. The semiconductor layer 19 is composed of, for example, microcrystalline germanium or polycrystalline germanium. The semiconductor layer 19 is connected to an interconnect layer 21 comprising one of the interconnects for reading one of the signal lines and various types. In the same layer as the interconnect layer 21, an extraction electrode 18a connected to one of the electrodes 18 above the photoelectric transducer 20A is provided. These interconnect layers 21 and extraction electrodes 18a are composed of, for example, Ti, Al, Mo, W or Cr.

The disclosure has been described above based on the examples and modification examples. However, the present disclosure is not limited to the above embodiments and the like and various modifications can be made. For example, in the above-described embodiment and the like, the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked from the substrate side in this order. However, the semiconductor layer may be stacked in the order of the n-type semiconductor layer, the i-type semiconductor layer, and the p-type semiconductor layer from the substrate side.

Further, in the above modification examples 1 and 2, a structure in which the wall surface of the contact hole has one of two stepped portions is taken as an example. However, the number of step portions may be three or more. That is, one step shape having one or three or more levels can be formed by performing three or more steps of etching while forming the contact holes. Further, in this case, the contact holes are formed such that at least a stepped portion larger than the stepped portion closest to the substrate is formed.

Furthermore, it is not necessary to include all of the respective layers described for the above-described embodiments and the like and may instead comprise another layer. For example, a protective film composed of, for example, SiN may be further formed on the upper electrode 18.

The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application No. 2010-179555, filed on Jan.

1. . . Radiation imaging device

2. . . Photoelectric conversion device

10. . . Photoelectric conversion element

11. . . Substrate

12. . . Gate electrode

13. . . Insulating film

13a. . . SiNx layer

13b. . . SiO ₂ layer

14. . . P-type semiconductor layer

14A. . . Amorphous germanium (α-Si) layer

14B. . . Polycrystalline germanium (p-Si) layer

15A. . . First interlayer insulating film

15A1. . . SiO ₂ layer

15A2. . . SiNx layer

15A3. . . SiO ₂ layer

15B. . . Second interlayer insulating film

15C. . . First interlayer insulating film

15C1. . . SiO ₂ layer

15C2. . . SiNx layer

15C3. . . SiO ₂ layer

15S1. . . Wall surface

15S2. . . Wall surface

16. . . I-type semiconductor layer

16e. . . Corner section

16e1. . . Corner section

16e2. . . Corner section

16h. . . Lower extraction interconnect

16S1. . . Step structure

16S2. . . Step structure

17. . . N-type semiconductor layer

18. . . Upper electrode

18a. . . Extraction electrode

19. . . Semiconductor layer

19a. . . Lightly doped bungee (LDD)

19b. . . Lightly doped bungee (LDD)

20. . . Unit pixel

20A. . . Photoelectric converter

20B. . . Part of the transistor

twenty one. . . Interconnect layer

twenty four. . . I-type semiconductor layer

24e. . . Corner section

25. . . N-type semiconductor layer

26. . . Protective film

40. . . Wavelength converter

100. . . Photoelectric conversion element

101. . . Substrate

103. . . Insulating film

104. . . P-type semiconductor layer

105A. . . First interlayer insulating film

106. . . I-type semiconductor layer

106S. . . Class

107. . . N-type semiconductor layer

109A. . . Contact hole

112. . . Pixel unit

113. . . Column scanning unit

114. . . Horizontal selector

115. . . Line scanning unit (horizontal drive)

116. . . System controller

117. . . Pixel drive line

118. . . Vertical signal line

119. . . Horizontal signal line

150A. . . Contact hole

150B. . . Contact hole

150C. . . Contact hole

A-A'. . . line

B-B'. . . line

Da. . . width

Db. . . width

L. . . laser

P1. . . Predetermined location

S1. . . Stepped part

S2. . . Stepped part

X. . . crack

1 is a cross-sectional view showing a configuration of a photoelectric conversion element according to an embodiment of the present disclosure;

2 is a schematic view showing a planar configuration of a p-type semiconductor layer, an i-type semiconductor layer (n-type semiconductor layer), and a hole portion of the photoelectric conversion element shown in FIG. 1;

Figure 3 is a cross-sectional view showing the configuration of the photoelectric conversion element along the line BB' shown in Figure 2;

4A to 4C are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element shown in Fig. 1;

5A to 5C are cross-sectional views showing subsequent steps of FIGS. 4A to 4C;

6A to 6B are cross-sectional views showing subsequent steps of Figs. 5A to 5C;

7A-7B are cross-sectional views showing subsequent steps of FIGS. 6A and 6B;

8A to 8B are cross-sectional views showing subsequent steps of Figs. 7A and 7B;

9 is a schematic view showing a planar configuration of a p-type semiconductor layer, an i-type semiconductor layer (n-type semiconductor layer), and a hole portion according to a comparative example;

10A and 10B show a cross-sectional configuration of the photoelectric conversion element shown in FIG. 9: FIG. 10A is a cross-sectional view taken along line AA' and FIG. 10B is a cross-sectional view taken along line BB';

11A and 11B are schematic views for explaining one of the cracks generated in the i-type semiconductor layer: FIG. 11A shows a comparative example and FIG. 11B shows an embodiment;

Figure 12 is a photograph of one of the cracks generated in the i-type semiconductor layer;

Figure 13 is a cross-sectional view showing the configuration of a photoelectric conversion element according to Modification Example 1;

Figure 14 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Modification Example 2;

15A to 15C are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element shown in Fig. 13;

Figure 16 is a cross-sectional view showing the configuration of a photoelectric conversion element according to Modification Example 3;

Figure 17 is a cross-sectional view showing the configuration of a photoelectric conversion element according to Modification Example 4;

18A to 18C are cross-sectional views for explaining a method of manufacturing the photoelectric conversion element shown in Fig. 16;

Figure 19 is a system configuration diagram of a photoelectric conversion device according to an application example;

20 is a schematic view showing one of radiation imaging devices fabricated by combining a photoelectric conversion device and a wavelength converter; and

Figure 21 is a cross-sectional view showing one of the configuration of one unit pixel of the same transistor.

10. . . Photoelectric conversion element

11. . . Substrate

13. . . Insulating film

13a. . . SiNx layer

13b. . . SiO ₂ layer

14. . . P-type semiconductor layer

15A. . . First interlayer insulating film

15A1. . . SiO ₂ layer

15A2. . . SiNx layer

15A3. . . SiO ₂ layer

15B. . . Second interlayer insulating film

15S1. . . Wall surface

16. . . I-type semiconductor layer

16e. . . Corner section

16S1. . . Step structure

17. . . N-type semiconductor layer

18. . . Upper electrode

150A. . . Contact hole

Da. . . width

Db. . . width

P1. . . Predetermined location

Claims (15)

A photoelectric conversion element comprising: a first semiconductor layer (i) configured to exhibit a first conductivity type, (ii) disposed above a substrate, and (iii) configured to function as a An electrode operable to read a signal charge; a second semiconductor layer (i) configured to exhibit a second conductivity type and (ii) disposed opposite the first semiconductor layer; And a third semiconductor layer (i) disposed between the first semiconductor layer and the second semiconductor layer, (ii) configured to exhibit a substantially intrinsic conductivity type, and (iii) having no Contacting at least one corner portion of the first semiconductor layer, wherein the first semiconductor layer is embedded in the third semiconductor layer such that one of the first semiconductor layers facing away from the second semiconductor layer The lowest surface is coplanar with the lowest surface of one of the third semiconductor layers that also faces away from the second semiconductor layer. The photoelectric conversion element of claim 1, further comprising: an interlayer insulating film configured to have a via hole opposite to the first semiconductor layer and provided over the substrate, wherein: the third semiconductor layer Extending from one of the through holes to a top surface of one of the interlayer insulating films and having a stepped structure depending on the shape of one of the wall surfaces of the through hole. The photoelectric conversion element of claim 2, wherein: a surface of the third semiconductor layer on one side of the interlayer insulating film Flat, and the corner portion is one end edge portion of the third semiconductor layer on one side of the substrate. The photoelectric conversion element of claim 2, wherein: one of the openings on one side of the substrate is provided to form a region around one of the first semiconductor layers in a direction along a surface of a substrate. The photoelectric conversion element of claim 2, wherein: a surface shape of one of the third semiconductor layers on one side of the interlayer insulating film is a stepped shape in a section along a direction perpendicular to a surface of a substrate, and The corner portion is one end edge portion of the third semiconductor layer on one side of the substrate or a protruding portion protruding toward the side of the interlayer insulating film. The photoelectric conversion element of claim 5, wherein: at least a stepped portion of the plurality of stepped portions of the stepped shape is larger than a stepped portion closest to the substrate. The photoelectric conversion element of claim 1, further comprising: an interlayer insulating film configured to have a via hole opposite to the first semiconductor layer and provided over the substrate, wherein: the third semiconductor layer A hole is provided in the through hole to be separated from a wall surface of the through hole. The photoelectric conversion element of claim 1, wherein: The photoelectric conversion element is a positive-essential-negative photodiode. A method for fabricating a photoelectric conversion element, the method comprising: forming a first semiconductor layer exhibiting a first conductivity type in a selected region above a substrate; forming a third on the first semiconductor layer a semiconductor layer having a contact with at least one corner portion of the first semiconductor layer and exhibiting a substantially intrinsic conductivity type; and forming a second conductivity type on the third semiconductor layer a second semiconductor layer, wherein the first semiconductor layer is embedded in the third semiconductor layer such that a lower surface of the first semiconductor layer facing away from the second semiconductor layer and the back side of the second semiconductor layer The lowest surface of one of the third semiconductor layers is coplanar. A method for manufacturing a photoelectric conversion element according to claim 9, the method further comprising: forming a first semiconductor layer over the substrate after the first semiconductor layer is formed and before the third semiconductor layer is formed An interlayer insulating film of one of the via holes, wherein: when a third semiconductor layer is formed, the third semiconductor layer is formed to extend from inside one of the via holes to a top surface of the interlayer insulating film. A method for manufacturing a photoelectric conversion element according to claim 10, wherein: when an interlayer insulating film is formed, the via hole is etched by one step The program is formed such that one of the wall surfaces of the through hole is a flat surface. A method for manufacturing a photoelectric conversion element according to claim 10, wherein: the through hole is formed such that one of the through holes on one side of the substrate surrounds the first one in a direction along a surface of a substrate One of the semiconductor layers is formed outside of one of the regions. A method for manufacturing a photoelectric conversion element according to claim 10, wherein: in forming an interlayer insulating film, the via hole is formed by a two-step or multi-step etching process such that a shape of a wall surface of the one via hole It is a step shape. A method for manufacturing a photoelectric conversion element according to claim 13, wherein: the through hole is formed such that at least a stepped portion of the plurality of stepped portions in the stepped shape is larger than a stepped portion closest to the substrate . A method for manufacturing a photoelectric conversion element according to claim 9, the method further comprising: forming a first semiconductor layer over the substrate after the first semiconductor layer is formed and before the third semiconductor layer is formed An interlayer insulating film of one of the through holes, wherein: when a third semiconductor layer is formed, the third semiconductor layer is formed in the through hole of the interlayer insulating film to be separated from a wall surface of the through hole.