JP2012009652A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device in which desensitization incident to microfabrication of pixel cells can be minimized, and to provide a method of manufacturing the same.SOLUTION: The solid-state imaging device comprises a first conductivity type semiconductor layer 1, and a charge storage area 7 consisting of a second conductivity type impurity area. A detection part 8 consisting of a second conductivity type impurity area to which signal charges accumulated in a charge accumulation area are transferred is provided, corresponding to the charge storage area 7, in the semiconductor layer 1 while spaced apart from the charge storage area 7. Furthermore, a transfer gate electrode 5 is provided on the surface of the semiconductor layer 1 to overlap the charge storage area 7 with an insulating film 4 interposed therebetween, and at least a part of the overlapping portion consists of a transparent conductor having transmissivity for visible light.

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  In recent years, in response to a demand for higher image quality, the number of pixels in a solid-state imaging device has been increased. However, with the miniaturization of the pixel cells accompanying the increase in the number of pixels, the light receiving area (photoelectric conversion area) of each pixel cell is reduced, and the amount of light incident on the light receiving area is reduced. For this reason, there is a problem of sensitivity reduction such as an image becoming dark or a signal-to-noise ratio (S / N ratio) being deteriorated, and a technique for solving such sensitivity reduction is required.

  Conventionally, polysilicon is used as a gate electrode material such as a reading transistor that transfers signal charges generated in the light receiving region of each pixel cell to a detection unit (floating diffusion) (see, for example, Patent Document 1). Since polysilicon absorbs much visible light, the region where the gate electrode is disposed in the pixel cell cannot function as a light receiving region. In this type of solid-state imaging device, it is possible to suppress the above-described reduction in sensitivity by further reducing the gate dimension to reduce the gate electrode arrangement area in the pixel cell and increase the light receiving area. .

JP-A-11-274461

  However, for example, when the gate size of the read transistor is reduced, the signal charge read characteristic is deteriorated. FIG. 8 is a diagram for explaining the deterioration of the read characteristics. FIG. 8A is a cross-sectional view schematically showing a pixel cell in which the gate length of the read transistor is large, and FIG. 8B is a view in which the gate length of the read transistor is smaller than that in FIG. It is sectional drawing which shows a pixel cell typically.

  As shown in FIGS. 8A and 8B, each pixel cell is formed in a region separated by element isolation 102 on the surface portion of the semiconductor substrate 100. Each pixel cell includes a photodiode 120 which is a light receiving region, a floating diffusion 108, and a gate electrode 105 of a reading transistor. In the following description, when distinguishing the gate electrode 105 of each pixel cell, the gate electrode 105 having the long gate length of the pixel cell in FIG. 8A is referred to as a gate electrode 105a, and the pixel cell in FIG. The gate electrode 105 having a short gate length is referred to as a gate electrode 105b.

  In this example, the photodiode 120 and the floating diffusion 108 are formed in the P-type well 101. The photodiode 120 has a buried structure in which a P-type impurity region 106 is formed on the surface portion of the N-type impurity region 107. The N-type impurity region 107 is also in contact with a P-type impurity region 103 formed around the element isolation 102. The N-type impurity region 107 constitutes a source region of a reading transistor including the reading gate electrode 105. The floating diffusion 108 forms a drain region of the reading transistor.

  This pixel cell transfers the signal charge (electrons) generated and accumulated in the photodiode 120 to the floating diffusion 108 by turning on the reading transistor. A pixel signal is output by reading the potential of the floating diffusion 108 to which the signal charge has been transferred through, for example, an amplification transistor (not shown).

  In the pixel cell of FIG. 8B, the N-type impurity region 107 is expanded toward the floating diffusion 108 by the amount that the gate length of the gate electrode 105 is smaller than that of the pixel cell of FIG. Yes.

  In the configuration shown in FIG. 8B, the light receiving region is larger than the configuration shown in FIG. 8A, but the distance between the N-type impurity region 107 and the floating diffusion 108 is shortened. Therefore, in the configuration shown in FIG. 8B, signal charge punch-through is likely to occur. That is, a punch-through phenomenon in which the signal charge moves from the N-type impurity region 107 to the floating diffusion 108 is likely to occur regardless of whether the reading transistor is on or off. A pixel signal output in a situation where such a punch-through phenomenon has occurred cannot be said to be a normal value. In FIGS. 8A and 8B, such an electron movement path is schematically indicated by an arrow.

  For the above reasons, in a recent solid-state imaging device in which the gate length has been shortened, it is not possible to employ a method of further reducing the gate electrode region in the pixel cell and increasing the light receiving region.

  In FIGS. 9A and 9B, a potential for turning on the readout transistor is applied to the gate electrode 105 of the pixel cell shown in FIGS. 8A and 8B, respectively. It is a figure which shows potential distribution (this potential line) in a case. Note that arrows Ap and Bp indicated by dotted lines in FIGS. 9A and 9B schematically indicate electron readout paths. In addition, arrows Aw and Bw indicated by solid lines schematically indicate the width of the electron readout path.

  As can be understood from FIGS. 9A and 9B, the width Bw of the readout path of the pixel cell having a small gate length is narrower than the width Aw of the readout path of the pixel cell having a large gate length. . When the width of the read path is narrowed, the charge transfer efficiency is lowered. Therefore, the signal charge accumulated in the N-type impurity region 107 is reduced within a predetermined time during which a predetermined potential for reading signal charges is applied to the read gate electrode 105. There is a possibility that signal charges remain in the N-type impurity region 107 because the data cannot be completely read out to the floating diffusion 108. A pixel signal output in a situation where such signal charge remains is not a normal value. Further, in order to prevent such signal charge from remaining, it is necessary to apply a large potential to the read gate electrode 105 when reading the signal charge.

  The present invention has been made in view of such a conventional problem, and can suppress a decrease in sensitivity even when a pixel cell is miniaturized, and also suppress a deterioration in readout characteristics. It is an object of the present invention to provide a solid-state imaging device capable of performing the same and a manufacturing method thereof.

  In order to solve the above-described problems, the present invention employs the following technical means. That is, the present invention is a solid-state imaging device including a plurality of charge accumulation regions for converting incident light into signal charges and accumulating the first conductivity type semiconductor layer and the second conductivity provided in the semiconductor layer. And a charge storage region composed of a type impurity region. In addition, a detection unit including a second conductivity type impurity region to which the signal charge accumulated in the charge accumulation region is transferred is provided in the semiconductor layer at a distance from the charge accumulation region corresponding to the charge accumulation region. ing. The solid-state imaging device according to the present invention is provided on the surface of the semiconductor layer via an insulating film so as to overlap with the charge accumulation region, and at least a part of the overlapping portion is transparent to visible light. A transfer gate electrode made of a transparent conductor. The transfer gate electrode controls the transfer of the signal charge accumulated in the charge accumulation region to the detection unit.

  On the other hand, from another viewpoint, the present invention can also provide a method for manufacturing a solid-state imaging device suitable for realizing the solid-state imaging device. That is, the method for manufacturing a solid-state imaging device according to the present invention includes a step of forming a charge accumulation region including a second conductivity type impurity region in the first conductivity type semiconductor layer. The surface of the semiconductor layer on which the charge accumulation region is formed is a transfer made of a transparent conductor in which at least a part of the overlap portion is transparent to visible light in a state where it overlaps a part of the charge accumulation region A gate electrode is formed via an insulating film. Also, in the method of manufacturing the solid-state imaging device according to the present invention, the semiconductor layer includes the impurity region of the second conductivity type corresponding to the charge accumulation region, and the signal charge accumulated in the charge accumulation region is transferred to the transfer gate electrode. A step of forming the detection portion transferred by the step with a distance from the charge storage region.

  According to the present invention, it is possible to achieve both suppression of punch-through and suppression of sensitivity reduction in a fine pixel cell. Furthermore, since the gate length of the transfer gate electrode functioning as the gate electrode of the reading transistor can be made relatively large, it is possible to suppress deterioration of the signal charge reading characteristics.

Sectional drawing which shows the principal part of the solid-state imaging device of one Embodiment of this invention The top view which shows the principal part of the solid-state imaging device of one Embodiment of this invention Schematic diagram showing the state of photoelectric conversion in the solid-state imaging device of one embodiment of the present invention and a conventional solid-state imaging device Process sectional drawing which shows the manufacture process of the solid-state imaging device in one Embodiment of this invention Process sectional drawing which shows the manufacture process of the solid-state imaging device in one Embodiment of this invention Sectional drawing which shows the principal part of the modification of the solid-state imaging device of one Embodiment of this invention Sectional drawing which shows the principal part of the modification of the solid-state imaging device of one Embodiment of this invention Figure showing the relationship between charge readout characteristics degradation and gate length Diagram showing the relationship between potential distribution and gate length during charge readout

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied as a MOS (Metal Oxide Semiconductor) type solid-state imaging device including a photodiode and an N-channel type readout transistor, that is, a MOS type solid-state imaging device whose signal charge is an electron. . In the following embodiments, the same effect can be obtained even if the conductivity type of each impurity region is reversed.

  First, the configuration of a solid-state imaging device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram illustrating a main part of the solid-state imaging device according to the present embodiment, and FIG. 2 is a plan view illustrating a main part of the solid-state imaging device according to the present embodiment. The solid-state imaging device of the present embodiment has a pixel region in which a plurality of pixel cells are arranged in an array, and FIGS. 1 and 2 show one pixel cell constituting the pixel region. In the plan view shown in FIG. 2, the charge storage region, the detection unit, the well region between them, and the transfer gate electrode are shown, and the other elements are not shown. Moreover, the cross section along the AA line shown in FIG. 2 corresponds to FIG.

  As shown in FIG. 1, the solid-state imaging device of this embodiment includes a semiconductor substrate 10 made of an N-type silicon single crystal substrate or the like provided with a well region 1 (semiconductor layer) made of a P-type impurity region on the surface. Formed. Each pixel cell is separated from other adjacent pixel cells by element isolation 2 having an STI (Shallow Trench Isolation) structure.

  Each pixel cell includes a photodiode 20. The photodiode 20 has a buried structure in which a P-type impurity region 6 (surface defect suppression region) is formed on the surface portion of an N-type impurity region 7 (charge storage region) that converts incident light into signal charges and accumulates them. . The N-type impurity region 7 is in contact with the P-type impurity region 3 formed in the semiconductor substrate 10 around the element isolation 2 in a state of surrounding the element isolation 2. P-type impurity region 3 is also in contact with P-type impurity region 6, and P-type impurity region 3 and P-type impurity region 6 are electrically connected. The P-type impurity region 6 functions as a defect suppression region that prevents unnecessary charges generated due to surface defects or the like from accumulating in the N-type impurity region 7 on the surface of the semiconductor substrate 10. The region 3 functions as a defect suppression region that prevents unnecessary charges generated due to lattice defects or the like from accumulating in the N-type impurity region 7 at the interface of the STI structure (trench).

  The well region 1 is provided with a floating diffusion 8 (detection unit) corresponding to the N-type impurity region 7 and spaced from the N-type impurity region 7. A gate electrode 5 (transfer gate electrode) is disposed on the surface of the well region 1 between the N-type impurity region 7 and the floating diffusion 8 via a transparent gate insulating film 4 made of a silicon oxide film or the like. As shown in FIG. 1, the P-type impurity region 6 is formed on the surface of an N-type impurity region 7 exposed between the gate electrode 5 and the element isolation 2, and the N-type impurity region 7 is formed on the gate electrode. It is extended to just under 5. That is, as shown in FIGS. 1 and 2, the gate electrode 5 and the N-type impurity region 7 are arranged so that at least a part thereof overlaps in plan view. As shown in FIG. 2, the N-type impurity region 7 has a substantially rectangular planar shape, and the gate electrode 5 is arranged at one corner of the rectangle. Note that the gate electrode 5, the N-type impurity region 7, and the floating diffusion 8 constitute an N-channel transistor that functions as the reading transistor 30.

  This pixel cell transfers the signal charge (here, electrons) generated and accumulated in the N-type impurity region 7 to the floating diffusion 8 by bringing the readout transistor 30 into a conductive state. The potential of the floating diffusion 8 to which the signal charge has been transferred is read out as a pixel signal via an amplification transistor (not shown), for example. A reset transistor (not shown) is connected to the floating diffusion 8, and the charge flowing into the floating diffusion 8 is discharged by turning on the reset transistor.

  In the present embodiment, the gate electrode 5 is made of a transparent conductor that is transparent to visible light. For this reason, when visible light reaches the gate electrode 5, the visible light passes through the gate electrode 5 and enters the N-type impurity region 7. Therefore, signal charges corresponding to incident light are also generated in the N-type impurity region 7 immediately below the gate electrode 5. As the transparent conductor constituting the gate electrode 5, for example, indium tin oxide (hereinafter simply referred to as ITO), zinc oxide, indium oxide, tin oxide, indium oxide and zinc oxide are used. A transparent material composed of magnesium hydroxide and carbon, a titanium dioxide-based transparent material, a conductive transparent resin, a conductive transparent organic compound, and the like can be used. The visible light transmittance of the transparent conductor is preferably 80% or more. In the present embodiment, “transparent” means a visible light transmittance equivalent to that of the transparent conductor.

  A light shielding film 12 made of tungsten, aluminum, or the like is disposed above the gate electrode 5 via a transparent insulating film 11 made of a silicon oxide film or the like. The light shielding film 12 has a function of covering a region excluding the photodiode 20 (light receiving region), such as the well diffusion 1 immediately below the floating diffusion 8 and the gate electrode 5, and preventing unnecessary light from entering the covered region. . As shown in FIG. 1, in the present embodiment, a structure in which the end portion of the light shielding film 12 on the photodiode 20 side coincides with the end portion of the N-type impurity region 7 on the floating diffusion 8 side in plan view is employed. . As will be described later, in the present embodiment, a structure in which an optical waveguide is disposed on the photodiode 20 to improve the light condensing property to the photodiode 20 is employed. It is possible to suppress the entry to a level where there is no practical problem. A transparent flattening film 13 made of boron phosphorus silicate glass (BPSG) or the like is provided on the light shielding film 12, and unevenness caused by the gate electrode 5, the light shielding film 12, wiring not shown, etc. is flattened. .

  An opening 19 is provided in the transparent planarization film 13 on the photodiode 20, and a low refractive index transparent film 14 is laminated on the entire surface including the opening 19. The opening 19 covered with the low refractive index transparent film 14 is filled with the high refractive index transparent film 15. The low refractive index transparent film 14 may be any transparent material having a refractive index lower than that of the high refractive index transparent film 15, and the high refractive index transparent film 15 is transparent having a refractive index higher than that of the low refractive index transparent film 14. Any material can be used. For example, a silicon oxynitride film (SiON) having a refractive index of about 1.6 is used as the low refractive index transparent film 14, and a silicon nitride film (SiNx) having a refractive index of about 2.0 is used as the high refractive index transparent film 15. ) Can be used.

  Thus, the structure in which the high refractive index transparent film 15 is surrounded by the low refractive index transparent film 14 functions as an optical waveguide for guiding incident light to the photodiode 20. Although not particularly limited, in this embodiment, the opening 19 has an opening area that is narrower from the upper end toward the bottom. Thus, by providing the side wall of the opening 19 with a taper, leakage of incident light to the outside of the optical waveguide is suppressed. Although the opening shape of the opening part 19 is not specifically limited, In this embodiment, as shown in FIG. 2, it is a regular octagon shape. In this example, the center of the regular octagon overlaps the center of the N-type impurity region 7 (intersection of the bisector of the long side Ld and the bisector of the short side Wd of the N-type impurity region 7). Is arranged. In FIG. 2, the opening shape at the bottom of the opening 19 is indicated by a dotted line.

  In the example shown in FIG. 1, a color filter layer 16 including a filter portion 16a of a desired color is disposed on the optical waveguide on the upper surface of the structure. The filter portion 16a is made of, for example, a transparent polymer resin colored in red, blue, or green. On the filter part 16a, an on-chip lens 17 made of a transparent polymer resin such as an acrylic resin is provided. In order to suppress reflection of incident light at the interface between the layers, the refractive index of the filter portion 16a is preferably equal to or lower than the refractive index of the high refractive index transparent film 15 (for example, about 1.55), and The refractive index of the on-chip lens 17 is preferably equal to or lower than the refractive index of the filter portion 16a (for example, about 1.5). Further, in the configuration illustrated in FIG. 1, the low refractive index transparent film 14 can be omitted by making the refractive index of the transparent planarizing film 13 lower than the refractive index of the high refractive index transparent film 15.

  FIG. 3 shows the above-described solid-state imaging device of the present embodiment and a conventional solid-state imaging device that employs a non-transparent material having absorptivity (or light shielding property) such as polysilicon as a gate electrode material of a reading transistor. It is a schematic diagram which shows the mode of photoelectric conversion. 3A corresponds to the solid-state imaging device of the present embodiment, and FIG. 3B corresponds to a conventional solid-state imaging device. FIGS. 3A and 3B show a source-drain connection as shown in FIG. 8A in order to avoid punch-through due to a reduction in the distance between the source and drain of the reading transistor. It corresponds to the state where the distance is expanded (the gate length is also expanded). 3A and 3B, only the material of the gate electrode is different, and the other structures are the same. 3A and 3B, for the sake of explanation, a P-type impurity region functioning as a defect suppression region at the gate electrode, element isolation, and element isolation interface and an N-type impurity region of the photodiode are illustrated. ing. The circles with “-” shown in FIG. 3A and FIG. 3B schematically show signal charges.

  As shown in FIG. 3B, in a conventional solid-state imaging device including a gate electrode 105 made of a non-transparent material, incident light is absorbed (or shielded) by the gate electrode 105. Therefore, the effective light receiving region becomes narrow due to the increase in the gate length accompanying the increase in the distance between the source and the drain, and the photoelectric conversion efficiency is lowered. On the other hand, in the solid-state imaging device of this embodiment, as shown in FIG. 3A, incident light is transmitted through the gate electrode 5 and enters the N-type impurity region 7. Therefore, even when the gate length is increased as the source-drain distance is increased, the effective light receiving region is not narrowed and the photoelectric conversion efficiency is not lowered. That is, in the structure of the present embodiment, in the photodiode having the embedded structure, it has been extended to just below the gate electrode in order to improve the signal charge read characteristic, and has not conventionally contributed to the generation of the signal charge. It becomes possible to cause the portion of the N-type impurity region 7 to function as a photoelectric conversion region.

  As described above, in the pixel cell of the solid-state imaging device according to the present embodiment, the gate electrode 5 that transfers signal charges from the N-type impurity region 7 to the floating diffusion 8 is formed of the transparent conductor, and the gate electrode 5 is N-type. The structure overlaps at least part of the impurity region 7. In this structure, light can enter the N-type impurity region 7 directly below the gate electrode 5 through the gate electrode 5, so that the region immediately below the gate electrode 5 can also function as a photoelectric conversion region, unlike the conventional solid-state imaging device. That is, unlike the conventional solid-state imaging device using polysilicon or the like as the gate electrode, it is not necessary to reduce the gate length of the reading transistor in order to increase the light receiving region. Therefore, it is not necessary to reduce the distance between the source and the drain of the reading transistor in accordance with the reduction in the gate length, and it is not necessary to employ a fine source-drain interval that causes punch-through. As a result, punch-through suppression and sensitivity reduction suppression can both be achieved in a fine pixel cell.

  In the above-described structure, the gate length of the gate electrode 5 of the read transistor 30 can be made relatively large, so that the signal charge read path can be expanded and deterioration of the signal charge read characteristics can be suppressed. (See FIG. 9). Furthermore, when realizing the same cell size and the same light receiving region area as the conventional structure, a gate electrode having a longer gate length can be adopted compared to the conventional structure. There is no need to make it bigger.

  Next, a method for manufacturing a solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to the drawings. 4 and 5 are cross-sectional views showing the manufacturing process of the solid-state imaging device according to the embodiment of the present invention.

In the manufacturing process of the solid-state imaging device of this embodiment, as shown in FIG. 4A, first, ion implantation is performed through a mask having an opening in a charge accumulation region formation region, thereby forming an N-type semiconductor substrate 10. Impurities are introduced. As a result, an N-type impurity region 7 having an impurity concentration of about 1.0 × 10 ¹⁷ cm ⁻³ and a depth of about 100 to 300 nm is formed. Although not particularly limited, arsenic is ion-implanted here under an implantation condition of an implantation energy of 160 keV to 800 keV and a dose of 1.0 × 10 ¹² cm ^{−2 to} 8.0 × 10 ¹² cm ^−2. ing. Here, the semiconductor substrate 10 is made of an N-type silicon single crystal substrate having an impurity concentration of about 1.0 × 10 ¹⁴ cm ⁻³ .

Next, as shown in FIG. 4B, element isolation 2 is formed on the surface portion of the semiconductor substrate 10 by a known method. The element isolation 2 can be formed by filling a trench having a depth of about 150 to 250 nm with an insulating film such as a silicon oxide film. In this embodiment, ion implantation is performed through a mask having an opening in a portion corresponding to the trench after the trench is formed in the surface portion of the semiconductor substrate 10 until the trench is filled with the silicon oxide film. By carrying out, P-type impurities are introduced into the semiconductor substrate 10 constituting the side and bottom surfaces of the trench. Thereby, the P-type impurity region 3 having an impurity concentration of about 1.0 × 10 ¹⁷ cm ⁻³ and a depth of about 10 to ²⁰ nm is formed. Here, boron is ion-implanted under implantation conditions of an implantation energy of 10 keV or more and 20 keV or less, and a dose amount of 3.0 × 10 ¹³ cm ⁻² or more and 8.0 × 10 ¹³ cm ⁻² or less. After the element isolation 2 is formed, ion implantation of boron or the like is performed on the semiconductor substrate 10 to form the well region 2 having an impurity concentration of about 1.0 × 10 ¹⁵ cm ⁻³ .

  Subsequently, as shown in FIG. 4C, the transparent gate insulating film 4 is formed on the surface of the semiconductor substrate 10. In this embodiment, a silicon oxide film having a thickness of about 6 nm to 10 nm is formed as a gate insulating film by a thermal oxidation method. A transparent conductor film is formed on the transparent gate insulating film 4. Here, as the transparent conductor film, an ITO film having a thickness of about 100 nm to 200 nm is formed by sputtering or the like. A gate electrode 5 is formed by applying a known photolithography technique and etching technique to the ITO film. As described above, the gate electrode 5 is formed so as to cover at least a part of the N-type impurity region 7. The width of the overlapping portion between gate electrode 5 and N-type impurity region 7 is not particularly limited. As will be described later, a P-type impurity region is formed on the surface of the N-type impurity region 7 exposed between the gate electrode 5 and the element isolation 2 to suppress unnecessary charges due to surface defects of the semiconductor substrate 10. Therefore, it is preferable that the gate electrode 5 overlaps only a part of the N-type impurity region 7. However, the configuration in which the gate electrode 5 covers the entire N-type impurity region 7 is not excluded. For example, in the example shown in FIG. 2, the long side Ld of the N-type impurity region 7 is 1225 nm, the short side Wd is 835 nm, the long side Wg of the gate electrode 5 is 560 nm, and the short side Lg is 330 nm. The width d is 150 nm.

  Note that the gate electrodes of the amplification transistor, reset transistor, selection transistor, and the like formed on the semiconductor substrate 10 and the transistor constituting the peripheral circuit may be formed of a conventional gate electrode material such as polysilicon. it can. In this case, these gate electrodes may be formed either before or after the gate electrode 5 is formed.

Next, as shown in FIG. 4D, ion implantation is performed through a mask having an opening in a portion corresponding to the N-type impurity region 7 not covered with the gate electrode 5, thereby forming the N-type impurity region 7. P-type impurities are introduced into the surface portion. Thereby, a P-type impurity region 6 having an impurity concentration of about 1.0 × 10 ²⁰ cm ⁻³ and a depth of about 50 nm is formed. Here, boron is ion-implanted under implantation conditions of an implantation energy of 1 keV to 10 keV and a dose of 1.0 × 10 ¹⁴ cm ^{−2 to} 1.0 × 10 ¹⁵ cm ⁻² .

Subsequently, as shown in FIG. 5A, ion implantation is performed through a mask having an opening in the floating diffusion formation region, thereby facing the N-type impurity region 7 across the gate electrode 5 in plan view. N-type impurities are introduced into the surface portion of the semiconductor substrate 10. As a result, the floating diffusion region 8 having an impurity concentration of about 3.0 × 10 ¹⁹ cm ⁻³ and a depth of about 30 nm to 50 nm is formed. Here, phosphorus or arsenic is ion-implanted under implantation conditions of an implantation energy of 20 keV to 50 keV and a dose of 1.0 × 10 ¹⁵ cm ^{−2 to} 3.0 × 10 ¹⁵ cm ⁻² .

  Thereafter, on the semiconductor substrate 10, the transparent insulating film 11, the light shielding film 12, the transparent flattening film 13, the opening 19, the low refractive index transparent film 14, the high refractive index transparent film 15, the color filter layer 16, and the on-chip lens 17. Etc. are sequentially formed, and a solid-state imaging device as shown in FIG. 5B is completed. Various electrodes of various transistors, wirings electrically connected to the electrodes, and the like are sequentially formed in the process of forming these upper layer structures. In order to prevent the gate electrode 5 from being etched in the etching step for forming the opening 19, it is preferable that a transparent film such as a silicon nitride film functioning as an etching stopper is provided on the gate electrode 5.

  As described above, in the method of manufacturing the solid-state imaging device according to the present embodiment, the pixel cell includes the gate electrode 5 made of a transparent conductor, and the gate electrode 5 overlaps at least part of the N-type impurity region 7. It has a structure. As a result, punch-through suppression and sensitivity reduction suppression can both be achieved in a fine pixel cell.

  Further, as can be understood from FIG. 2, in this configuration, relative to the mask used in the lithography process for forming the N-type impurity region 7 and the mask used in the lithography process for forming the gate electrode 5. Even when a slight misalignment occurs, the effective area of the light receiving region does not vary. Therefore, it is possible to obtain an effect that the sensitivity characteristics in each pixel cell do not vary.

  In the above description, the gate electrode of the reading transistor is made of a transparent conductor. However, the gate electrode is effective if at least a part of the overlapping portion with the charge storage region is made of a transparent conductor. The area of a typical light receiving region can be increased.

  FIG. 6 is a cross-sectional view illustrating a main part of a modification of the solid-state imaging device according to the embodiment of the present invention. This modification is different from the solid-state imaging device shown in FIG. 1 only in the structure of the gate electrode. The planar shape of the gate electrode is the same as the planar shape of the gate electrode 5 shown in FIG. In FIG. 6, the description of the upper layer structure is omitted.

  In this modification, the gate electrode 25 of the read transistor has a non-transparent portion 25a made of a conventional non-transparent electrode material such as polysilicon and a transparent portion 25b made of a transparent conductor. Here, the non-transparent portion 25 a is provided on the well region 1 between the N-type impurity region 7 and the floating diffusion 8 via the transparent gate insulating film 4. The transparent portion 25 b is provided on the N-type impurity region 7 via the transparent gate insulating film 4. Note that the non-transparent portion 25a and the transparent portion 25b are electrically connected. Although not particularly limited, in this example, as shown in FIG. 6, the electrical connection is realized by forming the transparent portion 25 b in contact with the side surface and the upper surface of the non-transparent portion 25 a on the photodiode 20 side.

  Also in this modification, punch-through suppression and sensitivity reduction suppression can be made compatible in a fine pixel cell, as in the solid-state imaging device shown in FIGS. Note that the solid-state imaging device shown in FIG. 6 can be realized, for example, by changing the formation process of the gate electrode in the manufacturing method described above. That is, a conductive polysilicon film having a film thickness of about 50 nm to 100 nm is formed on the transparent gate insulating film 4 formed on the surface of the semiconductor substrate 10 by a low pressure CVD method or the like. The non-transparent portion 25a is formed by applying a known photolithography technique and etching technique to the conductive polysilicon film. At this time, the gate electrode of the amplification transistor, the reset transistor, the selection transistor, the gate electrode of the transistor constituting the peripheral circuit, or the like may be formed at the same time.

  Next, an ITO film having a thickness of about 50 nm to 100 nm is formed on the semiconductor substrate 10 by sputtering or the like. By applying a known photolithography technique and etching technique to the ITO film, the transparent portion 25b is formed. In this example, since the non-transparent portion 25a is formed of conductive polysilicon, the surface oxide film of the non-transparent portion 25a is removed immediately before the ITO film is deposited. The subsequent steps are as described above.

  In the above, the case where the gate electrode of the reading transistor is configured by one electrically connected electrode has been described. However, the gate electrode may be configured by a plurality of electrically separated electrodes. it can.

  FIG. 7 is a cross-sectional view illustrating a main part of another modification of the solid-state imaging device according to the embodiment of the present invention. This modification is different from the solid-state imaging device shown in FIG. 1 only in the structure of the gate electrode. The planar shape of the gate electrode is the same as the planar shape of the gate electrode 5 shown in FIG. In FIG. 7, the description of the upper layer structure is omitted.

  In this modification, the gate electrode 35 of the reading transistor has a first gate electrode 35a and a second gate electrode 35b made of a transparent conductor. Here, the first gate electrode 35 a is provided on the well region 1 between the N-type impurity region 7 and the floating diffusion 8 via the transparent gate insulating film 4. A second gate electrode 35 b is provided on the N-type impurity region 7 via the transparent gate insulating film 4. The first gate electrode 35a is electrically separated from the second gate electrode 35b. The method of electrical separation is not particularly limited. For example, as shown in FIG. 6, the gate electrode having a laminated structure may have a configuration in which an insulating film is interposed between the layers.

  Also in this modification, punch-through suppression and sensitivity reduction suppression can be made compatible in a fine pixel cell, as in the solid-state imaging device shown in FIGS. In this configuration, since the first gate electrode 35a and the second gate electrode 35b are electrically separated, different potentials can be applied to the respective gate electrodes. Therefore, by applying a large potential that increases the width of the signal charge readout path (see FIG. 9) to the second gate electrode 35b, the signal charge readout characteristics can be further improved. In this configuration, the first gate electrode 35a can be formed of a non-transparent conductor made of a conventional electrode material such as polysilicon. The structure of the modified example can be realized by sequentially forming the first gate electrode 35a and the second gate electrode 35b, for example, similarly to the modified example shown in FIG.

  As described above, according to the present invention, it is possible to achieve both suppression of punch-through and suppression of sensitivity reduction in a fine pixel cell. Furthermore, since the gate length of the transfer gate electrode functioning as the gate electrode of the reading transistor can be made relatively large, it is possible to suppress deterioration of the signal charge reading characteristics.

  The present invention is not limited to the embodiment described above, and various modifications and applications are possible within the scope of the effects of the present invention. The feature of the present invention is to make the region covered with the transfer gate electrode function as a photoelectric conversion region. Therefore, it is possible to replace the process used in each of the above steps with another equivalent process without departing from the technical idea. Moreover, it is also possible to change a process order and to change a material kind. For example, the transparent gate insulating film is not limited to an oxide film, and other insulating films such as an oxynitride film can be employed. The light receiving region size, the gate electrode size, and the size of the region where the charge storage region and the gate electrode overlap are merely examples, and other values may be used. Furthermore, the upper layer structure is an example, and other structures may be employed. For example, a configuration in which an interlayer lens is disposed on the optical waveguide or a configuration in which the optical waveguide is omitted can be employed.

  In the above description, the case where each pixel cell includes a floating diffusion has been described. However, the floating diffusion may be provided in association with the charge accumulation region of each pixel cell. That is, one floating diffusion is provided corresponding to a plurality of charge accumulation regions, and the signal charges accumulated in each charge accumulation region are sequentially transferred to the one floating diffusion, thereby accumulating in each charge accumulation region. The signal charge may be detected.

  INDUSTRIAL APPLICABILITY The present invention can suppress a decrease in sensitivity due to pixel cell miniaturization, and is useful as a solid-state imaging device and a manufacturing method thereof.

1 P-type well region (semiconductor layer)
4 Transparent gate insulating film 5, 25, 35 Gate electrode (transfer gate electrode)
6 P-type impurity region (surface defect suppression region)
7 N-type impurity region (charge storage region)
8 Floating diffusion (detector)
10 Semiconductor substrate 12 Light shielding film 25a Non-transparent portion 25b Transparent portion 35a First gate electrode 35b Second gate electrode

Claims (4)

A solid-state imaging device including a plurality of charge storage regions that convert incident light into signal charge and store the signal charge,
A first conductivity type semiconductor layer;
A charge storage region comprising an impurity region of a second conductivity type provided in the semiconductor layer;
Corresponding to the charge accumulation region, the charge accumulation region is formed of an impurity region of a second conductivity type provided in the semiconductor layer at a distance from the charge accumulation region and transferring the signal charge accumulated in the charge accumulation region. A detection unit;
The transfer is provided on the surface of the semiconductor layer through an insulating film so as to overlap with the charge storage region, and at least a part of the overlapping portion is made of a transparent conductor that transmits visible light. A transfer gate electrode to be controlled;
A solid-state imaging device comprising:   The solid-state imaging device according to claim 1, wherein the transfer gate electrode overlaps only a part of the charge storage region.   The solid-state imaging device according to claim 1, wherein the transfer gate electrode includes a plurality of electrically separated electrodes. A method of manufacturing a solid-state imaging device including a plurality of charge storage regions that convert incident light into signal charge and store the signal charge,
Forming a charge storage region comprising a second conductivity type impurity region in the first conductivity type semiconductor layer;
Transfer in which at least a part of the overlapping part is made of a transparent conductor that is transparent to visible light on the surface of the semiconductor layer on which the charge storage area is formed, in a state of overlapping the part of the charge storage area Forming a gate electrode through an insulating film;
Corresponding to the charge storage region, the semiconductor layer is formed of a second conductivity type impurity region, and a detection unit to which the signal charge stored in the charge storage region is transferred by the transfer gate electrode is connected to the charge storage region. Forming with a gap from the region;
A method for manufacturing a solid-state imaging device, comprising:

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