KR101656487B1 - Array substrate for X-ray detector and Method for fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate for an X-ray detector in which a thin film transistor is formed and a method of manufacturing the same.

An array substrate for an X-ray detector according to the present invention includes a plurality of pixel regions formed on a substrate and defined in a matrix form by intersection of a plurality of gate wirings and a plurality of data wirings, A plurality of thin film transistors including a plurality of source electrodes having protrusions and a plurality of drain electrodes connected to the other ends of each of the plurality of active layers,

A plurality of photodiodes connected to each of the plurality of drain electrodes, a plurality of bias wirings for applying a bias voltage to the plurality of photodiodes, and a plurality of readout wirings connected to the protruding portions of each of the plurality of source electrodes .

X-ray detector, thin film transistor, bias wiring, read wiring

Description

[0001] The present invention relates to an array substrate for X-ray detector,

The present invention relates to an array substrate for an X-ray detector in which a thin film transistor is formed and a method of manufacturing the same.

When an x-ray emitted from an x-ray source passes through a subject, a scintillator changes x-rays to green light, which is a visible ray region, according to the density of the subject. Diagnostic radiography is a method of detecting the amount of electric charge generated when a green light passes through a photoelectric conversion sensor and converting the detected amount of charge into a digital signal to convert the digital image into a digital image. Diagnostic radiography is now widely used. Diagnostic radiography is divided into a method of image processing and a storage medium, and is divided into an analogue type and a digital radiography method.

With the development of medical diagnostic devices, the use of the analog type is gradually decreasing. Digital diagnostic radiography is divided into computerized radiography (CR) and digital radiography (DR) according to the sensor used.

The DR system for performing fundamental image processing of the medical diagnostic apparatus includes a CCD (charge coupled device) DR, a complementary metal-oxide semiconductor (CMOS) DR, and a FP (flat) image sensor depending on the type of the sensor that converts green light incident from the scintillator. panel DR. The three basic DR principles are the same for digital image processing.

The flat panel glass is a method that can achieve the best X-ray image by matching 1: 1 with a large-sized panel and applying it to a photo-electric sensor. Currently, the most advanced DR is Flat Panel X Ray Detecting (FPXD). FPXD DR is divided into direct and indirect methods. Currently, DR is the most popular structure.

In the non-direct type flat panel portion, a PIN photodiode is formed on the array substrate to detect x-rays, and a siltilator is disposed on the PIN photodiode. The x-ray irradiated scintillator converts light into the light of the most sensitive wavelength in the PIN photodiode through photoconversion, and the photodiode converts it into an electrical signal. These electrical signals are transmitted as video signals through the transistors.

Hereinafter, a conventional array substrate for an X-ray detector and a manufacturing method thereof will be described in detail with reference to the drawings.

FIG. 1 is a plan view of an array substrate for an X-ray detector according to the related art, FIG. 2 is a cross-sectional view of an array substrate according to a conventional technique, And FIGS. 4A and 4B are process cross-sectional views showing a method of manufacturing an array substrate according to another example of the prior art step by step.

1, an array substrate 10 includes a plurality of data lines 12, a plurality of gate lines 14, a plurality of data lines 12, and a plurality of gate lines 14, A plurality of photodiodes 20 located in each of the plurality of pixel regions PA and converting a photoelectric signal into an electrical signal and a plurality of photodiodes 20 in order to drive the plurality of photodiodes 20, 18).

The thin film transistor 18 includes a gate electrode 22 connected to the gate wiring 14, an active layer 24 located on the gate electrode 22, and a data line 12 connecting one end of the active layer 24 and the data line 12 A source electrode 26a and a drain electrode 26b connected to the other end of the active layer 24. [ The drain electrode 26b is connected to the photodiode 20.

The array substrate 10 includes a readout wiring 28 connected to the source electrode 26a, a bias wiring 30 for applying a bias voltage capable of controlling electrons or holes of the photodiode 20, And a gate pad portion 34 connected to an end of the gate wiring 14 and to which a scanning signal is applied from the outside. The bias wiring 30 is formed of an opaque metal material and shields the gate electrode 22 in order to prevent malfunction of the thin film transistor 18.

FIG. 2 is a cross-sectional view of the thin film transistor 18 taken along line II in FIG. 1, a cross section taken along line II-II of the bias line 30, a cross-sectional view taken along line III- Sectional view of section 32 taken along line IV-IV. The array substrate 10 is divided into the data wiring region 12 in which the data wiring 12, the thin film transistor 18, the photodiode 20, the data pad portion 32 and the gate pad portion 34 are formed, A sectional view of the array substrate 10 is shown divided into a plurality of pixel regions DA, a thin film transistor region TA, a photodiode region DIA, a data pad region DPA, and a gate pad region GPA.

1 corresponds to the gate insulating layer 42 on the insulating substrate 40 including the gate electrode 22 and the gate electrode 22 and the gate electrode 22 corresponding to the gate electrode 22. In the thin film transistor region TA, And source and drain electrodes 26a and 26b connected to one end and the other end of the active layer 24 and spaced apart from each other. The active layer 24 is composed of a first amorphous silicon layer 44a not doped with an impurity and a second amorphous silicon layer 44b doped with an N-type impurity.

In the photodiode region DIP, the photodiode 20 has a lower electrode 54 formed on the drain electrode 26a of the thin film transistor 18 and connected to the drain electrode 26a, a lower electrode 54 formed on the lower electrode 54, A conductor layer 52 and an upper electrode 56 on the photoconductor layer 52. [ The photoconductor layer 52 includes an N-type semiconductor layer 52a containing an N-type impurity, an intrinsic semiconductor layer 52b containing no impurity, and a P-type semiconductor layer 52c containing a P-type impurity .

The first passivation layer 58 is formed on the thin film transistor 18 and the photodiode 20 and the first contact hole 60 exposing the source electrode 26a and the first passivation layer 58 exposing the source electrode 26a are formed in the first passivation layer 58. [ A second contact hole 62 exposing the second contact hole 56 is formed. The source electrode 26a and the readout wiring 68 are connected through the first contact hole 60 and the upper electrode 56 and the bias wiring 70 are connected through the second contact hole 62. [ The second passivation layer 76 is formed on the first passivation layer 58 including the readout wiring 68 and the bias wiring 70.

In the gate pad region GPA, the gate pad portion 34 includes a gate pad 34a and a gate pad electrode 34b, and the gate pad electrode 34b includes a gate pad 34a. In the data pad region DPA, the data pad portion 32 includes a data pad 32a and a data pad electrode 32b, and the data pad electrode 32b includes a data pad (not shown) through the data pad contact hole 66 32a.

3A to 3G, a method of manufacturing an array substrate according to the related art will be described step by step. 3A to 3G are cross-sectional views of the thin film transistor 18 taken along line II in FIG. 1, cross-sectional views of the bias wiring 30 taken along line II-II, cross-sectional views of the gate pad 34 taken along line III- And a cross-sectional view of the data pad portion 32 taken along line IV-IV. The array substrate 10 is divided into the data wiring region 12 in which the data wiring 12, the thin film transistor 18, the photodiode 20, the data pad portion 32 and the gate pad portion 34 are formed, A sectional view of the array substrate 10 is shown divided into a plurality of pixel regions DA, a thin film transistor region TA, a photodiode region DIA, a data pad region DPA, and a gate pad region GPA.

As shown in FIG. 3A, a first metal layer (not shown) containing aluminum is formed on the insulating substrate 40, and the first metal layer is selectively etched to form the gate wiring 14 shown in FIG. The illustrated gate electrode 22, and the gate pad 34a are formed. The gate electrode 22 is formed in the thin film transistor region TA and the gate pad 34a is formed in the gate pad region GPA.

The gate insulating layer 42 is formed on the insulating substrate 40 including the gate wiring 14, the gate electrode 22 and the gate pad 34a as shown in FIG. 3B, The active layer 24 is formed on the gate insulating layer 42. The gate insulating layer 42 may be made of silicon oxide or silicon nitride. The active layer 24 is composed of a first amorphous silicon layer 44a not doped with an impurity and a second amorphous silicon layer 44b doped with an N-type impurity.

The second metal layer 50 is formed on the gate insulating layer 42 including the active layer 24 as shown in FIG. The second metal layer 50 may be formed as a single layer or a double layer composed of the first and second sub metallic layers 50a and 50b. Each of the first and second sub-metal layers 50a and 50b may be formed of aluminum-nidium (AlNd) and molybdenum (Mo).

Then, a photodiode 20 is formed on the second metal layer 50 of the pixel region PA. The photodiode 20 is comprised of a photoconductor layer 52, a lower electrode 54 between the photoconductor layer 52 and the metal layer 50, and an upper electrode 56 on the photoconductor layer 52. The photoconductor layer 52 includes an N-type semiconductor layer 52a containing an N-type impurity, an intrinsic semiconductor layer 52b containing no impurity, and a P-type semiconductor layer 52c containing a P-type impurity .

The upper electrode 56 is formed on an upper substrate (not shown) facing the array substrate 10 and is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper electrode 56 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or the like in order to increase the transmission efficiency of light transmitted from a scintillator, which is irradiated with X- And is formed of a transparent conductive material. The lower electrode 54 is formed of a metal layer such as molybdenum (Mo).

A method of forming the photodiode 20 includes forming a third metal layer (not shown), an N-type silicon layer (not shown), an intrinsic silicon layer (not shown), a P- A silicon layer (not shown), and a transparent conductive material layer (not shown) are sequentially stacked and selectively etched.

The first metal layer 50 is selectively etched to form the data line 12, the source and drain electrodes 26a and 26b, and the data pad 32a as shown in FIG. 3D. 1 is formed of the gate electrode 22, the gate insulating layer 42, the active layer 24, and the source and drain electrodes 26a and 26b in the thin film transistor region TA . A data pad 32a is formed in the data pad region DPA by patterning the second metal layer 50. [ The second metal layer 50 is removed in the gate pad area GPA. The source and drain electrodes 26a and 26b are spaced apart from each other with the channel region CH of the active layer 24 therebetween. Then, the second amorphous silicon layer 44b of the channel region CH is etched.

The first passivation layer 58 is formed on the insulating substrate 40 including the thin film transistor 18 and the photodiode 20 as shown in FIG. The first passivation layer 58 may be formed of an inorganic or organic insulating material. The inorganic insulating material may be silicon oxide or silicon nitride.

A first contact hole 60 for exposing the source electrode 26a and a second contact hole 62 for exposing the upper electrode 56 of the photodiode 20 are formed by selectively etching the first passivation layer 58, . The gate pad 34a is exposed by etching the first passivation layer 58 and the gate insulating layer 42 in the gate pad area GPA simultaneously with the formation of the first and second contact holes 60 and 62. [ The first passivation layer 58 is etched in the pad contact hole 64 and the data pad area DPA to form a data pad contact hole 66 exposing the data pad 32a.

The first protective layer 58 includes a first contact hole 60 for connecting the readout wiring 68 and the source electrode 26a of FIG. 2 and a second contact hole 60 for connecting the bias wiring 70 and the upper electrode 56 of FIG. 2 Since the second contact hole 62 is formed, the first passivation layer 58 is formed to be sufficiently thick, about 4000 ANGSTROM or more, in order to secure reliability.

A fourth metal layer (not shown) is formed on the first passivation layer 58 including the first and second contact holes 60 and 62 and the gate and data pad contact holes 64 and 66, Out line 68 connected to the source electrode 26a through the first contact hole 60 and the readout line 68 connected to the photodiode 20 through the second contact hole 62. [ A gate pad electrode 34b connected to the gate pad 34a through the gate pad contact hole 64 and a gate pad electrode 34b connected to the data pad contact hole 66 A data pad electrode 32b connected to the data pad 32a is formed. At this time, the bias wiring 70 passes over the upper portion of the first protective layer 58 corresponding to the gate electrode 22 in order to prevent malfunction of the thin film transistor 18.

A second passivation layer 76 is formed on the first passivation layer 58 including the readout wiring 68, the bias wiring 70 and the gate and data pad electrodes 34b and 32b as shown in Fig. 3G, And the second protective layer 76 of the data pad area GPA, DPA are removed.

The array substrate for an X-ray detector according to the related art and the manufacturing method thereof have the following problems.

First, to form the lower electrode 54 of the photodiode 20, a second metal layer 50, which is located under the third metal layer and used as the source and drain electrodes 26a and 26b when the third metal layer is etched, May be damaged.

As shown in FIG. 3C, when the third metal layer is etched to form the lower electrode 54 of the photodiode 20, a second metal layer 50 is located under the third metal layer. Therefore, when the third metal layer is etched to form the lower electrode 54, the second metal layer 50 may be damaged because the etch selectivity between the second metal layer 50 and the third metal layer is very small. Even when the second metal layer 50 is formed as the first and second sub metal layers 50a and 50b of aluminum-aluminum (AlNd) and molybdenum (Mo), when the third metal layer made of molybdenum is etched, The second sub-metal layer 50b of the second metal layer 50 located under the third metal layer is simultaneously etched.

The second metal layer 50 is used as the source and drain electrodes 26a and 26b in FIG. 2, and the source electrode 26a is connected to the readout wiring 68. Therefore, the damage of the second metal layer 50 may increase the contact resistance between the source electrode 26a and the protruding wiring 68, thereby causing defects.

Second, by the first and second protective layers 58 and 76, the light efficiency delivered to the photoconductor layer 52 can be reduced.

The upper electrode 56 shown in FIG. 2 is formed on an upper substrate (not shown) opposite to the array substrate 10 and has a light arrival efficiency from a scintillator which is irradiated with X- A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is used.

The first protective layer 58 includes a first contact hole 60 for connecting the readout wiring 68 and the source electrode 26a of FIG. 2 and a second contact hole 60 for connecting the bias wiring 70 and the upper electrode 56 2 < / RTI > thick enough to ensure the reliability of the < RTI ID = 0.0 > contact hole 62. < / RTI > Thus, due to the first and second protective layers 58 and 76, the light efficiency delivered to the photoconductor layer 52 can be reduced.

Third, the process margin of the first contact hole 60 formed in the first passivation layer 58 on the source electrode 26a adjacent to the data line 12 and connecting the readout line 68 to the source electrode 26a An unnecessary space A is generated between the thin film transistor 18 and the photodiode 20 as shown in FIG. 1 to reduce the fill factor.

As shown in Fig. 1, the bias wiring 30 shields the gate wiring 24 in order to prevent malfunction of the thin film transistor 18. Therefore, the bias wiring 30 has the form of a linear wiring passing through the gate electrode 22. [ A region where a first contact hole 60 connecting the source electrode 26a and the readout wiring 68 of the thin film transistor 18 is formed is provided between the data line 12 and the gate electrode 22 . Therefore, unnecessary waste space exists between the photodiode 20 and the thin film transistor 18 as shown in FIG. 1A in order to secure the area of the first contact hole 60, thereby reducing the fill factor.

3C and FIG. 3D, in forming the lower electrode 54 of the photodiode 20, the source and drain electrodes 26a and 26b are formed in the array substrate for an X- The interlayer insulating layer 80 is formed between the second metal layer 50 and the third metal layer as shown in FIGS. 4A and 4B in order to prevent damage to the second metal layer 50 stacked for the formation of the second metal layer 50 .

A gate insulating layer 42 is formed on the gate electrode 22 and the gate electrode 22 on the insulating substrate 40 and a gate insulating layer 42 is formed on the gate insulating layer 42 The active layer 24 composed of the first and second amorphous silicon layers 44a and 44b is formed. The first metal layer 50 is formed on the gate insulating layer 42 including the active layer 24. An interlayer insulating layer 80 is formed on the first metal layer 50 and a drain contact hole 82 is formed by selectively etching the interlayer insulating layer 80 to expose the first metal layer 50.

The second metal layer 50 may be formed as a single layer or a double layer like the first and second sub metal layers 50a and 50b. Each of the first and second sub-metal layers 50a and 50b may be formed of aluminum-nidium (AlNd) and molybdenum (Mo). The interlayer insulating layer 80 may be formed of silicon oxide or silicon nitride.

In the photodiode region DIA, a photodiode 20 connected to the second metal layer 50 through the drain contact hole 82 is formed. The photodiode 20 is comprised of a photoconductor layer 52, a lower electrode 54 between the photoconductor layer 52 and the metal layer 50, and an upper electrode 56 on the photoconductor layer 52. The photoconductor layer 52 includes an N-type semiconductor layer 52a containing an N-type impurity, an intrinsic semiconductor layer 52b containing no impurity, and a P-type semiconductor layer 52c containing a P-type impurity .

The method of forming the photodiode 20 includes forming a second metal layer (not shown), an N-type silicon layer (not shown), an intrinsic silicon layer (not shown) on the interlayer insulating layer 80 including the drain contact hole 82, (Not shown), a P-type silicon layer (not shown), and a transparent conductive material layer (not shown) are sequentially stacked and selectively etched. Therefore, when the lower electrode 54 of the photodiode 20 is formed, the second metal layer 50 laminated to form the source and drain electrodes 26a and 26b of FIG. 2 is not damaged.

The interlayer insulating layer 80 and the second metal layer 50 are selectively etched to form the source and drain electrodes 26a and 26b, as shown in FIG. 4B. A thin film transistor 18 composed of a gate electrode 22, a gate insulating layer 42, an active layer 44, and source and drain electrodes 26a and 26b is formed in the thin film transistor region TA. The source and drain electrodes 26a and 26b are spaced apart from each other with the channel region CH of the active layer 24 therebetween. Then, the second amorphous silicon layer 44b of the channel region CH is etched.

The first passivation layer 58 is formed on the insulating substrate 40 including the thin film transistor 18 and the photodiode 20 and the first passivation layer 58 and the interlayer insulating layer 80 are selectively etched A first contact hole 60 exposing the source electrode 26a and a second contact hole 62 exposing the upper electrode 56 of the photodiode 20 are formed.

A first passivation layer 58 and an interlayer insulating layer 80 are formed on the source electrode 26a and a first passivation layer 58 is formed on the upper electrode 56. [ The second contact hole 62 formed on the upper electrode 56 is excessively etched as compared with the first contact hole 60 formed on the source electrode 26a. Thus, in order to prevent damage to the first metal layer 50 deposited to form the source and drain electrodes 26a and 26b when forming the lower electrode 54 of the photodiode 20, The upper electrode 56 under the second contact hole 62 may be damaged when the interlayer insulating layer 80 is formed between the first metal layer 50 and the second metal layer. Damage to the upper electrode 56 increases the contact resistance between the upper electrode 56 and the bias wiring 30, which may cause defects.

In order to solve the above problems, the present invention is characterized in that the bias wiring is disposed close to the data wiring by connecting one end of the active layer and one side of the data wiring and connecting the protruding portion of the source electrode protruding to the other side of the data wiring to the read wiring, It is an object of the present invention to provide an array substrate for an X-ray detector capable of improving a fill factor.

According to the present invention, a contact region of a bias wiring contacting a top electrode of a photodiode is extended in the same straight line as a wiring portion of a bias wiring on one side facing the data wiring, and a contact region is formed on the other side of the bias wiring from a wiring portion Another object of the present invention is to provide an array substrate for an X-ray detector capable of improving a fill factor by bringing a data wiring and a bias wiring close to each other.

In the protective layer of the transparent conductive material formed on the upper electrode of the photodiode, the thickness of the protective layer corresponding to the central portion of the photodiode is formed to be thinner than the thickness of the protective layer corresponding to the peripheral portion of the photodiode, Another object of the present invention is to provide an array substrate for an X-ray detector capable of improving light transmission efficiency to be transmitted to an electrode.

In the present invention, when the thickness of the insulating layer on the source electrode of the thin film transistor is larger than the thickness of the insulating layer on the upper electrode of the photodiode, the insulating layer is etched to expose the first contact hole and the upper electrode, A method of manufacturing an array substrate for an X-ray detector that prevents excessive etching of an upper electrode when forming a second contact hole by using an end-point detector capable of detecting a substance of a source electrode when forming a second contact hole To provide a separate purpose.

According to an aspect of the present invention, there is provided an array substrate for an X-ray detector, including: a plurality of pixel regions formed on a substrate and defined in a matrix form by vertical intersections of a plurality of gate lines and a plurality of data lines; A plurality of gate electrodes disposed in each of the plurality of pixel regions and connected to each of the plurality of gate wirings, a plurality of active layers on each of the plurality of gate electrodes, one end of each of the plurality of active layers, A plurality of thin film transistors including a plurality of source electrodes connected to the plurality of data lines and having protrusions protruding to the other side of each of the plurality of data lines, and a plurality of drain electrodes connected to the other ends of each of the plurality of active layers; A plurality of photodiodes coupled to each of the plurality of drain electrodes; A plurality of bias lines for applying a bias voltage to the plurality of photodiodes; And a plurality of readout wirings connected to the protrusions of each of the plurality of source electrodes.

In the array substrate for an X-ray detector, each of the plurality of photodiodes includes a first depression corresponding to the protrusion of each of the plurality of source electrodes, and each of the plurality of pixel regions includes a plurality of source electrodes And a second depressed portion corresponding to the protruding portion.

In the above-described array substrate for an X-ray detector, each of the plurality of bias wirings includes a wiring portion and a contact region which is in contact with each of the plurality of photodiodes and has a wider width than the wiring portion.

In the array substrate for an X-ray detector as described above, in the one side of the plurality of bias wirings facing the plurality of data wirings, the wiring portion and the contact region extend in the same straight line, and the plurality And the contact region protrudes from the wiring portion on the other side of the bias wiring.

In the above-described array substrate for an X-ray detector, the plurality of bias wirings shield the plurality of gate electrodes.

In the array substrate for an X-ray detector as described above, a protective layer is formed on the plurality of photodiodes, and the thickness of the protective layer corresponding to the periphery of each of the plurality of optical multi- And a light transmitting region having a thickness is formed.

A plurality of gates and data pads connected to the plurality of gates and data wirings; a plurality of gates and data pads formed on the plurality of gates and the data pads; And a data pad electrode is formed.

In the above-described array substrate for an X-ray detector, each of the plurality of photodiodes may include a lower electrode connected to each of the plurality of drain electrodes, a photoconductor layer formed on the lower electrode, And an upper electrode formed on the upper electrode, wherein each of the plurality of bias wirings is connected to the upper electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for an X-ray detector, including: forming a plurality of gate wirings formed on a substrate and a plurality of gate electrodes connected to the plurality of gate wirings; Forming a gate insulating layer on the substrate including the plurality of gate wirings and the plurality of gate electrodes; A plurality of data lines, one end of each of the plurality of data lines, and one end of each of the plurality of active layers, and a plurality of data lines, each of the plurality of data lines, Forming a plurality of source electrodes having projections protruding to the other side and a plurality of drain electrodes connected to the other ends of each of the plurality of active layers; And forming a plurality of bias wirings connected to the plurality of photodiodes and a plurality of read wirings connected to the plurality of source electrodes, respectively.

In the above-described method of manufacturing an array substrate for X-ray detection, an interlayer insulating layer is formed on the gate insulating layer including the plurality of data lines and the plurality of source and drain electrodes. Forming a plurality of drain contact holes exposing each of the plurality of drain electrodes by selectively etching the interlayer insulating layer; And forming the plurality of photodiodes connected to the plurality of drain electrodes through the plurality of drain contact holes on the interlayer insulating layer.

In the method of manufacturing an array substrate for X-ray detection as described above, a plurality of lower electrodes connected to each of the plurality of drain contact holes is formed on the interlayer insulating layer. Forming a transparent conductive material layer on the silicon layer and the silicon layer on the interlayer insulating layer including the plurality of lower electrodes; And patterning the transparent conductive material layer and the silicon layer to form a plurality of upper electrodes and a plurality of photoconductor layers.

In the method of manufacturing an array substrate for X-ray detection as described above, a step of forming a protective layer on the interlayer insulating layer including the plurality of photodiodes; Forming a plurality of first contact holes through which the plurality of source electrodes are exposed and a plurality of second contact holes through which the plurality of photodiodes are exposed by selectively etching the passivation layer and the gate insulating layer, ; Forming a plurality of bias lines connected to the plurality of photodiodes through the plurality of read lines and the plurality of second contact holes connected to the plurality of source electrodes through the plurality of first contact holes, Further comprising the steps of:

In the method for manufacturing an array substrate for X-ray detection as described above, each of the plurality of bias wirings includes a wiring portion and a contact region corresponding to each of the plurality of second contact holes, .

In the method for manufacturing an array substrate for an X-ray detector as described above, in the one side of the plurality of bias wirings facing each of the plurality of data wirings, the wiring portion and the contact region extend in the same straight line, And the contact region is protruded from the wiring portion on the other side of each of the plurality of bias wirings.

In the method for manufacturing an array substrate for an X-ray detector as described above, the plurality of source electrodes are formed of a metal layer including molybdenum on the uppermost layer, the plurality of upper electrodes are formed of ITO or ZTO, The dry etching is stopped when the molybdenum is detected in the end point detector in the step of forming the plurality of first and second contact holes by dry etching the layer.

In the method of manufacturing an array substrate for X-ray detection as described above, a plurality of gates and data pads connected to each of the plurality of gates and data wirings are formed. Forming a plurality of first gate and data pad electrodes on each of the plurality of gates and data pads; And forming a plurality of second gates and data pad electrodes made of ITO or ZTO on the plurality of first gate and data pad electrodes, respectively.

In the method of manufacturing an array substrate for an X-ray detector, each of the plurality of photodiodes includes a first depression corresponding to the protrusion of each of the plurality of source electrodes, and the plurality of gates and the data lines are orthogonal Wherein the plurality of pixel regions define a plurality of pixel regions in which the plurality of photodiodes are located, and each of the plurality of pixel regions has a second depression corresponding to the protrusion of each of the plurality of source electrodes.

The method of manufacturing an array substrate for an X-ray detector as described above may include forming a protective layer on the plurality of photodiodes, wherein a thickness of the protective layer of the plurality of photodiodes is greater than a thickness of the plurality of photodiodes, Is thinner than the thickness of the protective layer.

The array substrate for an X-ray detector of the present invention and its manufacturing method have the following effects.

The source electrode of the present invention has a protrusion connecting one end of the active layer of the thin film transistor and one side of the data line and protruding to the other side of the data line. By connecting the protruding portion of the source electrode to the readout wiring, the bias wiring can be brought close to the data wiring, and unnecessary space can be prevented from being generated, and the fill factor can be improved.

According to the present invention, a contact region of a bias wiring contacting a top electrode of a photodiode is extended in the same straight line as a wiring portion of a bias wiring on one side facing the data wiring, and a contact region is formed on the other side of the bias wiring from a wiring portion By protruding, the bias wiring can be brought close to the data wiring, so that the fill factor can be further improved.

The protective layer of the transparent conductive material formed on the upper electrode of the photodiode is formed such that the thickness of the protective layer corresponding to the central portion of the photodiode is made thinner than the thickness of the protective layer corresponding to the peripheral portion of the photodiode, It is possible to improve the light transmission efficiency.

In the array substrate for X-ray detection of the present invention, an interlayer insulating layer and a protective layer are formed on the source electrode of the thin film transistor, a protective layer is formed on the upper electrode of the photodiode, Is greater than the thickness of the insulating layer. An end-point detector capable of detecting the material of the source electrode is used when forming the first contact hole exposing the source electrode and the second contact hole exposing the upper electrode simultaneously by etching the insulating layer having different thicknesses, When the material of the electrode is detected, the etching is terminated to prevent the excessive etching of the upper electrode corresponding to the second contact hole. Therefore, the contact resistance between the bias wiring and the upper electrode of the photodiode can be improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a plan view of an array substrate for an X-ray detector according to an embodiment of the present invention, FIG. 6 is a sectional view of an array substrate for an X-ray detector according to the present invention, In a stepwise manner.

5, the array substrate 110 includes a plurality of data lines 112, a plurality of gate lines 114, a plurality of data lines 112, and a plurality of gate lines 114, A plurality of photodiodes 120 and a plurality of photodiodes 120, which are located in each of the plurality of pixel regions PA and convert the photoelectric signals into electrical signals, 118).

The thin film transistor 120 includes a gate electrode 122 connected to the gate wiring 114, an active layer 124 formed on the gate electrode 122 through a gate insulating layer (not shown), an active layer 124 A source electrode 126a connecting one end and the data line 112 and a drain electrode 126b connecting the other end of the active layer 124 and the photodiode 120. [ The source electrode 126a has one end of the data line 112 and one end of the active layer 124 and a protrusion 192 protruding to the other side of the data line 112. [

The photodiode 120 has a first depression 194 corresponding to the protrusion 192 of the source electrode 126a protruding to the other side of the data line 112. The pixel region PA has a second depression corresponding to the protrusion 192 of the source electrode 126a protruding to the other side of the data line 112. [

The array substrate 110 includes a readout wiring 128 connected to the protruding portion 192 of the source electrode 126a, a bias wiring 130 for applying a bias voltage for controlling electrons or holes of the photodiode 120, A data pad portion 132 connected to an end portion of the data line 112 and applied with an image signal from the outside and a gate pad portion 134 connected to an end portion of the gate line 114 and receiving a scan signal from the outside, .

The readout wiring 128 is connected to the protruding portion 192 of the source electrode 126a projecting to the other side of the data wiring 112. [ The bias wiring 130 includes a contact region 130b in contact with the wiring portion 130a and the photodiode 120. [ The bias wiring 130 is formed of an opaque metal material and shields the gate electrode 122 to prevent malfunction of the thin film transistor 118. The bias wiring 130 is in the form of a linear wiring and passes through the gate electrode 122. The contact region 130b has a larger width than the wiring portion 130a. The wiring 130a and the contact region 130b extend in the same straight line and the other side of the bias wiring 130 extends from the wiring portion 130a to one side of the bias wiring 130 facing the data wiring 112 The contact region 130b protrudes.

In the bias wiring 130, the contact region 130b is necessary to secure a process margin to connect with the photodiode 120. [ The contact region 130b is connected to the pixel region PA that is not one side of the bias wiring 130 facing the data wiring 112 in order to arrange the bias wiring 130 as close as possible to the data wiring 112. [ That is, on the other side of the bias wiring 130. The readout wiring 128 is connected to the protruding portion 192 of the source electrode 126a protruding to the other side of the data wiring 112 and the contact region 130b of the bias wiring 130 protrudes in the pixel direction , The space generated between the photodiode 120 and the thin film transistor 118 can be minimized to improve the fill factor.

6 is a cross-sectional view taken along the line VV of the data line 112, the thin film transistor 118 and the protruding portion 192 of the source electrode 126a, a cross-sectional view taken along line VI-VI of the bias line 130, Sectional view of the pad portion 134 cut to VII-VII, and a cross-sectional view of the data pad portion 132 taken along line VIII-VIII. The protruding portion 192 of the source electrode 126a, the data line 112, the thin film transistor 118, the photodiode 120, the gate pad portion 134, and the data pad portion 132 The data line area DA, the thin film transistor area TA, the photodiode area DIA, the gate pad area GPA and the data pad area DPA, Fig.

5 formed in the thin film transistor region TA includes a gate electrode 122, a gate insulating layer 142 on the insulating substrate 140 including the gate electrode 122, a gate electrode 122, An active layer 124 on the corresponding gate insulating layer 142 and source and drain electrodes 126a and 126b connected to and spaced apart from one end and the other end of the active layer 124. The source electrode 126a connects one end of the data line 112 and one end of the active layer 124. [ A data wiring 112 is formed in the data wiring region DA and one side of the data wiring 112 is connected to the source electrode 126a of the thin film transistor 118. A protrusion 192 of the source electrode 126a connected to the other side of the data line 112 is formed in the extended area EA.

The active layer 124 is composed of a first amorphous silicon layer 144a that is not doped with an impurity and a second amorphous silicon layer 144b that is doped with an N type impurity.

The photodiode 120 formed in the photodiode region DIA includes a lower electrode 154 connected to the drain electrode 126a of the thin film transistor 118, a photoconductor layer 152 on the lower electrode 154, And an upper electrode 156 on the conductor layer 152. The photoconductor layer 152 includes an N-type semiconductor layer 152a containing an N-type impurity, an intrinsic semiconductor layer 152b containing no impurity, and a P-type semiconductor layer 152c containing a P-type impurity .

The photodiode 120 is formed with an interlayer insulating layer 180 having a drain contact hole 182 on a gate insulating layer 140 including source and drain electrodes 126a and 126b of the thin film transistor 118 A lower electrode 154 connected to the drain electrode 126b through the drain contact hole 182 on the interlayer insulating layer 180, a photoconductor layer 152 on the lower electrode 154, and a photoconductor layer The upper electrode 156 is formed.

The first passivation layer 158 is formed on the interlayer insulating layer 140 including the photodiode 120 and the interlayer insulating layer 140 and the first passivation layer 158 are selectively etched to form the source electrode A first contact hole 160 exposing the protrusion 192 of the first contact hole 126a and a second contact hole 162 exposing the upper electrode 156 are formed. A readout wiring 168 connected to the protruding portion 192 of the source electrode 126a through the first contact hole 160 on the first protection layer 158 and the upper electrode 156 The bias wiring 170 is formed. The bias wiring 170 is formed of an opaque metal material such as molybdenum (Mo) or aluminum-neodymium (AlNd) and overlapped with the upper portion of the gate electrode 122 to prevent malfunction of the thin film transistor 118.

The gate pad portion 134 formed in the gate pad region GPA is connected to the first gate pad 134a and the first gate pad contact hole 164a formed simultaneously with the gate wiring 114 and the gate wiring 114 A first gate pad electrode 172a connected to the first gate pad 134a and connected to the second gate pad 134b through the second gate pad 134b and the second gate pad contact hole 164b, And a second gate pad electrode 172b connected to the first gate pad electrode 172a through the third gate pad contact hole 164c. The first gate pad 134a is formed simultaneously with the gate electrode 122 and the second gate pad 134b is formed simultaneously with the source and drain electrodes 126a and 126b and the first gate pad electrode 172a is read The wiring 168 and the bias wiring 170 are simultaneously formed.

The data pad portion 132 formed in the data pad region DPA includes a first data pad 132a and a first data pad electrode connected to the data pad 132a through the first data pad contact hole 166a And a second data pad electrode 174b connected to the first data pad electrode 174a through a second data pad contact hole 166b. The first data pad 132a is formed simultaneously with the data line 112 and the first data pad electrode 174a is formed simultaneously with the read line 168 and the bias line 170. [

The second gate and data pad electrodes 172b and 174b connected to the first gate and data pad electrodes 172a and 174a may be formed of a transparent conductive material to prevent corrosion of the first gate and data pad electrodes 172a and 174a, , For example, ITO or ZTO.

7A to 7J, a method of manufacturing the array substrate 110 according to the present invention will be described step by step. 7A to 7J are cross-sectional views in which the protrusion 192 of the source electrode 126a, the data line 112 and the thin film transistor 118 are cut in VV in FIG. 5, the bias line 130 is cut in VI-VI A cross section cut into gate pads 134 to VII-VII, and a cross section cut to data pads 132 through VIII-VIII. The protruding portion 192 of the source electrode 126a, the data line 112, the thin film transistor 118, the photodiode 120, the gate pad portion 134, and the data pad portion 132 The data line area DLA, the thin film transistor area TA, the photodiode area DIA, the gate pad area GPA, and the data pad area DPA, Fig.

7A, a first metal layer (not shown) containing aluminum is formed on the insulating substrate 140 and the first metal layer is selectively etched to form the gate wiring 114, the gate electrode 122 ), And a first gate pad 134a. The gate electrode 122 is formed in the thin film transistor area TA and the first gate pad 134a is formed in the gate pad area GPA.

A gate insulating layer 142 is formed on an insulating substrate 140 including a gate wiring 114, a gate electrode 122 and a first gate pad 134a, And the active layer 124 is formed on the corresponding gate insulating layer 142. The gate insulating layer 142 may be made of silicon oxide or silicon nitride. The active layer 124 is composed of a first amorphous silicon layer 144a not doped with an impurity and a second amorphous silicon layer 144b doped with an N-type impurity.

The first gate pad contact hole 164a is formed in the gate pad area GPA by etching the gate insulating layer 142 corresponding to the first gate pad 134a.

A second metal layer 150 is formed on the gate insulating layer 142 including the active layer 124 and the first gate pad contact hole 164a. The second metal layer 150 may be formed as a triple layer like the first to third sub-metal layers 150a, 150b and 150c. The first and third sub-metal layers 150a and 150c may be formed of molybdenum (Mo), and the second sub-metal layer 150b may be formed of aluminum-nidium (AlNd).

The second metal layer 150 is selectively etched to form the data line 112 shown in FIG. 5 and the source and drain electrodes 126a and 126b shown in FIG. 7C, the first data pad 132a, Two gate pads 132b are formed.

In the thin film transistor region TA, a thin film transistor 118 composed of a gate electrode 122, a gate insulating layer 142, an active layer 124, and source and drain electrodes 126a and 126b is formed. The source and drain electrodes 126a and 126b are connected to one end and the other end of the active layer 124, respectively. The source and drain electrodes 126a and 126b are spaced apart from each other with the channel region CH of the active layer 124 therebetween. Then, the second amorphous silicon layer 144b in the channel region CH is etched. The source electrode 126a is connected to the data line 112 and a part of the source electrode 126a has a first protrusion 192 protruding to an adjacent pixel area PA as shown in Fig. As shown in FIG. 5, the drain electrode 126b is connected to the photodiode 120. FIG.

 The first data pad 132a is formed in the data pad area DPA by patterning the second metal layer 150 and the first data pad 132a is formed in the gate pad area GPA through the first gate pad contact hole 164a. A second gate pad 134b connected to the first gate pad 134a is formed.

An interlayer insulating layer 180 is formed on the gate insulating layer 142 including the source and drain electrodes 126a and 126b, the first data pad 132a and the second gate pad 134b, A drain contact hole 182 is formed to selectively expose the drain electrode 126b. The interlayer insulating layer 180 may be formed of silicon oxide or silicon nitride.

A third metal layer (not shown) is formed on the interlayer insulating layer 180 including the drain contact hole 182 and the third metal layer is selectively etched to form the drain contact hole 182 The lower electrode 154 of the photodiode 120 of FIG. 6 connected to the drain electrode 126b is formed in the photodiode region DIA. 5, the photodiode 120 has a first depression 194 corresponding to the protrusion 192 of the source electrode 126a. The lower electrode 154 may be formed of a metal such as molybdenum (Mo).

An n-type silicon layer (not shown), an intrinsic silicon layer (not shown), a p-type silicon layer (not shown) are formed on the interlayer insulating layer 180 including the lower electrode 154, , And a transparent conductive material layer (not shown) are sequentially stacked. Then, the transparent conductive material layer is selectively etched to form the upper electrode 156 of the photodiode 120 shown in FIG. The upper electrode 156 is formed on an upper substrate (not shown) facing the array substrate 110 and increases the light reaching efficiency from a scintillator that is irradiated with X-rays to convert wavelengths (Indium tin oxide), indium zinc oxide (IZO), or the like. Subsequently, the N-type silicon layer, the intrinsic silicon layer, and the P-type silicon layer are selectively etched to form the photoconductor layer 152 of the photodiode 120 shown in FIG.

7D and 7E, the lower electrode 154 connected to the drain electrode 126b of the thin film transistor 118, the photoconductor layer 152 on the lower electrode 154 and the photoconductor layer 152 on the photoconductor layer 152 A photodiode 120 composed of an upper electrode 156 is formed. The photoconductor layer 152 includes an N-type semiconductor layer 152a containing an N-type impurity, an intrinsic semiconductor layer 152b containing no impurity, and a P-type semiconductor layer 152c containing a P-type impurity .

The first passivation layer 158 is formed on the interlayer insulating layer 180 including the photodiode 120 as shown in FIG. A first contact hole 160 for selectively etching the first passivation layer 158 and the interlayer insulating layer 180 to expose the protrusion 192 of the source electrode 126a, A second gate contact hole 164b exposing the second gate pad 134b and a first data pad contact hole 164b exposing the first data pad 132a, (166a).

The first passivation layer 158 may be formed of an inorganic or organic insulating material. The inorganic insulating material may be silicon oxide or silicon nitride. The first passivation layer 158 includes a first contact hole 160 and a bias wiring 170 and an upper electrode 156 for connecting the readout wiring 168 of FIG. 5 and the protruding portion 192 of the source electrode 126a. The second contact holes 162 are formed to have a thickness of about 4000 ANGSTROM or more thick enough to ensure the reliability of the second contact holes 162.

A first passivation layer 158 and an interlayer insulating layer 180 are formed on the source electrode 126a, the first data pad 132a and the second gate pad 134b, and the upper part of the photodiode 120 An interlayer insulating layer 180 is formed on the electrode 156. Accordingly, when the second contact hole 162 is formed, the interlayer insulating layer 180 is formed in the first contact hole 160, the second gate pad contact hole 164b, and the first data pad contact hole 166a, The upper electrode 156 located under the interlayer insulating layer 180 may be damaged. Accordingly, an end point detector (not shown) may be used to prevent damage to the upper electrode 156. [

The end point detector used in the present invention can detect molybdenum (Mo). 7B, the first metal layer 150 is composed of a triple layer like the first to third sub-metal layers 150a, 150b and 150c, and the third sub-metal layer 150c located on the uppermost layer is composed of molybdenum (Mo) . The source electrode 126a, the second gate pad 134b and the first data pad 132a are formed by selective etching of the first metal layer 150 as shown in FIG. 7C.

Although not shown in detail in the drawings, when the end point detector is provided in the etching apparatus and the first passivation layer 158 and the interlayer insulating layer 180 are etched, the first contact hole 160, The first data pad contact hole 164a and the first data pad contact hole 166a are formed on the uppermost layer of the source electrode 126a, the second gate pad 134b and the first data pad 132a, Molybdenum (Mo), which is a constituent material of the first electrode 150c, starts to be detected.

When molybdenum (Mo) is detected in the end point detector, the source electrode 126a of the lower portion of the first contact hole 160, the second gate pad contact hole 164b and the first data pad contact hole 166a, The pad 134b and the first data pad 132a are completely exposed, and the etching process is stopped. Therefore, when the second contact hole 162 is formed, the interlayer insulating layer 180 is excessively etched to prevent the upper electrode 156 located under the interlayer insulating layer 180 from being damaged.

7G, on the first passivation layer 158 including the first and second contact holes 160 and 162, the second gate pad contact hole 164b, and the first data pad contact hole 166a, A read-out line 168 connected to the protruding portion 192 of the source electrode 126a through the first contact hole 160, and a fourth metal layer (not shown) A bias line 170 connected to the upper electrode 156 of the photodiode 120 through the second contact hole 162 and a second gate pad 134b through the second gate pad contact hole 164b. And a first data pad electrode 174a connected to the data pad 132 through a data pad contact hole 166. The first data pad electrode 174a is connected to the data pad 132 through the first gate pad electrode 172a.

7H, the first passivation layer 158 corresponding to the central portion of the photodiode 120 is etched. The first passivation layer 158 includes a first contact hole 160 connecting the readout wiring 168 and the source electrode 126a of FIG. 6 and a second contact hole 160 connecting the bias wiring 170 and the upper electrode 156, Is formed to have a thickness of about 4000 ANGSTROM or more thick enough to ensure the reliability of the hole 162. [ Thus, due to the first passivation layer 158, the light efficiency delivered to the photoconductor layer 152 can be reduced. Accordingly, the first passivation layer 158 is etched to form the light transmitting region 178 in order to prevent a decrease in light efficiency.

The first passivation layer 158 corresponding to the photodiode 120 includes a central portion 157a and a peripheral portion 157b including the bias wiring 170 and a first passivation layer 158 for improving light efficiency, The central portion 157a of the second semiconductor layer 157 is etched to a predetermined depth. Therefore, the thickness of the central portion 157a of the first protective layer 158 is much thinner than the thickness of the peripheral portion 157b.

A second passivation layer 158 is formed on the first passivation layer 158 including the readout wiring 168, the bias wiring 170, the first gate electrode 174a and the first data pad electrode 172a, A third gate pad contact hole 164c and a first data pad electrode 172a exposing the first gate pad electrode 174a are selectively formed by selectively etching the second passivation layer 176 Thereby forming a second gate pad contact hole 166b.

A transparent conductive material layer (not shown) is formed on the second passivation layer 176 including the third gate pad contact hole 164c and the second gate pad contact hole 166b, A second gate pad electrode 174b connected to the first gate pad electrode 174a and a second data pad electrode 172b connected to the first data pad electrode 172a are formed. The second gate and data pad electrodes 172b and 174b use ITO or ZTO, which is a transparent conductive material, to prevent corrosion of the first gate and data pad electrodes 172a and 174a.

It will be apparent that the present invention is not limited to the above-described embodiments, and various modifications and changes may be made without departing from the spirit and scope of the present invention.

1 is a plan view of an array substrate for an X-

2 is a cross-sectional view of an array substrate according to the related art

FIGS. 3A to 3G are process sectional views showing steps of a method of manufacturing an array substrate according to the prior art

Figs. 4A and 4B are process sectional views showing steps of a method of manufacturing an array substrate according to another example of the related art

5 is a plan view of an array substrate for an X-ray detector according to an embodiment of the present invention.

6 is a cross-sectional view of an array substrate for an X-

7A to 7I are sectional views of the steps of a method of manufacturing an array substrate according to the prior art,

Claims (18)

A plurality of pixel regions formed on a substrate and defined in a matrix form by intersection of a plurality of gate lines and a plurality of data lines; A plurality of gate electrodes disposed in each of the plurality of pixel regions and connected to each of the plurality of gate wirings, a plurality of active layers on each of the plurality of gate electrodes, one end of each of the plurality of active layers, A plurality of thin film transistors including a plurality of source electrodes connected to the plurality of data lines and having protrusions protruding to the other side of each of the plurality of data lines, and a plurality of drain electrodes connected to the other ends of each of the plurality of active layers; A plurality of photodiodes coupled to each of the plurality of drain electrodes; A plurality of bias lines for applying a bias voltage to the plurality of photodiodes; A plurality of read lines connected to the projections of each of the plurality of source electrodes; / RTI > Wherein each of the plurality of photodiodes includes a first depression corresponding to the protrusion of each of the plurality of source electrodes and each of the plurality of pixel regions has a second depression corresponding to the protrusion of each of the plurality of source electrodes Array substrate for x-ray detector. delete The method according to claim 1, Wherein each of the plurality of bias wirings includes a wiring portion and a contact region which is in contact with each of the plurality of photodiodes and has a wider width than the wiring portion. The method of claim 3, Wherein the wiring portion and the contact region extend in the same straight line on one side of the plurality of bias wirings facing the plurality of data wirings and the contact region on the other side of the plurality of bias wirings opposite to the one side, Ray detector array. The method according to claim 1, And the plurality of bias wirings shield the plurality of gate electrodes. The method of claim 1, wherein Ray detector in which a protective layer is disposed on the plurality of photodiodes and a light transmitting region having a thickness thinner than a thickness of the protective layer corresponding to a peripheral portion of each of the plurality of optical multi- Array substrate. The method according to claim 1, An array substrate for an X-ray detector, comprising: a plurality of gates and data pads connected to the plurality of gates and data lines and having a plurality of gates and data pad electrodes formed of transparent conductive material on the plurality of gates and data pads; . The method according to claim 1, Wherein each of the plurality of photodiodes includes a lower electrode connected to each of the plurality of drain electrodes, a photoconductor layer positioned on the lower electrode, and an upper electrode formed on the photoconductor layer, And each wiring is connected to the upper electrode. Forming a plurality of gate wirings formed on a substrate and a plurality of gate electrodes connected to the plurality of gate wirings; Forming a gate insulating layer on the substrate including the plurality of gate wirings and the plurality of gate electrodes; A plurality of data lines, one end of each of the plurality of data lines, and one end of each of the plurality of active layers, and a plurality of data lines, each of the plurality of data lines, Forming a plurality of source electrodes having projections protruding to the other side and a plurality of drain electrodes connected to the other ends of each of the plurality of active layers; Forming a plurality of bias wirings connected to each of the plurality of photodiodes and a plurality of read wirings connected to each of the plurality of source electrodes; / RTI > Each of the plurality of photodiodes including a first depression corresponding to the protrusion of each of the plurality of source electrodes, Wherein the plurality of gate electrodes and the data lines are orthogonal to each other to define a plurality of pixel regions where each of the plurality of photodiodes is located and each of the plurality of pixel regions includes a second recess corresponding to the protrusion of each of the plurality of source electrodes Ray detector array substrate having an X-ray detecting portion. 10. The method of claim 9, Forming an interlayer insulating layer on the gate insulating layer including the plurality of data lines and the plurality of source and drain electrodes; Forming a plurality of drain contact holes exposing each of the plurality of drain electrodes by selectively etching the interlayer insulating layer; Forming the plurality of photodiodes connected to the plurality of drain electrodes through the plurality of drain contact holes on the interlayer insulating layer; The method comprising the steps of: forming an array substrate on a substrate; 11. The method of claim 10, Forming a plurality of lower electrodes connected to each of the plurality of drain contact holes on the interlayer insulating layer; Forming a transparent conductive material layer on the silicon layer and the silicon layer on the interlayer insulating layer including the plurality of lower electrodes; Patterning the transparent conductive material layer and the silicon layer to form a plurality of upper electrodes and a plurality of photoconductor layers; The method comprising the steps of: forming an array substrate on a substrate; 11. The method of claim 10, Forming a protective layer on the interlayer insulating layer including the plurality of photodiodes; Forming a plurality of first contact holes through which the plurality of source electrodes are exposed and a plurality of second contact holes through which the plurality of photodiodes are exposed by selectively etching the passivation layer and the gate insulating layer, ; Forming a plurality of bias lines connected to the plurality of photodiodes through the plurality of read lines and the plurality of second contact holes connected to the plurality of source electrodes through the plurality of first contact holes, step; The method comprising the steps of: forming an array substrate on a substrate; 13. The method of claim 12, Wherein each of the plurality of bias wirings includes a wiring portion and a contact region corresponding to each of the plurality of second contact holes, and the width of the contact region is larger than that of the wiring portion . 14. The method of claim 13, Wherein the wiring portion and the contact region extend in the same straight line on one side of the plurality of bias wirings facing each of the plurality of data wirings and on the other side of each of the plurality of bias wirings opposite to the one side, Is protruded from the wiring portion. 13. The method of claim 12, Wherein the plurality of source electrodes are formed of a metal layer including molybdenum on the uppermost layer, the plurality of upper electrodes are formed of ITO or ZTO, and the passivation layer and the interlayer insulating layer are dry-etched to form the plurality of first and second contacts Wherein the dry etching is stopped when the molybdenum is detected in the end point detector in the step of forming the hole. 10. The method of claim 9, Forming a plurality of gates and data pads connected to each of the plurality of gates and data lines; Forming a plurality of first gate and data pad electrodes on each of the plurality of gates and data pads; Forming a plurality of second gates and data pad electrodes of ITO or ZTO on the plurality of first gate and data pad electrodes, respectively; Ray detector array substrate. delete The method of claim 9, wherein And forming a protective layer on the plurality of photodiodes, wherein a thickness of the protective layer at the center of the plurality of photodiodes is thinner than a thickness of the protective layer at the periphery of the plurality of photodiodes. Wherein the method comprises the steps of:

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