JP2013026264A - Solid state image pickup sensor, solid state image pickup sensor manufacturing method, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device which can improve blooming characteristics.SOLUTION: A solid state image pickup device 30 comprises a photodiode 14 formed on the surface of a semiconductor substrate, a flat type and a vertical type gate electrode 16 and a floating diffusion 18. The vertical type gate electrode 16B is formed at a position where, when voltage is applied to the gate electrode 16 at electric charge storage time, a difference in potential height occurs in regions below the flat type gate electrode 16A on both sides across the vertical type gate electrode 16B in an effective gate width Wdirection.

Description

  The present technology relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus including the solid-state imaging device.

A technique for transferring charges accumulated in a buried photodiode (PD) formed in the depth direction in the vertical direction using a vertical transistor (Tr) as a transfer gate is disclosed (see Patent Document 1). In the configuration described in Patent Document 1, a reduction in the area of the PD can be reduced by disposing the vertical Tr on the outer periphery of the PD, and further, the loss of the saturation charge amount (Qs) can be reduced. In Patent Document 1, a plurality of vertical Tr formation positions, the number of formations, and the like are described.
In addition, a solid-state imaging device having a configuration that forms an overflow path for transferring a signal charge exceeding the saturation charge amount of the PD to the floating diffusion (FD) has been proposed (see Patent Document 2). The solid-state imaging device described in Patent Document 2 includes a vertical charge readout gate electrode, a transfer channel for transferring signal charges read from a PD, and an FD region for storing transferred signal charges. A vertical Tr is provided. In addition, an overflow path that connects between the PD and the FD region is formed during charge accumulation in the photodiode.

JP 2010-114273 A JP 2010-114275 A

  In the solid-state imaging device provided with the above-described vertical Tr, an improvement in blooming characteristics is generally required.

  The present technology provides a solid-state imaging device capable of improving blooming characteristics, a method for manufacturing the solid-state imaging device, and an electronic apparatus.

The solid-state imaging device of the present technology is formed on the periphery of the photodiode formed on the surface of the semiconductor substrate and the region where the photodiode is formed via the gate insulating film in the depth direction from the surface of the semiconductor substrate. A gate electrode. A floating diffusion for accumulating signal charges read from the photodiode is provided.
In this solid-state imaging device, a gate electrode includes a planar gate electrode formed on a semiconductor substrate, and a vertical gate electrode formed integrally with the planar gate electrode and formed in a depth direction from the semiconductor substrate. Become. In addition, when a voltage is applied to the gate electrode during charge accumulation, the vertical gate electrode generates a difference in potential height in the area under the planar gate electrode on both sides of the vertical gate electrode in the effective gate width direction. It is formed in the position to do.
An electronic device of the present technology includes the solid-state imaging device, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device.

The solid-state imaging device manufacturing method of the present technology includes a step of forming a photodiode on the surface of the semiconductor substrate, a step of forming a gate electrode around the photodiode formation region, and a floating diffusion on the surface of the semiconductor substrate. Forming the step.
The step of forming the gate electrode includes the step of forming a trench in the semiconductor substrate, the formation of a conductor layer in the trench and on the surface of the semiconductor substrate, the formation of a vertical gate electrode in the trench, and the formation on the semiconductor substrate. Forming a planar gate electrode. The trench is formed at a position where a potential difference is generated in a region under the planar gate electrode on both sides sandwiching the vertical gate electrode in the effective gate width direction when a voltage is applied to the gate electrode during charge accumulation.

According to the solid-state imaging device and the solid-state imaging device manufactured by the manufacturing method, when a voltage is applied to the gate electrode, there is a difference in potential height between the semiconductor regions on both sides of the vertical gate electrode. Occur. For this reason, an overflow path is formed along the region where the potential is lowered, and the blooming characteristic of the solid-state imaging device is improved.
In addition, by applying the solid-state imaging device, an electronic device with less blooming can be configured.

  According to the present technology, it is possible to provide a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an electronic device that can improve blooming characteristics.

It is a top view which shows the structure of the principal part of a solid-state image sensor. It is sectional drawing which shows the structure of the principal part of a solid-state image sensor. It is a figure which shows the potential gradient of a solid-state image sensor by a contour-line display. It is a figure which shows the potential cross section of the gate length direction of a solid-state image sensor. It is a figure which shows the potential cross section of the effective gate width direction of a solid-state image sensor. It is a top view which shows the structure of the principal part of a solid-state image sensor. It is a figure which shows the potential cross section of the effective gate width direction of a solid-state image sensor. It is a whole block diagram of the solid-state image sensor of the solid-state image sensor of 1st Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of 1st Embodiment. It is sectional drawing which shows the structure of the principal part of the solid-state image sensor of 1st Embodiment. It is a figure which shows the potential gradient of the solid-state image sensor of 1st Embodiment by a contour-line display. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of 1st Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 1 of 1st Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 1 of 1st Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 2 of 1st Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 2 of 1st Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 3 of 1st Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 3 of 1st Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of 2nd Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 1 of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 1 of 2nd Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 2 of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 2 of 2nd Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 3 of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 3 of 2nd Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 4 of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 4 of 2nd Embodiment. It is a top view which shows the structure of the principal part of the solid-state image sensor of the modification 5 of 2nd Embodiment. It is a figure which shows the potential cross section of the effective gate width direction of the solid-state image sensor of the modification 5 of 2nd Embodiment. A to C are process diagrams for explaining a manufacturing process of a solid-state imaging device. DF is process drawing for demonstrating the manufacturing process of a solid-state image sensor. It is a schematic block diagram of the electronic device to which a solid-state image sensor is applied.

Hereinafter, examples of the best mode for carrying out the present technology will be described, but the present technology is not limited to the following examples.
The description will be given in the following order.
1. 1. Overview of solid-state imaging device 1. First embodiment of solid-state imaging device 2. Second embodiment of solid-state imaging device 4. Manufacturing method of solid-state imaging device Electronics

<1. Overview of solid-state image sensor>
First, an outline of the solid-state image sensor will be described.
FIG. 1 shows a plan configuration diagram of a solid-state imaging device having a vertical transistor (Tr) as a transfer gate and having a photodiode (PD) formed on a substrate surface. FIG. 2 is a cross-sectional view of the solid-state imaging device shown in FIG.

The solid-state imaging device 10 shown in FIGS. 1 and 2 includes a second conductive type (n-type) semiconductor region 15 and a high-concentration second conductive type (n ⁺ -type) semiconductor region 13 from the back side of the semiconductor substrate 11. And a photodiode (PD) 14 formed of a first conductive type (p ⁺ type) semiconductor region 12 having a high concentration. The PD 14 is mainly composed of a PN junction between the n ⁺ type semiconductor region 13 and the p ⁺ type semiconductor region 12.

The solid-state imaging device 10 includes a vertical transistor (Tr) that reads the charge of the PD 14. The vertical Tr is composed of a transfer gate electrode 16 formed via a gate insulating film 17 and a floating diffusion (FD) region 18 for accumulating transferred signal charges.
The transfer gate electrode 16 includes a planar gate electrode 16A formed on the semiconductor substrate 11 and a vertical gate electrode 16B formed in a column shape in the depth direction from the surface of the semiconductor substrate 11 below the planar gate electrode 16A. Become.
The FD region 18 is composed of a high-concentration second conductivity type (n ⁺ -type) semiconductor region, and is formed on the surface of the semiconductor substrate 11 at a position facing the PD 14 with the transfer gate electrode 16 interposed therebetween.

  In the vertical transistor Tr, when a positive voltage is applied to the transfer gate electrode 16 at the time of reading, the potential (potential) immediately below the transfer gate electrode 16 changes. Then, the signal charge accumulated in the PD 14 passes through a region around the vertical gate electrode 16B of the transfer gate electrode 16 and is transferred to the FD region 18 for horizontal reading.

  In the solid-state imaging device 10 described above, when signal charges are accumulated in the PD 14, an area around the vertical gate electrode 16 </ b> B immediately below the transfer gate electrode 16 has an overflow path (OFP) that is a transfer path of excess charge. I also serve. The OFP is used as a path for transferring the signal charge (excess charge) in excess of the saturation charge amount of the PD 14 to the FD region 18 when the signal charge is accumulated in the PD 14. That is, if a negative voltage (about −1V) is applied to the transfer gate electrode 16 during the accumulation of signal charges in the PD 14, OFP is formed around the vertical gate electrode 16B, and the PD 14 and the FD 18 region are electrically connected. Connected.

The solid-state imaging device having the vertical Tr in the transfer gate having the configuration shown in FIGS. 1 and 2 has a higher modulation power with respect to the PD 14 than the transfer Tr having a normal planar gate electrode. For this reason, the PD 14 can be formed in a deep portion, and a large saturation signal amount Qs can be obtained.
However, since the vertical Tr has a strong modulation power, the potential of the overflow barrier becomes too high when a negative voltage is applied to the transfer gate electrode 16 during charge accumulation in the PD 14. As a result, a sufficient overflow path is not formed under the transfer gate electrode 16 and the blooming characteristic is deteriorated.

FIG. 3 shows the potential distribution on the plane of the vertical Tr in a state where a negative voltage is applied to the transfer gate electrode 16 by contour lines. FIG. 4 shows a potential cross section in the gate length L direction at the position where the OFP 19 is formed under the transfer gate electrode 16. FIG. 5 shows a potential cross section under the transfer gate electrode 16 in the effective gate width W _eff direction.

  In the configuration shown in FIG. 3, the vertical gate electrode 16B is arranged at the center of the vertical Tr (position on the vertical line from the center of gravity of the planar gate electrode 16A to the side of the planar gate electrode 16A on the PD side). Type Tr. In this configuration, an overflow path (OFP) 19 is formed on both sides of the vertical gate electrode 16B under the transfer gate electrode 16.

As shown in FIG. 4, when a negative voltage is applied to the transfer gate during charge accumulation in the PD, the charge transfer path under the transfer gate electrode 16 is affected by the potential applied to the vertical gate electrode 16B. The potential of the region becomes higher. This increased potential becomes an overflow barrier. In particular, in the vertical Tr, the potential of the region under the transfer gate electrode 16 increases toward the position where the vertical gate electrode 16B is formed. As described above, since the vertical Tr has a large modulation power with respect to the PD 17, the overflow barrier becomes too high as compared with a general Tr, and becomes an obstacle to overflow from the PD 14 to the FD 18.
Since the OFPs 19 on both sides of the vertical gate electrode 16B have the same distance from the vertical gate electrode 16B, they are both equipotential as shown in FIG.

  As described above, the potential below the transfer gate electrode 16 shown in FIG. 4 affects the potential height of the OFP 19 on both sides of the vertical gate electrode 16B when a negative voltage is applied to the transfer gate electrode 16. In the solid-state imaging device including the vertical Tr, the potential of the OFP 19 formed on both sides of the vertical gate electrode 16B becomes too high, so that it is difficult for the excess charge to overflow satisfactorily and the blooming characteristics are deteriorated.

In the configuration described in Patent Document 1 described above, vertical charge transfer is performed from the embedded PD to the FD using the vertical Tr. For this reason, unlike the configuration in which the movement path of excess charges is read out in the lateral direction, it is not possible to obtain an advantage in the technique for forming the overflow path.
Therefore, there is a demand for a solid-state imaging device that includes a vertical Tr and performs horizontal readout so that excess charges can easily overflow from PD to FD.

  In order to form a favorable OFP, for example, it is conceivable that the overflow barrier is lowered by decreasing the potential of the region under the transfer gate electrode 16 by increasing the dose of the n-type impurity immediately below the transfer gate electrode 16. However, when the dose amount of the n-type impurity below the transfer gate electrode 16 is increased, phenomena such as an increase in the transfer barrier and an increase in the number of electrons trapped in the transfer gate electrode 16 are induced as a solid-state imaging device. There is a fear.

Therefore, the present disclosure proposes a configuration in which the potential height is different in the regions on both sides in the effective gate width W _eff direction of the vertical gate electrode in the configuration in which the potential is transferred in the lateral direction from the PD to the FD. . With this configuration, a structure in which excess charges are efficiently discharged to the FD while utilizing the transfer capability of the vertical Tr can be obtained.
As a specific example of such a configuration, as shown in FIG. 6, the center of the vertical gate electrode is the center of the vertical Tr of the gate electrode 16B (from the center of gravity of the planar gate electrode 16A to the PD side of the planar gate electrode 16A). The position is shifted from the position on the vertical line to the side.

FIG. 7 shows a potential cross section when a negative potential is applied to the vertical Tr having a configuration in which the vertical Tr shown in FIG. 6 is shifted from the center of the normal transfer gate electrode 16 by + X along the effective gate width W _eff direction. Indicates.
By causing the vertical Tr to be unevenly distributed to one side along the effective gate width W _eff direction, a potential difference is generated on both sides of the vertical gate electrode 16B, and the other potential is lowered. Here, the potential under the transfer gate electrode 16 decreases at a position opposite to the + X direction (−X direction). This means that the overflow barrier is lowered at the position where the potential is lowered. Accordingly, the OFP 19 is likely to be formed at a position where the potential is lowered.

  Since the OFP 19 is formed by forming the OFP with the configuration of the transfer gate electrode 16 as described above, it is not necessary to consider the impurity dose for the overflow of excess charge, so that the dose below the transfer gate electrode 16 can be reduced. It becomes. By reducing the dose, the transfer barrier can be reduced and the number of electrons trapped under the transfer gate electrode 16 can be reduced. Therefore, improvement in linear characteristics can be expected.

In the present disclosure, in the gate length direction below the transfer gate electrode 16, the position where the potential is highest in the gate length L direction is connected in the gate width direction in a state where a negative voltage is applied to the transfer gate during charge accumulation. The length is an effective gate width W _eff . Then, the direction along this effective gate width _{W eff} the effective gate width _{W eff} direction.

<2. First Embodiment of Solid-State Image Sensor>
[Configuration example of solid-state imaging device: schematic configuration diagram]
Hereinafter, specific embodiments of the solid-state imaging device of the present embodiment will be described.
FIG. 8 shows a schematic configuration diagram of a MOS (Metal Oxide Semiconductor) type solid-state imaging device as an example of the solid-state imaging device.

  A solid-state imaging device 40 shown in FIG. 8 includes a pixel portion (so-called imaging region) 43 in which pixels 42 including photodiodes serving as a plurality of photoelectric conversion units are regularly arranged two-dimensionally on a semiconductor substrate, for example, a silicon substrate. And a peripheral circuit section. The pixel 42 includes a photodiode and a plurality of pixel transistors (so-called MOS transistors).

  The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors.

  The peripheral circuit section includes a vertical drive circuit 44, a column signal processing circuit 45, a horizontal drive circuit 46, an output circuit 47, a control circuit 48, and the like.

  The control circuit 48 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 44, the column signal processing circuit 45, the horizontal drive circuit 46, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The control circuit 48 inputs these signals to the vertical drive circuit 44, the column signal processing circuit 45, the horizontal drive circuit 46, and the like.

  The vertical drive circuit 44 is configured by a shift register, for example. The vertical drive circuit 44 selectively scans each pixel 42 of the pixel unit 43 in the vertical direction sequentially in units of rows, and a pixel based on a signal charge generated according to the amount of light received by the photoelectric conversion element of each pixel 42 through the vertical signal line 49. The signal is supplied to the column signal processing circuit 45.

  The column signal processing circuit 45 is arranged for each column of the pixels 42, for example, and outputs a signal output from the pixels 42 for one row from the black reference pixel (formed around the effective pixel region) for each pixel column. To perform signal processing such as noise removal. That is, the column signal processing circuit 45 performs signal processing such as CDS (correlated double sampling) for removing fixed pattern noise unique to the pixel 42 and signal amplification. At the output stage of the column signal processing circuit 45, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 41.

The horizontal drive circuit 46 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 45 in order, and outputs a pixel signal from each of the column signal processing circuits 45 to the horizontal signal line. 41 is output.
The output circuit 47 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 45 through the horizontal signal line 41.

  When the above-described solid-state imaging device 40 is applied to a back-illuminated solid-state imaging device, a wiring layer is not formed on the back surface on the light incident surface (so-called light receiving surface) side, and the wiring layer is opposite to the light receiving surface. It is formed on the surface side.

[Configuration Example of Solid-State Image Sensor: Pixel Unit]
Next, FIG. 9 shows a plan view of a main part constituting one pixel of the solid-state imaging device of the present embodiment. FIG. 10 is a cross-sectional view taken along line AA of the solid-state imaging device shown in FIG. The solid-state imaging device shown in FIGS. 9 and 10 has the same configuration as the solid-state imaging device shown in FIGS. 1 and 2 except for the configuration of the gate electrode. For this reason, the same code | symbol is attached | subjected to the structure similar to the solid-state image sensor of the structure shown in the above-mentioned FIG.1 and FIG.2, and detailed description is abbreviate | omitted.

  A solid-state imaging device 30 shown in FIG. 9 includes a photodiode (PD) 14 that is formed on a semiconductor substrate 11 and forms a pixel portion. In addition, the transfer transistor (Tr) is configured by the PD 14, the transfer gate electrode 16, and the floating diffusion (FD) 18 formed to extend from the corner on the gate electrode side of the PD to the outside region.

The semiconductor substrate 11 is composed of a first conductivity type (p-type) silicon substrate or the like. Then, from the back surface (light incident surface) side of the semiconductor substrate 11, the second conductive type (n-type) semiconductor region 15, the high concentration second conductive type (n ⁺ type) semiconductor region 13, and the high concentration A photodiode (PD) 14 is formed by the first conductivity type (p ⁺ -type) semiconductor region 12. The PD 14 is mainly composed of a PN junction between the n ⁺ type semiconductor region 13 and the p ⁺ type semiconductor region 12.

  As shown in FIG. 10, the PD 14 is formed in a substantially rectangular shape, and is partitioned for each pixel by a pixel isolation region constituted by a p-type semiconductor substrate 11. In the present description, the PD 14 has a rectangular shape, but is not limited to this, and may have various shapes such as a square shape and a polygonal shape. In the plan view shown in FIG. 9, the region where the photodiode is formed in the pixel isolation region is shown as PD14.

The FD region 18 is formed of a high-concentration second conductivity type (n ⁺ -type) semiconductor region, and is formed at a position facing the PD 14 with the transfer gate electrode 16 in between. The FD region 18 is formed in a region on the surface side of the semiconductor substrate 11 so as to extend outward from the corner of the PD 14 adjacent to the transfer gate electrode 16.

One transfer gate electrode 16 is formed on the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 16 is formed integrally with the planar gate electrode 16A formed on the semiconductor substrate 11 and the planar gate electrode 16A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a vertical gate electrode 16B.
The planar gate electrode 16A is formed in a substantially triangular shape with a corner portion of the PD 14 having a long side facing the PD 14 side dropped. The vertical gate electrode 16 </ b> B is formed with a circular planar shape on the surface of the semiconductor substrate 11. The vertical gate electrode 16B is formed in such a size that it does not become the entire surface under the planar gate electrode 16A.

  The planar gate electrode 16A is formed in a region extending from the corner of the PD 14 to the FD 18. The vertical gate electrode 16B is formed through the gate insulating film 17 from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. ing.

Further, the vertical gate electrode 16B is formed at a position where a difference occurs between the gate widths on both sides of the vertical gate electrode 16B in the effective gate width W _eff direction indicated by an arrow in FIG.
As described above, as a configuration in which the gate width is different on both sides of the vertical gate electrode 16B in the effective gate width W _eff direction, the center of the vertical gate electrode 16B and the center of the effective gate width W _eff are different from each other. Thus, the vertical gate electrode 16B is formed at a position shifted in the effective gate width W _eff direction.

Specifically, the vertical gate electrode 16B is formed so that the center of the planar gate electrode 16A and the center of the vertical gate electrode 16B are at different positions in the effective gate width W _eff direction. In FIG. 9, the vertical gate electrode 16B is moved by + X in the effective gate width W _eff direction from the center of the planar gate electrode 16A. Therefore, the gate width W _{−X in the} −X direction is larger than the gate width W _{+ X in} the + X direction of the vertical gate electrode 16B on both sides in the effective gate width W _eff direction of the vertical gate electrode 16B.

The center of the planar gate electrode 16A is a position on a perpendicular line from the center of gravity of the planar gate electrode 16A to the side of the planar gate electrode 16A on the PD side. The center of the planar gate electrode 16A is located on a line in the channel length direction (center line of the channel width) passing through the center of the channel width of the vertical Tr. For example, in the shape of the planar gate electrode 16A shown in FIG. 9, the perpendicular to the side on the PD 14 side that passes through the center of gravity of the planar gate electrode 16A is the center line of the channel width of the vertical Tr.
That is, the vertical gate electrode 16B is formed at a position deviated from the center in the gate width direction of the transfer channel formed under the transfer gate electrode 16 to one side in the gate width direction. As shown in FIG. 9, the center of the vertical gate electrode 16B is the center of the circle when the planar shape of the vertical gate electrode 16B is circular, and the plane when the planar shape of the other polygons is other than that. It can be the center of gravity of the shape.

[Operation]
In the vertical transistor Tr configured as described above, a positive voltage is applied to the transfer gate electrode 16 during reading, whereby the potential (potential) immediately below the transfer gate electrode 16 changes. Then, the signal charge accumulated in the PD 14 passes through the region on the side surface of the vertical gate electrode 16B of the transfer gate electrode 16 and is transferred to the FD region 18 for horizontal reading.

First, when light is irradiated on the solid-state imaging device, the light condensed by an optical unit such as an on-chip lens (not shown) enters the PD 14 in the semiconductor substrate 11. The light incident on the PD 14 is photoelectrically converted at the n ⁺ type semiconductor region 13 or the PN junction portion between the n ⁺ type semiconductor region 13 and the p ⁺ type semiconductor region 12 to generate a signal charge. The generated signal charge is accumulated in a potential well formed in the PD 14. When the signal charge is accumulated, a negative voltage is applied to the transfer gate electrode 16.

FIG. 11 shows the potential distribution generated under the PD 14, the FD 18, and the transfer gate electrode 16 in a state where a negative voltage is applied to the transfer gate electrode 16, with contour lines. FIG. 12 shows a potential cross section under the transfer gate electrode 16 in the effective gate width W _eff direction.
As shown in FIGS. 11 and 12, when a negative voltage is applied to the transfer gate electrode 16, the potential in the region under the transfer gate electrode 16 increases due to the potential applied to the vertical gate electrode 16 </ b> B. In particular, the potential of the region under the transfer gate electrode 16 increases toward the position where the vertical gate electrode 16B is formed.

At this time, by moving the formation position of the vertical gate electrode 16B from the center of the planar gate electrode 16A in the effective gate width W _eff direction, the effective gate width W _{eff on} both sides of the vertical gate electrode 16B is different. . The difference in distance from the vertical gate electrode 16B causes a difference in potential on both sides of the vertical gate electrode 16B in the region below the planar gate electrode 16A.

In FIG. 11, by moving the vertical gate electrode 16B by + X, as shown in FIG. 12, the region potential on the side of the gate width W _{+ X in the} + X direction where the distance from the vertical gate electrode 16B is reduced becomes higher. Further, the potential of the region on the side of the gate width W− _{X in the} −X direction, which is located away from the vertical gate electrode 16B, is lowered.

As described above, by shifting the position of the vertical gate electrode 16B from the center of the transfer gate electrode 16, the potential of a part of the region in the effective gate width W _eff direction can be lowered. Then, excess charge overflows from the PD 14 to the FD 18 along the region where the potential formed on the gate width W- _X side decreases. That is, an overflow path (OFP) 19 is formed in the region on the gate width W− _X side in the −X direction, and excess charge accumulated in the PD through the OFP 19 is likely to overflow to the FD. For this reason, the blooming characteristic of the solid-state imaging device 30 is improved.

The formation position of the vertical gate electrode 16B is the vertical center of the gate electrode 16B and the center of the effective gate width W _eff is different positions, and, the vertical gate electrode 16B in the center of the effective gate width W _eff It is preferable that the position is in contact. Alternatively, the position is preferably in contact with the center line of the planar gate electrode 16A and the vertical gate electrode 16B. If the formation position of the vertical gate electrode 16B is too far from the center of the effective gate width W _{eff or} the center of the planar gate electrode 16A, the distance between the end of the PD 14 on the opposite side to the moving direction of the vertical gate electrode 16B is increased. Too much. For this reason, when a positive voltage is applied to the transfer gate electrode to read out the charge, the charge transfer efficiency from the PD 14 is lowered.
Accordingly, the vertical gate electrode 16B is formed at a position where a potential difference is sufficiently generated in the regions on both sides of the vertical gate electrode 16B in the effective gate width W _eff direction and near the center of the effective gate width W _eff. It is preferable to form.

[Modification Example 1 of Solid-State Image Sensor: Gate Shape (Rectangle)]
Next, as a solid-state image sensor according to Modification 1 of the first embodiment, a configuration in the case where the shape of the gate electrode is different in the above-described solid-state image sensor will be described. In the following description, since the configuration other than the gate electrode is the same as that of the first embodiment, the same reference numerals are given and detailed description thereof is omitted. In addition, the cross-sectional view of the solid-state imaging device according to the first modification of the first embodiment is the same as the configuration shown in FIG. The same components as those shown in FIG. 10 will be described with the same reference numerals as those in FIG.

FIG. 13 is a plan view of the main part constituting one pixel of the solid-state imaging device of Modification 1 of the first embodiment. FIG. 14 shows a potential cross section in the effective gate width W _eff direction of the region under the transfer gate electrode 21 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 13, the solid-state imaging device 31 includes a transfer transistor (Tr) that includes a photodiode (PD) 14, a transfer gate electrode 21, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  One transfer gate electrode 21 is formed at the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 21 is formed integrally with the planar gate electrode 21A formed on the semiconductor substrate 11 and the planar gate electrode 21A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a vertical gate electrode 21B.

  The planar gate electrode 21A is formed in a rectangular shape whose long side is in contact with the PD 14 and the FD 18 side at the corner of the PD 14, and the vertical gate electrode 21B is formed in a square shape on the surface of the semiconductor substrate 11. . The vertical gate electrode 21B is formed in a size that does not cover the entire surface under the planar gate electrode 21A.

  The planar gate electrode 21A is formed in a region extending from the corner of the PD 14 to the FD 18. The vertical gate electrode 21B is formed through the gate insulating film 17 from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. ing.

The vertical gate electrode 21B is formed at a position shifted in the effective gate width W _eff direction so that the center of the vertical gate electrode 21B and the center of the effective gate width W _eff are different. For this reason, in the effective gate width W _eff direction indicated by an arrow in FIG. 13, the gate width is formed at a position where a difference in gate width occurs on both sides of the vertical gate electrode 21B.

In FIG. 13, the vertical gate electrode 21B is configured to move −X from the center of the planar gate electrode 21A in the effective gate width W _eff direction. Therefore, the gate width W _{+ X in the} + X direction is larger than the gate width W _{−X in} the −X direction of the vertical gate electrode 21B on both sides in the effective gate width W _eff direction of the vertical gate electrode 16B.

The center of the planar gate electrode 21A passes through the center of gravity of the planar gate electrode 21A and is located on a perpendicular line from the side on the FD 18 side to the side on the PD 14 side of the planar gate electrode 21A. The center of the planar gate electrode 21A is located on a line in the channel length direction (center line of the channel width) passing through the center of the channel width of the vertical Tr. For example, in the case of the rectangular planar gate electrode 21A shown in FIG. 13, the perpendicular from the long side on the FD 18 side to the long side on the PD 14 side passing through the center of gravity of the planar gate electrode 21A is the center of the channel width of the vertical Tr Is a line.
The center of the vertical gate electrode 21B is the center of gravity of the planar shape.

With the above configuration, by shifting the formation position of the vertical gate electrode 21B in the effective gate width W _eff direction from the center of the planar gate electrode 21A, both sides of the effective gate width W _eff of the vertical gate electrode 21B is different configurations .
With this configuration, as shown in FIG. 14, the region potential on the side of the gate width W− _{X in the} −X direction, which is close to the vertical gate electrode 21B, is increased. Further, the potential of the region on the side of the gate width W _{+ X in the} + X direction, which is far from the vertical gate electrode 21B, becomes low.

As described above, when the distance from the vertical gate electrode 21B is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. An overflow path (OFP) is formed along the region of the gate width W _{+ X} side where the potential is lowered, and excess charge accumulated in the PD 14 is easily overflowed to the FD 18 through this OFP. For this reason, the blooming characteristic of the solid-state image sensor 31 is improved.

[Modification Example 2 of Solid-State Image Sensor: Gate Shape (L-shaped)]
Next, a solid-state imaging device according to Modification 2 of the first embodiment will be described. In the following description, since the configuration other than the gate electrode is the same as that of the first embodiment, the same reference numerals are given and detailed description thereof is omitted. Moreover, since the cross-sectional view of the solid-state imaging device of the second modification of the first embodiment is the same as the configuration shown in FIG. 10 described above, the illustration is omitted. The same components as those shown in FIG. 10 will be described with the same reference numerals as those in FIG.

FIG. 15 is a plan view of the main part constituting one pixel of the solid-state imaging device of Modification 2 of the first embodiment. FIG. 16 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 22 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 15, the solid-state imaging device 32 includes a photodiode (PD) 14, a transfer gate electrode 22, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11 to form a transfer transistor (Tr). .

  The transfer gate electrode 22 is formed in a substantially L shape that is a peripheral portion of the PD 14 and includes two rectangles along two sides sandwiching the corner portion. The transfer gate electrode 22 is formed integrally with the planar gate electrode 22A formed on the semiconductor substrate 11 and the planar gate electrode 22A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a vertical gate electrode 22B. The vertical gate electrode 22B is formed so that the planar shape on the surface of the semiconductor substrate 11 is substantially elliptical and does not become the entire surface under the planar gate electrode 22A.

The planar gate electrode 22A is formed in a region extending from the corner of the PD 14 to the FD 18. The vertical gate electrode 22B is formed through the gate insulating film 17 from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. ing.
In the planar L-shaped transfer gate electrode 22, as indicated by an arrow in FIG. 15, the effective gate width W _eff passes over the vertical gate electrode 22B and is provided along the L-shape of the planar gate electrode 22A.

Vertical gate electrode 22B, as the center of the vertical gate electrode 22B and the center of the effective gate width W _eff is different positions, are formed at positions shifted in the effective gate width W _eff direction. Therefore, the vertical gate electrode 22B is formed at a position where there is a difference in gate width on both sides of the vertical gate electrode 22B along the effective gate width W _eff direction.

In FIG. 15, the vertical gate electrode 22B is configured to move −X from the center of the planar gate electrode 22A in the effective gate width W _eff direction. Therefore, the gate width W _{+ X in the} + X direction is larger than the gate width W _{−X in} the −X direction of the vertical gate electrode 22B on both sides in the effective gate width W _eff direction of the vertical gate electrode 16B.

The center of the planar gate electrode 22A is located on a straight line connecting the centroid of the planar gate electrode 22A and the centroid of the PD. The center of the planar gate electrode 22A is located on a line in the channel length direction (center line of the channel width) passing through the center of the channel width of the vertical Tr. For example, in the case of the L-shaped planar gate electrode 22A shown in FIG. 15, the line that passes through the center of gravity of the planar gate electrode 22A and serves as the axis of line symmetry is the center line of the channel width of the vertical Tr.
The center of the vertical gate electrode 22B is a middle point that is the intersection of the major and minor axes of the plane ellipse.

With the above configuration, the gate width on both sides of the vertical gate electrode 22B is different by shifting the formation position of the vertical gate electrode 22B from the center of the planar gate electrode 22A in the effective gate width W _eff direction.
With this configuration, as shown in FIG. 16, in the effective gate width W _eff direction, the region potential on the gate width W _−X side in the −X direction where the distance from the vertical gate electrode 22B is short increases. Further, in the effective gate width W _eff direction, the potential of the region on the gate width W _{+ X} side in the + X direction that is far from the vertical gate electrode 22B becomes low.

As described above, when the distance from the vertical gate electrode 22B is different, the potential of a part of the region in the region in the effective gate width W _eff direction can be lowered. An overflow path (OFP) is formed along the position where the potential on the gate width W _{+ X} side decreases, and excess charge accumulated in the PD 14 is likely to overflow to the FD 18 through this OFP. For this reason, the blooming characteristic of the solid-state imaging device 32 is improved.

[Modification Example 3 of Solid-State Image Sensor: Gate Shape (L-shaped)]
Next, a solid-state imaging element according to Modification 3 of the first embodiment will be described. In the following description, since the configuration other than the gate electrode is the same as that of the first embodiment, the same reference numerals are given and detailed description thereof is omitted. In addition, the cross-sectional view of the solid-state imaging device of Modification 3 of the first embodiment is the same as the configuration shown in FIG. The same components as those shown in FIG. 10 will be described with the same reference numerals as those in FIG.

In FIG. 17, the top view of the principal part which comprises 1 pixel of the solid-state image sensor of the modification 3 of 1st Embodiment is shown. FIG. 18 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 23 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 17, the solid-state imaging device 33 includes a photodiode (PD) 14, a transfer gate electrode 23, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11 to form a transfer transistor (Tr). .

  The transfer gate electrode 23 is a peripheral portion of the PD 14 and is formed in a substantially L shape in which two rectangles each having a long side orthogonal to two sides sandwiching a corner portion are combined. The transfer gate electrode 23 is formed integrally with the planar gate electrode 23A formed on the semiconductor substrate 11 and the planar gate electrode 23A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a vertical gate electrode 23B. The vertical gate electrode 23B is formed so that the planar shape on the surface of the semiconductor substrate 11 is a rectangular shape and does not become the entire surface under the planar gate electrode 23A.

The planar gate electrode 23A is formed in a region extending from the corner of the PD 14 to the FD 18. The vertical gate electrode 23B is formed through the gate insulating film 17 from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. ing.
In the planar L-shaped transfer gate electrode 23, as indicated by an arrow in FIG. 17, the effective gate width W _eff passes along the vertical gate electrode 23B and is provided along the L-shape of the planar gate electrode 23A.

The vertical gate electrode 23B is formed at a position shifted in the effective gate width W _eff direction so that the center of the vertical gate electrode 23B and the center of the effective gate width W _eff are different. Therefore, the vertical gate electrode 23B is formed at a position where a difference occurs in the gate width on both sides of the vertical gate electrode 23B along the effective gate width W _eff direction.

In FIG. 17, the vertical gate electrode 23B is configured to move + X from the center of the planar gate electrode 23A in the effective gate width W _eff direction. Therefore, the gate width W _{−X in the} −X direction is larger than the gate width W _{+ X in} the + X direction of the vertical gate electrode 23B on both sides in the effective gate width W _eff direction of the vertical gate electrode 16B.

The center of the planar gate electrode 23A is located on a straight line connecting the centroid of the planar gate electrode 23A and the centroid of the PD 14. The center of the planar gate electrode 23A is located on a line in the channel length direction (center line of the channel width) passing through the center of the channel width of the vertical Tr. For example, in the case of the L-shaped planar gate electrode 23A shown in FIG. 17, the line that passes through the center of gravity of the planar gate electrode 23A and serves as the axis of line symmetry is the center line of the channel width of the vertical Tr.
The center of the vertical gate electrode 23B is the center of gravity of a planar rectangular shape.

With the above configuration, by shifting the formation position of the vertical gate electrode 23B from the center of the planar gate electrode 23A in the effective gate width W _eff direction, on both sides of the effective gate width W _eff of the vertical gate electrode 23B is different configurations .
With this configuration, as shown in FIG. 18, in the effective gate width W _eff direction, the region potential on the gate width W _{+ X} side in the + X direction where the distance from the vertical gate electrode 23B is short becomes high. Further, in the effective gate width W _eff direction, the potential of the region on the gate width W- _X side in the −X direction, which is far from the vertical gate electrode 23B, is lowered.

As described above, when the distance from the vertical gate electrode 23B is different, the potential of a part of the region in the region in the effective gate width W _eff direction can be lowered. An overflow path (OFP) is formed along the position where the potential on the gate width W- _X side decreases, and excess charge accumulated in the PD 14 is likely to overflow to the FD 18 through this OFP. For this reason, the blooming characteristic of the solid-state image sensor 33 is improved.

<3. Second Embodiment of Solid-State Image Sensor>
[Configuration Example of Solid-State Image Sensor: Pixel Unit]
Next, a second embodiment of the solid-state image sensor will be described. The second embodiment is a solid-state imaging device including a transfer gate electrode having a plurality of vertical gate electrodes.
FIG. 19 is a plan view of the main part constituting one pixel of the solid-state imaging device of the second embodiment. FIG. 20 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 24 when a negative potential is applied to the vertical Tr. In the following description, since the configuration other than the gate electrode is the same as that of the first embodiment, the same reference numerals are given and detailed description thereof is omitted. Moreover, since the cross-sectional view of the solid-state imaging device of the second embodiment is the same as the configuration shown in FIG. In the following description of the second embodiment and its modifications, the same components as those shown in FIG. 10 will be described with the same reference numerals as those in FIG.

  As shown in FIG. 19, the solid-state imaging device 34 includes a photodiode (PD) 14, a transfer gate electrode 24, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11 to form a transfer transistor (Tr). .

  One transfer gate electrode 24 is formed at the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 24 is formed integrally with the planar gate electrode 24A formed on the semiconductor substrate 11 and the planar gate electrode 24A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a first vertical gate electrode 24B and a second vertical gate electrode 24C.

  The planar gate electrode 24A is formed in a substantially triangular shape with the corners of the PD 14 with the long sides facing the PD 14 side dropped. The first vertical gate electrode 24B and the second vertical gate electrode 24C are formed so that the planar shape on the surface of the semiconductor substrate 11 is a circle. The first vertical gate electrode 24B and the second vertical gate electrode 24C are formed in a size that does not cover the entire surface under the planar gate electrode 24A.

  The planar gate electrode 24A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 24B and the second vertical gate electrode 24C extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 24, as indicated by an arrow in FIG. 19, the effective gate width W _eff passes over the first vertical gate electrode 24B and the second vertical gate electrode 24C and extends along the gate width direction of the planar gate electrode 24A. Provided.
The effective gate width W _eff is divided into three regions in the effective gate width W _eff direction by the first vertical gate electrode 24B and the second vertical gate electrode 24C. Here, from the end of the first vertical gate electrode 24B side of the planar gate electrode 24A, the region from the first vertical gate electrode 24B and the gate width W _1. Then, the region between the first vertical gate electrode 24B and the second vertical gate electrode 24C and the gate width W _2. From the second vertical gate electrode 24C, the area to the end of the second vertical gate electrode 24C side of the planar gate electrode 24A and the gate width W _3.

The first vertical gate electrode 24B and the second vertical gate electrode 24C are formed at positions where a difference occurs in at least one of the gate widths W ₁ , W ₂ , and W ₃ . With this configuration, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 24B and the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 24C in the effective gate width W _eff direction. In some cases, regions having different potential heights are formed.

Specifically, in FIG. 19, the gate width W ₂ provided between the first vertical gate electrode 24B and the second vertical gate electrode 24C is larger than the other gate widths W ₁ and W _3. The first vertical gate electrode 24B and the second vertical gate electrode 24C are formed at these positions.
With the configuration shown in FIG. 19, when a negative voltage is applied to the transfer gate electrode 24, the distance between the first vertical gate electrode 24B and the second vertical gate electrode 24C is long as shown in FIG. potential large gate width W ₂ region of the gate width is reduced. The distance between the first vertical gate electrode 24B and the second vertical gate electrode 24C is near the potential of the region of small gate width of the gate width W ₁ and the gate width W ₃ becomes high.

As described above, when the distance from the first vertical gate electrode 24B and the second vertical gate electrode 24C is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. Then, an overflow path (OFP) is formed along the region (gate width W ₂ ) formed on the side where the potential decreases in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state imaging device 34 is improved.

Further, by forming the OFP between the first vertical gate electrode 24B and the second vertical gate electrode 24C, the width (gate width) in which the OFP is formed is the same as the first vertical gate electrode 24B and the second vertical gate electrode 24B. It is defined by the interval between the vertical gate electrodes 24C.
For example, when there is one vertical gate electrode, a difference occurs in the effective gate width of one region of the vertical gate electrode for each pixel of the solid-state imaging device due to a pattern misalignment or the like when forming the transfer gate electrode. There is a case. On the other hand, in the configuration in which the OFP is formed between the first vertical gate electrode 24B and the second vertical gate electrode 24C, the first vertical gate electrode even when the transfer gate electrode formation position is shifted for each pixel. The distance between 24B and the second vertical gate electrode 24C can be made constant. This is because, in the normal transfer gate electrode formation process, the first vertical gate electrode 24B and the second vertical gate electrode 24C are formed on the same photomask, so that the transfer gate electrode pattern shifts. In this case, the pattern is kept constant.

  In the case where there is one vertical gate electrode, if the distance from the vertical gate electrode is non-uniform, the height of the potential of the region where the OFP is formed becomes non-uniform, and the saturation charge amount varies from pixel to pixel. A difference occurs in blooming characteristics. By forming the OFP between the first vertical gate electrode 24B and the second vertical gate electrode 24C, the vertical type in the region where the OFP is formed even when the pattern shift of the transfer gate electrode occurs. The distance from the gate electrode is constant, and the potential height in the region where the OFP is formed becomes uniform. As a result, the saturation charge amount of the PD in each pixel becomes constant, and the blooming characteristic can be made uniform.

[Modification Example 1 of Solid-State Image Sensor: Gate Shape (Rectangle)]
Next, a configuration when the shape of the gate electrode is different in the above-described solid-state imaging device will be described as a solid-state imaging device according to Modification 1 of the second embodiment. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

FIG. 21 is a plan view of the main part constituting one pixel of the solid-state imaging device of Modification 1 of the second embodiment. FIG. 22 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 25 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 21, in the solid-state imaging device 35, a transfer transistor (Tr) is composed of a photodiode (PD) 14, a transfer gate electrode 25, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  One transfer gate electrode 25 is formed on the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 25 is formed integrally with the planar gate electrode 25A formed on the semiconductor substrate 11 and the planar gate electrode 25A, and is buried in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a first vertical gate electrode 25B and a second vertical gate electrode 25C.

  The planar gate electrode 25A is formed in a rectangular shape whose long side is in contact with the PD 14 and the FD 18 at the corner of the PD 14, and the first vertical gate electrode 25B and the second vertical gate electrode 25C are formed on the surface of the semiconductor substrate 11. The planar shape is formed as a square. The first vertical gate electrode 25B and the second vertical gate electrode 25C are formed in a size that does not cover the entire surface under the planar gate electrode 25A.

  The planar gate electrode 25A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 25B and the second vertical gate electrode 25C extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 25, as indicated by an arrow in FIG. 21, the effective gate width W _eff passes over the first vertical gate electrode 25B and the second vertical gate electrode 25C and extends in the gate width direction of the planar gate electrode 25A. Provided. The effective gate width W _eff is divided into three regions of gate widths W ₁ , W ₂ , and W ₃ by the first vertical gate electrode 25B and the second vertical gate electrode 25C.

The first vertical gate electrode 25B and the second vertical gate electrode 25C are formed at positions where a difference occurs in at least one of the gate widths W ₁ , W ₂ , and W ₃ . With this configuration, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 25B and the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 25C in the effective gate width W _eff direction. In some cases, regions having different potential heights are formed.

Specifically, in FIG. 21, the gate width W ₂ provided between the first vertical gate electrode 25B and the second vertical gate electrode 25C is larger than the other gate widths W ₁ and W _3. In this position, the first vertical gate electrode 25B and the second vertical gate electrode 25C are formed.
With the configuration shown in FIG. 21, when a negative voltage is applied to the transfer gate electrode 25, the distance between the first vertical gate electrode 25B and the second vertical gate electrode 25C is long as shown in FIG. potential large gate width W ₂ region of the gate width is reduced. The distance between the first vertical gate electrode 25B and the second vertical gate electrode 25C is short, the potential of the region of small gate width of the gate width W ₁ and the gate width W ₃ becomes high.

As described above, when the distance from the first vertical gate electrode 25B and the second vertical gate electrode 25C is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. Then, an overflow path (OFP) is formed along the region (gate width W ₂ ) formed on the side where the potential decreases in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state imaging device 35 is improved.

[Modification Example 2 of Solid-State Image Sensor: Gate Shape (L-shaped)]
Next, a solid-state imaging device according to Modification 2 of the second embodiment will be described. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

FIG. 23 is a plan view of the main part constituting one pixel of the solid-state imaging device of Modification 2 of the second embodiment. FIG. 24 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 26 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 23, in the solid-state imaging device 36, a transfer transistor (Tr) is configured by a photodiode (PD) 14, a transfer gate electrode 26, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  The transfer gate electrode 26 is an outer peripheral portion of the PD 14 and is formed in a substantially L shape combining two rectangles along two sides sandwiching the corner portion. The transfer gate electrode 26 is formed integrally with the planar gate electrode 26A formed on the semiconductor substrate 11 and the planar gate electrode 26A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a first vertical gate electrode 26B and a second vertical gate electrode 26C. The first vertical gate electrode 26B and the second vertical gate electrode 26C are formed so that the planar shape on the surface of the semiconductor substrate 11 is substantially elliptical and does not become the entire surface under the planar gate electrode 26A.

  The planar gate electrode 26A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 26B and the second vertical gate electrode 26C extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 26, as indicated by an arrow in FIG. 23, the effective gate width W _eff passes over the first vertical gate electrode 26B and the second vertical gate electrode 26C, and extends along the gate width direction of the planar gate electrode 26A. Provided. The effective gate width W _eff is divided into three regions of gate widths W ₁ , W ₂ , and W ₃ by the first vertical gate electrode 26B and the second vertical gate electrode 26C.

The first vertical gate electrode 26B and the second vertical gate electrode 26C are formed at positions where a difference occurs in at least one gate width of the gate widths W ₁ , W ₂ , and W ₃ . With this configuration, in the effective gate width W _eff direction, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 26B and the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 26C are arranged. In some cases, regions having different potential heights are formed.

Specifically, in FIG. 23, the gate width W ₂ which is provided between the first vertical gate electrode 26B and the second vertical gate electrode 26C is larger configurations and than other gate width W ₁ and the gate width W ₃ In this position, the first vertical gate electrode 26B and the second vertical gate electrode 26C are formed.
With the configuration shown in FIG. 23, when a negative voltage is applied to the transfer gate electrode 26, the distance between the first vertical gate electrode 26B and the second vertical gate electrode 26C is long as shown in FIG. potential large gate width W ₂ region of the gate width is reduced. The distance between the first vertical gate electrode 26B and the second vertical gate electrode 26C is short, the potential of the region of small gate width of the gate width W ₁ and the gate width W ₃ becomes high.

As described above, when the distance from the first vertical gate electrode 26B and the second vertical gate electrode 26C is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. Then, an overflow path (OFP) is formed along the region (gate width W ₂ ) formed on the side where the potential decreases in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state image sensor 36 is improved.

[Modification Example 3 of Solid-State Image Sensor: Gate Shape (L-shaped)]
Next, a solid-state imaging element according to Modification 3 of the second embodiment will be described. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

FIG. 25 is a plan view of a main part constituting one pixel of a solid-state imaging device according to Modification 3 of the second embodiment. FIG. 26 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 27 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 25, in the solid-state imaging device 37, a transfer transistor (Tr) is configured by a photodiode (PD) 14, a transfer gate electrode 27, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  The transfer gate electrode 27 is an outer peripheral portion of the PD 14 and is formed in a substantially L shape in which two rectangles each having a long side orthogonal to the two sides sandwiching the corner portion are combined. The transfer gate electrode 27 is formed integrally with the planar gate electrode 27A formed on the semiconductor substrate 11 and the planar gate electrode 27A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a first vertical gate electrode 27B and a second vertical gate electrode 27C. The first vertical gate electrode 27B and the second vertical gate electrode 27C are formed so that the planar shape on the surface of the semiconductor substrate 11 is substantially elliptical and does not become the entire surface under the planar gate electrode 27A.

  The planar gate electrode 27A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 27B and the second vertical gate electrode 27C extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 27, as indicated by an arrow in FIG. 25, the effective gate width W _eff passes over the first vertical gate electrode 27B and the second vertical gate electrode 27C and extends along the gate width direction of the planar gate electrode 27A. Provided. The effective gate width W _eff is divided into three regions of gate widths W ₁ , W ₂ , and W ₃ by the first vertical gate electrode 27B and the second vertical gate electrode 27C.

The first vertical gate electrode 27B and the second vertical gate electrode 27C are formed at positions where there is a difference in at least one of the gate widths W ₁ , W ₂ , and W ₃ . With this configuration, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 27B and the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 27C in the effective gate width W _eff direction. In some cases, regions having different potential heights are formed.

Specifically, in FIG. 25, the gate width W ₂ provided between the first vertical gate electrode 27B and the second vertical gate electrode 27C is larger than the other gate widths W ₁ and W _3. In this position, the first vertical gate electrode 27B and the second vertical gate electrode 27C are formed.
With the configuration shown in FIG. 25, when a negative voltage is applied to the transfer gate electrode 27, the distance between the first vertical gate electrode 27B and the second vertical gate electrode 27C is long as shown in FIG. potential large gate width W ₂ region of the gate width is reduced. The distance between the first vertical gate electrode 27B and the second vertical gate electrode 27C is short, the potential of the region of small gate width of the gate width W ₁ and the gate width W ₃ becomes high.

As described above, when the distance from the first vertical gate electrode 27B and the second vertical gate electrode 27C is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. Then, an overflow path (OFP) is formed along the region (gate width W ₂ ) formed on the side where the potential decreases in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state image sensor 37 improves.

[Modification Example 4 of Solid-State Image Sensor: Vertical Gate Electrode]
Next, a configuration when the shape of the gate electrode is different in the above-described solid-state imaging device will be described as a solid-state imaging device according to Modification 4 of the second embodiment. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

In FIG. 27, the top view of the principal part which comprises 1 pixel of the solid-state image sensor of the modification 4 of 2nd Embodiment is shown. FIG. 28 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 28 when a negative potential is applied to the vertical Tr.

  As shown in FIG. 27, in the solid-state imaging device 38, a transfer transistor (Tr) is composed of a photodiode (PD) 14, a transfer gate electrode 28, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  One transfer gate electrode 28 is formed on the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 28 is formed integrally with the planar gate electrode 28A formed on the semiconductor substrate 11 and the planar gate electrode 28A, and is embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. It consists of a first vertical gate electrode 28B and a second vertical gate electrode 28C.

  The planar gate electrode 28A is formed in a substantially triangular shape with the corners of the PD 14 having their long sides facing the PD 14 dropped. The first vertical gate electrode 28B and the second vertical gate electrode 28C are formed so that the planar shape on the surface of the semiconductor substrate 11 is a circle. The first vertical gate electrode 28B and the second vertical gate electrode 28C are formed in a size that does not cover the entire surface under the planar gate electrode 28A.

  The planar gate electrode 28A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 28B and the second vertical gate electrode 28C extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD 14 formed in the semiconductor substrate 11. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 28, as indicated by an arrow in FIG. 27, the effective gate width W _eff passes over the first vertical gate electrode 28B and the second vertical gate electrode 28C, and extends along the gate width direction of the planar gate electrode 28A. Provided. Further, the first vertical gate electrode 28B is formed in contact with a perpendicular (center line) from the center of gravity of the planar gate electrode 28A of the planar gate electrode 28A to the side of the planar gate electrode 28A on the PD side. The second vertical gate electrode 28C is formed on the end side in the effective gate width W _eff direction of the first vertical gate electrode 28B. At this time, the center of the first vertical gate electrode 28B may be on the center line of the planar gate electrode 28A, and the center of the first vertical gate electrode 28B is different from the center line of the planar gate electrode 28A. May be.
The effective gate width W _eff is divided into three regions of gate widths W ₁ , W ₂ , and W ₃ by the first vertical gate electrode 28B and the second vertical gate electrode 28C.

The first vertical gate electrode 28B and the second vertical gate electrode 28C are formed at positions where there is a difference in at least one of the gate widths W ₁ , W ₂ , and W ₃ . With this configuration, in the effective gate width W _eff direction, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 28B and the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 28C. In some cases, regions having different potential heights are formed.

Specifically, in FIG. 27, the gate width W ₁ is the position where the larger configuration than the other gate width W ₂ and the gate width W _3, the planar gate electrode 28A and the first vertical gate electrode 28B side is formed . In this case, the gate width W ₂ which is provided between the first vertical gate electrode 28B and the second vertical gate electrode 28C, the second vertical gate electrode 28C of the planar gate electrode 28A from the second vertical gate electrode 28C the size of the gate width W ₃ of the end portion of the side is not particularly limited. The gate width W ₂ and the gate width W ₃ being may be the same size, or may be one large structure.

With the configuration shown in FIG. 27, when a negative voltage is applied to the transfer gate electrode 28, the distance between the first vertical gate electrode 28B and the second vertical gate electrode 28C is long as shown in FIG. potential large gate width W ₁ region of the gate width is reduced. The distance between the first vertical gate electrode 28B and the second vertical gate electrode 28C is short, the potential of the region of small gate width of the gate width W ₂ and the gate width W ₃ becomes high.

As described above, when the distance from the first vertical gate electrode 28B and the second vertical gate electrode 28C is different, the potential of a partial region in the effective gate width W _eff direction can be lowered. An overflow path (OFP) is formed along a region (gate width W ₁ ) formed on the side where the potential is lowered in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state image sensor 38 is improved.

As described above, the overflow path, may be configured to be formed in the gate width W ₁ between the end portion and the first vertical gate electrode 28B of the first vertical gate electrode 28B side of the planar gate electrode 28A. Further, similarly to the modified example 4, also be configured to form an overflow path to the gate width W ₃ to the end of the second vertical gate electrode 28C side of the planar gate electrode 28A from the second vertical gate electrode 28C it can.

[Modification Example 5 of Solid-State Image Sensor: Vertical Gate Electrode]
Next, as a solid-state imaging device according to Modification 5 of the second embodiment, a configuration when the shape of the gate electrode is different in the above-described solid-state imaging device will be described. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

In FIG. 29, the top view of the principal part which comprises 1 pixel of the solid-state image sensor of the modification 5 of 2nd Embodiment is shown. FIG. 30 shows a potential cross section in the effective gate width W _eff direction in the region under the transfer gate electrode 29 when a negative potential is applied to the vertical Tr. In the following description, since the configuration other than the gate electrode is the same as that of the second embodiment, the same reference numerals are given and detailed description thereof is omitted.

  As shown in FIG. 29, in the solid-state imaging device 39, a transfer transistor (Tr) is configured by a photodiode (PD) 14, a transfer gate electrode 29, and a floating diffusion (FD) 18 formed on the semiconductor substrate 11. .

  One transfer gate electrode 29 is formed on the outer periphery of the PD 14 and at one corner of the PD 14. The transfer gate electrode 29 includes a planar gate electrode 29 </ b> A formed on the semiconductor substrate 11. The first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate are formed integrally with the planar gate electrode 29A and embedded in a column shape in the depth direction from the surface of the semiconductor substrate 11. An electrode 29D is provided.

  The planar gate electrode 29A is formed in a rectangular shape whose long side is in contact with the PD 14 and the FD 18 side at the corner of the PD 14. The first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D are formed with a circular planar shape on the surface of the semiconductor substrate 11. The first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D are formed in a size that does not cover the entire surface under the planar gate electrode 29A.

  The planar gate electrode 29A is formed in a region extending from the corner of the PD 14 to the FD 18. The first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D extend from the surface of the semiconductor substrate 11 to a depth in contact with the n-type semiconductor region 15 located on the back side of the PD. The gate insulating film 17 is interposed therebetween.

In the transfer gate electrode 29, as indicated by an arrow in FIG. 29, the effective gate width W _eff passes over the first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D, and the transfer gate It is provided along the gate width direction of the electrode 29.
The effective gate width W _eff is divided into four regions in the effective gate width W _eff direction by the first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D.

Here, from the end of the first vertical gate electrode 29B side of the planar gate electrode 29A, the region from the first vertical gate electrode 29B and the gate width W _1. Then, the region between the first vertical gate electrode 29B and the second vertical gate electrode 29C and the gate width W _2. The area between the second vertical gate electrode 29C and the third vertical gate electrode 29D and gate width W _3. A third vertical gate electrode 29D, a region to the end of the third vertical gate electrode 29D side of the planar gate electrode 29A and the gate width W _4.

The first vertical gate electrode 29B and the second vertical gate electrode 29C are formed at positions where a difference occurs in at least one of the gate widths W ₁ , W ₂ , W ₃ , W ₄ . With this configuration, the regions (W ₁ , W ₂ ) on both sides of the first vertical gate electrode 29B, the regions (W ₂ , W ₃ ) on both sides of the second vertical gate electrode 29C, and the third vertical gate electrode Regions having different potential heights are formed in any of the regions (W ₃ , W ₄ ) on both sides of 29D.

Specifically, in FIG. 29, the gate width W ₂ provided between the first vertical gate electrode 29B and the second vertical gate electrode 29C is larger than the other gate widths W ₁ , W ₃ , W _4. It is formed in the position.
With the configuration shown in FIG. 29, when a negative voltage is applied to the transfer gate electrode 29, as shown in FIG. 30, the distance between the first vertical gate electrode 29B and the second vertical gate electrode 29C is long, potential large gate width W ₂ region of the gate width is reduced. Further, the potentials of the regions of the gate widths W ₁ , W ₃ , and W _{4 having} a small gate width are close to the first vertical gate electrode 29B, the second vertical gate electrode 29C, or the third vertical gate electrode 29D. Get higher.

As described above, the distances from the first vertical gate electrode 29B, the second vertical gate electrode 29C, and the third vertical gate electrode 29D are different, so that a part of the region in the effective gate width W _eff direction can be obtained. Potential can be lowered. Then, an overflow path (OFP) is formed along the region (gate width W ₂ ) formed on the side where the potential decreases in the effective gate width W _eff , and excess charge accumulated in the PD 14 through this OFP is transferred to the FD 18. It becomes easy to overflow. For this reason, the blooming characteristic of the solid-state imaging device 39 is improved.

As described above, in the transfer gate electrode, the number of vertical gate electrodes is not particularly limited, and may be one or more. In the effective gate width W _eff direction, at least one of a region provided between the end of the planar gate electrode and the vertical gate electrode and a region provided between the vertical gate electrodes is another gate. Any structure may be used as long as the area is larger than the width. The potential of the region larger than this other gate width is lowered, and the OFP is formed along this region.

In the above-described embodiment, a method of shifting the position of the vertical gate electrode from the center of the channel width is described as a method of generating a difference in the gate width on both sides of the vertical gate electrode in the effective gate width W _eff direction. Yes. In the present technology, the position and shape of the vertical gate electrode are not limited as long as a difference occurs in the gate width on both sides in the effective gate width W _eff direction, not limited to the configuration of the present embodiment. For example, by changing the shape of the vertical gate electrode, even when the center of gravity of the vertical gate electrode is made coincident with the center line of the channel width, the gate width is different on both sides in the effective gate width W _eff direction. The transfer gate electrode can also be used. In addition, a configuration in which a difference is generated between the gate widths on both sides of the vertical gate power may be achieved by other configurations without being limited thereto.

<4. Manufacturing method of solid-state imaging device>
Next, the manufacturing method of the solid-state imaging device according to the first embodiment will be described as an example of the manufacturing method of the solid-state imaging device. In the following description of the manufacturing method, the same components as those of the semiconductor device according to the first embodiment shown in FIGS. 9 and 10 are denoted by the same reference numerals, and detailed description of each component is omitted.
In the following manufacturing method, only a method for manufacturing a photodiode (PD), a floating diffusion (FD), and a transfer gate electrode will be described as an example of a method for manufacturing a solid-state imaging device. Note that description of a method for manufacturing a semiconductor substrate, a wiring layer, other various transistors, and various elements formed on the solid-state imaging element is omitted. These can be produced by a conventionally known method.

First, as shown in FIG. 31A, a gate insulating film 17 is formed on a semiconductor substrate 11 of a first conductivity type (p-type) or the like. Then, a second conductivity type impurity is ion-implanted into the deep portion of the semiconductor substrate 11 in the region where the photodiode (PD) is to be formed through the gate insulating film 17. Thereby, as shown in FIG. 31B, the second conductivity type (n-type) semiconductor region 15 is formed in the deep portion of the semiconductor substrate 11.
Further, as shown in FIG. 31C, a second conductivity type impurity is ion-implanted into the surface of the semiconductor substrate 11 through the gate insulating film 17 so as to have a higher concentration than the n-type semiconductor region 15. As a result, a high-concentration second conductivity type (n ⁺ -type) semiconductor region 13 is formed on the surface of the semiconductor substrate 11.

Next, as shown in FIG. 32D, a resist layer 51 is formed on the region where the transfer gate electrode, the floating diffusion (FD) and the like are formed so as to open the region where the PD is formed. Then, a first conductivity type impurity is ion-implanted into the surface of the semiconductor substrate 11 to form a high-concentration first conductivity type (p ⁺ type) semiconductor region 12 on the n ⁺ type semiconductor region 13. Through the above steps, the PD 14 is formed on the semiconductor substrate 11.

Next, as shown in FIG. 32E, a resist layer 52 is formed on the semiconductor substrate 11 in a pattern that opens a position where a vertical gate electrode is to be formed. Then, the semiconductor substrate 11 is etched from the opening of the resist layer 52 to form a trench 54 in the semiconductor substrate 11.
The trench 54 is formed at an arbitrary position based on the formation position of the vertical gate electrode formed on the transfer gate electrode of the solid-state imaging device of the first embodiment, the second embodiment, and each of the modifications described above. To do. Further, the number of trenches 54 is one or more per pixel according to the number of vertical transfer gates formed in one pixel of the solid-state imaging device.

  As shown in FIG. 32F, the gate insulating film 17 is formed in the trench. Then, a conductor layer such as a polysilicon layer is formed in the trench and on the entire surface of the semiconductor substrate 11. Then, a resist pattern in the shape of the planar gate electrode of the transfer gate electrode is formed on the formed conductor layer. Then, the polysilicon layer is etched in accordance with the resist pattern, thereby forming the transfer gate electrode 16 including the planar gate electrode 16A and the vertical gate electrode 16B. Specifically, the planar gate electrode 16A is formed in the shape of the above-described first embodiment (including modifications) or the second embodiment (including modifications).

Further, a resist layer 53 having a pattern that opens a region where the FD 18 is to be formed is formed. Then, a second conductivity type impurity is ion-implanted into the surface of the semiconductor substrate 11 to form a high-concentration second conductivity type (n ⁺ type) semiconductor region FD 18 on the n ⁺ type semiconductor region 13.
Furthermore, the ion-implanted impurities are activated by applying a heat treatment such as annealing, for example, a heat treatment at about 1000 ° C.
Through the above steps, the solid-state imaging device of the first embodiment can be manufactured.

  It should be noted that, by changing the shape of the planar gate electrode and the shape of the vertical gate electrode from the method for manufacturing the solid-state imaging device of the first embodiment described above, the modification of the first embodiment described above, the second embodiment. The solid-state image sensor of a form and the modification of 2nd Embodiment can be manufactured.

<5. Embodiment of Electronic Device>
Next, an embodiment of an electronic device including the above-described solid-state imaging device will be described.
The above-described solid-state imaging device can be applied to electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. FIG. 33 illustrates a schematic configuration when a solid-state imaging device is applied to a camera capable of capturing a still image or a moving image as an example of an electronic device.

  The camera 60 of this example includes a solid-state image sensor 61, an optical system 62 that guides incident light to the light receiving sensor portion of the solid-state image sensor 61, a shutter device 63 provided between the solid-state image sensor 61 and the optical system 62, And a drive circuit 64 for driving the image sensor 61. Further, the camera 60 includes a signal processing circuit 65 that processes an output signal of the solid-state image sensor 61.

  As the solid-state image sensor 61, the solid-state image sensor of the above-described first embodiment (including modifications) and second embodiment (including modifications) can be applied. The optical system (optical lens) 62 forms image light (incident light) from the subject on an imaging surface (not shown) of the solid-state imaging device 61. Thereby, signal charges are accumulated in the solid-state imaging device 61 for a certain period. The optical system 62 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 63 controls the light irradiation period and the light shielding period of the incident light to the solid-state image sensor 61.

  The drive circuit 64 supplies drive signals to the solid-state image sensor 61 and the shutter device 63. The drive circuit 64 controls the signal output operation to the signal processing circuit 65 of the solid-state image sensor 61 and the shutter operation of the shutter device 63 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 61 to the signal processing circuit 65 is performed by a drive signal (timing signal) supplied from the drive circuit 64.

  The signal processing circuit 65 performs various types of signal processing on the signal transferred from the solid-state image sensor 61. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

  In the solid-state imaging device according to each of the embodiments described above, the case where the present invention is applied to an image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. However, the above-described solid-state imaging device is not limited to application to an image sensor, and can be applied to all column-type solid-state imaging devices in which column circuits are arranged for each pixel column of the pixel array unit. .

In addition, the solid-state imaging device described above is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image. The present invention can be applied to a solid-state imaging device for imaging. In a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.
Furthermore, the above-described solid-state imaging device is not limited to a solid-state imaging device that sequentially scans each unit pixel of the pixel array unit in units of rows and reads a pixel signal from each unit pixel. For example, the present invention can also be applied to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads signals from the selected pixels in pixel units.
The solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

  Further, in the solid-state imaging device of each of the embodiments described above, the solid-state imaging device using electrons as signal charges has been described, but the present invention can also be applied to a solid-state imaging device using holes as signal charges. In this case, in the above example, the first conductivity type is p-type and the second conductivity type is n-type, and the first conductivity type is n-type and the second conductivity type is p-type. In the driving method, the voltage applied to each pixel transistor replaces the positive voltage with a negative voltage and the negative voltage with a positive voltage.

In addition, this indication can also take the following structures.
(1) A photodiode formed on the surface of a semiconductor substrate and a gate formed in the depth direction from the surface of the semiconductor substrate through a gate insulating film around the region where the photodiode is formed. An electrode and a floating diffusion for accumulating signal charges read from the photodiode, and the gate electrode is formed integrally with the planar gate electrode formed on the semiconductor substrate, The vertical gate electrode is formed in the depth direction from the semiconductor substrate, and the vertical gate electrode is formed in the effective gate width direction when a voltage is applied to the gate electrode during charge accumulation. Solid imaging formed at a position where there is a difference in potential height in the area under the planar gate electrode on both sides of the gate electrode. Element.
(2) In the effective gate width direction, the potential of a region far from the vertical gate electrode to the end of the planar gate electrode is lowered, and the distance from the vertical gate electrode to the end of the planar gate electrode is reduced. The solid-state imaging device according to (1), wherein the potential in the near region is high.
(3) The gate electrode has only one vertical gate electrode, and the center of the vertical gate electrode on the surface of the semiconductor substrate and the center of the planar gate electrode are different in the effective gate width direction. The solid-state image sensor as described in (1) or (2) in a position.
(4) The gate electrode has two vertical gate electrodes, and in the effective gate width, a region between the two vertical gate electrodes is wider than other regions (1) or (2) The solid-state image sensor described in 1.
(5) A step of forming a photodiode on the surface of the semiconductor substrate, a step of forming a gate electrode around the photodiode formation region, and a step of forming a floating diffusion on the surface of the semiconductor substrate. Forming a gate electrode, forming a trench in the semiconductor substrate, forming a conductor layer in the trench and on the surface of the semiconductor substrate, and forming a vertical gate electrode in the trench; Forming a planar gate electrode on the semiconductor substrate, and the trench is formed on both sides of the vertical gate electrode in the effective gate width direction when a voltage is applied to the gate electrode during charge accumulation. A method of manufacturing a solid-state imaging device, which is formed at a position where a difference in potential height occurs in a region under a planar gate electrode.
(6) The solid-state imaging device according to any one of (1) to (4), an optical system that guides incident light to the imaging unit of the solid-state imaging device, and signal processing that processes an output signal of the solid-state imaging device An electronic device having a circuit.

10, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 61 Solid-state imaging device, 11 Semiconductor substrate, 12, 13, 15 Semiconductor region, 14 Photodiode, 17 Gate insulating film, 18 FD region, 19 overflow path (OFP), 16, 21, 22, 23, 24, 25, 26, 27, 28, 29 transfer gate electrode, 16A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A Planar gate electrode, 16B, 21B, 22B, 23B Vertical gate electrode, 24C, 25C, 26C, 27C, 28C, 29C Second vertical gate electrode, 24B, 25B, 26B, 27B, 28B, 29B First Vertical gate electrode, 29D Third vertical gate electrode, 41 Horizontal signal line, 42 pixels, 43 pixel section, 44 Vertical drive circuit, 45 Lamb signal processing circuit, 46 horizontal drive circuit, 47 output circuit, 48 control circuit, 49 vertical signal line, 51, 52, 53 resist layer, 54 trench, 60 camera, 62 optical system, 63 shutter device, 64 drive circuit, 65 Signal processing circuit, W1, W2, W3, W4 gate width, W _eff effective gate width

Claims (6)

A photodiode formed on a semiconductor substrate surface;
Around the region where the photodiode is formed, a gate electrode formed through a gate insulating film in the depth direction from the surface of the semiconductor substrate;
A floating diffusion for accumulating signal charges read from the photodiode,
The gate electrode comprises a planar gate electrode formed on the semiconductor substrate, and a vertical gate electrode formed integrally with the planar gate electrode and formed in a depth direction from the semiconductor substrate,
The vertical gate electrode has a potential height in a region under the planar gate electrode on both sides of the vertical gate electrode in the effective gate width direction when a voltage is applied to the gate electrode during charge accumulation. A solid-state image sensor formed at a position where a difference occurs.   In the effective gate width direction, the potential of a region where the distance from the vertical gate electrode to the end of the planar gate electrode is long is low, and the distance from the vertical gate electrode to the end of the planar gate electrode is short. The solid-state imaging device according to claim 1, wherein the potential of the region becomes high.   The gate electrode has only one vertical gate electrode, and the center of the vertical gate electrode on the surface of the semiconductor substrate is different from the center of the planar gate electrode in the effective gate width direction. The solid-state imaging device according to claim 1.   2. The solid-state imaging device according to claim 1, wherein the gate electrode has two vertical gate electrodes, and a region between the two vertical gate electrodes is larger than another region in the effective gate width direction. . Forming a photodiode on the surface of the semiconductor substrate;
Forming a gate electrode around a region where the photodiode is formed;
Forming a floating diffusion at a position facing the photodiode across the gate electrode on the surface of the semiconductor substrate,
Forming the gate electrode includes forming a trench in the semiconductor substrate; forming a conductor layer in the trench and on the surface of the semiconductor substrate; forming a vertical gate electrode in the trench; Forming a planar gate electrode on a semiconductor substrate,
In the trench, when a voltage is applied to the gate electrode during charge accumulation, a difference occurs in potential height in the region under the planar gate electrode on both sides of the vertical gate electrode in the effective gate width direction. A method of manufacturing a solid-state image sensor formed at a position to be moved. A photodiode formed on the surface of the semiconductor substrate, a gate electrode formed in the depth direction from the surface of the semiconductor substrate around the region where the photodiode is formed, and a gate insulating film; A floating diffusion for accumulating signal charges read from the photodiode, wherein the gate electrode is formed integrally with the planar gate electrode and the planar gate electrode, The vertical gate electrode sandwiches the vertical gate electrode in the effective gate width direction when a voltage is applied to the gate electrode during charge accumulation. A solid-state imaging device formed at a position where a difference in potential height occurs in the region under the planar gate electrode on both sides;
An optical system for guiding incident light to the imaging unit of the solid-state imaging device;
And a signal processing circuit for processing an output signal of the solid-state imaging device.

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