JP2007281344A - Solid state imaging apparatus, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that in a conventional solid-state imaging apparatus for transferring photoelectrically converted charges to a p-type minute region, the capacity of the p-type minute region is varied due to variation in the shape of the p-type minute region or variation in a distance between the p-type minute region and a source region, and thereby variation in an output signal voltage is increased. <P>SOLUTION: Photoelectrically converted charges accumulated in a buried region 6 are transferred and accumulated to/in a source neighborhood area 4 through a charge transfer channel region 8. Therein, overlapped dimensions d3, d4 between the transfer channel regions 8 and ring-shaped gate electrodes 1 are determined by ion penetration depth from the outer periphery of the ring-shaped gate electrodes 1 and are almost the same value. Since the widths W1, W2 of the ring-shaped gate electrodes 1 are formed by the photo-process and etching of the same process by using photomasks of the same dimensions, the widths W1, W2 are regarded as almost the same values. Consequently the overlapped dimensions d1, d2 of the source neighborhood area 4 and the ring-shaped gate electrodes 1 are almost equal without being influenced by pattern matching errors in the photo-process. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device including an amplifying element having a ring-shaped gate electrode in a pixel and a manufacturing method thereof.

  Solid-state imaging devices can be roughly classified into two types: CCD (Charge Coupled Device) and CMOS (Complementary MOS) sensors.

  The CCD has a structure in which charges obtained by photoelectric conversion by a photodiode in a pixel are transferred to a reading unit through a vertical charge transfer path and a horizontal charge transfer path, and converted into a voltage there to obtain an output signal. Since the charge photoelectrically converted in all pixels is converted into a voltage by a single readout unit, the CCD has the feature that there is little signal variation between pixels and low noise. In addition, since the charges photoelectrically converted by the photodiodes can be transferred to the vertical charge transfer path simultaneously in all pixels and then sequentially transferred to read the signals, a so-called global shutter (collective shutter) operation can be easily realized. On the other hand, the CCD requires several kinds of high voltages for charge transfer and consumes a large amount of power. When the number of pixels increases, the charge transfer, particularly horizontal charge transfer, takes time and cannot operate at high speed.

  On the other hand, a CMOS sensor converts a charge obtained by photoelectric conversion with a photodiode into a voltage or current signal in the pixel, amplifies the signal with an amplifying transistor provided in the pixel, and then out of the pixel. Take the structure to output. Since the pixel units arranged in a matrix are switched and switched to read out signals, the CMOS sensor operates at a high speed, and the pixel unit and the peripheral drive circuit are composed of CMOS, so the CMOS sensor can be driven at a low voltage and is low. The power consumption is reduced, and further, signal processing circuits such as AD converters can be mounted on the same chip.

  On the other hand, since the CMOS sensor amplifies a signal with an individual amplification transistor provided in a pixel, signal variation between pixels is large, and noise characteristics are disadvantageous compared to a CCD. In addition, when trying to realize a global shutter operation that can be easily realized with a CCD without deteriorating noise characteristics with a CMOS sensor, the number of transistors per pixel is increased to 5 and a signal storage area for batch transfer is provided in the pixel. It is necessary to provide the chip, and the chip area is increased and the cost is increased. For this reason, in a general one-pixel four-transistor CMOS sensor, a so-called line shutter (rolling shutter, focal plane shutter) operation in which a signal is read and a photoelectric conversion area is reset for each line of a screen scanning line is basic. It has become.

  Here, the relationship between the image captured by the solid-state imaging device and the shutter operation will be described. When a fast-moving subject is taken with an imaging device (CMOS sensor) that operates with a line shutter, the image is distorted. For example, when a circular ball 100 moving up and down as shown in FIG. 16A is taken with a CMOS sensor that reads out one line at a time from the upper end of the screen, if the ball 100 moves up, ), The captured image of the ball becomes a flat image in the horizontal direction. When the ball 100 moves downward, the captured image of the ball extends in a vertically long ellipse as shown in FIG. It becomes an image. This phenomenon is a particularly noticeable defect when a captured image is read as a still image.

  Therefore, when applying a CMOS sensor with line shutter operation to a video / still image camera, the same function as a global shutter is realized by using a mechanical shutter together to make the light reception time of all photodiodes the same. However, when the mechanical shutter is inserted, there is a problem that the optical system becomes large and the cost increases.

  Thus, there have been disclosed some attempts to reduce the number of transistors per pixel of the CMOS sensor to 4 or less and enable a global shutter operation (see, for example, Patent Documents 1 and 2). In the solid-state imaging device (CMOS sensor) described in Patent Document 1, a unit pixel is configured by a ring-shaped gate readout transistor, a transfer gate, and a photoelectric conversion region, thereby realizing a global shutter operation.

  In the solid-state imaging device (CMOS sensor) described in Patent Document 2, the unit pixel is configured by a ring-shaped gate readout transistor, a transfer gate, a photoelectric conversion region, and a charge discharge gate adjacent to the photoelectric conversion region. Global shutter operation is possible.

JP 10-41493 A JP 2002-134729 A

  However, in the conventional solid-state imaging device described in Patent Document 1, since the photoelectrically converted charge is transferred to the p-well that is installed under the ring-shaped gate electrode, the charge-voltage conversion efficiency is low and the output voltage is low. There is a small bug.

  In another conventional solid-state imaging device described in Patent Document 2, photoelectrically converted charges are supplied to a p-type minute region provided in a p-well that is provided entirely under a ring-shaped gate electrode. However, the capacitance of the p-type micro region fluctuates due to variations in the shape of the p-type micro region and the distance between the p-type micro region and the source region, resulting in an output signal. The voltage variation increases.

  The cause is that the p-type microregion of this solid-state imaging device is created by implanting boron ions from a narrow ring-shaped photoresist window, but the narrow ring-shaped photoresist dimensions are likely to vary, This is because the shape of the p-type micro region varies, and therefore the capacitance between the p-type micro region and the gate electrode varies. In addition, the relative position between the p-type microregion and the source region varies due to a mask alignment error when forming the ring-shaped photoresist window, and the capacitance between the p-type microregion and the source region varies. Increases variation in output signal voltage.

  The present invention has been made in view of the above points, and is capable of a global shutter operation, has a high charge-voltage conversion efficiency, and provides a large output voltage. Furthermore, the shape variation of the charge-voltage conversion region and mask alignment can be achieved. An object of the present invention is to provide a solid-state imaging device in which fluctuations in output voltage due to errors are suppressed and a method for manufacturing the same.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a ring-shaped gate electrode having a ring shape on a substrate, and a source region provided at a position of the substrate corresponding to a central opening of the ring-shaped gate electrode. And a source vicinity region provided on the substrate so as to surround the source region and not to reach the outer periphery of the ring-shaped gate electrode, and output the amount of input charge as a change in threshold voltage A plurality of unit pixels including a charge transistor, a photoelectric conversion region for converting light into charge, and a charge transfer means for transferring the charge accumulated in the photoelectric conversion region to a region near the source of the signal output transistor. The means includes a charge transfer channel region provided on the substrate, the charge transfer channel region being in contact with a source vicinity region of the signal output transistor and near the source. And wherein the surrounding region.

  In the present invention, since the photoelectrically converted charge is transferred to the source vicinity region having a small area of the signal output transistor, the charge voltage conversion efficiency can be increased. In the present invention, the size of the source vicinity region can be set to a value obtained by subtracting the overhanging size of the charge transfer channel region from the width of the ring-shaped gate electrode. By adjusting the amount of protrusion of the region, the size of the source vicinity region can be narrowed.

  Here, the charge transfer channel region of the charge transfer means may have an impurity concentration higher than the impurity concentration in the vicinity of the source of the signal output transistor.

  In order to achieve the above object, the manufacturing method of the present invention for manufacturing the solid-state imaging device of the present invention includes a first step of forming a second conductivity type well in a first conductivity type substrate. A second step of forming the first conductivity type enlarged source vicinity region and the first conductivity type photoelectric conversion region separately in the second conductivity type well; A third step of forming a ring-shaped gate electrode on which a planar shape is formed in a ring shape via a gate insulating film, and an outer peripheral end thereof is located on an inner side of an outer peripheral end of a region near the enlarged source; Using the outer periphery of the electrode as a mask, the second conductivity type impurity is ion-implanted from an oblique direction, and the second conductivity type is formed in a region reaching from the outer peripheral end of the region near the enlarged source to a portion below the ring-shaped gate electrode. And forming a charge transfer channel region of Characterized in that it comprises a fourth step of leaving the enlarged vicinity of the source region including a position corresponding to the central opening of the not formed as a charge transferring channel region ring-shaped gate electrode as a source region near.

  In this invention, ion implantation is performed from an oblique direction using the outer periphery of the ring-shaped gate electrode as a mask, and a charge transfer channel region is formed in a region reaching from the outer peripheral end of the region near the enlarged source to a portion below the ring-shaped gate electrode. In addition, since the enlarged source vicinity region including the position corresponding to the central opening of the ring-shaped gate electrode not formed as the charge transfer channel region is left as the source vicinity region, the size of the source vicinity region is determined in a self-aligning manner. Can be made unaffected by pattern alignment errors in the photo process.

  In order to achieve the above object, the manufacturing method of the present invention for manufacturing the solid-state imaging device of the present invention includes a first step of forming a second conductivity type well in a first conductivity type substrate. A second step of forming the first conductivity type enlarged source vicinity region and the first conductivity type photoelectric conversion region separately in the second conductivity type well; A third step of forming a ring-shaped gate electrode on which a planar shape is formed in a ring shape via a gate insulating film, and an outer peripheral end thereof is located on an inner side of an outer peripheral end of a region near the enlarged source; Impurity ion implantation of the second conductivity type is performed using the outer periphery of the electrode as a mask to form a second conductivity type charge transfer channel region on the surface of the well outside the outer periphery of the ring-shaped gate electrode. And the ring after heat treatment after ion implantation The charge transfer channel region is diffused so as to reach a part below the gate electrode, and the enlarged source vicinity region including the position corresponding to the central opening of the ring-shaped gate electrode that is not diffused as the charge transfer channel region is adjacent to the source And a fifth step of remaining as a region.

  In this invention, ion implantation is performed using the outer peripheral portion of the ring-shaped gate electrode as a mask, a charge transfer channel region is formed on the surface of the well outside the outer peripheral portion of the ring-shaped gate electrode, and then heat treatment is performed. The charge transfer channel region is diffused so as to reach a part below, and the diffused source vicinity region including the position corresponding to the central opening of the ring-shaped gate electrode that is not diffused as the charge transfer channel region is sourced Since it is left as a neighboring region, the size of the source neighboring region can be determined in a self-aligned manner, and can be prevented from being affected by the pattern alignment error of the photo process.

  According to the present invention, since the dimension of the source vicinity region can be set to a value obtained by subtracting the protruding dimension of the charge transfer channel region from the width of the ring gate electrode, a wide ring gate electrode pattern is formed, and the charge transfer channel is formed. By adjusting the amount of overhang of the region, the size of the region near the source can be narrowed, so that it is not necessary to create a ring-shaped photoresist pattern with a narrow width as in the past, and the size variation in the region near the source is reduced. In addition, since the photoelectrically converted charges are transferred to the source vicinity region where the area of the signal output transistor is small, the charge voltage conversion efficiency can be increased.

  In addition, according to the present invention, the size of the source vicinity region can be determined in a self-aligned manner and can be prevented from being affected by the pattern alignment error of the photo process. As a result, variations in potential in the source vicinity region and variations in capacitance between the source vicinity region and the ring-shaped gate electrode can be reduced. In addition, according to the present invention, the source vicinity region is configured to be in contact with and surround the source region, so that the capacitance between the source vicinity region and the source region is not affected by the pattern alignment error of the photo process. In addition, the value is almost constant. From the above, according to the present invention, variations in potential and capacitance in the vicinity of the source where photoelectric conversion charges are transferred can be suppressed, so that fluctuations in the signal output voltage can be improved.

  According to the present invention, since the number of transistors per pixel is small, increasing the area ratio of the photodiode in the unit pixel also contributes to an increase in signal output, and further resets the signal readout transistor. In this case, since the region near the source is completely depleted, there is an effect that no reset noise is generated due to variations in the residual charge amount at the time of reset.

  Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a unit pixel according to an embodiment of the solid-state imaging device according to the present invention, and FIG. 2 is a cross-sectional view of the unit pixel according to an embodiment of the solid-state imaging device according to the present invention. FIG. 2 is a cross-sectional view taken along line X-X ′ of FIG. 1, and the same components are denoted by the same reference numerals in both drawings. The unit pixel of the present embodiment is composed of three elements: a signal reading unit, a photoelectric conversion unit, and a charge transfer unit.

In FIG. 1, the signal readout means includes a ring-shaped gate electrode 1 having a ring shape in plan view, a source region 2 in the central opening of the ring-shaped gate electrode 1, and a drain region 3 surrounding the ring-shaped gate electrode 1. It is a MOS transistor. A p-type source vicinity region 4 is formed around the n-type source region 2. The photoelectric conversion means is a photodiode having a p ⁻ type buried region 6 and an n ⁺ type surface region 7 on the surface thereof. Between the p ⁻ type buried region 6 and the ring-shaped gate electrode 1, a transfer gate electrode 5 is disposed as a charge transfer means.

Further, as shown in the cross-sectional view of FIG. 2, in this embodiment, a substrate obtained by growing a p ⁻ type epitaxial layer 10 on a p ⁺ silicon substrate 9 is used. A deep n-type well 11 and a shallow n-type well 12 are formed adjacent to each other in the p ⁻ -type epitaxial layer 10. A ring-shaped gate electrode 1 is formed on the n-type well 12 with a gate oxide film 13 interposed therebetween. There is an n ⁺ -type source region 2 on the surface of the n-type well 12 located at the central opening of the ring-shaped gate electrode 1, and a p-type source so as to surround the source region 2 adjacent to the source region 2. There is a neighborhood region 4.

The source region 2 and the n-type well 12 are separated by the source vicinity region 4. The periphery of the source vicinity region 4 is surrounded by an n-type transfer channel region 8. The transfer channel region 8 is formed not only under the transfer gate electrode 5 but also around the source vicinity region 4. A p ⁺ type reset buried region 14 is provided in the p ⁻ type epitaxial layer 10 below the source vicinity region 4. There is an n ⁺ -type drain region 3 on the surface of the n-type well 12 away from the source region 2 and the source vicinity region 4.

Further, a p ⁻ type buried region 6 is formed in the n type well 11 outside the ring-shaped gate electrode 1, and the p ⁻ type buried region 6, the surface n ⁺ type surface region 7, and the n type well 11 are formed. Thus, an embedded photodiode which is a photoelectric conversion region is configured. The n ⁺ type surface region 7 is connected to the n ⁺ type drain region 3 at the outer peripheral portion of the unit pixel area. A transfer gate electrode 5 is provided between the p ⁻ type buried region 6 and the ring-shaped gate electrode 1, and this transfer gate electrode 5 is a polysilicon layer different from the polysilicon layer constituting the ring-shaped gate electrode 1. Form with.

In the present embodiment described with reference to FIG. 2, the photoelectric conversion charge accumulated in the p ⁻ type buried region 6 of the photodiode is transferred to the source vicinity region 4 through the transfer channel region 8 and has the ring-shaped gate electrode 1. A signal is output as a change in the threshold voltage of the signal read transistor. Therefore, if the overlapping dimensions d1 and d2 of the source vicinity region 4 and the ring-shaped gate electrode 1 vary, the capacitance between the source vicinity region 4 and the ring-shaped gate electrode 1 varies, and the potential of the source vicinity region 4 also varies. The output voltage fluctuates.

  Therefore, in this embodiment, the impurity concentration of the transfer channel region 8 is made higher than or equal to the impurity concentration of the source vicinity region 4, and oblique ion implantation is performed using the outer peripheral portion of the ring-shaped gate electrode 1 as a mask. By forming the transfer channel region 8 by diffusion, the overlapping dimensions d3 and d4 of the ring-shaped gate electrode 1 and the transfer channel region 8 are made constant. The widths W1 and W2 of the ring-shaped gate electrode 1 can be regarded as almost the same because they are formed by the same photo process and etching using a photomask having the same dimensions.

  Here, the impurity in the source vicinity region 4 refers to a dopant for making the source vicinity region 4 p-type. The impurity in the transfer channel region 8 refers to a dopant for making the transfer channel region 8 n-type.

  As a result, the overlapping dimensions d1 and d2 between the source vicinity region 4 and the ring-shaped gate electrode 1 are substantially the same, and variations in potential in the source vicinity region 4 and capacitance variations in the source vicinity region 4 and the ring-shaped gate electrode 1 are reduced. is doing. This point will be described in detail later together with the description of FIGS.

  FIG. 3 shows an equivalent circuit diagram in an embodiment of the solid-state imaging device according to the present invention. The unit pixels are arranged in m rows and n columns in the pixel spread area, but only one of them is represented by the equivalent circuit of FIG. The pixel equivalent circuit shown in FIG. 3 includes a signal readout transistor 18 having a ring-shaped gate electrode 1, a photodiode 19 having a buried region 6, and a pixel transfer transistor 20 having a transfer gate electrode 5. Is connected to the n-type of the photodiode 19, the source of the charge transfer transistor 20 is connected to the p-type of the photodiode 19, and the drain of the charge transfer transistor 20 is the back gate of the signal readout transistor 18 (source-near region 4 in FIG. 2). ).

  The ring-shaped gate electrode of the signal readout transistor 18 in the pixel is connected to the vertical scanning circuit 25 through the ring gate bus line 21, and the gate electrode of the charge transfer transistor 20 (transfer gate electrode 5 in FIGS. 1 and 2) is The transfer gate line 22 is connected to the transfer gate drive circuit 26, and the drain electrode of the signal read transistor 18 is connected to the drain voltage control circuit 27 via the drain bus line 23.

  Since the ring-shaped gate electrode 1 is controlled for each row of the pixel array, wiring is performed in the horizontal direction. However, since the transfer gate electrode 5 is controlled at the same time for all pixels, vertical wiring may be used. is doing. The drain voltage control circuit 27 has a case where the drains of all the pixels are controlled all at once and a case where the drains are controlled for each row. The wiring 24 connected to the source electrode of the signal readout transistor 18 is wired in the vertical direction, and one of the wirings 24 is connected to the source potential control circuit 28 and the other is connected to the signal output circuit 29. The signal output circuit 29 has a so-called CDS (correlated double sampling) function of reading a difference between the signal voltage and the reset voltage by a clamp circuit, a sample hold circuit, and a differential amplifier (not shown). The signal output from the signal output circuit 29 is output via a switch controlled by the horizontal scanning circuit 30.

Next, the operation of the equivalent circuit of FIG. 3 will be described with reference to the timing chart of FIG. The timing chart of FIG. 4 shows an arbitrary line in the pixel area. In the period up to time t1 in FIG. 4, light enters the embedded photodiode 19 and an electron hole pair is generated by the photoelectric effect, and a hole is formed in the p ⁻ type embedded region (6 in FIG. 1 and FIG. 2) of the photodiode 19. Is accumulated. At time t1, as shown in FIG. 4B, the potential VTG of the transfer gate electrode 5 becomes low level (Low), and hole charges are transferred from the photodiode 19 to the back gate of the signal readout transistor 18 all at once in all pixels. The The source potential VS of the signal read transistor 18 is set to S1 by the source potential control circuit 28 as shown in FIG. S1> Low, which keeps the signal readout transistor 18 off and prevents current from flowing.

  At time t2, the transfer gate electrode potential VTG becomes high level (Vdd) again as shown in FIG. 4B, and the charge transfer transistor 20 is turned off. In the photodiode 19, hole charge accumulation starts again, and this continues until charge transfer in the next frame (field). Since the signal reading of each pixel is performed in order for each row, the period from time t2 to time t3 is a waiting time until the signal of the pixel of one line focused in FIG. 4 is read. The signal readout transistor 18 in the standby state is in an off state because the gate potential VR of the ring-shaped gate electrode 1 is at a low level (Low) as shown in FIG. The source potential VS of the signal readout transistor 18 in the standby state is indicated by S1 in FIG. 4D. While the signal readout from another row is being performed, the signal potential from the pixel Various values other than S1 can be taken.

  At time t3, reading of pixels of one line focused in FIG. 4 starts. First, at time t3, the ring-shaped gate electrode potential VR becomes Vg1 as shown in FIG. This Vg1 is a potential between Low and Vdd. On the other hand, a source follower circuit is connected to the output line 24 by a switch in the signal output circuit 29, and the source potential VS of the signal read transistor 18 becomes S2 (= Vg1-Vth1) as shown in FIG. Here, Vth1 is the threshold voltage of the signal read transistor 18 in a state where there is a hole in the back gate (source vicinity region 4) of the signal read transistor 18. This source potential S 2 is stored in the first capacitor C 1 in the signal output circuit 29.

Next, at time t4, the ring-shaped gate electrode potential VR becomes Vg2 as shown in FIG. 4C, and the source electrode potential VS of the signal read transistor 18 becomes S3 as shown in FIG. Here, Vg2, S3> Low, and it is desirable to set the potential so that the signal read transistor 18 is turned on and no current flows. Further, Vg2 and S3 ≦ Vdd are desirable. In a simple setting, Vg2 = S3 = Vdd. At this time, the potential of the source vicinity region 4 shown in FIG. 2 is raised, and the holes accumulated in the source vicinity region 4 are discharged to the p ⁻ type epitaxial layer 2 beyond the barrier of the n-type well 12 (reset operation). ).

At the end of the reset operation, the impurity concentration in the source vicinity region 4 is selected so that all the holes in the source vicinity region 4 are discharged and the source vicinity region 4 is completely depleted. In the cross-sectional view of FIG. 2, the p ⁺ type reset buried region 14 in the p ⁻ type epitaxial layer 10 below the source vicinity region 4 is provided to lower the voltage of this reset operation.

  Next, at time t5, as shown in FIG. 4C, the ring-shaped gate electrode potential VR becomes Vg1 again. On the other hand, a source follower circuit is connected to the output line 24 in the signal output circuit 29, and the source potential VS of the signal read transistor 18 becomes S0 (= Vg1-Vth0) as shown in FIG. Here, Vth0 is a threshold voltage of the signal readout transistor 18 in a state where there is no hole in the back gate (source vicinity region 4) of the signal readout transistor 18, and it varies depending on the shape of the signal readout transistor 18 and variations in impurity concentration. , Take a slightly different value for each pixel.

  This source potential S0 is stored in the second capacitor C2 in the signal output circuit 29, and the potential difference between the capacitor C1 and the capacitor C2, that is, (Vth0−Vth1) is output by the differential amplifier. This output value is a change in threshold voltage corresponding to the amount of hole charge accumulated by photoelectric conversion, and is a value obtained by correcting variations in threshold voltage characteristics for each pixel. This potential difference signal is output outside the sensor through a switch in the horizontal scanning circuit 30. Note that, after time t1, the drain voltage VD output from the drain voltage control circuit 27 is Vdd as shown in FIG.

  In the above description, the source potential S3 at the time of resetting from time t4 to t5 is supplied from the source potential control circuit 28. However, there is a method in which the potential is made floating. In this case, when the ring-shaped gate electrode potential is Vg2, the signal read transistor 18 is turned on, current is supplied from the drain to the source, and the source electrode potential rises. Accordingly, the potential of the source vicinity region 4 in FIG. 1 is raised, and holes are discharged to the p-type epitaxial layer 10 beyond the barrier of the n-type well 12 (reset operation). The source electrode potential when the holes are completely discharged becomes (Vg2-Vth0). This method can reduce the number of transistors that supply S3 in the source potential control circuit 28, and can reduce the chip area.

  As is apparent from the above description, in this solid-state imaging device, a CMOS sensor is formed by two transistors per pixel, while all the pixels are transferred all at once from the photodiode 19 to the signal readout transistor 18. Therefore, a global shutter function can be realized. In addition, since the photoelectrically converted charge is transferred to the source vicinity region 4 having a small area, the charge-voltage conversion efficiency is high and the output can be increased.

  Further, since the number of transistors per pixel is small, increasing the area ratio of the photodiode in the pixel also contributes to an increase in signal output. Further, when the signal readout transistor 18 is reset, since the source vicinity region 4 is completely depleted, there is an excellent feature that no reset noise is generated due to variations in the residual charge amount at the time of reset.

  The applicant of the present invention has proposed a solid-state imaging device that is represented by the same equivalent circuit as the pixel equivalent circuit and performs the same operation as described above in Japanese Patent Application No. 2004-21895. A cross-sectional view of the proposed solid-state imaging device is as shown in FIG. 14, and the configuration around the source vicinity region 4 is different from that of the embodiment (FIG. 2) of the present invention. In FIG. 14, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  Returning to FIG. 2 again, variations in the overlap dimensions d1 and d2 between the source vicinity region 4 and the ring-shaped gate electrode 1 and variations in the output voltage will be described. When the overlapping dimensions d1 and d2 vary, the capacitance between the source vicinity region 4 and the ring-shaped gate electrode 1 varies, and the potential of the source vicinity region 4 also varies. For example, when the overlap dimensions d1 and d2 are different for each pixel, the capacitance between the source vicinity region 4 and the ring-shaped gate electrode 1 is different for each pixel. As a result, even when the same amount of charge accumulated in the photodiode buried region 6 is transferred to the source vicinity region 4, the output voltage varies for each pixel.

  In addition, when the overlapping dimension is d2> d1 in the same pixel, the potential of the source vicinity region 4 on the overlapping dimension d2 side becomes deeper than that of the d1 side, and the signal charge transferred to the source vicinity region 4 is on the d2 side. It is biased to accumulate. In particular, when the transferred signal charge is small, charge accumulates only on the d2 side of the deeper potential when d1 = d2, and as a result, the output voltage when d2> d1 is smaller than d1 = d2. Since the fluctuation of the output voltage is caused by the range of charge distribution after the photoelectric conversion charge is transferred to the source vicinity region 4 and the bias of the charge distribution, the charge in the source vicinity region 4 described with reference to FIGS. The method of subtracting the output when there is no signal cannot be corrected sufficiently.

  Here, the reason why the overlapping dimension between the source vicinity region 4 and the ring-shaped gate electrode 1 varies will be described with reference to a cross-sectional view (FIG. 14) of the solid-state imaging device proposed by the present applicant in Japanese Patent Application No. 2004-21895. The source vicinity region 4 and the ring-shaped gate electrode 1 shown in FIG. 14 are formed by a general photo process, ion implantation, and etching in an LSI process. Among the manufacturing methods according to this application, a method for manufacturing a portion related to the variation in the overlap size will be described together with the manufacturing process of FIG. 15A to 15E, the same components as those in FIG. 14 are denoted by the same reference numerals.

  First, in FIG. 15A, B (boron) ions are implanted into the n-type well 12 through the gate oxide film 13 using the photoresist 41 as a mask, and the source vicinity region 4 is formed. When making the pattern of the photoresist 41, for example, pattern alignment is performed with reference to an alignment mark made by using a step between the gate oxide film and the isolation oxide film. It varies.

  Next, in FIG. 15B, after removing the photoresist 41 of FIG. 15A, a polysilicon film 42 is deposited on the surface of the gate oxide film 13, and in FIG. 15C, a ring-shaped gate electrode is formed. The pattern of the photoresist 43 for creating the pattern is made. Even when the pattern of the photoresist 43 is formed, the pattern alignment is performed based on the alignment mark using the step between the gate oxide film and the isolation oxide film, so that the position of the ring-shaped gate electrode 1 varies by the pattern alignment error. .

  Next, using the photoresist 43 of FIG. 15C as a mask, the polysilicon film 42 is etched to form the ring-shaped gate electrode 1 using the polysilicon film 42. Subsequently, after the photoresist 43 is peeled off, FIG. ), The transfer gate electrode 5 is formed of a polysilicon layer different from the ring-shaped gate electrode 1, and then As (arsenic) ions are implanted using the ring-shaped gate electrode 1 and the transfer gate electrode 5 as a mask. A source region 2 and a drain region 3 are formed.

  In FIG. 15E where the above steps have been completed, the source region 2 is formed by ion implantation using the central opening of the ring-shaped gate electrode 1 as a mask, so the relative position between the source region 2 and the ring-shaped gate electrode 1 It will not come off. On the other hand, since the source vicinity region 4 and the ring-shaped gate electrode 1 are separately subjected to pattern alignment based on the same alignment mark, the relative position error between them is increased to twice the pattern alignment error of one time. In an ordinary LSI process, a pattern alignment error of about ± 0.1 μm is expected as a single pattern alignment error. Therefore, a pattern alignment error of ± 0.2 μm at maximum occurs in FIG. Even if the overlapping size of the source vicinity region 4 and the ring-shaped gate electrode 1 is designed to be 0.6 μm on both the left and right sides, in reality, as shown by d5 and d6 in FIG. It will vary between 4 and 0.8 μm.

  Next, a first embodiment of the manufacturing method of the solid-state imaging device of the present invention that can suppress the variation in the overlapping dimension between the source vicinity region 4 and the ring-shaped gate electrode 1 will be described with reference to FIGS. 5 to 10 show only processes related to the overlapping dimension between the source vicinity region 4 and the ring-shaped gate electrode 1. 5 to 10, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.

First, as shown in FIG. 5, a photoresist 31 having a region where the ring-shaped gate electrode 1 and the source vicinity region 4 are formed as openings 31 a is formed on the gate oxide film 13, and then the photoresist 31 is formed. As a mask, B (boron) is ion-implanted into the n-type well 12 through the gate oxide film 13 under conditions of an acceleration energy of 100 keV and a dose of 1.0E12 cm ⁻² to form a p-type enlarged source vicinity region 32. To do. A part of the enlarged source vicinity region 32 finally becomes the source vicinity region 4. When the pattern of the photoresist 31 is formed, the pattern alignment is performed with reference to an alignment mark formed by using a step between the gate oxide film 13 and the isolation oxide film, for example. 32 positions vary.

  Next, in FIG. 6, after removing the photoresist 31 of FIG. 5, the polysilicon film deposited on the surface of the gate oxide film 13 is processed by a photo process and etching to form the ring-shaped gate electrode 1. Even when the photoresist pattern of the ring-shaped gate electrode 1 is formed, pattern alignment is performed with reference to an alignment mark using a step between the gate oxide film 13 and the isolation oxide film. The relative position of 32 varies by an amount corresponding to two pattern alignment errors. Also in this case, r1 in FIG. 6 is set to a size of about two pattern alignment errors so that the outer end of the ring-shaped gate electrode 1 is at the same position as the outer periphery of the enlarged source vicinity region 32.

Next, as shown in FIG. 7, a photoresist 33 is formed so as to cover the upper part of the p ⁻ type buried region 6 of the photodiode and the central opening of the ring-shaped gate electrode 1. At this time, since pattern alignment is performed with reference to an alignment mark using a polysilicon film in the same layer as the ring-shaped gate electrode 1, the relative position between the ring-shaped gate electrode 1 and the photoresist 33 at its central opening is It varies according to the pattern matching error of one time. Also in this case, the outer end of the ring-shaped gate electrode 1 indicated by r2 in FIG. 7 and the outer periphery of the photoresist 33 so that the outer periphery of the photoresist 33 covering the central opening portion is located on the inner side with respect to the outer end of the ring-shaped gate electrode 1. The distance from the outer peripheral edge of the photoresist 33 covering the central opening is made larger than one pattern alignment error. This is because ion implantation is performed using the outer end of the ring-shaped gate electrode 1 as a mask in a later step.

Next, as shown in FIG. 8, by using the photoresist 33 and the ring-shaped gate electrode 1 as a mask and applying an ion implantation method, for example, P (phosphorus) under the conditions of an acceleration energy of 350 keV and a dose of 2.0E12 cm ^−2. ) Ions are implanted from an oblique direction to form the n-type transfer channel region 8. Since the substrate is rotated when ions are implanted from an oblique direction, the implanted P ions enter the lower part from the periphery of the ring-shaped gate electrode 1. If oblique ion implantation is performed so that the impurity concentration of the transfer channel region 8 is higher than or equal to the impurity concentration of the enlarged source vicinity region 32 in FIG. 7, the peripheral region below the ring-shaped gate electrode 1 is also formed. A transfer channel region 8 is formed.

  The dimension of the overlapping portion of the transfer channel region 8 and the ring-shaped gate electrode 1 is determined by the implantation angle of oblique ion implantation, the implantation voltage, and the implantation amount. But it is almost the same value. As a result of the transfer channel region 8 being also formed under the ring-shaped gate electrode 1, the portion of the enlarged source vicinity region 32 shown in FIG. 7 where the transfer channel region 8 is not formed is the source vicinity region 4. Become.

Next, after removing the photoresist 33 shown in FIG. 8, as shown in FIG. 9, a transfer gate electrode 5 is formed with a polysilicon layer different from the ring-shaped gate electrode 1, As shown, As (arsenic) ions are implanted under the conditions of, for example, an acceleration energy of 50 keV and a dose of 1.5E15 cm ^{−2 by using} the ring-shaped gate electrode 1 and the transfer gate electrode 5 as a mask. Then, an n ⁺ type source region 2 and an n ⁺ type drain region 3 are formed.

  In FIG. 10, the overlapping dimensions d1 and d2 between the source vicinity region 4 and the ring-shaped gate electrode 1 are the overlapping dimensions d3 and d4 between the transfer channel region 8 and the ring-shaped gate electrode 1 from the ring-shaped gate widths W1 and W2. Subtracted value. The overlapping dimensions d3 and d4 of the transfer channel region 8 and the ring-shaped gate electrode 1 are determined by the ion penetration depth from the outer periphery of the ring-shaped gate electrode 1 as shown in FIG. Further, the widths W1 and W2 of the ring-shaped gate electrode 1 can be regarded as substantially the same because they are formed by the same photo process and etching using a photomask having the same dimensions.

  As a result, the overlapping dimensions d1 and d2 of the source vicinity region 4 and the ring-shaped gate electrode 1 are substantially the same. As is apparent from the above description, the overlapping dimensions d1 and d2 are not affected by the pattern alignment error of the photo process, and d1 = d2 can be stably realized, and variations in potential and capacitance in the source vicinity region 4 are reduced. it can.

  That is, according to the present embodiment, the size of the source vicinity region 4 can be determined in a self-aligned manner and can be prevented from being affected by the pattern alignment error of the photo process, so that variations in the source vicinity region 4 can be reduced. As a result, variations in potential in the source vicinity region 4 and variations in capacitance between the source vicinity region 4 and the ring-shaped gate electrode 1 can be reduced.

  In addition, according to the present embodiment, the source vicinity region 4 is configured to be in contact with and surround the source region 2, so that the capacitance between the source vicinity region 4 and the source region 2 is the pattern of the photo process. The value is almost constant without being affected by the alignment error. From the above, according to the present embodiment, variations in potential and capacitance of the source vicinity region 4 for transferring photoelectric conversion charges can be suppressed, so that a solid-state imaging device with improved variation in signal output voltage can be manufactured.

Next, the manufacturing process of the principal part of 2nd Embodiment of the manufacturing method of the solid-state imaging device which becomes this invention is demonstrated with reference to FIGS. FIG. 11 is a device sectional view in the manufacturing process corresponding to FIG. 7 of the first embodiment, in which a p-type enlarged source vicinity injection region 34 and a ring-shaped gate electrode 1 are formed, and a photodiode is formed. A photoresist pattern 33 is formed so as to cover the upper part of the p ⁻ type buried region 6 and the central opening of the ring-shaped gate electrode 1. In FIG. 11, the p-type enlarged source vicinity implantation region 34 and the reset buried implantation region 35 are formed with a shallower junction depth than the corresponding enlarged source neighborhood region 32 and p ⁺ type reset buried region 14 in FIG. Is done.

Next, in FIG. 12, by using the photoresist 33 and the ring-shaped gate electrode 1 as a mask and applying an ion implantation method, for example, P (phosphorus) ions under conditions of an acceleration energy of 200 keV and a dose of 2.0E12 cm ^−2. N-type transfer channel injection region 36 is formed. Unlike the oblique ion implantation in FIG. 8 of the first embodiment, this ion implantation is performed by a normal method of implanting at an angle of about 0 degrees to 10 degrees. After removing the photoresist 33 after ion implantation, cleaning and heat treatment are performed, and each ion implantation layer is diffused as shown in FIG. 13 to expand the vicinity of the enlarged source implantation region 34, the transfer channel implantation region 36, the reset embedding in FIG. The injection region 35 becomes the source vicinity region 4, the transfer channel region 8, and the reset buried region 37 in FIG.

  The transfer channel implantation region 36 shown in FIG. 12 has an impurity concentration higher than or substantially the same as that of the enlarged source vicinity implantation region 34. Therefore, in FIG. The junction of the region 4 enters under the ring-shaped gate electrode. The overlapping dimension of the transfer channel region 8 and the ring-shaped gate electrode 1 is determined by the temperature and time of the heat treatment, but is almost the same value in the entire outer periphery of the ring-shaped gate electrode.

  That is, the oblique ion implantation process of FIG. 8 in the first embodiment is replaced with normal ion implantation and heat treatment in the manufacturing process of the present embodiment. The subsequent manufacturing process and the stability of the overlapping dimension between the source vicinity region 4 and the ring-shaped gate electrode 1 are the same as those in the manufacturing process of the first embodiment, and the description thereof will be omitted.

  As described above, in the manufacturing method according to the embodiment of the present invention, the impurity concentration of the transfer channel region 8 is made higher than or equal to the impurity concentration of the source vicinity region 4, and the ring-shaped gate electrode By forming the transfer channel region 8 by oblique ion implantation or normal ion implantation and diffusion using the outer peripheral portion of 1 as a mask, the overlapping dimensions d3 and d4 of the ring-shaped gate electrode 1 and the transfer channel region 8 are made constant. As a result, variations in the overlap dimensions d1 and d2 between the source vicinity region 4 and the ring-shaped gate electrode 1 are reduced.

  8, 9, 10, and 13, which show the above manufacturing process, show device cross sections when the impurity concentration of the transfer channel region 8 is higher than the impurity concentration of the source vicinity region 4. When the impurity concentration of the channel region 8 and the source vicinity region 4 is approximately the same, the vicinity of the boundary between the transfer channel region 8 and the source vicinity region 4 is depleted, and the depletion layer enters under the ring-shaped gate electrode 1. Since the width of the depletion layer at this time is determined in a self-aligned manner by oblique ion implantation or diffusion using the ring-shaped gate electrode 1 as a mask, the same effects as those described in the above embodiment can be obtained.

It is a top view of the unit pixel of one embodiment of the solid-state imaging device of the present invention. It is sectional drawing of the unit pixel of one Embodiment of the solid-state imaging device of this invention. 1 is an equivalent circuit diagram of an embodiment of a solid-state imaging device of the present invention. 5 is a timing chart for explaining the operation of the equivalent circuit of FIG. 4. It is element sectional drawing (the 1) for manufacturing process description of 1st Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is element sectional drawing (the 2) for manufacturing process description of 1st Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is element sectional drawing (the 3) for manufacturing process description of 1st Embodiment of the manufacturing method of the solid-state imaging device of this invention. FIG. 6 is a cross-sectional view (part 4) of an element for explaining a manufacturing process of the first embodiment of the manufacturing method of the solid-state imaging device of the present invention. It is element sectional drawing (the 5) for manufacturing process description of 1st Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is element sectional drawing (the 6) for manufacturing process description of 1st Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is element sectional drawing (the 1) for manufacturing process description of 2nd Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is element | device sectional drawing for explaining the manufacturing process of 2nd Embodiment of the manufacturing method of the solid-state imaging device of this invention (the 2). It is element sectional drawing (the 3) for manufacturing process description of 2nd Embodiment of the manufacturing method of the solid-state imaging device of this invention. It is sectional drawing of an example of the solid-state imaging device concerning the previous application by this applicant. It is a manufacturing process figure of an example of the manufacturing method of the solid-state imaging device concerning the previous application by the present applicant. It is explanatory drawing of the image distortion of a line shutter operation | movement.

Explanation of symbols

1 Ring-shaped gate electrode
2 Source region 3 Drain region 4 Source neighborhood region
5 p ^- type transfer gate electrode
6 p ⁻ type buried region 7 n ⁺ type surface region 8 transfer channel region
9 p ⁺ substrate 10 p ^- epitaxial layer 11, 12 n-type well 13 gate oxide film 14 p ⁺ -type reset buried region 18 signal readout transistor 19 photodiode 20 pixel transfer transistor 21 ring gate bus wiring 22 transfer bus wiring 23 for drain Bus wiring 24 Output line 25 Vertical scanning circuit 26 Transfer gate drive circuit 27 Drain voltage control circuit 28 Source potential control circuit 29 Signal output circuit 30 Horizontal scanning circuit 31, 33 Photoresist 32 Expanded source vicinity area 34 Expanded source vicinity injection area 35 Reset Embedded injection region 36 Transfer channel injection region 37 Reset embedded region

Claims (4)

A ring-shaped gate electrode having a ring shape on a substrate, a source region provided at a position of the substrate corresponding to a central opening of the ring-shaped gate electrode, and surrounding the source region, and the ring shape A signal output transistor that includes a region near the source provided on the substrate so as not to reach the outer periphery of the gate electrode, and outputs the amount of input charge as a change in threshold voltage;
A photoelectric conversion region for converting light into electric charge;
A plurality of unit pixels including charge transfer means for transferring the charge accumulated in the photoelectric conversion region to the source vicinity region of the signal output transistor;
The charge transfer means includes a charge transfer channel region provided on the substrate, the charge transfer channel region being in contact with the source vicinity region of the signal output transistor and surrounding the source vicinity region. A solid-state imaging device.   2. The solid-state imaging device according to claim 1, wherein the charge transfer channel region of the charge transfer means has an impurity concentration higher than an impurity concentration in a region near the source of the signal output transistor. A manufacturing method for manufacturing the solid-state imaging device according to claim 1,
A first step of forming a second conductivity type well in a first conductivity type substrate;
A second step of forming a first conductivity type enlarged source vicinity region and a first conductivity type photoelectric conversion region apart from each other in the second conductivity type well;
A ring-shaped gate electrode is formed on the enlarged source vicinity region via a gate insulating film, the ring-shaped gate electrode having a planar shape in a ring shape and having an outer peripheral end located inside an outer peripheral end of the enlarged source vicinity region. And the process of
Using the outer periphery of the ring-shaped gate electrode as a mask, the second conductivity type impurity is ion-implanted from an oblique direction so as to reach from the outer peripheral end of the region near the enlarged source to a portion below the ring-shaped gate electrode A second conductivity type charge transfer channel region is formed, and the enlarged source vicinity region including a position corresponding to a central opening of the ring-shaped gate electrode not formed as the charge transfer channel region is left as a source vicinity region. A solid-state imaging device manufacturing method comprising: a fourth step. A manufacturing method for manufacturing the solid-state imaging device according to claim 1,
A first step of forming a second conductivity type well in a first conductivity type substrate;
A second step of forming a first conductivity type enlarged source vicinity region and a first conductivity type photoelectric conversion region apart from each other in the second conductivity type well;
A ring-shaped gate electrode is formed on the enlarged source vicinity region via a gate insulating film, the ring-shaped gate electrode having a planar shape in a ring shape and having an outer peripheral end located inside an outer peripheral end of the enlarged source vicinity region. And the process of
Using the outer periphery of the ring-shaped gate electrode as a mask, ion implantation of impurities of the second conductivity type is performed, and a second conductivity-type charge transfer channel is formed on the surface of the well outside the outer periphery of the ring-shaped gate electrode. A fourth step of forming the region;
The charge transfer channel region is diffused so as to reach a part under the ring-shaped gate electrode by heat treatment after the ion implantation, and the central opening of the ring-shaped gate electrode that is not diffused as the charge transfer channel region And a fifth step of leaving the enlarged source vicinity region including the position corresponding to the part as the source vicinity region.

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