JP2007073544A - Solid state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging device in which linearity of a source-follower circuit can be enhanced and a dynamic range can be widened while suppressing back bias effect as compared with prior art, and to provide its manufacturing method. <P>SOLUTION: A pixel cell comprising a light receiving element and a first transistor is provided in a pixel region A on a semiconductor substrate 21, a peripheral circuit comprising a second transistor is provided in a peripheral circuit region B, and the conductivity type of the source-drain region 29 of the second transistor is identical to that of the source-drain region 29 of the first transistor. In the fabrication process of such a solid state imaging device, first ion implantation is performed in the second transistor forming region within the peripheral circuit region B, and second ion implantation is performed in the second transistor forming region and the first transistor forming region A2 within the pixel region A. Consequently, a well (semiconductor region 26) having impurity concentration lower than that in the well (semiconductor region 24A) of the peripheral circuit B is formed in the pixel region A. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, in particular, a MOS solid-state imaging device and a manufacturing method thereof.

  In recent years, a solid-state imaging device (MOS-type solid-state imaging device) including an amplification type MOS transistor has attracted attention in terms of high sensitivity and the like. The MOS type solid-state imaging device includes a photodiode and a MOS transistor for each pixel, and amplifies a signal detected by the photodiode by the MOS transistor.

  A conventional MOS type solid-state imaging device will be described with reference to FIGS. FIG. 4 is a plan view showing a schematic configuration of a conventional MOS solid-state imaging device. As shown in FIG. 4, the MOS type solid-state imaging device 90 includes a plurality of pixel cells (see FIG. 5) in the pixel region 200 on the semiconductor substrate 7. In addition, peripheral areas (peripheral circuit areas) 201 and 202 of the pixel area are provided with peripheral circuits for driving the pixel cells.

  FIG. 5 is a circuit diagram showing an example of a circuit configuration of a conventional MOS type solid-state imaging device. As shown in FIG. 5, the MOS type solid-state imaging device 90 includes a plurality of pixel cells 96 in the pixel region 200 on the semiconductor substrate 7. The plurality of pixel cells 96 are arranged in a matrix on the semiconductor substrate 7. Each pixel cell 96 includes a photodiode 3, a transfer transistor 4, an amplification transistor 14, a reset transistor 15, and a vertical selection transistor 16.

  The photodiode 3 converts incident light into signal charges and accumulates them. The transfer transistor 4, the amplification transistor 14, the reset transistor 15, and the vertical selection transistor 16 are used for reading signal charges accumulated in the photodiode 3.

  Specifically, the transfer transistor 4 reads signal charges accumulated in the photodiode 3. The amplification transistor 14 amplifies the signal charge read by the transfer transistor 4 and outputs it. The reset transistor 15 resets the signal charge accumulated in the photodiode 3.

  The solid-state imaging device 90 includes a vertical drive circuit 12, a horizontal drive circuit 13, a load transistor group 17, and a row signal storage unit 18 in the peripheral circuit region on the semiconductor substrate 7. The vertical drive circuit 12 is connected to the gate of the reset transistor 15 for each horizontal line via a plurality of reset transistor control lines 111. The reset transistor control lines 111 are arranged in parallel to each other along the horizontal direction at a constant interval.

  The vertical drive circuit 12 is also connected to the transfer transistor 4 for each horizontal line via a plurality of transfer transistor control lines 131. The transfer transistor control lines 131 are also arranged in parallel to each other along the horizontal direction at a constant interval.

  Further, the vertical drive circuit 12 is also connected to the vertical selection transistor 16 for each horizontal line via a plurality of vertical selection transistor control lines 121. The vertical drive circuit 12 selects a row from which a signal is read via the vertical selection transistor control line 121. As with the reset transistor control line 111, the vertical selection transistor control lines 121 are also arranged in parallel to each other along the horizontal direction at a constant interval.

  The horizontal drive circuit 13 is connected to the row signal storage unit 18. The row signal storage unit 18 includes a switching transistor for capturing a signal for one row. The row signal storage unit 18 and the load transistor group 17 are connected via a vertical signal line 161. The row signal storage unit 18 and the load transistor group 17 are connected to the source of the vertical selection transistor 16 for each vertical line via the vertical signal line 161.

  Next, the operation of the solid-state imaging device shown in FIG. 5 will be described with reference to FIG. FIG. 6 is a timing chart for explaining the operation of the conventional solid-state imaging device shown in FIG. In the following description, FIG. 5 is taken into consideration as appropriate.

  As shown in FIG. 6, first, a high-level row selection pulse 101-1 is applied from the vertical drive circuit 12 to the vertical selection transistor control line 121 of the selected row. As a result, the vertical selection transistors 16 in the selected row are turned on. At this time, a source follower circuit is configured by the amplification transistor 14 and the load transistor group 17 in the selected row.

  Next, while the row selection pulse 101-1 is at the high level, the high level reset pulse 102-1 is applied to the reset transistor control line 111 of the selected row. As a result, the potential of the floating diffusion layer (semiconductor region 154 shown in FIG. 7 described later) connected to the gate of the amplification transistor 14 in the selected row is reset.

  Next, while the row selection pulse 101-1 is at the high level, the high level transfer pulse 103-1 is applied to the transfer transistor control line 131 of the selected row. Thereby, the signal charge accumulated in the photodiode 3 is transferred to the floating diffusion layer.

  Further, when the high-level transfer pulse 103-1 is applied, the gate voltage of the amplification transistor 14 connected to the floating diffusion layer becomes equal to the potential of the floating diffusion layer, and a voltage substantially equal to this gate voltage is obtained. It appears on the vertical signal line 161. Then, a signal based on the signal charge accumulated in the photodiode 3 is transferred to the row signal accumulation unit 18.

  Thereafter, until the vertical drive circuit 12 selects the next row, the high-level column selection pulses 106-1-x and 106-2- are sequentially supplied from the horizontal drive circuit 13 to the vertical signal lines 161. x,... 106-mx (m is a natural number, x is any one of 1 to n (natural number)) is output. At this time, the row signal storage unit 18 takes out signals transferred thereto as output signals 107-1, 107-2,... 107-n for each row.

  Next, a specific configuration of the solid-state imaging device illustrated in FIG. 5 will be described with reference to FIGS. 7 and 8. FIG. 7 is an enlarged plan view showing a part of the conventional solid-state imaging device shown in FIG. FIG. 8 is an enlarged cross-sectional view showing a part of the conventional solid-state imaging device shown in FIG. The cross section shown in FIG. 8 is a cross section cut along the cutting line A-B-C-D shown in FIG. In FIG. 7, the illustration of the semiconductor substrate is omitted.

  As shown in FIG. 7, the photodiode 3 includes an n-type semiconductor region 151 provided in the semiconductor substrate 7 (see FIG. 8). In the semiconductor substrate 7, an element isolation portion 92 is formed between adjacent semiconductor regions 151. A plurality of n-type semiconductor regions 5 a to 5 c are formed in the region adjacent to the semiconductor region 151 of the photodiode 3 in the horizontal direction via the element isolation part 91. The semiconductor regions 5a to 5c are arranged in the vertical direction. Further, an n-type semiconductor region 154 is formed in a region adjacent to the semiconductor region 151 in the vertical direction.

  Gate electrodes 153a and 153b are formed between the adjacent semiconductor regions 5a and 5b and between the semiconductor regions 5b and 5c through gate insulating films 156 (see FIG. 8), respectively. Has been. Further, a gate electrode 152 extending in the horizontal direction is formed between the semiconductor region 151 and the semiconductor region 154 via a gate insulating film (not shown). The gate electrode 152 also functions as a transfer transistor control line 131 (see FIG. 5).

  7 and 8, the transfer transistor 4 is configured by the gate electrode 152, the semiconductor region 154, the semiconductor region 151, and the gate insulating film (not shown). The transfer transistor 4 uses the semiconductor region 151 of the photodiode 3 as a source region. In addition, the reset transistor 15 is configured by the gate electrode 153a, the semiconductor regions 5a and 5b, and the gate insulating film 156, and the amplification transistor 14 is configured by the gate electrode 153b, the semiconductor regions 5b and 5c, and the gate insulating film 156. Has been. The reset transistor 15 and the amplification transistor 14 share the semiconductor region 15b.

  In FIG. 7, reference numeral 155 denotes a wiring. The wiring 155 is connected to the semiconductor region 154, the semiconductor region 5a, and the gate electrode 153b through a contact 156.

  By the way, as shown in FIG. 7 and FIG. 8, an element isolation portion is formed in the pixel cell. With the recent miniaturization of pixels in MOS type solid-state imaging devices, the element isolation portion is often It is formed by using STI (Shallow Trench Isolation) method for forming a groove in a semiconductor substrate.

  However, an element isolation part formed by the STI method (hereinafter referred to as “STI element isolation part”) has a problem that crystal defects and stress defects occur in the vicinity of the element isolation part. Specifically, when a crystal defect occurs in the MOS type fixed imaging device, the output is large and white point defects, so-called white scratches, are observed on the reproduction screen. The number depends on the STI formation method and the scale of the solid-state imaging device, but can be from several to thousands. Further, when a stress defect occurs in the MOS type solid-state imaging device, the STI stress defect layer generates a leak current that flows from the element isolation portion to the photodiode, so that a small nonuniformity is observed on the reproduction screen.

  Among such defects, the local point defect (white flaw) due to the former crystal defect can be corrected by recent advances in digital technology, and is no longer a major problem. However, it is difficult to correct small unevenness due to the latter STI stress defect layer by digital processing. This is because a large-capacity memory is required to correct unevenness that occurs over the entire screen, and the cost of the system for correction is high.

  Therefore, it has been proposed to provide an STI leak stopper by introducing an impurity having a conductivity type opposite to that of the source / drain region of the MOS transistor into the formation region of the STI element isolation portion (see, for example, Patent Document 1). .) Patent Document 1 discloses an example in which an STI leak stopper is formed so as to surround a side surface and a bottom surface of an element isolation portion. In the case where the STI leak stopper is provided, the leakage current flowing from the element isolation portion to the photodiode can be prevented, and thereby uneven unevenness in the reproduction screen can be reduced.

  Here, a conventional STI leak stopper will be described with reference to FIG. FIG. 9 is a partial cross-sectional view showing a manufacturing process of a conventional MOS type solid-state imaging device in which an STI leak stopper is formed, and FIGS. 9A to 9D show a series of main processes. 9A to 9D, the pixel region A is shown on the left half, and the peripheral circuit region B is shown on the right half.

  In general, in the case of a MOS type solid-state imaging device, both an N-channel MOS transistor and a P-channel MOS transistor are formed on a semiconductor substrate. In FIGS. 9A to 9D, an N-channel MOS transistor is used. Only the region where the transistor is formed (NMOS region) is shown. Moreover, in FIG. 9 (a)-(d), only the line which appeared in the cross section is shown in figure.

  First, as shown in FIG. 9A, a groove 701 for forming the STI element region is selectively formed in the STI element isolation region formation region in the semiconductor substrate 7. Next, a resist pattern 702 having an opening in the pixel region A is formed, and using this as a mask, impurities are ion-implanted from an oblique direction. As a result, the STI leak stopper 703 is formed along the side surface and the bottom surface of the groove 701. In this example, the semiconductor substrate 7 is an n-type silicon substrate. Here, a p-type impurity is ion-implanted because it also serves to separate two photodiodes formed by an n-type impurity described later.

  However, when the process of FIG. 9A is performed, the p-type impurity is used to read out the region other than the formation region of the STI element isolation portion, that is, the formation region A1 of the photodiode and the signal charge accumulated in the photodiode. It is also injected into the formation region A2 of the transistor to be used (readout transistor). For this reason, the concentration of the wells (see FIG. 9B) formed in the formation region A1 and the formation region A2 is higher than the concentration of the wells formed in the peripheral circuit region B (see FIG. 9B). .

  Next, as shown in FIG. 9B, after removing the resist pattern 702, an insulator such as a silicon oxide film is embedded in the groove 701 to form an STI element isolation portion 704. Next, a resist pattern 705 having openings in the formation region A2 and the peripheral circuit region B is formed, and p-type impurities are ion-implanted using the resist pattern 705 as a mask. As a result, a p-type well 706 is formed.

Subsequently, p-type impurities are ion-implanted using the resist pattern 705 as a mask. As a result, a transistor channel region 707 is formed in the formation region A2 and the peripheral circuit region B. Note that the threshold voltage V _T of the transistor can be controlled by adjusting the impurity concentration in the channel region 707.

  Next, as shown in FIG. 9C, after removing the resist pattern 705, a resist pattern 709 (indicated by a broken line) having an opening in the formation region A1 is formed, and using this as a mask, n-type impurities are ion-implanted. To do. As a result, an n-type semiconductor region 710 constituting the photodiode is formed. Note that the semiconductor region 710 can be formed before the channel region 707 is formed.

  Next, after removing the resist pattern 709, a gate insulating film 714 made of a silicon oxide film and a gate electrode 708 made of polysilicon are sequentially formed in the formation region A2 and the peripheral circuit region B.

  Next, as shown in FIG. 9D, an insulating film is formed and etched to form sidewall insulating films (sidewall spacers) 711 on the side surfaces of the gate insulating film 714 and the gate electrode 708. Subsequently, a resist pattern 712 having openings in the formation region A2 and the peripheral circuit region B is formed, and n-type impurities are ion-implanted using the resist pattern 712 as a mask. Thereby, a source / drain region 713 of the transistor is formed. Thereafter, an interlayer insulating film, various wirings, microlenses, and the like are formed to complete the MOS type solid-state imaging device.

  In the example shown in FIG. 9, since the STI leak stopper 703 is formed in this way, the leak current flowing from the element isolation portion 704 to the photodiode (semiconductor region 710) can be prevented. As a result, uneven unevenness on the playback screen can be reduced.

  However, if a leak stopper is formed in the vicinity of the element isolation portion, the concentration of the well formed in the pixel region increases due to the formation of the leak stopper. For this reason, the back bias effect is likely to occur in the transistor formed on the semiconductor substrate, and the output characteristics of the source follower circuit configured in the MOS solid-state imaging device are deteriorated. This point will be described below.

In general, in a MOSFET, one of the most important parameters is the threshold voltage V _T. The ideal threshold voltage V _T is given by the following formula (1). In the following formula (1), ε _S is the dielectric constant of silicon, q is the charge amount of one electron, N _A is the impurity concentration of the semiconductor substrate (substrate), ψ _B is the Fermi level of silicon, C _OX Is a gate oxide film capacitance value per unit area.

In the MOSFET, the threshold voltage V _T is affected by the substrate bias voltage V _BS . That is, when a reverse voltage is applied between the semiconductor substrate and the source, the width of the depletion layer increases and the threshold voltage V _T necessary for causing inversion increases. This is called a so-called back bias effect. The threshold voltage V _T can be expressed by the following equation (2) using the substrate bias V _BS . In the following formula (2), V _T0 is a threshold voltage when V _BS is 0 (zero).

  Here, as shown in the following formula (3), when γ is set, the above formula (2) can be expressed by the following formula (4). In the following equation (4), the voltage represented on the right side represents an error from the ideal output.

FIG. 10 is a circuit diagram showing a circuit configuration of a basic source follower circuit. The source follower circuit can be used with a low power supply voltage and has a quick response, and is useful as a level shift circuit. In FIG. 10, since the transistor M _A is not grounded, the threshold voltage V _T is easily affected by the back bias effect. Further, the potentials V _in , V _G , and V _OUT shown in FIG. 10 can be expressed by the following formula (5) using the above formula (4).

Furthermore, in the source follower circuit shown in FIG. 10, the voltage gain A _v (= V _out / V _in ) is expressed by the following formula (6) from the following formula (5).

From the above equation (6), when the value of γ is small, A _v ≈1. Further, from the above equation (6), the larger the value of γ, the more the linearity is lost and the voltage gain becomes smaller. For this reason, if the value of γ is reduced, the linearity of the source follower circuit can be improved. Also, if the value of γ is reduced, the voltage gain can be increased, so that the dynamic range can be expanded in the MOS type solid-state imaging device.

From the equation (3), in order to reduce the value of γ may can be seen that by reducing the impurity concentration N _A of the semiconductor substrate. Therefore, the output characteristics of the source follower circuit can be improved by reducing the concentration of the well formed in the pixel region.

  However, as described above, when the leak stopper is formed in the vicinity of the element isolation portion, the concentration of the well formed in the pixel region increases due to the formation of the leak stopper. For this reason, it is difficult to improve the linearity of the source follower circuit and to expand the dynamic range.

In order to solve such a problem, a method has been proposed in which an impurity having a conductivity type opposite to that of the well is counter-doped immediately below the gate of the output transistor constituting the source follower circuit (for example, Patent Document 2). reference.). According to the method disclosed in Patent Document 2, it is possible to reduce the impurity concentration N _A of the semiconductor substrate, it is possible to increase the linearity improved and the dynamic range of the source follower circuit. Further, since the impurity concentration in the surface layer of the well can be reduced, fluctuations in the threshold voltage V _T can be suppressed, and as a result, the back bias effect in the transistor can also be suppressed.
JP 2004-253729 A JP 2004-241638 A

However, in the counter-doping disclosed in Patent Document 2, since impurity ions having different conductivity types are implanted a plurality of times, there is a problem that variations in the respective impurity concentrations are combined to increase the variations. In practice, it is difficult to completely cancel the n-type impurity and the p-type impurity in the same amount, and there is a problem that the threshold voltage V _T varies depending on the degree of cancellation. For this reason, the method disclosed in Patent Document 2 has a problem that the back bias effect cannot be sufficiently suppressed.

  An object of the present invention is to provide a solid-state imaging device capable of solving the above-described problems, suppressing the back bias effect as compared with the prior art, and improving the linearity of the source follower circuit and expanding the dynamic range, and a manufacturing method thereof. There is to do.

  To achieve the above object, a first solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region. Each of the plurality of pixel cells includes a light receiving element and a plurality of first transistors for reading signal charges accumulated in the light receiving element, and the peripheral circuit includes a source region. And a plurality of second transistors having the same conductivity type as the source region and the drain region of the first transistor, and the source region and the drain region of each of the plurality of first transistors are: A source region and a drain region of each of the plurality of second transistors are formed in a first semiconductor region formed in the pixel region. The impurity concentration of the first semiconductor region formed in the second semiconductor region formed in the peripheral region and in the pixel region is the second semiconductor region formed in the peripheral region. It is characterized by being set to a value lower than the impurity concentration.

  In order to achieve the above object, a second solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region. In the solid-state imaging device provided, each of the plurality of pixel cells includes a light receiving element and a plurality of transistors for reading signal charges accumulated in the light receiving element, and the pixel region and the peripheral region A plurality of element isolation portions are provided, and among the element isolation portions provided in the pixel region, the side surface side and the bottom surface side of the element isolation portion that separates adjacent light receiving elements are separated from the light receiving element and the transistor. A leak stopper is formed on the light receiving element side of the element isolation portion to be formed by an impurity having a conductivity type opposite to the conductivity type of the source region and the drain region of the first transistor. And said that you are.

  In order to achieve the above object, a first method for manufacturing a solid-state imaging device according to the present invention includes a semiconductor substrate, and reads a light receiving element and a signal charge accumulated in the light receiving element in a pixel region on the semiconductor substrate. A plurality of pixel cells including a plurality of first transistors, a peripheral circuit including a plurality of second transistors provided in a peripheral region of the pixel region, and a source region and a drain region of the second transistor Is a method for manufacturing a solid-state imaging device in which the conductivity type of the first transistor is the same as the conductivity type of the source region and the drain region of the first transistor, and (a) a formation region of the plurality of second transistors in the peripheral region And (b) forming the plurality of second transistors in the peripheral region, and the plurality of first transistors in the pixel region. The formation region of the transistor, and having a step of performing a second ion implantation.

  In order to achieve the above object, a second method for manufacturing a solid-state imaging device according to the present invention includes a semiconductor substrate, and a light receiving element and a signal charge accumulated in the light receiving element are provided in a pixel region on the semiconductor substrate. A manufacturing method of a solid-state imaging device in which a plurality of pixel cells each including a plurality of transistors for reading are provided, and a peripheral circuit is provided in a peripheral region of the pixel region, wherein (a) the pixel region and the peripheral region A step of forming a plurality of element isolation portions; and (b) a side surface side and a bottom surface side of an element isolation portion that isolates adjacent light receiving elements, and the light reception of the element isolation portion that isolates the light receiving element and the transistor. A conductivity type opposite to the conductivity type of the source region and drain region of the transistor from a direction inclined with respect to the normal line of the semiconductor substrate so that a leak stopper is formed on the element side And having a step of ion-implanting an impurity.

  In the first solid-state imaging device and the manufacturing method thereof according to the present invention, the impurity concentration of the semiconductor region in which the first transistor of the pixel cell is disposed is higher than the impurity concentration of the semiconductor region in which the second transistor of the peripheral circuit is disposed. Is also set to a low value.

Therefore, in the first solid-state imaging device and the first solid-state imaging device manufacturing method of the present invention, the back bias effect of the output transistor can be suppressed, so that the dynamic range and linearity in the source follower circuit are ensured. In addition, since it is not necessary to perform counter doping as in the prior art, fluctuations in the threshold voltage V _T of the output transistor constituting the source follower circuit can be suppressed.

  In addition, according to the second solid-state imaging device and the second solid-state imaging device manufacturing method of the present invention, the side surface side and the bottom surface side of the element separation unit that separates adjacent light receiving elements, and the light receiving element and the transistor are separated A leak stopper is formed only on the light receiving element side of the element separating portion. Therefore, it can be suppressed that the impurity concentration of the semiconductor region in which the transistor constituting the pixel cell is arranged is increased by the leak stopper.

For this reason, in the 2nd solid-state imaging device of this invention and the manufacturing method of the 2nd solid-state imaging device, since the back bias effect of an output transistor can be suppressed, the dynamic range and linearity in a source follower circuit are ensured. In addition, since it is not necessary to perform counter doping as in the prior art, fluctuations in the threshold voltage V _T of the output transistor constituting the source follower circuit can be suppressed.

  A first solid-state imaging device according to the present invention is a solid-state imaging device including a semiconductor substrate, wherein a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region. Each of the plurality of pixel cells includes a light receiving element and a plurality of first transistors for reading signal charges accumulated in the light receiving element, and the peripheral circuit has a conductivity type of a source region and a drain region. A plurality of second transistors having the same conductivity type as the source region and drain region of the first transistor are provided, and the source region and the drain region of each of the plurality of first transistors are formed in the pixel region. Formed in the first semiconductor region, and the source region and the drain region of each of the plurality of second transistors are formed in the peripheral region. The impurity concentration of the first semiconductor region formed in the semiconductor region is lower than the impurity concentration of the second semiconductor region formed in the peripheral region. It is characterized by being set.

  In the first solid-state imaging device according to the present invention, the first semiconductor region functions as a well of the first transistor, and the second semiconductor region functions as a well of the second transistor. .

  In the first solid-state imaging device according to the present invention, a plurality of element isolation portions are provided in the pixel region and the peripheral region, and among the plurality of element isolation portions, an element isolation portion formed in the pixel region. Preferably, a leak stopper is formed on the side surface and the bottom surface of the first transistor by an impurity having a conductivity type opposite to that of the source region and the drain region of the first transistor. According to this aspect, it is possible to suppress leakage current from flowing from the element isolation portion to the photodiode. Further, in the above aspect, an oxide film embedded in a groove formed in the semiconductor substrate can be used as the plurality of element isolation portions.

  A second solid-state imaging device according to the present invention is a solid-state imaging device comprising a semiconductor substrate, wherein a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region. Each of the plurality of pixel cells includes a light receiving element and a plurality of transistors for reading out signal charges accumulated in the light receiving element, and a plurality of element separation portions are provided in the pixel region and the peripheral region, Of the element separation portions provided in the pixel region, the side surface side and the bottom surface side of the element separation portion that separates adjacent light receiving elements, and the light receiving element side of the element separation portion that separates the light receiving element and the transistor Is characterized in that a leak stopper is formed of an impurity having a conductivity type opposite to that of the source region and the drain region of the first transistor. In the second solid-state imaging device, a leak stopper is formed. Therefore, compared with the first solid-state imaging device, it is possible to suppress a leakage current from flowing from the element isolation portion to the photodiode and to reduce the pixel size. Can be easily accommodated.

  In the second solid-state imaging device according to the present invention, the peripheral circuit includes a plurality of second circuits in which the conductivity types of the source region and the drain region are the same as the conductivity types of the source region and the drain region of the plurality of transistors of the pixel cell. And a source region and a drain region of each of the plurality of transistors of the pixel cell are formed in a first semiconductor region formed in the pixel region, and each of the plurality of second transistors is formed. A source region and a drain region are formed in a second semiconductor region formed in the peripheral region, and an impurity concentration of the first semiconductor region formed in the pixel region is formed in the peripheral region. It is preferable that the second semiconductor region is set to a value lower than the impurity concentration of the second semiconductor region. If it is set as this aspect, the effect by a 1st solid-state imaging device can be added to a 2nd solid-state imaging device.

  In the second solid-state imaging device according to the present invention, the first semiconductor region functions as a well of the transistor of the pixel cell, and the second semiconductor region is a well of the second transistor. Function as.

  A manufacturing method of a first solid-state imaging device includes a semiconductor substrate, and a light receiving element and a plurality of first transistors for reading signal charges accumulated in the light receiving element are provided in a pixel region on the semiconductor substrate. Provided with a plurality of pixel cells, a peripheral circuit including a plurality of second transistors is provided in a peripheral region of the pixel region, and a conductivity type of the source region and the drain region of the second transistor is the first transistor. A method of manufacturing a solid-state imaging device having the same conductivity type as that of the source region and the drain region of the semiconductor device, wherein: (a) first ion implantation is performed on the formation regions of the plurality of second transistors in the peripheral region. (B) forming a second ion in a formation region of the plurality of second transistors in the peripheral region and a formation region of the plurality of first transistors in the pixel region; Characterized by a step of performing injection.

  The second method for manufacturing a solid-state imaging device according to the present invention includes a semiconductor substrate, and a plurality of transistors for reading a light receiving element and a signal charge accumulated in the light receiving element in a pixel region on the semiconductor substrate. A solid-state imaging device in which a peripheral circuit is provided in a peripheral region of the pixel region, and (a) a plurality of element isolation portions in the pixel region and the peripheral region And (b) leaking into the side surface side and the bottom surface side of the element separating part that separates adjacent light receiving elements, and to the light receiving element side of the element separating part that separates the light receiving element and the transistor. Impurities having a conductivity type opposite to that of the source and drain regions of the transistor are ion-implanted from a direction inclined with respect to the normal line of the semiconductor substrate so that a stopper is formed. Characterized by a step

(Embodiment 1)
Hereinafter, a solid-state imaging device and a method for manufacturing the solid-state imaging device according to Embodiment 1 of the present invention will be described with reference to the drawings. The solid-state imaging device according to the first embodiment is a MOS solid-state imaging device. Also in the first embodiment, as shown in FIG. 4 in the background art, the solid-state imaging device includes a semiconductor substrate, a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a region around the pixel region ( A peripheral circuit is provided in the peripheral circuit region).

  Also in the first embodiment, the peripheral circuit region is provided with a vertical drive circuit, a horizontal drive circuit, a load transistor group, and a row signal storage unit as in the example shown in FIG. 5 in the background art. .

  Further, the plurality of pixel cells are arranged in a matrix, and the circuit configuration of the solid-state imaging device is the same as the example shown in FIG. 5 in the background art. Each pixel cell further includes a photodiode functioning as a light receiving element and a plurality of transistors (readout transistors) for reading out signal charges stored in the photodiode.

  Examples of the reading transistor include a transfer transistor, an amplification transistor, a reset transistor, and a vertical selection transistor. Among these, the amplification transistor constitutes a source follower circuit together with a load transistor group provided in the peripheral circuit region.

  Here, a method of manufacturing the solid-state imaging device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a method for manufacturing a solid-state imaging device according to Embodiment 1 of the present invention, and FIGS. 1A to 1D each show a series of main steps. 1A to 1D, the pixel area A is shown on the left half, and the peripheral circuit area B is shown on the right half. Moreover, in FIG. 1 (a)-(d), only the line which appeared in the cross section is shown in figure.

  Furthermore, in the first embodiment, both the N channel MOS transistor and the P channel MOS transistor are formed on the semiconductor substrate. In FIGS. 1A to 1D, the N channel MOS transistor is Only the region to be formed is shown. FIG. 1D also shows the configuration of the solid-state imaging device according to the first embodiment.

  First, as shown in FIG. 1A, a groove 41 for forming the STI element isolation portion 22 is formed in the pixel region A and the peripheral circuit region B of the semiconductor substrate 21. Next, a resist pattern 20 having an opening in the pixel region A is formed, and using this as a mask, impurities are ion-implanted from an oblique direction. As a result, in the pixel region A, the STI leak stopper 22 is formed on the side surface side and the bottom surface side of the groove 41.

  In addition, the process shown to Fig.1 (a) is a process similar to the process shown to Fig.9 (a) in background art. Also in the first embodiment, the semiconductor substrate 21 is an n-type silicon substrate. Further, the impurity ion-implanted in the step shown in FIG. 1A is a p-type impurity such as boron (B).

  Next, as shown in FIG. 1B, after removing the resist pattern 20, a silicon oxide film is formed so as to fill the groove 41, and the surface is polished to obtain a plurality of element isolation portions (element isolation regions). ) 22 is formed.

Next, a resist pattern 25 having an opening in the peripheral circuit region B is formed to cover the photodiode formation region A1 and the read transistor formation region A2. Further, p-type impurities are ion-implanted using the resist pattern 25 as a mask. In this case, ion implantation is performed such that the diffusion layer depth from the substrate surface is 1.0 μm to 1.5 μm, for example, so that impurities are distributed to deep regions. Specifically, for example, if the p-type impurity to be ion-implanted is boron (B), the implantation energy is set to 250 KeV to 500 KeV, and the dose amount is 1 × 10 ¹³ / cm ² to 1 ×. Set to 10 ¹⁴ pieces / cm ² .

  As a result, a p-type semiconductor region 24 is formed in the peripheral circuit region B. The semiconductor region 24 functions as a well of a transistor (N channel MOS transistor) formed in the peripheral circuit region B.

  Next, as shown in FIG. 1C, after removing the resist pattern 25, a new resist pattern 28 is formed in which the formation region A2 of the reading transistor and the peripheral circuit region B constituting the pixel cell are opened. . Next, p-type impurities are ion-implanted using the resist pattern 28 as a mask.

  As a result, the p-type semiconductor region 26 is also formed in the read transistor formation region A2. The semiconductor region 26 functions as a well of a transistor (N channel MOS transistor) formed in the pixel cell. Further, the impurity concentration of the semiconductor region 24 formed in the process shown in FIG. 1B is increased by the process shown in FIG. Therefore, the transistor in the peripheral circuit region B is disposed in a well having a higher impurity concentration than the reading transistor in the pixel region A. The semiconductor region 24 after the process of FIG. 1C is completed is referred to as “semiconductor region 24A”.

By the way, when the peripheral circuit is configured by CMOS, in order to suppress latch-up in each of the NMOS region and the PMOS region, the impurity concentration of the well is set so that the peak is 1 × 10 ¹⁸ / cm ³ or more. It is preferable to do this.

  Note that it is considered that latch-up begins to be a problem in CMOS semiconductor integrated circuits in the case of a generation of fine transistors whose design rule is at least 0.25 μm. In this generation, the depth of the diffusion layer of the well (bonding position with the substrate) is approximately 1 μm to 2 μm. Furthermore, wells in this generation may take a retrograde well structure with a profile that is lighter at the substrate surface than at the central portion.

On the other hand, in setting the impurity concentration of the well in the pixel region A, since the pixel cell is composed of only the N-channel MOS transistor, there is no need to worry about latch-up, and the concentration is 1 × 10 ¹⁸ / cm ³ or less. Can be set. However, there is a concern about element destruction when a surge due to static electricity enters. Therefore, since it is necessary to secure a junction with the semiconductor substrate in order to release the surge, it is preferable to set the impurity concentration of the well to be higher than the impurity concentration of the semiconductor substrate.

Accordingly, in the step of FIG. 1C, the concentration of the semiconductor region 26 is set to a concentration higher than that when, for example, a silicon substrate having an impurity concentration of 1 × 10 ¹⁵ / cm ³ is used as the semiconductor substrate. Is good. In this case, for example, if the p-type impurity to be ion-implanted is boron (B), the implantation energy is set to 450 KeV to 600 KeV, and the dose is 1 × 10 ¹⁰ / cm ² to 1 ×. It is good to set to 10 ¹² pieces / cm ² . Also in the process of FIG. 1C, as in the process shown in FIG. 1B, ion implantation is performed so that the diffusion layer depth from the substrate surface is 1.0 μm to 1.5 μm. It is.

Thereafter, a p-type impurity is ion-implanted to form a shallow semiconductor region 27 in the formation region A2 and the peripheral circuit region B. The semiconductor region 27 is a channel region. By adjusting the impurity concentration of the semiconductor region 27, the threshold voltage V _T of the transistor can be controlled. Further, for example, when boron (B) is used for NMOS threshold voltage control, the implantation energy is set to 10 KeV to 30 KeV, and the dose amount is 1 × 10 ¹² / cm 2 to 1 × 10 ¹³ / cm 2. It is preferable to set to.

  Next, as shown in FIG. 1D, after removing the resist pattern 28, the gate insulating film 32 made of a silicon oxide film and the polysilicon are formed in the read transistor formation region A2 and the peripheral circuit region B. The gate electrode 31 is formed in order. Next, a resist pattern (not shown) having an opening in the photodiode formation region A1 is formed, and using this as a mask, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted. Thereby, the n-type semiconductor region 30 constituting the photodiode is formed.

  Subsequently, after removing the resist pattern, an insulating film is formed and etched to form side wall insulating films (side wall spacers) 33 on the side surfaces of the gate insulating film 32 and the gate electrode 31.

  Next, a resist pattern (not shown) in which the read transistor formation region A2 and the peripheral circuit region B are opened is formed, and n-type impurities are ion-implanted using the resist pattern as a mask. Thereby, a source / drain region 29 of the transistor is formed. Thereafter, an interlayer insulating film, various wirings, a microlens, and the like are formed, and the MOS type solid-state imaging device according to the first embodiment is completed. In addition, the process shown in FIG.1 (d) is performed according to the process shown in FIG.9 (c) and (d) in background art.

  As described above, according to the method of manufacturing the solid-state imaging device of the first embodiment, the impurity concentration of the well (semiconductor region 26) in the pixel region A and the well (semiconductor region 24A) in the NMOS region of the peripheral circuit region B. The solid-state imaging device according to the first embodiment in which the impurity concentration is individually set is obtained. In the solid-state imaging device according to the first embodiment, the impurity concentration of the well (semiconductor region 26) in the pixel region is set to a value lower than the impurity concentration of the well (semiconductor region 24A) in the NMOS region of the peripheral circuit region B. The Therefore, even when the STI leak stopper is formed, it is possible to avoid an increase in the impurity concentration of the well (semiconductor region 26) formed in the pixel region A.

For this reason, according to the first embodiment, since the back bias effect of the output transistor can be suppressed, the dynamic range and linearity in the source follower circuit are ensured. In addition, since it is not necessary to perform counter doping as in the prior art, fluctuations in the threshold voltage V _T of the output transistor constituting the source follower circuit can be suppressed.

Further, according to the manufacturing method in the first embodiment, after forming the well, a channel region for controlling the threshold voltage V _T is formed. Therefore, it is possible to avoid the threshold voltage V _T from fluctuating due to the diffusion of impurities in the subsequent processes. In the example of FIG. 1, the element isolation part 22 is formed using the STI method, but the first embodiment is not limited to this example. In the first embodiment, the element isolation portion can also be formed using a LOCOS (Local Oxidation Of Silicon) method. Further, in the first embodiment, an aspect in which the STI leak stopper 22 is not formed may be employed.

  In the first embodiment, the process of forming the semiconductor region 26 in the pixel region A and the semiconductor region 24A in the peripheral circuit region B is not limited to the example shown in FIG. For example, after performing ion implantation to the formation region A2 and the peripheral circuit region B shown in FIG. 1C, the ion implantation to the peripheral circuit region B shown in FIG. 1B may be performed.

(Embodiment 2)
Next, a solid-state imaging device and a method for manufacturing the solid-state imaging device according to Embodiment 2 of the present invention will be described with reference to the drawings. In the second embodiment, unlike the first embodiment, the STI leak stopper is provided only in a part, and the well concentration in the pixel region A and the well concentration in the peripheral circuit region B are set to the same value. Has been.

  However, the solid-state imaging device according to the second embodiment is also a MOS solid-state imaging device, and is configured in the same manner as the solid-state imaging device according to the first embodiment except for the above points. Hereinafter, a description will be given with reference to FIG.

  FIG. 2 is a cross-sectional view showing a method for manufacturing a solid-state imaging device according to Embodiment 2 of the present invention, and FIGS. 2A to 2D each show a series of main steps. 2A to 2D, the pixel region A is shown on the left half, and the peripheral circuit region B is shown on the right half. Further, in FIGS. 2A to 2D, only lines appearing in the cross section are shown.

  Furthermore, in the second embodiment, both the N channel MOS transistor and the P channel MOS transistor are formed on the semiconductor substrate. In FIGS. 2A to 2D, the N channel MOS transistor is not formed. Only the region to be formed is shown. FIG. 2D also shows the configuration of the solid-state imaging device according to the second embodiment.

  First, as shown in FIG. 2A, grooves 41 for forming STI element isolation portions are formed in the pixel region A and the peripheral circuit region B of the semiconductor substrate 21. Further, the STI leak stopper 43 is formed by ion implantation of p-type impurities from an oblique direction. At this time, in the second embodiment, a resist pattern 45 having an opening only in the photodiode formation region A1 is formed, and this is used as a mask during ion implantation.

  Next, as shown in FIG. 2B, after removing the resist pattern 45, a silicon oxide film is formed so as to fill the groove 41, and the surface is polished. As a result, an element isolation part 42a that isolates adjacent photodiodes, an element isolation part 42b that isolates the photodiode and the transistor, and an element isolation part 42c that isolates the transistors in the peripheral circuit region B are formed. . Although not shown in FIG. 2, in the pixel region A, an element isolation portion that isolates adjacent transistors is also formed.

  As a result of the steps shown in FIGS. 2A and 2B, in the second embodiment, the STI leak stopper 43 is formed only in the photodiode formation region A1. Specifically, the STI leak stopper 43 is formed only on the side surface side and the bottom surface side of the element isolation part 42a and on the light receiving element side of the element isolation part 42b. In the second embodiment, the STI leak stopper 43 is formed so as not to overlap a well of a transistor to be described later.

  Next, as shown in FIG. 2C, a resist pattern 46 in which the read transistor formation region A2 and the peripheral circuit region B are opened is formed. Next, p-type impurities are ion-implanted using the resist pattern 46 as a mask. As a result, a p-type semiconductor region 44a is formed in the read transistor formation region A2, and a p-type semiconductor region 44b is formed in the peripheral circuit region B. The semiconductor region 44a functions as a well of a transistor (N channel MOS transistor) formed in the pixel cell. The semiconductor region 44b functions as a well of a transistor (N channel MOS transistor) formed in the peripheral circuit region B.

In this case, ion implantation is performed so that the diffusion layer depth from the substrate surface is 1.0 μm to 1.5 μm, for example, so that the impurities are distributed to a deep region. Specifically, for example, if the p-type impurity to be ion-implanted is boron (B), the implantation energy is set to 250 KeV to 500 KeV, and the dose amount is 1 × 10 ¹³ / cm ² to 1 ×. It is good to set it to 10 ¹⁴ pieces / cm ² .

Next, a channel region 47 is formed by ion implantation of p-type impurities. Formation of channel region 47 is performed in the same manner as the step shown in FIG. The ion implantation conditions for the channel region 47 are also set according to the design value of the threshold voltage V _T.

  Next, as shown in FIG. 2D, after the resist pattern 46 is removed, the gate insulating film 51, the gate electrode 50, and the photodiode are formed in the read transistor formation region A2 and the peripheral circuit region B. An n-type semiconductor region 49 is formed. Further, after forming a sidewall insulating film (sidewall spacer) 52, ion implantation of n-type impurities is performed to form a source / drain region 48 of the transistor. Thereafter, an interlayer insulating film, various wirings, microlenses, and the like are formed to complete the MOS solid-state imaging device according to the second embodiment. In addition, the process shown in FIG.1 (d) is performed according to the process shown in FIG.9 (c) and (d) in background art.

As described above, according to the solid-state imaging device and the manufacturing method thereof according to the second embodiment, it is possible to avoid the impurity concentration of the well (semiconductor region 44a) formed in the pixel region A from being increased by the STI leak stopper 43. . For this reason, according to the second embodiment, since the back bias effect of the output transistor can be suppressed, the dynamic range and linearity in the source follower circuit are ensured. Further, unlike the prior art, since it is not necessary to perform counter doping, the threshold value of the output transistor constituting the source follower circuit while preventing leakage current flowing from the element isolation parts 42a and 42b to the photodiode (semiconductor region 43). The fluctuation of the voltage V _T can be suppressed.

Also in the second embodiment, a channel region for controlling the threshold voltage V _T is formed after the well is formed, as in the first embodiment. Therefore, it is possible to avoid the threshold voltage V _T from fluctuating due to the diffusion of impurities in the subsequent processes. Furthermore, also in the second embodiment, the element isolation parts 42a to 42c can be formed using a LOCOS (Local Oxidation Of Silicon) method.

(Embodiment 3)
Next, a solid-state imaging device and a method for manufacturing the solid-state imaging device according to Embodiment 3 of the present invention will be described with reference to the drawings. The third embodiment shows an example provided with both the feature in the first embodiment and the feature in the second embodiment. That is, the third embodiment is common to the first embodiment in that the well concentration in the pixel region A and the well concentration in the peripheral circuit region B are individually set. Further, the third embodiment is common to the second embodiment in that the STI leak stopper is provided only in part. Also in the third embodiment, the solid-state imaging device is a MOS solid-state imaging device.

  FIG. 3 is a cross-sectional view showing a method for manufacturing a solid-state imaging device according to Embodiment 3 of the present invention, and FIGS. 3A to 3E show a series of main steps. 3A to 3E, the pixel area A is shown on the left half, and the peripheral circuit area B is shown on the right half. 3A to 3E show only the lines that appear in the cross section.

  Further, in the third embodiment, both the N channel MOS transistor and the P channel MOS transistor are formed on the semiconductor substrate. In FIGS. 3A to 3E, the N channel MOS transistor is Only the region to be formed is shown. FIG. 3E also shows the configuration of the solid-state imaging device according to the third embodiment.

  First, as shown in FIG. 3A, grooves 41 for forming STI element isolation portions are formed in the pixel region A and the peripheral circuit region B of the semiconductor substrate 21. Further, a resist pattern 45 having an opening only in the photodiode formation region A1 is formed, and using this as a mask, p-type impurities are ion-implanted from an oblique direction. As a result, the STI leak stopper 43 is formed only in the photodiode formation region A1.

  Next, as shown in FIG. 3B, after removing the resist pattern 45, a silicon oxide film is formed so as to fill the groove 41, and the surface is polished. As a result, an element isolation part 42a that isolates adjacent photodiodes, an element isolation part 42b that isolates the photodiode and the transistor, and an element isolation part 42c that isolates the transistors in the peripheral circuit region B are formed. .

  The steps shown in FIGS. 3A and 3B are the same as the steps shown in FIGS. 2A and 2B in the second embodiment. Therefore, also in the third embodiment, the STI leak stopper 43 is formed only on the side surface and bottom surface side of the element isolation part 42a and on the light receiving element side of the element isolation part 42b. The semiconductor substrate 21 is a p-type silicon substrate.

  Next, as shown in FIG. 3C, a resist pattern 61 having an opening in the peripheral circuit region B is formed to cover the photodiode formation region A1 and the read transistor formation region A2. Next, p-type impurities are ion-implanted using the resist pattern 61 as a mask.

  As a result, a p-type semiconductor region 62 is formed in the peripheral circuit region B. The semiconductor region 62 functions as a well of a transistor (N channel MOS transistor) formed in the peripheral circuit region B. The process shown in FIG. 3C is the same as the process shown in FIG. 1B in the first embodiment, and the ion implantation conditions are the same as those shown in FIG. 1B. Set to the condition.

  Next, as shown in FIG. 3D, after removing the resist pattern 65, a new resist pattern 65 is formed in which the formation region A2 of the read transistor constituting the pixel cell and the peripheral circuit region B are opened. . Next, p-type impurities are ion-implanted using the resist pattern 65 as a mask. Subsequently, p-type impurities are ion-implanted into the shallow region to form the channel region 64.

Note that the step shown in FIG. 3D is the same as the step shown in FIG. 1C in the first embodiment. 3D, a p-type semiconductor region 63 functioning as a well is formed in the read transistor formation region A2, and the impurity concentration of the semiconductor region 62 is increased. Further, the semiconductor region 62 after the step of FIG. 3D is completed is referred to as “semiconductor region 62A”. Furthermore, the ion implantation conditions for the channel region 64 are also set in accordance with the design value of the threshold voltage V _T.

  Thereafter, as shown in FIG. 3E, after the resist pattern 65 is removed, a gate insulating film 69, a gate electrode 68, and a photodiode are formed in the read transistor formation region A2 and the peripheral circuit region B. A type semiconductor region 67 is formed. Further, after forming a sidewall insulating film (sidewall spacer) 70, ion implantation of n-type impurities is performed to form a source / drain region 66 of the transistor. Thereafter, an interlayer insulating film, various wirings, a microlens, and the like are formed to complete the MOS solid-state imaging device according to the third embodiment. In addition, the process shown in FIG.3 (e) is performed according to the process shown in FIG.9 (c) and (d) in background art.

  Thus, according to the third embodiment, as in the first embodiment, the impurity concentration of the well in the pixel region A is set lower than the impurity concentration of the well in the peripheral circuit region B. Similarly to the second embodiment, the STI leak stopper 43 can prevent the impurity concentration of the well (semiconductor region 63) formed in the pixel region A from increasing. For this reason, according to the third embodiment, both the effects of the first embodiment and the effects of the second embodiment can be obtained.

  The solid-state imaging device according to the present invention can suppress the back bias effect as compared with the prior art, and can further improve the linearity of the source follower circuit and expand the dynamic range. Therefore, the imaging device such as a digital video camera or a digital still camera can be used. Useful as. Therefore, the solid-state imaging device and the solid-state imaging device manufacturing method of the present invention have industrial applicability.

It is sectional drawing which shows the manufacturing method of the solid-state imaging device in Embodiment 1 of this invention, and each of Fig.1 (a)-FIG.1 (d) has shown a series of main processes. It is sectional drawing which shows the manufacturing method of the solid-state imaging device in Embodiment 2 of this invention, and each of Fig.2 (a)-FIG.2 (d) has shown a series of main processes. It is sectional drawing which shows the manufacturing method of the solid-state imaging device in Embodiment 3 of this invention, and each of Fig.3 (a)-FIG.3 (e) has shown a series of main processes. It is a top view which shows schematic structure of the conventional MOS type solid-state imaging device. It is a circuit diagram which shows an example of the circuit structure of the conventional MOS type solid-state imaging device. It is a timing chart for demonstrating operation | movement of the conventional solid-state imaging device shown in FIG. It is a top view which expands and shows a part of the conventional solid-state imaging device shown in FIG. It is sectional drawing which expands and shows a part of conventional solid-state imaging device shown in FIG. FIG. 9A is a partial cross-sectional view showing a manufacturing process of a conventional MOS solid-state imaging device in which an STI leak stopper is formed, and FIGS. 9A to 9D show a series of main processes. It is a circuit diagram which shows the circuit structure of a basic source follower circuit.

Explanation of symbols

20, 25, 28, 45, 46, 61, 65 Resist pattern 21 Semiconductor substrate 22, 42a, 42b, 42c Element isolation part 23, 43 STI leak stopper 24, 62 Semiconductor region to be a transistor well in the peripheral circuit region (low concentration)
24A, 62A Semiconductor region (high concentration) to be a transistor well in the peripheral circuit region
26, 44a, 63 Semiconductor region 27, 47, 64 channel region (semiconductor region) which becomes well of transistor in pixel region
29, 48, 66 Source / drain regions 30, 49, 67 Semiconductor regions 31, 50, 68 which become photodiodes Gate electrodes 32, 51, 69 Gate insulating films 33, 52, 70 Side wall insulating films 41 Grooves 44b Transistors in peripheral circuit regions Semiconductor region to become well of A A Pixel region A1 Photodiode formation region A2 Transistor for driving pixel cell B Peripheral circuit region

Claims (9)

A solid-state imaging device comprising a semiconductor substrate, wherein a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region,
Each of the plurality of pixel cells includes a light receiving element and a plurality of first transistors for reading signal charges accumulated in the light receiving element,
The peripheral circuit includes a plurality of second transistors in which the conductivity type of the source region and the drain region is the same as the conductivity type of the source region and the drain region of the first transistor,
A source region and a drain region of each of the plurality of first transistors are formed in a first semiconductor region formed in the pixel region,
A source region and a drain region of each of the plurality of second transistors are formed in a second semiconductor region formed in the peripheral region,
The impurity concentration of the first semiconductor region formed in the pixel region is set to a value lower than the impurity concentration of the second semiconductor region formed in the peripheral region. Solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the first semiconductor region functions as a well of the first transistor, and the second semiconductor region functions as a well of the second transistor. A plurality of element isolation portions are provided in the pixel region and the peripheral region,
Among the plurality of element isolation parts, leakage is caused by a conductivity type impurity opposite to the conductivity type of the source region and the drain region of the first transistor on the side surface side and the bottom surface side of the element isolation part formed in the pixel region. The solid-state imaging device according to claim 1, wherein a stopper is formed.   The solid-state imaging device according to claim 3, wherein the plurality of element isolation portions are oxide films embedded in a groove formed in the semiconductor substrate. A solid-state imaging device comprising a semiconductor substrate, wherein a plurality of pixel cells are provided in a pixel region on the semiconductor substrate, and a peripheral circuit is provided in a peripheral region of the pixel region,
Each of the plurality of pixel cells includes a light receiving element and a plurality of transistors for reading signal charges accumulated in the light receiving element,
A plurality of element isolation portions are provided in the pixel region and the peripheral region,
Of the element separation portions provided in the pixel region, the side surface side and the bottom surface side of the element separation portion that separates adjacent light receiving elements, and the light receiving element side of the element separation portion that separates the light receiving element and the transistor In the solid-state imaging device, a leak stopper is formed of an impurity having a conductivity type opposite to that of the source region and the drain region of the first transistor. The peripheral circuit includes a plurality of second transistors whose source region and drain region have the same conductivity type as the source region and drain region of the plurality of transistors of the pixel cell,
A source region and a drain region of each of the plurality of transistors of the pixel cell are formed in a first semiconductor region formed in the pixel region,
A source region and a drain region of each of the plurality of second transistors are formed in a second semiconductor region formed in the peripheral region,
The impurity concentration of the first semiconductor region formed in the pixel region is set to a value lower than the impurity concentration of the second semiconductor region formed in the peripheral region. Solid-state imaging device.   The solid-state imaging device according to claim 6, wherein the first semiconductor region functions as a well of the transistor of the pixel cell, and the second semiconductor region functions as a well of the second transistor. A plurality of pixel cells each including a semiconductor substrate, the pixel region on the semiconductor substrate including a light receiving element and a plurality of first transistors for reading signal charges accumulated in the light receiving element; A peripheral circuit including a plurality of second transistors is provided in the peripheral region of the first transistor, and the conductivity type of the source region and the drain region of the second transistor is the same as the conductivity type of the source region and the drain region of the first transistor. A method of manufacturing a solid-state imaging device,
(A) performing a first ion implantation on a formation region of the plurality of second transistors in the peripheral region;
And (b) performing a second ion implantation on the plurality of second transistor formation regions in the peripheral region and the plurality of first transistor formation regions in the pixel region. A method for manufacturing a solid-state imaging device. A plurality of pixel cells each including a semiconductor substrate, the pixel region on the semiconductor substrate including a light receiving element and a plurality of transistors for reading signal charges accumulated in the light receiving element; A manufacturing method of a solid-state imaging device in which a peripheral circuit is provided,
(A) forming a plurality of element isolation portions in the pixel region and the peripheral region;
(B) Leak stoppers are formed on the side surface side and bottom surface side of the element separating portion that separates adjacent light receiving elements, and on the light receiving element side of the element separating portion that separates the light receiving element and the transistor. And a step of ion-implanting impurities of a conductivity type opposite to the conductivity type of the source region and the drain region of the transistor from a direction inclined with respect to the normal line of the semiconductor substrate. Manufacturing method.

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