JP2005117018A - Solid imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a junction transistor constituting a leakage current path to a source region from being structured. <P>SOLUTION: A solid imaging device comprises: a first another conduction type diffusion layer 21 formed on one conduction type substrate; a photoelectric conversion device PD formed on the substrate for generating light generation charge corresponding to incident light; one conduction type accumulating well 4 formed on the first diffusion layer 21 for accumulating the light generation charge; and one conduction type well 5 for modulation which maintains the light generation charge transferred from the accumulation well 4. Furthermore, the solid imaging device further comprises: a modulation transistor TM outputting a pixel signal corresponding to the light generation charge by controlling a channel threshold voltage by means of the light generation charge maintained by the well 5 for modulation; and a second conduction type diffusion layer 91 formed between the well 5 for modulation and the first diffusion layer 21. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device having high image quality characteristics and low power consumption characteristics, and a manufacturing method thereof.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Patent Document 1.

  The image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit pixel has a photodiode for performing accumulation, a modulation transistor for performing readout, and an overflow drain gate for performing initialization.

  FIG. 9 is a schematic cross-sectional view showing the modulation transistor portion of the image sensor disclosed in Patent Document 1. As shown in FIG.

  In the image sensor of FIG. 9, a photodiode and a modulation transistor 101 (not shown) are arranged adjacent to each other on the substrate 100 for each unit pixel. The gate 102 of the modulation transistor 101 is formed in a ring shape, and a source region 103 is formed in the central opening of the ring gate 102. A drain region 104 is formed around the ring gate 102.

Charges (photogenerated charges) generated by light incident from the opening region of the photodiode are transferred to the region of the P-type well 105 below the ring gate 102 and accumulated in the carrier pocket 106 formed in this portion. The threshold voltage of the modulation transistor 101 changes due to the photogenerated charges accumulated in the carrier pocket 106. As a result, a signal (pixel signal) corresponding to incident light can be extracted from the source region 103 of the modulation transistor 101.
JP 2002-134729 A

In FIG. 10, the gate voltage VG is taken on the horizontal axis and the source voltage VS is taken on the vertical axis, and the characteristics of the modulation transistor 101 when the threshold voltage is high (the amount of incident light is small) and low (the amount of incident light is large) are shown. It is a graph to show. A characteristic A indicates a characteristic when the incident light is at a normal level, and a characteristic B indicates a characteristic when the incident light is extremely bright. As the threshold voltage changes according to the amount of incident light, the VG-VS characteristic of the modulation transistor changes. When the gate voltage VG is sufficiently increased, the source voltage VS of the modulation transistor is saturated and substantially matches the drain voltage.
When the gate voltage VG is fixed (for example, the level of the broken line) so that the modulation transistor is not saturated, the source voltage changes according to the threshold voltage of the modulation transistor. Thereby, the source voltage according to the photogenerated charge can be acquired.

  However, in the sensor cell of FIG. 9, a junction transistor is formed by the N-type diffusion layer constituting the N-type diffusion layer 107, the P-type well 105, and the source region 103 below the region of the P-type well 105. Leakage current flows through 103.

  FIG. 11 is a circuit diagram showing an equivalent circuit in this case. The drain region 104 (D in FIG. 11) around the ring gate 102 and the N-type diffusion layer 107 are electrically connected. In FIG. 11, the leak path from the drain region 104 to the N-type diffusion layer 107 has a resistance Rl. It is indicated by A collector-emitter path of the junction transistor Tj is formed between the N-type diffusion layer 107 and the source region 103 (S in FIG. 11). Not only does a current flow from the drain region 104 to the source region 103 via the channel of the modulation transistor 101, but also a leak current flows from the drain region 104 to the source region 103 via the resistor Rl and the jack transistor Tj.

  Further, in the sensor cell of FIG. 9, with the miniaturization, a short channel effect of the modulation transistor occurs, and a leak current flows between the drain and the source.

FIG. 12 shows changes in VG-VS characteristics due to the influence of leakage current. The broken line in FIG. 12 indicates the characteristic when there is no leakage current, and the solid line indicates the characteristic when there is a leakage current.
As shown in FIG. 12, particularly in the region where the gate voltage VG is relatively low (the gate voltage indicated by the alternate long and short dash line), the influence of the leakage current becomes large, and the photogenerated charge corresponding to the incident light is accurately detected. Can not do it. For example, when reading is performed by applying two kinds of gate voltages of a normal level (a gate voltage indicated by a broken line) and a relatively low level indicated by a one-dot chain line to the gate, a change in characteristics due to an influence of a leakage current is caused. However, the amount of received light cannot be detected accurately, and there is a problem that black smear may occur depending on the setting.

  The present invention has been made in view of such a problem, and provides a solid-state imaging device and a method for manufacturing the same that can prevent the formation of a junction transistor under a source region and achieve high image quality. For the purpose.

  A solid-state imaging device according to the present invention includes a first diffusion layer of the other conductivity type formed on a substrate of one conductivity type, and a photoelectric conversion that generates photogenerated charges according to incident light formed on the substrate. An element, a one-conductivity type accumulation well formed on the first diffusion layer for accumulating the photogenerated charge, and a one conductivity type modulation well for retaining the photogenerated charge transferred from the accumulation well. A modulation transistor that outputs a pixel signal corresponding to the photogenerated charge by controlling a threshold voltage of the channel by the photogenerated charge held in the modulation well, the modulation well, and the first And a second diffusion layer of one conductivity type formed between the diffusion layer and the diffusion layer.

  According to such a configuration, the photo-generated charges generated by the photoelectric conversion element are accumulated in the accumulation well. The photo-generated charges accumulated in the accumulation well are transferred to the modulation well. The threshold voltage of the channel of the modulation transistor is controlled by the photogenerated charge held in the modulation well, and a pixel signal corresponding to the photogenerated charge is output from the modulation transistor. The source region of the modulation transistor is composed of the other conductivity type, and a modulation conductivity well for one conductivity type and a first diffusion layer of the other conductivity type are formed in the formation region of the modulation transistor. However, below the source region, a second diffusion layer of one conductivity type is formed between the modulation well and the first diffusion layer. Therefore, for example, it is possible to prevent a leakage current path from being formed by the junction transistor below the source region. In addition, since the second diffusion layer of one conductivity type is formed between the drain and the source, the short channel effect of the modulation transistor can be suppressed. As a result, high image quality can be achieved, and for example, occurrence of black smear or the like can be prevented.

  The second diffusion layer is formed in a portion corresponding to the source region of the modulation transistor so as to be in contact with the modulation well and the first diffusion layer.

  According to such a configuration, it is possible to reliably prevent a leakage current path from being formed by the junction transistor below the source region. Furthermore, the short channel effect of the modulation transistor can also be suppressed.

  The modulation well further includes a one-conductivity type carrier pocket having a higher concentration than that of the modulation well, and the second diffusion layer is interposed between the carrier pocket and the first diffusion layer. It is formed.

  According to such a configuration, photogenerated charges are accumulated in the carrier pocket. Since the second diffusion layer is formed between the carrier pocket and the first diffusion layer, it is possible to reliably prevent a leakage current path from being formed by the junction transistor below the source region. Furthermore, the short channel effect of the modulation transistor can also be suppressed.

  The second diffusion layer is formed at a concentration lower than the concentration of the carrier pocket and higher than the concentration of the modulation well.

  According to such a configuration, it is possible to reliably prevent the junction transistor of the other conductivity type, the one conductivity type, and the other conductivity type from being formed below the source region.

  The method for manufacturing a solid-state imaging device according to the present embodiment includes a step of forming a first diffusion layer of the other conductivity type on a substrate of one conductivity type, and light generation generated by a photoelectric conversion element formed on the substrate Forming one conductivity type accumulation well for accumulating charge and one conductivity type modulation well for retaining the photogenerated charge transferred from the accumulation well; and holding the modulation well The threshold voltage of the channel is controlled by the photogenerated charge, and below the portion corresponding to the source region of the modulation transistor that outputs a pixel signal corresponding to the photogenerated charge, the first diffusion layer and the modulation And a step of forming a second diffusion layer of one conductivity type between the well and the well.

  According to such a configuration, the other conductivity type first diffusion layer is formed on the substrate, and the one conductivity type modulation well is formed on the first diffusion layer. A source region of the other conductivity type of the modulation transistor is formed on the modulation well. However, since the second diffusion layer of one conductivity type is formed below the source region and between the first diffusion layer and the modulation well, a junction transistor serving as a leakage current path to the source region is formed. This can prevent the short channel effect of the modulation transistor.

  Further, the second diffusion layer is formed at a concentration lower than the concentration of the carrier pocket and higher than the concentration of the modulation well.

  According to such a configuration, it is possible to reliably prevent a junction transistor serving as a leakage current path from being formed below the source region, and to suppress the short channel effect of the modulation transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 8 relate to a first embodiment of the present invention, FIG. 1 is a cross-sectional view showing a cross-sectional shape of a solid-state imaging device according to the present embodiment, and FIG. 2 is a solid-state imaging device according to the present embodiment. FIG. 3 is a block diagram showing the overall structure of the element, and FIG. 4 is an equivalent circuit diagram of the sensor cell. FIG. 5 is a graph showing the characteristics of the modulation transistor in the solid-state imaging device. 6 to 8 are process diagrams for explaining a method of manufacturing an element.

  In this embodiment, in a solid-state imaging device having a photoelectric conversion element such as a photodiode and a modulation transistor that outputs a pixel signal based on a charge (photogenerated charge) generated in the photoelectric conversion element, a source region in a modulation transistor formation region By forming a high-concentration one-conductivity-type impurity layer in the junction transistor formation part between the first and the other-conductivity-type diffusion layer, modulation is performed so that a junction transistor serving as a leakage current path to the source region is not formed. Due to the short channel effect of the transistor, the leakage current does not flow easily by introducing one conductivity type impurity into a region serving as a leakage current path.

<Structure of sensor cell>
As will be described later, the solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells as unit pixels are arranged in a matrix. Each sensor cell accumulates photogenerated charges generated according to incident light and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  First, the structure of each sensor cell will be described with reference to FIGS. FIG. 2 shows one sensor cell. One sensor cell is a range indicated by a broken line in FIG. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible. FIG. 1 shows a cross-sectional structure of the cell cut along the line A-A ′ of FIG. 2.

  As shown in the plan view of FIG. 2, a photodiode PD and a modulation transistor TM are provided adjacent to each other in a sensor cell 3 that is a unit pixel. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used. The unit pixel has a substantially rectangular shape, and each side thereof is inclined obliquely with respect to the column or row direction of the sensor cell array.

  In a photodiode PD formation region (PD in FIG. 1) which is a photoelectric conversion element formation region, an opening region 2 is formed on the surface of the substrate 1, and a region wider than the opening region 2 at a relatively shallow position on the surface of the substrate 1. A well (hereinafter referred to as an accumulation well) 4 for accumulating photogenerated charges generated by the photoelectric conversion element is formed. A P-type well is formed in the modulation transistor TM formation region (FPW in FIG. 1) separated from the accumulation well 4 by a predetermined distance, and the photo-generated charges accumulated in the accumulation well 4 are transferred to control the modulation transistor. A well 5 (hereinafter referred to as a modulation well) 5 is formed.

On the modulation well 5, a ring-shaped gate (ring gate) 6 is formed on the surface of the substrate 1, and a region near the surface of the substrate 1 in the central opening of the ring gate 6 is a high-concentration N-type region. A certain source region 7 is formed. An N-type drain region 8 is formed around the ring gate 6. An N ⁺ -layer drain contact region 9 is formed near the surface of the substrate 1 at a predetermined position of the drain region 8.

The modulation well 5 controls the threshold voltage of the channel of the modulation transistor TM.
In the modulation well 5, a carrier pocket 10 (FIG. 1) that is a P-type high concentration region is formed below the ring gate 6. The modulation transistor TM is constituted by the modulation well 5, the ring gate 6, the source region 7 and the drain region 8, and the threshold voltage of the channel changes according to the electric charge accumulated in the modulation well 5 (carrier pocket 10). It is like that.

  A depletion region (not shown) is formed in a boundary region between an N-type well 21 and a P-type accumulation well 4 as a first diffusion layer, which will be described later, formed on the substrate 1 below the opening region 2 of the photodiode PD. In this depletion region, photogenerated charges due to light incident through the opening region 2 are generated. In the present embodiment, the generated photo-generated charges are accumulated in the accumulation well 4.

  The charges accumulated in the accumulation well 4 are transferred to the modulation well 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of charge transferred to the modulation well 5, that is, the incident light to the photodiode PD.

  On the surface of the substrate 1 in the vicinity of the storage well 4, unnecessary charges (hereinafter referred to as unnecessary charges) that do not contribute to the image signal including charges overflowing from the storage well 4 among the photogenerated charges stored in the storage well 4 are discharged. A contact region (hereinafter referred to as an OD contact region) 11 is formed by a high concentration P-type diffusion layer. On the surface of the substrate 1 between the OD contact region 11 and the storage well 4 region, a path for unnecessary charges including charges overflowed between the OD contact region 11 and the storage well 4 region (hereinafter referred to as an unnecessary charge discharge path). A lateral overflow drain (hereinafter referred to as LOD) transistor TL LOD gate 12 for forming RL is formed. One end of the LOD gate 12 hangs over the region of the storage well 4 in plan view.

  By providing the LOD transistor TL as an unnecessary charge discharge control element, the potential barrier between the OD contact region 11 and the accumulation well 4 is controlled, and unnecessary charges are transferred from the OD contact region 11 to the substrate via the LOD transistor TL. Can be discharged through the wiring.

  In the present embodiment, a transfer transistor TT as a transfer control element is formed between the accumulation well 4 and the modulation well 5. The transfer gate 13 of the transfer transistor TT is formed on the surface of the substrate 1 of a path RT (hereinafter simply referred to as a transfer path) between the storage well 4 and the modulation well 5. The transfer transistor TT can control the potential barrier of the transfer path RT to control the transfer of charge from the accumulation well 4 to the modulation well 5.

  Further, in the present embodiment, a contact region for discharging residual charges (hereinafter referred to as discharge) for discharging charges remaining in the modulation well (hereinafter referred to as residual charges) on the substrate surface in the vicinity of the modulation well 5. 15 (referred to as a contact region) is formed by a high-concentration P-type diffusion layer. On the surface of the substrate 1 between the discharge contact region 15 and the modulation well 5 region, a potential barrier of RC (hereinafter referred to as residual charge discharge route) RC between the discharge contact region 15 and the modulation well 5 region. A clear gate 14 of the clear transistor TC is formed as a residual charge discharge control element for controlling the above. One end of the clear gate 14 hangs over the region of the modulation well 5 in plan view.

<Sensor cell cross section>
Furthermore, the cross-sectional structure of the sensor cell 3 will be described in detail with reference to FIG. In FIG. 1, the subscripts-and + of N and P indicate the state from the portion with the lower impurity concentration (subscript ---) to the portion with higher density (subscript +++) depending on the number.

  FIG. 1 shows one unit pixel (cell) and a photodiode PD formation region (PD) of a pixel adjacent to the cell. One cell has a photodiode PD formation region (PD) and a modulation transistor TM formation region (FPW). An isolation region (ISO) is provided between the photodiode PD formation region and the modulation transistor TM formation region in the cell and between adjacent cells.

At a relatively deep position of the substrate 1, an N ⁻ N type well 21 is formed over the entire area of the P type substrate 1a. An isolation region 22 for element isolation by an N ⁻ layer is formed on the N-type well 21. On the N-type well 21, a P ⁻ layer 23 is formed over the entire element except for the isolation region 22.

The P ⁻ layer 23 in the photodiode PD formation region functions as the storage well 4. The P ⁻ layer 23 in the modulation transistor TM formation region functions as the modulation well 5, and a carrier pocket 10 is formed in the modulation well 5 by P ⁻ diffusion.

In the isolation region 22 between the photodiode PD formation region and the modulation transistor TM formation region in the cell, the transfer transistor TT is formed on the substrate surface side.
The transfer transistor TT is configured by forming a P ^--- diffusion layer 24 constituting a channel on the substrate surface and forming a transfer gate 13 via a gate insulating film 25 on the substrate surface. The P ^--- diffusion layer 24 is connected to the storage well 4 and the modulation well 5 to form a transfer path RT, and the potential barrier of the transfer path RT is controlled according to the voltage applied to the transfer gate 13.

In the modulation transistor TM formation region, the ring gate 6 is formed on the substrate surface via the gate insulating film 26, and the N 2 ⁻ diffusion layer 27 constituting the channel is formed on the substrate surface below the ring gate 6. An N ⁺⁺ diffusion layer is formed on the substrate surface at the center of the ring gate 6 to constitute the source region 7. An N ⁺ diffusion layer is formed on the substrate surface around the ring gate 6 to form the drain region 8. The N 2 ⁻ diffusion layer 27 constituting the channel is connected to the source region 7 and the drain region 8.

In the isolation region 22 between the photodiode PD formation region and the modulation transistor TM formation region of adjacent cells, the discharge contact region 15 and the OD contact region 11 are formed on the substrate surface side. In the present embodiment, the discharge contact region 15 and the OD contact region 11 are shared, but they may be configured separately. The discharge and OD contact regions 15, 11 are obtained by forming a P ⁺⁺ diffusion layer on the substrate surface.

A clear transistor TC is formed on the substrate surface side between the modulation transistor TM formation region and the discharge and OD contact regions 15 and 11. In the clear transistor TC, a P ^--- diffusion layer 28 constituting a channel is formed on the substrate surface between the modulation transistor TM formation region and the discharge and OD contact regions 15 and 11, and a gate insulating film 29 is formed on the substrate surface. And a clear gate 14 is formed. This P ^--- diffusion layer 28 is connected to the modulation well 5 and the discharge and OD contact regions 15 and 11 to form a residual charge discharge path RC, and this residual charge discharge path according to the voltage applied to the clear gate 14. The RC potential barrier is controlled.

An LOD transistor TL is formed on the substrate surface side between the photodiode PD formation region and the discharge and OD contact regions 15 and 11. In the LOD transistor TL, a P ^--- diffusion layer 30 constituting a channel is formed on the substrate surface between the photodiode PD formation region and the discharge and OD contact regions 15 and 11, and a gate insulating film 31 is formed on the substrate surface. The LOD gate 12 is formed through the configuration. This P ^--- diffusion layer 30 is connected to the storage well 4 and the discharge and OD contact regions 15 and 11 to form an unnecessary charge discharge path RL, and this unnecessary charge discharge path RL according to the voltage applied to the LOD gate 12. The potential barrier is controlled.

An N ⁺ diffusion layer 32 as a pinning layer is formed on the substrate surface side of the photodiode PD formation region.

  A lower wiring layer 45 is formed on the substrate surface via an interlayer insulating film 41, and an upper wiring layer 46 is formed on the lower wiring layer 45 via an interlayer insulating film 42. Further, a light shielding layer 47 is formed on the upper wiring layer 46 via an interlayer insulating film 43, and a passivation film 44 is formed on the light shielding layer 47. The clear gate 14, the LOD gate 12, the transfer gate 13, the discharge and OD contact regions 15 and 11, and the source region 7 are electrically connected to each wiring 52 of the lower wiring layer 45 by a contact hole 51 opened in the interlayer insulating film 41. Connected. The wirings 52 and 53 of the lower and upper wiring layers 45 and 46 are made of a metal material such as aluminum.

  Further, each wiring 52 of the lower wiring layer 45 and each wiring 53 of the upper wiring layer 46 are electrically connected through a contact hole 54 formed in the interlayer insulating film 42. Further, a contact hole 55 for connecting the light shielding film 56 formed in the light shielding layer 47 and one wiring of the upper wiring layer 46 is opened in the interlayer insulating film 43, and the discharge and OD contact regions 15, 11 are formed. Are connected to the light shielding film 56 through the lower and upper wiring layers 45 and 46.

Furthermore, in the present embodiment, a P-type diffusion layer 91 as a second diffusion layer is formed between the N-type well 21 and the carrier pocket 10 below the source region 7 in the modulation transistor TM formation region. . P-type diffusion layer 91 has a lower end is in contact with the N-type well 21, an upper end with contacts in the carrier pocket 10, has the same planar shape as the planar shape of the source region 7, P ^- modulation well layers 23 5 so as to be embedded in 5. The concentration of the P-type diffusion layer 91 is lower than that of the carrier pocket 10 and higher than that of the P ⁻ layer 23.

<Circuit configuration of the entire device>
Next, a circuit configuration of the entire solid-state imaging device according to the present embodiment will be described with reference to FIG.

  The solid-state imaging device 61 includes a sensor cell array 62 including the sensor cell 3 of FIG. 2 and circuits 64 to 70 for driving each sensor cell 3 in the sensor cell array 62. The sensor cell array 62 is configured by arranging the cells 3 in a matrix. The sensor cell array 62 includes, for example, a 640 × 480 cell 3 and an optical black (OB) region (OB region). When the OB region is included, the sensor cell array 62 is composed of, for example, 712 × 500 cells 3.

<Equivalent circuit of sensor cell>
FIG. 4 shows a specific circuit configuration of each sensor cell in FIG. FIG. 4A shows an equivalent circuit of the sensor cell, and FIG. 4B shows the connection between the sensor cell and each signal line.

  Each sensor cell 3 includes a photodiode PD that performs photoelectric conversion, a modulation transistor TM for detecting and reading an optical signal, and a transfer transistor TT that controls transfer of photogenerated charges. The photodiode PD generates a charge (photogenerated charge) corresponding to the incident light, and stores the generated charge in the storage well 4 (corresponding to the connection point PDW in FIG. 4). The transfer transistor TT converts the photo-generated charges accumulated in the accumulation well 4 during the accumulation period into the carrier pocket 10 in the modulation well 5 (corresponding to the connection point TMW in FIG. 4) of the modulation transistor TM during the transfer period. To be transferred and held.

  The modulation transistor TM is equivalent to a change in the back gate bias due to the photogenerated charge held in the carrier pocket 10, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 10. As a result, the source voltage of the modulation transistor TM corresponds to the charge in the carrier pocket 10, that is, corresponds to the brightness of the incident light of the photodiode PD.

  A clear transistor TC, which is a residual charge discharge control element, is disposed between the modulation well 5 and the terminal. The clear transistor TC controls the potential barrier between the modulation well 5 and the terminal, and discharges the charge remaining in the modulation well 5 of the cell 3 to the terminal after the reading of the pixel signal is completed. On the other hand, an LOD transistor TL as an unnecessary charge discharge control element is disposed between the storage well 4 and the terminal. The LOD transistor TL controls a potential barrier between the storage well 4 and the terminal, and discharges unnecessary charges in the storage well 4 to the terminal.

  In this way, in each cell 3, the drive signal is applied to the ring gate 6, the source and drain of the modulation transistor TM, the transfer gate 13 of the transfer transistor TT, the clear gate 14 of the clear transistor TC, and the LOD gate 12 of the LOD transistor TL. Thus, operations such as accumulation, transfer, reading, and discharging are exhibited. As shown in FIG. 3, signals are supplied from vertical drive scanning circuits 64 to 66, a drain drive circuit 67, and a transfer drive circuit 68 to each part of the cell 3.

  FIG. 4B shows the connection of the scanning circuits 64 to 66, the driving circuits 67 and 68, and the signal output circuit 69 for one of the cells 3 arranged in a matrix. The same applies to the connection state of other cells. Each cell 3 is provided corresponding to the intersection of a plurality of source lines arranged in the horizontal direction and a plurality of gate lines arranged in the vertical direction in the sensor cell array 62. In each cell 3 of each line arranged in the horizontal direction, the ring gate 6 of the modulation transistor TM is connected to a common gate line, and in each cell 3 of each column arranged in the vertical direction, the source of the modulation transistor TM is Connected to a common source line.

  By supplying an ON signal to one of the plurality of gate lines, each cell commonly connected to the gate line to which the ON signal is supplied is simultaneously selected, and each source line from each source of these selected cells is selected. A pixel signal is output via. The vertical drive scanning circuit 64 supplies an ON signal to the gate lines while sequentially shifting in one frame period. Pixel signals from each cell of the line to which the ON signal is supplied are simultaneously read from the source line for one line and supplied to the signal output circuit 69. Pixel signals for one line are sequentially output (line output) from the signal output circuit 69 for each pixel by the horizontal drive scanning circuit 70.

  In the present embodiment, the storage well 4 and the modulation well 5 are formed separately from each other in terms of potential, and the transfer transistor TT that controls the potential barrier between the storage well 4 and the modulation well 5 Accumulation of photogenerated charges by the photodiode PD and reading of pixel signals by the modulation transistor TM can be performed simultaneously. The transfer transistor TT is controlled by supplying a gate signal from the transfer drive circuit 68 to the transfer gate 13 of each transfer transistor TT.

In the present embodiment, as described above, the unnecessary charge discharge path RL of the adjacent storage wells 4 and the residual charge discharge path RC from the modulation well 5 are set to different paths, and these By providing the LOD transistor TL and the clear transistor TC that respectively control the potential barriers of the two paths, unnecessary charges are discharged from the storage well 4 and residual charges are discharged from the modulation well 5 in terms of potential. Can be done.
The LOD transistor TL and the clear transistor TC are controlled by supplying gate signals from the vertical drive scanning circuits 65 and 66 to the LOD gates 12 or the clear gates 14, respectively. The drain drive circuit 67 supplies a drain voltage to the drain of each modulation transistor TM.

<Action>
(Contrast with conventional example)
In the device of Patent Document 1 described above, the source regions of all the modulation transistors in the same column are connected in common, and the voltage applied to the gates of the modulation transistors in the selected row and the non-selected row is controlled, so that a desired The source voltage of the modulation transistor in the row is detected. That is, the potential (Vg) of the gate electrode is set high for all the pixels in the selected row, and the potential (Vg) of the gate electrode in the non-selected row is set to the ground potential.

  In addition, in order to eliminate variations between unit pixels and various noises, the apparatus disclosed in Patent Document 1 applies a potential to pixels in a non-selected row in a read operation following a read operation of an optical signal in a selected row. The pixels in the selected row are initialized while the state is kept as it is, and then the threshold voltage in the initialized state is read. Then, a signal of the difference between the threshold voltage corresponding to the photogenerated charge amount and the threshold voltage in the initialized state is calculated, and the net optical signal component is output as a video signal.

  This process will be described with reference to FIG. In FIG. 12, points a and b indicate pixel signal levels based on pixels in a selected row where normal level incident light is incident and pixel signal levels Vsa and Vnb based on noise components after initialization. Points c and d indicate the level of the pixel signal based on the pixels in the non-selected row where the extremely bright incident light is incident and the level Vsc and Vnd of the pixel signal due to the noise components after the initialization.

  Now, in a predetermined column, it is assumed that normal level incident light is incident on the pixels in the selected row and extremely bright incident light is incident on one of the pixels in the non-selected rows. At the time of reading the signal component before initialization, the level of the pixel signal based on the pixel in the selected row is Vsa. On the other hand, for the non-selected row to which a low gate voltage is applied, the characteristics change as indicated by the solid line characteristic B. The level Vsc of the pixel signal is higher than the level Vsa of the pixel signal based on the pixels in the selected row. Since the source regions are commonly connected in the same column, the level of the output pixel signal is Vsc in reading before initialization of all the pixels in the same column.

  Similarly, at the time of readout of the noise component after initialization, the pixel signal level Vnd is higher than the pixel signal level Vnb based on the pixel in the selected row for the pixels in the non-selected row where extremely bright incident light is incident. It has become. Therefore, the level of the output pixel signal is Vnd in the readout after initialization of all the pixels in the same column. The difference between Vsc and Vnd is relatively small, the output (Vsc−Vnd) of all the pixels in the same column is at a low level, and the screen display is a black smear in the vertical direction.

  On the other hand, in this embodiment, the P-type diffusion layer 91 does not form a leakage current path by a junction transistor between the N-type well 21 and the source region 7. Therefore, the VG-VS characteristic of the modulation transistor TM becomes linear, and the occurrence of black smear can be prevented.

  FIG. 5 shows the characteristics of the modulation transistor when the threshold voltage is high (low incident light amount) and low (high incident light amount), with the gate voltage VG on the horizontal axis and the source voltage VS on the vertical axis. It is a graph. A characteristic A indicates a characteristic when the incident light is at a normal level, and a characteristic B indicates a characteristic when the incident light is extremely bright.

  As shown in FIG. 5, in the present embodiment, a junction transistor that becomes a path of a leakage current to the source region 7 is not formed between the N-type well 21 and the source region 7, and between the drain and the source. Since the P-type impurity concentration is high and punch-through is difficult to occur, the VG-VS characteristic of the modulation transistor TM is substantially linear, and the output level of each pixel is a threshold voltage (incident light amount). As well as linearly according to the gate voltage VG.

  In FIG. 5, points a and b indicate pixel signal levels based on pixels in the selected row where normal level incident light is incident and pixel signal levels Vsa and Vnb based on the noise components after initialization. Points c and d indicate the level of the pixel signal based on the pixels in the non-selected row where the extremely bright incident light is incident and the level Vsc and Vnd of the pixel signal due to the noise components after the initialization.

  Now, in a predetermined column, it is assumed that normal level incident light is incident on the pixels in the selected row and extremely bright incident light is incident on one of the pixels in the non-selected rows. At the time of reading the signal component before initialization, the level of the pixel signal based on the pixel in the selected row is Vsa. On the other hand, since the VG-VS characteristic is substantially linear for a non-selected row to which a low gate voltage is applied, the pixel signal level Vsc is also applied to pixels in the non-selected row to which extremely bright incident light is incident. Is lower than the level Vsa of the pixel signal based on the pixels in the selected row. Even when the source regions are commonly connected in the same column, the level of the output pixel signal is Vsa in reading before initialization of the selected row pixel.

  Similarly, at the time of readout of the noise component after initialization, the pixel signal level Vnd is lower than the pixel signal level Vnb based on the pixels in the selected row for the pixels in the non-selected row where extremely bright incident light is incident. It has become. Therefore, in the readout after the initialization of the pixels in the selected row, the level of the output pixel signal is Vnb. That is, in the present embodiment, for the pixels in the selected row, even when there is a pixel with a very high incident light amount in the same column, the output pixel signal indicates the pixel value (Vsa−Vnb). As a result, it is possible to prevent the occurrence of vertical black smear even when pixels with a very high incident light amount exist in the same column.

  Further, in the above-described device of Patent Document 1, a leak current flows due to a punch-through phenomenon due to the short channel effect. When a voltage for turning off the modulation transistor TM is applied to the ring gate 6, the channel is not opened (a depletion layer cannot be formed) near the surface under the gate of the modulation transistor, and no leakage current flows. However, in a slightly deeper region, the P-type impurity concentration is low and the depletion layer extends from the drain toward the source. Thereby, punch-through between the drain and the source is likely to occur.

Therefore, in the present embodiment, regarding the leak, a current that flows in a slightly deep portion is considered instead of the substrate surface. That is, in the present embodiment, the P-type diffusion layer 91 having a higher P-type impurity concentration than the P ⁻ layer 23 is provided from the bottom of the source to the drain side. Then, a depletion layer extending from the drain can be suppressed. At this time, since a voltage is applied to the substrate surface so that the modulation transistor is turned off as described above, the channel is not opened near the surface under the gate of the modulation transistor (a depletion layer cannot be formed), and the leakage current is Not flowing.
That is, according to the present embodiment, punch-through due to a short channel of the modulation transistor can be prevented.

  In the case where the carrier pocket 10 is present, the P-type impurity concentration between the drain and the source is higher, so that a punch-through due to a short channel of the modulation transistor is less likely to occur.

<Process>
Next, a method for manufacturing the element will be described with reference to the process diagrams of FIGS. 6 to 8 show cross sections taken along the line AA ′ in FIG. 6 to 8, an arrow on the substrate indicates that ion implantation is performed, a black circle indicates an implantation material, and a frame indicates a mask. In the figure, LOD Tr, Clr Tr, R.R. G Tr and Tx Tr indicate an LOD transistor TL formation region, a clear transistor TC formation region, a modulation transistor TM formation region, and a transfer transistor TT formation region, respectively.

As shown in FIG. 6A, a sacrificial oxide film 81 of 20 nm is formed on the surface of the prepared P substrate 1. Next, phosphorus (P31 +) ions are implanted so that the peak position is about 1.5 μm and the peak impurity concentration is 8 × 10 ¹⁶ cm ⁻³ . As a result, as shown in FIG. 6A, an N ⁻ N-type well 21 is formed at a relatively deep position.

Next, as shown in FIG. 6B, a P ⁻ layer 23 is formed on the entire element on the N-type well 21. For example, boron (B11 +) ions are first set to have a peak position of about 0.6 μm and a peak impurity concentration of 3 × 10 ¹⁶ cm ⁻³ , and then a peak position of about 0.4 μm and a peak impurity concentration of 3 × 10 ¹⁶ cm ^−3. By implantation, the P ⁻ layer 23 is formed on the entire surface of the substrate.

Next, as shown in FIG. 6C, an isolation region 22 (N ⁻ layer) for element isolation is formed, and the P ⁻ layer 23 is divided into the accumulation well 4 and the modulation well 5. That is, the isolation region 22 is formed in all regions between the storage well 4 and the modulation well 5 in the own cell and between adjacent cells. The isolation region 22 includes, for example, phosphorus (P31 +) ions via a resist, with a peak position of about 0.45 μm, a peak impurity concentration of 2 × 10 ¹⁷ cm ^{−3, and} then a peak position of about 0.2 μm. It is formed by performing implantation so that the concentration becomes 1.5 × 10 ¹⁶ cm ⁻³ .

Further, on the surface of the formed isolation region 22, P ^--- layers 24 and 82 that are channel dopes of the modulation transistor TM, the LOD transistor TL, and the clear transistor TC are formed. This channel dope is formed by implanting boron (B11 +) ions so as to have a peak position of about 0.03 μm and a peak impurity concentration of 4.5 × 10 ¹⁷ cm ⁻³ . Formed throughout.

Next, after removing the sacrificial oxide film 81 on the substrate surface, as shown in FIG. 7A, a gate oxide film 85 having a thickness of about 30 nm is formed on the substrate surface by thermal oxidation. Next, boron is additionally implanted as the channel dope of the clear transistor TC. This channel dope (P ^--- diffusion layer 28) is formed by implanting boron (B11 +) ions so that the peak position is about 0.03 μm and the peak impurity concentration is 4.5 × 10 ¹⁷ cm ^−3. .
As a result, the threshold voltage Vth of the clear transistor TC is made lower than the Vth of other transistors. That is, the potential under the clear gate 14 is relatively lowered to facilitate the discharge of residual charges in the modulation well 5. In particular, since the potential of the modulation well 5 is originally low, the threshold voltage Vth of the channel of the clear transistor TC needs to be sufficiently low.

Next, as shown in FIG. 7B, a carrier pocket 10 made of a dense P ⁻ diffusion layer is formed in the P ⁻ layer 23 (modulation well 5) below the ring gate 6. The carrier pocket 10 is formed, for example, by implanting boron (B11 +) ions so that the peak position is about 0.13 μm and the peak impurity concentration is 5 × 10 ¹⁷ cm ⁻³ . Further, an N ⁻ layer 84 for obtaining a channel of the modulation transistor TM is formed in the vicinity of the substrate surface on the carrier pocket 10. The N 2 ⁻ layer 84 is formed, for example, by implanting arsenic (As75 +) ions so that the peak position is about 0.05 μm and the peak impurity concentration is 2 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG. 7C, a resist having an opening is formed at a planar position corresponding to the source region 7 in the modulation transistor TM formation region, and the lower end of the carrier pocket 10 is formed below the source region 7. A P-type diffusion layer 91 in contact with the upper end of the N-type well 21 is formed. The concentration of the P type diffusion layer 91 is lower than that of the carrier pocket 10 and higher than that of the P ⁻ layer 23. For example, the P-type diffusion layer 91 is implanted with boron (B11 +) ions so that the peak position is about 0.2 to 0.3 μm and the peak impurity concentration is 3.5 × 10 ^{16 to} 5.5 × 10 ¹⁶ cm ^−3. It is formed by doing.

  Next, as shown in FIG. 7D, in the modulation transistor TM formation region, the transfer transistor TT formation region, the LOD transistor TL formation region, and the clear transistor TC formation region on the gate oxide film 85, the ring gate 6, A transfer gate 13, an LOD gate 12, and a clear gate 14 are formed.

Next, as shown in FIG. 8A, after forming an oxide film on the ring gate 6, the LOD gate 12, and the clear gate 14, respectively, the clear transistor TC is positioned adjacent to the clear gate 14. In order to form the discharge contact region 15 and the OD contact region 11 connected to the channel region, a dense P ⁺⁺ layer 83 is formed on the substrate surface. In the present embodiment, the discharge contact region 15 and the OD contact region 11 are also used, and a diffusion layer 28 as a channel of the clear transistor TC is formed on one side of the P ⁺⁺ layer 83, and the other side. The diffusion layer 30 is formed as a channel of the LOD transistor TL. Note that the discharge contact region 15 and the OD contact region 11 may be provided separately.

The P ⁺⁺ layer 83 is formed, for example, by implanting boron (B11 +) ions so that the peak position is about 0.1 μm and the peak impurity concentration is 1 × 10 ¹⁸ cm ⁻³ . Next, sidewalls are formed on the respective gates so as to cover the oxide films on the ring gate 6, the LOD gate 12 and the clear gate 14.

Next, as shown in FIG. 8B, through the resist, the substrate surface in the photodiode PD formation region, the substrate surface between the ring gate 6 and the transfer gate 13, and the ring gate 6 and the clear gate 14 An N ⁺ layer 32 is formed on the surface of the substrate. The N ⁺ layer 32 is formed by implanting arsenic (As75 +) ions into the P ^--- layer on the substrate surface so that the peak position is about 0.02 μm and the peak impurity concentration is 2 × 10 ¹⁸ cm ^−3. The

Next, as shown in FIG. 8C, an interlayer insulating film 41 is formed on the substrate surface. The LOD gate 12 of the interlayer insulating film 41, the discharge and OD contact regions 15 and 11, the source region and the transfer gate 13 are formed. A contact hole 51 is opened on the drain region 8 (not shown). Next, N ⁺⁺ impurities are implanted into the LOD gate 12, the source region and the transfer gate 13, and the drain region 8 through the opened contact hole 51, so that each gate contact and source region 7 and drain contact region 9 are implanted. Form. Next, P ⁺⁺ impurity implantation is performed on the formation region of the discharge and OD contact through the opened contact hole 51 to form the discharge and OD contact regions 15 and 11.

  Next, for example, aluminum as a wiring material is embedded in each contact hole 51, so that the LOD gate 12, the discharge and OD contact regions 15 and 11, the source region 7 and the transfer gate 13, the drain contact region 9, and the lower wiring layer 45 are formed. Each wiring 52 is connected.

  Further, an upper wiring layer 46 is formed on the lower wiring layer 45 including these wirings 52 via an interlayer insulating film 43, and is connected to each wiring 52 of the lower wiring layer 45 via a contact hole 54. Further, a light shielding film 56 is formed on the upper wiring layer 46 via the interlayer insulating film 43, and a part of the upper wiring layer 46 is connected to the light shielding film 56. Finally, a passivation film 44 is formed on the light shielding layer 47.

  The discharge and OD contact regions 15 and 11 are connected to the light shielding film 56 via a contact hole 51 opened in the interlayer insulating film 41 and a contact hole 54 opened in the interlayer insulating film 42. The light shielding film is indispensable for the image sensor, and residual charges and unnecessary charges can be easily discharged by using the indispensable structure.

<Effect of Embodiment>
As described above, in the present embodiment, by forming the P-type diffusion layer 91 below the source region 7, there is a leakage current path between the N-type well 21 on the P-type substrate 1 a and the source region 7. It is possible to prevent the formation of a leak current, and it is possible to make it difficult to generate a leak current by increasing the P-type impurity concentration in a region that can be a drain path between the drain and the source. As a result, the occurrence of black smear or the like can be prevented, and the image quality can be improved.

  In this embodiment, an example in which a carrier pocket is provided in a modulation well has been described. However, the present invention can also be applied to an image sensor that does not include a carrier pocket.

In this case, the P-type diffusion layer has a lower end in contact with the N-type well 21 between the N-type well 21 and the vicinity of the source region 7 below the source region 7 in the modulation transistor TM formation region, and an upper end in the source region. 7 so as to have a planar shape similar to the planar shape of the source region 7. The P-type diffusion layer, P ^- as well as formed to be embedded in the modulation well fifth layer 23, the concentration, P ^- is set higher than layer 23.

Sectional drawing which shows the cross-sectional shape of the solid-state imaging device concerning this Embodiment. The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on this Embodiment. The block diagram which shows the whole structure of an element. The equivalent circuit diagram of a sensor cell. The graph which shows the characteristic of the modulation transistor in a solid-state imaging device. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. 10 is a schematic cross-sectional view showing a modulation transistor portion of an image sensor disclosed in Patent Document 1. FIG. The graph for demonstrating the characteristic of a modulation transistor. The circuit diagram which shows the equivalent circuit in a prior art example. The graph which shows the change of the VG-VS characteristic of the modulation transistor by the influence of leakage current.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Accumulation well, 5 ... Modulation well, 6 ... Ring gate, 7 ... Source region, 8 ... Drain region, 11 ... OD contact region, 15 ... Discharge contact region, 91 ... P type diffusion layer, PD ... Photodiode, TM ... Modulation transistor, TT ... Transfer transistor, TL ... LOD transistor, TC ... Clear transistor

Claims (6)

A first diffusion layer of the other conductivity type formed on the one conductivity type substrate;
A photoelectric conversion element that is formed on the substrate and generates a photo-generated charge according to incident light; a one-conductivity type storage well that is formed on the first diffusion layer and stores the photo-generated charge; and the storage A modulation type well that holds the photogenerated charge transferred from the well, and a threshold voltage of a channel is controlled by the photogenerated charge held in the modulation well, so that the photogenerated charge is A modulation transistor that outputs a corresponding pixel signal;
A solid-state imaging device comprising a one-conductive-type second diffusion layer formed between the modulation well and the first diffusion layer. 2. The solid according to claim 1, wherein the second diffusion layer is formed in contact with the modulation well and the first diffusion layer in a portion corresponding to a source region of the modulation transistor. Imaging device. The modulation well further includes a one-conductivity type carrier pocket having a higher concentration than the modulation well,
The solid-state imaging device according to claim 1, wherein the second diffusion layer is formed between the carrier pocket and the first diffusion layer. 4. The solid-state imaging device according to claim 3, wherein the second diffusion layer is formed at a concentration lower than the concentration of the carrier pocket and higher than the concentration of the modulation well. Forming a first diffusion layer of the other conductivity type on the one conductivity type substrate;
One conductivity type accumulation well for accumulating photogenerated charges generated by a photoelectric conversion element formed on the substrate, and one conductivity type modulation well for retaining the photogenerated charges transferred from the accumulation well Forming a step;
A threshold voltage of a channel is controlled by the photogenerated charge held in the modulation well, and below a portion corresponding to a source region of a modulation transistor that outputs a pixel signal corresponding to the photogenerated charge, and And a step of forming a second diffusion layer of one conductivity type between the one diffusion layer and the modulation well. A method of manufacturing a solid-state imaging device, comprising: 6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the second diffusion layer is formed at a concentration lower than the concentration of the carrier pocket and higher than the concentration of the modulation well.

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