JP2006237213A - Solid state imaging device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a black smear by preventing formation of a junction FET. <P>SOLUTION: The process for fabricating a solid state imaging device including a photoelectric conversion element and a transistor formed contiguously thereto comprises a step for forming a first diffusion layer of reverse conductivity type on a substrate of one conductivity type in the region for forming the photoelectric conversion element and the transistor, a step for forming a second diffusion layer of one conductivity type on the first diffusion layer in the region for forming the photoelectric conversion element, a step for forming a third diffusion layer of one conductivity type continuously to the second diffusion layer on the first diffusion layer in the region for forming the transistor, a step for forming a gate electrode having an opening on the substrate above the third diffusion layer, a step for forming an injection control layer of conductive material on the substrate located at the opening of the gate electrode, a step for forming an insulating film on the gate electrode and the injection control layer, a step for forming a contact hole in the insulating film, and a step for forming a source region in the vicinity of the substrate surface by introducing impurities through the contact hole. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device that prevents generation of black smear and a manufacturing method thereof.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Patent Document 1.

  The image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit pixel includes a light receiving diode for performing accumulation and a transistor for performing readout.

  FIG. 10 is a schematic cross-sectional view showing the image sensor disclosed in Patent Document 1. As shown in FIG.

  In the image sensor of FIG. 10, a light receiving diode 111 and an insulated gate field effect transistor 112 are adjacently arranged for each unit pixel on a substrate 119. The gate electrode 113 of the transistor 112 is formed in a ring shape, and a source region 114 is formed in the central opening of the gate electrode 113. A drain region 115 is formed around the gate electrode 113.

  Charges (photogenerated charges) generated by light incident from the opening region of the light receiving diode 111 are transferred to the P-type well region 116 below the gate electrode 113 and accumulated in the carrier pocket 117 formed in this portion. . The threshold voltage of the transistor 112 is changed by the photo-generated charges accumulated in the carrier pocket 117. Accordingly, a signal (pixel signal) corresponding to incident light can be extracted from the source region 114 of the transistor 112.

In the device disclosed in Patent Document 1, the outputs of the unit pixels arranged in the same column are extracted through a common source line. By controlling the voltage applied to the gate of the transistor 112 for each line, selective reading from the unit pixels of a predetermined line among the unit pixels connected to the common source line is enabled. That is, a relatively high gate voltage is applied to the transistor 112 of the unit pixel (selected pixel) that performs reading, and a relatively low gate voltage is applied to the transistor 112 of the other unit pixel (non-selected pixel) that does not perform reading. To do. The output of the transistor to which the high gate voltage is applied is higher than the output of the transistor to which the low gate voltage is applied, and the output of the selected pixel can be obtained from the source line.
JP 2001-177085 A

  Incidentally, in the step of forming the source region 114 of the unit pixel in FIG. 10, for example, phosphorus is implanted as an impurity. However, since phosphorus has a high diffusion coefficient, phosphorus is diffused to a part of the well region 116 (shaded region) below the source region 114 by ion implantation at a dose necessary for forming the source region. That is, the source region 114 is formed to a relatively deep position, and the well region 116 is eroded by the source region 114. In the region 122 surrounded by the broken line between the eroded portion and its adjacent portion, the junction field effect transistor (Hereinafter also referred to as junction FET) is formed.

  FIG. 11 is an explanatory diagram showing an equivalent circuit of the unit pixel of FIG. The drain region 115 around the gate electrode 113 and the N-type diffusion layer 118 are electrically connected, and a leak path 125 from the drain region 115 to the source region 114 is formed as shown in FIG. A JFET (junction transistor Tr 1 in FIG. 11) is formed in the region 122 between the N-type diffusion layer 118 and the source region 114.

  FIG. 12 is a graph showing the concentration distribution in the source region 114 and the well region 116 therebelow, with the substrate depth on the horizontal axis and the impurity concentration on the vertical axis.

  A curve a in FIG. 12 shows an impurity concentration distribution by impurity implantation when the well region 116 is formed. A curve a indicates that the impurity is implanted to a depth corresponding to the formation position of the well region 116 slightly separated from the substrate surface. As a result, the impurity concentration in the vicinity of the diffusion layer 118 in the well region 116 has a relatively high value.

  A curve b represents an impurity concentration distribution by impurity implantation when the source region 114 is formed. Ion implantation is performed so as to form the source region 114 in the vicinity of the substrate surface. However, as described above, the impurities are diffused to a relatively deep region by ion implantation at the time of forming the source region. As a result, the impurity concentration distribution of the source region 114 is as shown by a curve c in FIG. As is clear from the comparison of the curves a and c, the concentration of the well region 116 is lowered in the region below the source region 114 due to the influence of impurities for forming the source region.

  Note that such erosion by the source region 114 does not occur in the well region 116 other than the region below the source region 114. That is, the carrier pocket 117 formed immediately below the gate electrode 113 and the well region 116 below the carrier pocket 117 are formed in a high concentration P type, whereas the well region 116 below the source region 114 is eroded and eroded. The junction FET is formed by this portion and the dense P-type well region 116 adjacent thereto.

  As shown by the curve c, the well region 116 below the source region 114 has a significantly lower potential barrier, and even when the transistor 112 is not conductive, the junction FET (Tr1) is conductive and the leak path 125 is the drain region. The conductive state from 115 to the source region 114 is established. As described above, in the device of Patent Document 1, even when the transistor 112 is not conductive, the leak path 125 by JFET is formed between the drain region 115 and the source region 114.

  Therefore, the characteristics of the transistor 112 are affected by the leakage current, particularly in a region where the gate voltage Vg is relatively low. Due to the influence of this leakage current, the output of the non-selected pixels increases, and it may not be possible to detect the correct amount of received light. For example, when strong light is incident on a part, there is a problem in that vertical stripe noise (hereinafter referred to as black smear) that is displayed in black may be generated due to the influence of the incident light of the strong light.

  The present invention has been made in view of such a problem, and provides a solid-state imaging device and a method for manufacturing the same capable of suppressing leakage current due to a junction transistor, improving characteristics of a modulation transistor, and achieving high image quality. The purpose is to provide.

  A method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device including a photoelectric conversion element and a transistor formed adjacent to the photoelectric conversion element. Forming a reverse conductivity type first diffusion layer on a conductive type substrate; forming a one conductivity type second diffusion layer on the first diffusion layer in a formation region of the photoelectric conversion element; Forming a third diffusion layer of one conductivity type on the first diffusion layer in a transistor formation region so as to be continuous with the second diffusion layer; and opening above the substrate above the third diffusion layer Forming a gate electrode having a portion, forming an injection control layer of a conductive material on the substrate located in the opening of the gate electrode, and forming an insulating film on the gate electrode and the injection control layer And the step of Forming a border membranes in the contact hole, introducing impurities through the contact hole, characterized by comprising a step of forming a source region in the vicinity of the substrate surface.

  According to such a configuration, the first diffusion layer is formed on the substrate, and the second and third diffusion layers are formed on the first diffusion layer. The second diffusion layer is formed in the photoelectric conversion element formation region and generates photogenerated charges. The third diffusion layer is formed in the transistor formation region, and photogenerated charges from the second diffusion layer are transferred to control the threshold voltage of the transistor channel. An injection control layer is provided on the substrate surface at the opening of the gate electrode. In the insulating film formed above the substrate, a contact hole is formed above the implantation control layer. Impurities are introduced into the substrate surface at the opening of the gate electrode from above the implantation control layer through this contact hole to form a source region. Some of the impurities are blocked by the implantation control layer before being introduced into the substrate. That is, the source region is formed only in the shallow area of the substrate. This makes it difficult to form a junction transistor by the first diffusion layer and the source region, and can suppress the occurrence of black smear.

  The gate electrode and the injection control layer are formed in the same process.

  According to such a configuration, the injection control layer is formed in the same process as the gate electrode, and an increase in the number of processes can be suppressed.

  The solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion element and a transistor formed next to the photoelectric conversion element, and the substrate in the formation region of the substrate, the photoelectric conversion element, and the transistor A first diffusion layer formed on the first diffusion layer; a second diffusion layer formed on the first diffusion layer in the formation region of the photoelectric conversion element; and a first diffusion layer formed on the first diffusion layer in the formation region of the transistor. A third diffusion layer formed continuously with the second diffusion layer, a gate electrode having an opening formed on the substrate above the third diffusion layer, and the opening of the gate electrode An implantation control layer made of a conductive material formed on the substrate, an insulating film formed above the substrate including the gate electrode and the implantation control layer, and a source formed near the substrate surface below the implantation control layer Region and said Characterized by comprising a contact hole formed in the insulating film on the insertion controlling layer.

  According to such a configuration, photogenerated charges generated in the photoelectric conversion element formation region are transferred from the second diffusion layer to the third diffusion layer. The threshold voltage of the channel of the transistor is controlled by the photogenerated charge held in the third diffusion layer, and a pixel signal corresponding to the photogenerated charge is output from the transistor. An injection control layer is provided on the substrate surface at the opening of the gate electrode. In the insulating film formed above the substrate, a contact hole is formed above the implantation control layer. For example, impurities are introduced into the substrate from above the implantation control layer through this contact hole. Some of the impurities are blocked by the implantation control layer, and the source region is formed in a relatively shallow range. This makes it difficult to form a junction transistor by the first diffusion layer and the source region, and can suppress the occurrence of black smear.

  The injection control layer may be made of the same conductive material as the gate electrode.

  According to such a configuration, the injection control layer can be formed in the same process as the gate electrode, and an increase in the number of manufacturing processes can be suppressed.

  Further, the source region is formed by introducing impurities from above the implantation control layer.

  According to such a configuration, an impurity is introduced into the substrate surface of the opening portion of the gate electrode from above the implantation control layer through the contact hole to form the source region. Some of the impurities are blocked by the implantation control layer before being introduced into the substrate. Therefore, the source region is formed only in the shallow area of the substrate. This makes it difficult to form a junction transistor by the first diffusion layer and the source region, and can suppress the occurrence of black smear.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing a cross-sectional shape of one sensor cell of the solid-state imaging device according to the present embodiment, and FIG. 2 is an explanatory diagram showing a planar shape of one sensor cell of the solid-state imaging device according to the present embodiment. . 1 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a circuit block diagram showing the entire structure of the element by an equivalent circuit. FIG. 4 is a graph showing transistor characteristics in this embodiment. FIG. 5 to FIG. 9 are process diagrams for explaining the manufacturing method by the sectional shape of the element and the planar shape of the mask. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

<Structure of sensor cell>
The solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells that are unit pixels are arranged in a matrix. Each sensor cell collects and accumulates photogenerated charges generated according to incident light, and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  First, the structure of each sensor cell will be described with reference to FIGS. FIG. 2 shows one sensor cell. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible. FIG. 1 shows a cross-sectional structure of the cell cut along the line A-A ′ of FIG. 2.

  As shown in the plan view of FIG. 2, a photodiode PD and a modulation transistor TM are provided adjacent to each other in a sensor cell 3 that is a unit pixel. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used.

  In the photodiode PD formation region, which is a photoelectric conversion element formation region, an opening region that transmits light is formed in the step of forming a wiring layer on the surface of the substrate 1. A P-type well in a region wider than the opening region is formed at a relatively shallow position on the surface of the substrate 1, and a collection well 4 as a second diffusion layer for collecting photogenerated charges generated by the photoelectric conversion element is formed. Yes. An N-type diffusion layer 32 as a pinning layer is formed on the surface of the substrate 1 on the collection well 4.

  A P-type well is formed in the modulation transistor TM formation region at a position substantially the same substrate depth as that of the collection well 4, and the photo-generated charges collected in the collection well 4 are transferred to control the modulation transistor TM. A modulation well 5 as a three diffusion layer is formed. In the example of FIG. 1, the collection well 4 and the modulation well 5 are configured by the respective parts of the P well 24 formed integrally, but may be formed separately.

  An annular gate (ring gate) 6 is formed on the surface of the substrate 1 on the modulation well 5, and a region near the surface of the substrate 1 in the opening 6 e at the center of the ring gate 6 is a high-concentration N-type region. A certain source region 7 (the net line portion in FIG. 2) is formed. In FIG. 2, the ring gate 6 and carrier pockets to be described later are shown in a circular shape, but may be in an elliptical shape or an arbitrary polygonal shape (for example, an octagonal shape).

  As shown in FIG. 1, the ring gate 6 is composed of a polysilicon layer 6a, a tungsten silicide layer 6b, and an oxide film layer 6c from the lower layer. However, the ring gate 6 may have a single layer structure made of, for example, a polysilicon layer.

  In the present embodiment, an injection control layer 35 is formed in an island shape on the surface of the substrate 1 in the opening 6e. As shown in FIG. 1, the implantation control layer 35 includes a polysilicon layer 35a, a tungsten silicide layer 35b, and an oxide film layer 35c, which are conductive materials. The injection control layer 35 may be composed of only one polysilicon layer.

An N-type drain region 8 is formed around the ring gate 6. An N ⁺ drain contact region (not shown) is formed near the surface of the substrate 1 at a predetermined position of the drain region 8.

  The modulation well 5 controls the threshold voltage of the channel of the modulation transistor TM. In the modulation well 5, a carrier pocket 10 (shaded portion in FIG. 2) which is a P-type high concentration region is formed below the ring gate 6. The modulation transistor TM is constituted by the modulation well 5, the ring gate 6, the source region 7 and the drain region 8, and the threshold voltage of the channel changes according to the electric charge accumulated in the modulation well 5 (carrier pocket 10). It is like that.

<Sensor cell cross section>
Furthermore, the cross-sectional structure of the sensor cell 3 will be described in detail with reference to FIG.

  An isolation region 22 is provided between the photodiode PD formation region (PD) and the modulation transistor TM formation region (TM) of adjacent cells. N-type wells 21 and 21 ′ as first diffusion layers are formed in the entire region of the P-type substrate 1 at a relatively deep position of the substrate 1. A P-type collection well 4 is formed on the N-type well 21 in the photodiode formation region. An N-type diffusion layer 32 which is a pinning layer is formed on the substrate surface side above the collection well 4. The N-type well 21 is formed up to a relatively deep position on the substrate.

  On the other hand, a P-type buried layer 23 is formed on the substrate 1 in the modulation transistor TM formation region. The P-type buried layer 23 limits the N-type well 21 'to a relatively shallow position on the substrate. A P-type modulation well 5 is formed on the N-type well 21 ′ on the P-type buried layer 23. A carrier pocket 10 is formed in the modulation well 5.

The carrier pocket 10 is formed in a ring shape below the ring gate 6 in plan view. The carrier pocket 10 is a sufficiently high concentration diffusion layer by P ⁺ diffusion.

  In the modulation transistor TM formation region, the ring gate 6 is formed on the substrate surface via the gate oxide film 31, and the N-type diffusion layer 27 constituting the channel is formed on the substrate surface below the ring gate 6. As described above, the ring gate 6 has a three-layer structure including a polysilicon layer 6a made of a conductive material, a tungsten silicide layer 6b, and an insulating layer 6c. A side wall 6 d is formed on the side surface of the ring gate 6.

In the center opening 6e portion of the ring gate 6, an island-shaped injection control layer 35 is formed on the substrate surface. The island-shaped implantation control layer 35 includes a polysilicon layer 35a and a tungsten silicide layer 35b made of a conductive material. The lowermost layer of the implantation control layer 35 is a polysilicon layer 35a, and a source region 7 made of an N ⁺ diffusion layer is formed in a relatively shallow area near the surface of the substrate 1 including the polysilicon layer 35a.

  Further, an N-type diffusion layer is formed on the substrate surface around the ring gate 6 to constitute the drain region 8. The N type diffusion layer 27 constituting the channel is electrically connected to the source region 7 and the drain region 8. The isolation region 22 is electrically connected to the N-type wells 21 and 21 ′ and the drain region 8.

  The drain region 8, the diffusion layer 22, the diffusion layer 21, the diffusion layer 21 ′, and the diffusion layer 32 are biased to a positive potential by the application of the drain voltage, so that the diffusion layer 32 and A depletion layer extends from the boundary surface with the collection well 4 and from the boundary surface between the diffusion layer 21 and the collection well 4 to the entire collection well 4 and its periphery. In the depletion region, photogenerated charges due to light incident through the opening region are generated. As described above, the generated photo-generated charges are collected in the collection well 4.

  The charges collected in the collection well 4 are transferred to the modulation well 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of charge transferred to the modulation well 5, that is, the incident light to the photodiode PD.

  An interlayer insulating film 41 is formed on the entire surface of the substrate including the ring gate 6 and the injection control layer 35. A contact hole 42 is formed in the interlayer insulating film 41 on the source region 7, that is, on the implantation control layer 35, and a conductive material (not shown) is embedded in the contact hole 42. . The conductive material is connected to a wiring layer (not shown) formed on the interlayer insulating film 41. As will be described later, in the insulating layer 35c formed in the process of forming the implantation control layer 35, the contact hole 42 portion is removed when the contact hole 42 is formed.

  In the present embodiment, as will be described later, the source region 7 is formed by ion implantation through the contact hole 42. In this case, the implantation control layer 35 prevents a part of impurities for forming the source region 7 from proceeding into the substrate. Thereby, the source region 7 formed by ion implantation through the implantation control layer 35 is diffused only in a relatively shallow region of the substrate.

  For example, the source region 7 is formed in a range from the implantation control layer 35 to the vicinity of the modulation well 5 in the substrate 1. With this configuration, the path length of the leak current from the N-type well 21 ′ to the source region 7 becomes long, and the leak current can be made difficult to flow.

<Circuit configuration of the entire device>
Next, a circuit configuration of the entire solid-state imaging device according to the present embodiment will be described with reference to FIG.

  The solid-state imaging device 61 includes a sensor cell array 62 including the sensor cells 3 of FIG. 2 and circuits 63 to 65 for driving the sensor cells 3 in the sensor cell array 62. The sensor cell array 62 is configured by arranging the cells 3 in a matrix. The sensor cell array 62 includes, for example, a 640 × 480 cell 3 and an optical black (OB) region (OB region). When the OB region is included, the sensor cell array 62 is composed of, for example, 712 × 500 cells 3.

  Each sensor cell 3 includes a photodiode PD that performs photoelectric conversion and a modulation transistor TM for detecting and reading out an optical signal. The photodiode PD generates a charge (photogenerated charge) corresponding to the incident light, and the generated charge is collected in the collection well 4 (corresponding to the connection point PDW in FIG. 3). The photo-generated charges collected in the collection well 4 are transferred to and held in the carrier pocket 10 in the modulation well 5 (corresponding to the connection point TMW in FIG. 3) for threshold modulation of the modulation transistor TM.

  The modulation transistor TM is equivalent to a change in the back gate bias due to the photogenerated charge held in the carrier pocket 10, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 10. As a result, the source voltage of the modulation transistor TM corresponds to the charge in the carrier pocket 10, that is, corresponds to the brightness of the incident light of the photodiode PD.

  In this manner, each cell 3 exhibits operations such as accumulation, transfer, readout, and discharge by applying drive signals to the ring gate 6, the source region 7, and the drain region 8 of the modulation transistor TM. A signal is output from the source region 7 to a wiring (not shown) on the interlayer insulating film 41 via a conductive material (not shown) in the implantation control layer 35 and the contact hole 42.

  Signals are supplied to each part of the cell 3 (not shown) from a vertical drive scanning circuit 63, a drain drive circuit 64, and a horizontal drive scanning circuit 65, as shown in FIG. The vertical drive scanning circuit 63 supplies a scanning signal to the gate line 67 in each row, and the drain drive circuit 64 applies a drain voltage to the drain region 8 in each column. The horizontal drive scanning circuit 65 supplies a drive signal to the switch 68 connected to each source line 66.

  Each cell 3 is provided corresponding to the intersection of a plurality of source lines 66 arranged in the horizontal direction in the sensor cell array 62 and a plurality of gate lines 67 arranged in the vertical direction. In each cell 3 of each line arranged in the horizontal direction, the ring gate 6 of the modulation transistor TM is connected to a common gate line 67, and each cell 3 in each column arranged in the vertical direction is the source of the modulation transistor TM. Are connected to a common source line 66.

  By supplying an ON signal (selection gate voltage) to one of the plurality of gate lines 67, the cells commonly connected to the gate line 67 to which the ON signal is supplied are simultaneously selected, and these selected cells are selected. A pixel signal is output from each source via each source line 66. The vertical drive scanning circuit 63 supplies an ON signal to the gate line 67 while sequentially shifting it in one frame period. Pixel signals from each cell of the line to which the ON signal is supplied are simultaneously read from each source line 66 for one line and supplied to each switch 68. The pixel signals for one line are sequentially output (line output) for each pixel from the switch 68 by the horizontal drive scanning circuit 65.

  The switch 68 connected to each source line 66 is connected to the video signal output terminal 70 via a common constant current source (load circuit) 69. The source of the modulation transistor TM of each sensor cell 3 is connected to the constant current source 69, and the source follower circuit of the sensor cell 3 is configured.

<Action>
In the device of Patent Document 1 described above, the source regions of all the modulation transistors in the same column are connected in common, and the voltage applied to the gates of the modulation transistors in the selected row and the non-selected row is controlled, so The source voltage of the modulation transistor in the row is detected. That is, the potential (Vg) of the gate electrode is set high for all the pixels in the selected row, and the potential (Vg) of the gate electrode in the non-selected row is set to the ground potential.

  In addition, in order to eliminate variations between unit pixels and various noises, in the read operation, following the read operation of the optical signal of the selected row, the potential application state to the pixels of the non-selected row is left as it is. The pixels in the selected row are initialized, and subsequently the threshold voltage in the initialized state is read out. Then, a signal of the difference between the threshold voltage corresponding to the photogenerated charge amount and the threshold voltage in the initialized state is calculated, and the net optical signal component is output as a video signal.

  A reading process in the apparatus of Patent Document 1 will be described with reference to FIG. 4 showing characteristics of the modulation transistor TM. A characteristic A in FIG. 4 shows a Vg (gate voltage) -Vs (source voltage) characteristic in the dark, a characteristic B shows a Vg-Vs characteristic in a normal light incidence, and a characteristic C in a very strong light incidence. The Vg-Vs characteristic is shown, and the characteristic D shows the Vg-Vs characteristic at the time of clearing.

  In FIG. 4, the range of the arrow indicates the difference between the level Vsa of the pixel signal based on the pixels in the selected row where the normal level of incident light is incident and the level Vnb of the pixel signal due to the noise component after initialization. Further, the level Vc indicates the level of the pixel signal based on the pixels in the non-selected row where the extremely bright incident light is incident. When light of normal intensity is incident, a signal having a level of (Vsa−Vnb) (arrow range) is obtained as the pixel signal of the pixel in the selected row.

  Now, in a predetermined column, it is assumed that normal level incident light is incident on the pixels in the selected row and extremely bright incident light is incident on one of the pixels in the non-selected rows. The level of the pixel signal before initialization based on the pixels in the selected row is Vsa. However, the level Vnb of the pixel signal after initialization of the selected row is lower than the level Vc of the pixel signal based on the pixels of the non-selected row when extremely strong light is incident. Since the source regions are commonly connected in the same column, a higher level Vc is obtained as the pixel signal level after initialization at the time of readout after initialization. That is, a signal having a level (Vsa−Vc) is output as the pixel signal of the pixel in the selected row. (Vsa−Vc) is a relatively small value, and the display based on the pixel signal output is black. Until initialization of a pixel to which extremely intense light is incident is performed, the output of each pixel connected to the source line 66 is a relatively small value, and the screen display is a black smear in the vertical direction.

  On the other hand, in the present embodiment, the formation of the injection control layer 35 in contact with the substrate surface of the source region 7 prevents the occurrence of black smear when strong light is incident.

  First, the light detection and photogenerated charge collection operation of the photodiode PD of the sensor cell 3 and the read operation of the modulation transistor TM will be described.

  A low gate voltage is applied to the ring gate 6 of the modulation transistor TM, and a voltage (VDD) of approximately 2 to 4 V, for example, necessary for the operation of the transistor is applied to the drain region 8. As a result, the N-type well 21 is depleted. An electric field is generated between the drain region 8 and the source region 7.

  Light incident through the opening region 2 of the photodiode PD enters the depleted N-type well 21 to generate electron-hole pairs (photogenerated charges). The P-type collection well 4 has a low potential due to the introduction of high-concentration P-type impurities, and the photogenerated charges generated in the N-type well 21 are collected in the collection well 4. Further, the photogenerated charges are transferred from the collection well 4 to the modulation well 5 in the modulation transistor formation region and accumulated in the carrier pocket 10.

  In this case, the thickness of the modulation well 5 below the carrier pocket 10 is relatively thin, and most of the photogenerated charges are accumulated in the carrier pocket 10 near the substrate surface. Thereby, high modulation efficiency can be obtained.

  The threshold voltage of the modulation transistor TM is changed by the photo-generated charges accumulated in the carrier pocket 10. In this state, a gate voltage (selection gate voltage) of about 2 to 4 V, for example, is applied to the ring gate 6 of the selected pixel, and a voltage VDD of about 2 to 4 V, for example, is applied to the drain region 8. Further, a constant current is passed through the source region 7 of the modulation transistor TM by the constant current source 69. As a result, the modulation transistor TM forms a source follower circuit, and the source potential changes following the change in the threshold voltage of the modulation transistor TM due to the photo-generated charges, so that the output voltage changes. That is, an output corresponding to the incident light can be obtained.

  At the time of initialization, charges remaining in the carrier pocket 10, the collection well 4, and the modulation well 5 are discharged. For example, a high positive voltage of 5 V or more is applied to the drain region 8 and the ring gate 6 of the modulation transistor TM. Below the source region 7, the N-type well 21 ′ below the modulation well 5 is thin, and a high-concentration P-type buried layer 23 is formed on the substrate 1 facing the N-type well 21 ′. Therefore, the influence of the voltage applied to the ring gate 6 acts only on the modulation well 5 (particularly below the source region 7) and its adjacent region. That is, a sudden potential change occurs in the modulation well 5, and a strong electric field that sweeps out the photogenerated charge to the substrate 1 side is mainly applied to the modulation well 5, so that the remaining photogenerated charge is more reduced at a low reset voltage. It is reliably discharged onto the substrate 1.

  After initialization, a non-selection gate voltage having a relatively low voltage value is applied to the ring gate 6 of the non-selection pixel, and a selection gate voltage having a relatively high voltage value is applied to the ring gate 6 of the selection pixel. . Then, a signal output after initialization of the selected pixel is obtained from the commonly connected source line 66.

  In the present embodiment, an injection control layer 35 is formed on the substrate surface of the source region 7. Therefore, at the time of ion implantation through the contact hole 42, the impurities are implanted into the substrate surface through the implantation control layer 35, and the source region 7 having a relatively shallow depth from the substrate surface is formed. This makes it difficult to form a junction FET that serves as a leakage path, thereby preventing the occurrence of black smear.

  FIG. 4 shows a change in transistor characteristics in the present embodiment by a thick broken line. The transistor characteristics in the present embodiment are that the source region 7 is formed with a shallow depth from the substrate surface, and the leakage current path from the N-type well 21 ′ to the source region 7 is blocked. Even in the low gate voltage range, the linearity is good. FIG. 4 shows the characteristics of the modulation transistor TM by a solid line and a bold broken line, and each characteristic A to D is excellent in linearity even in a relatively low gate voltage range, as shown by the bold broken line. Vg-Vs characteristics are obtained.

  As shown in FIG. 4, even when a sufficiently low non-selection gate voltage is applied even in a non-selection pixel where strong light is incident, the output level Vc ′ of the pixel signal is the pixel signal level of the selection pixel after initialization. It becomes lower than Vnb. Thereby, even when each pixel in the same column is connected to the common source line 66, a sufficiently high selection gate voltage is applied to the ring gate 6 of the modulation transistor TM to select it as a pixel signal before and after initialization. A pixel signal obtained from the pixel can be obtained. That is, even when extremely strong light is incident, a signal before and after initialization based on the selected pixel can be obtained in the same manner as when normal brightness light is incident, and a normal pixel signal corresponding to the amount of incident light is obtained. Can be output, and the occurrence of black smear can be prevented.

<Process>
Next, a method for manufacturing the element will be described with reference to the process diagrams of FIGS. 5 to 8, the left side shows the cross-sectional shape of the element, and the right side shows the planar shape of the mask used in the manufacturing process of the left element. 5 to 8, the cross section at the position of the right AA ′ cutting line is shown as the left cross section. 5 to 9, the arrow on the substrate indicates that ion implantation is performed.

  As shown in FIG. 5A, boron (B) ions, for example, are implanted into the entire surface of the prepared P substrate 1 to form a P-type well 24 on the surface side of the substrate 1. The P-type well 24 constitutes the collection well 4 in the photodiode formation region and the modulation well 5 in the modulation transistor formation region.

  Next, a resist mask 91 is formed in a portion other than the photodiode formation region, and, for example, phosphorus (phosphorus (P)) ions are implanted to form the N-type well 21 (FIG. 5E). This ion implantation is performed up to a relatively deep position in the photodiode formation region (FIG. 5B).

  Next, phosphorus ions are implanted into the substrate 1 to form an N-type well below the P-type well 24. Thus, an N-type well 21 is formed in the photodiode formation region, and an N-type well 21 'is formed in the modulation transistor formation region (FIG. 5C).

  Next, using the resist mask 92 shown in FIG. 5F, P-type impurities are deeply ion-implanted in the modulation transistor formation region to form the P-type buried layer 23 (FIG. 5D). Further, an N-type diffusion layer 27 for obtaining a channel of the modulation transistor TM is formed in the vicinity of the surface of the substrate 1 using the same resist mask 92.

  Next, as shown in FIGS. 6A and 6E, a resist mask 93 is formed, and an isolation region 22 for element isolation is formed. Next, as shown in FIG. 6B, a gate oxide film 31 is formed on the surface of the substrate 1 by thermal oxidation.

  Next, in this embodiment, the resist mask 94 shown in FIG. 6F is formed, and the gate oxide film 31 at the position where the implantation control layer 35 is formed is removed (FIG. 6C). Thereby, the source region 7 described later can be electrically connected to the conductive material in the contact hole 42 through the implantation control layer 35.

Next, as shown in FIGS. 6D and 6G, using the resist mask 95, the carrier pocket 10 made of a dense P ⁺ diffusion layer is formed in the modulation well 5 below the ring gate 6. The planar shape of the ring gate 6 is annular.

  Next, as shown in FIG. 7A, a polysilicon layer 96, a tungsten silicide layer 97, and an insulating layer are formed on the gate oxide film 31 in order to form the ring gate 6 and the injection control layer 35 of the modulation transistor TM. 98 is formed. Next, as shown in FIGS. 7B and 7E, a three-layer ring gate 6 and an implantation control layer 35 are formed by etching using the resist masks 99 and 100 (FIG. 7C). ).

  Next, as shown in FIGS. 7D and 7F, N-type impurities are ion-implanted using the resist mask 101 and the ring gate 6 formed so as to close the central opening 6e of the ring gate 6 as a mask. Then, an N-type diffusion layer 32 as a pinning layer is formed on the surface of the substrate 1.

  Next, as shown in FIG. 8A, an oxide film 51 is deposited in order to form the sidewall 6 d on the ring gate 6. Next, as shown in FIG. 8B, sidewalls 6d are formed by anisotropic etching.

  Next, as shown in FIGS. 8C and 8E, N-type impurities are ion-implanted by using the resist mask 102 and the ring gate 6 covering the ring gate opening and the photodiode formation region as a mask to form the drain region 8. Form.

  Next, after forming an interlayer insulating film 41 on the surface of the substrate 1, a contact hole 42 reaching the tungsten silicide layer 35b of the implantation control layer 35 at the center of the opening of the ring gate 6 is formed (FIGS. 8D and 8F). )). When the contact hole 42 is formed, the insulating layer deposited on the upper layer of the implantation control layer 35 is also removed at the same time.

  Next, as shown in FIG. 9, the source region 7 is formed by ion implantation into the substrate surface via the contact hole 42. Since the implantation control layer 35 is formed on the substrate surface above the source region 7, the impurity implantation through the contact hole 42 is always performed through the implantation control layer 35. Therefore, part of the impurities is absorbed by the implantation control layer 35, and the source region 7 is formed only in a relatively shallow portion of the substrate surface. As a result, it is possible to prevent the junction FET from being formed by the N-type well 21 ′ and the source region 7 and to suppress the occurrence of black smear.

  Thereafter, a conductive material is formed in the contact hole 42. This conductive material is connected to the source region 7 through the injection control layer 35.

  Note that the ring gate and the implantation control layer in the above manufacturing method are constituted by the polysilicon layer, the tungsten silicide layer, and the oxide film layer from the lower layer, but may have a single layer structure made of, for example, a polysilicon layer. it is obvious.

  In the above manufacturing method, the example in which the injection control layer is formed using the same material as the ring gate when the ring gate is formed has been described. However, the injection control layer may be formed using another material at another timing. It is clear that it is good.

FIG. 3 is a schematic cross-sectional view showing a cross-sectional shape of one sensor cell of the solid-state imaging device according to the present embodiment. Explanatory drawing which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on this Embodiment. The circuit block diagram which shows the whole structure of an element with an equivalent circuit. 10 is a graph showing transistor characteristics in this embodiment. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. The top view for demonstrating the manufacturing method of an element. FIG. 6 is a schematic cross-sectional view showing an image sensor disclosed in Patent Document 1. Explanatory drawing which shows the equivalent circuit of the unit pixel of FIG. The graph showing the concentration distribution in the source region 114 and the well region 116 therebelow, with the substrate depth on the horizontal axis and the impurity concentration on the vertical axis.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Collection well, 5 ... Modulation well, 6 ... Ring gate, 7 ... Source region, 8 ... Drain region, 10 ... Carrier pocket, 35 ... Injection control layer, PD ... Photodiode, TM ... Modulation transistor .

Claims (5)

In a method for manufacturing a solid-state imaging device including a photoelectric conversion element and a transistor formed next to the photoelectric conversion element,
Forming a first diffusion layer of reverse conductivity type on a substrate of one conductivity type in the formation region of the photoelectric conversion element and the transistor;
Forming a second diffusion layer of one conductivity type on the first diffusion layer in the formation region of the photoelectric conversion element;
Forming a third diffusion layer of one conductivity type on the first diffusion layer in the transistor formation region so as to be continuous with the second diffusion layer;
Forming a gate electrode having an opening above the substrate above the third diffusion layer;
Forming an implantation control layer of a conductive material on the substrate located in the opening of the gate electrode;
Forming an insulating film on the gate electrode and the implantation control layer;
Forming a contact hole in the insulating film;
And a step of forming a source region in the vicinity of the substrate surface by introducing impurities through the contact hole.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the gate electrode and the injection control layer are formed by the same process. In a solid-state imaging device including a photoelectric conversion element and a transistor formed next to the photoelectric conversion element,
A substrate,
A first diffusion layer formed on the substrate in a formation region of the photoelectric conversion element and the transistor;
A second diffusion layer formed on the first diffusion layer in the formation region of the photoelectric conversion element;
A third diffusion layer formed on the first diffusion layer in the transistor formation region and formed continuously with the second diffusion layer;
A gate electrode having an opening formed on the substrate above the third diffusion layer;
An implantation control layer made of a conductive material formed on the substrate in the opening of the gate electrode;
An insulating film formed above the substrate including the gate electrode and the injection control layer;
A source region formed in the vicinity of the substrate surface below the implantation control layer;
And a contact hole formed in the insulating film on the injection control layer.   The solid-state imaging device according to claim 3, wherein the injection control layer is made of the same conductive material as the gate electrode.   The solid-state imaging device according to claim 3, wherein the source region is formed by introducing an impurity from above the implantation control layer.

Images