JP2013211295A - Solid state image pickup device and method of manufacturing the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device capable of improving conversion efficiency by reducing parasitic capacitance.SOLUTION: A solid state image pickup device is characterized in that a photoelectric conversion portion comprising a photodiode PD and a floating diffusion FD are formed on a semiconductor substrate 1; a first gate electrode 13 includes at least the part of the floating diffusion FD and transfers electric charges to the floating diffusion FD; and a recessed portion 11A is formed by digging the semiconductor substrate 11 located under a second gate electrode 14 which resets electric charges of the floating diffusion FD.

Description

  The present technology relates to a solid-state imaging device and a manufacturing method thereof. The present invention also relates to an electronic device including a solid-state imaging device.

  In order to improve conversion efficiency, which is one of the important characteristics in solid-state imaging devices, it is necessary to reduce parasitic capacitance such as fringe capacitance with peripheral circuit elements and gate overlap capacitance. desirable.

Therefore, a configuration has been proposed in which a high concentration impurity region of the floating diffusion is formed away from the transfer gate (see, for example, Patent Document 1 and Patent Document 2).
By forming the high-concentration impurity region of the floating diffusion away from the transfer gate in this way, it is possible to reduce the parasitic capacitance between the floating diffusion and the transfer gate and improve the conversion efficiency. .

JP 2002-368201 A JP 2011-54880 A

In the conventional configuration, the floating diffusion is formed in the active region surrounded by the element isolation region. For this reason, misalignment between the mask for forming the impurity region of the floating diffusion and the mask for forming the active region may occur.
When this mask misalignment occurs, it causes variations in floating diffusion characteristics.

  On the other hand, if the area of the floating diffusion is increased, a sufficient mask misalignment margin can be secured, but the pixel size is increased, which hinders miniaturization of the pixel size.

  In addition, in the structure in which the impurity region of the floating diffusion is formed away from the transfer gate, it is necessary to secure a large area by the distance from the transfer gate. In this case as well, the pixel size becomes large. It becomes an obstacle.

  An object of the present technology is to provide a solid-state imaging device that can reduce parasitic capacitance and improve conversion efficiency, and a manufacturing method thereof. Moreover, the electronic device provided with this solid-state imaging device is provided.

The solid-state imaging device according to the present technology includes a semiconductor substrate, a photoelectric conversion unit including a photodiode formed on the semiconductor substrate, and a floating diffusion formed on the semiconductor substrate.
A first gate electrode that transfers charges to the floating diffusion and a second gate electrode that resets the charges of the floating diffusion are included.
In addition, the semiconductor substrate includes a recess formed by digging into the semiconductor substrate rather than the semiconductor substrate below the first gate electrode and the second gate electrode, including at least the floating diffusion portion.

The method for manufacturing a solid-state imaging device according to the present technology is a method for manufacturing a solid-state imaging device in which a photoelectric conversion unit including a photodiode and a floating diffusion are formed on a semiconductor substrate.
Then, a step of forming the first gate electrode and the second gate electrode on the semiconductor substrate, and a semiconductor substrate between the first gate electrode and the second gate electrode are dug to form a recess in the semiconductor substrate. Forming.
Furthermore, the semiconductor substrate includes a step of forming a floating diffusion in a recess between the first gate electrode and the second gate electrode, and a step of forming a photoelectric conversion portion in the semiconductor substrate.

  An electronic apparatus of the present technology includes an optical system, a solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device, and the solid-state imaging device has the configuration of the solid-state imaging device of the present technology.

According to the above-described configuration of the solid-state imaging device of the present technology, the semiconductor substrate is dug and recessed, including at least the floating diffusion portion, rather than the semiconductor substrate below the first gate electrode and the second gate electrode. Is formed.
As a result, the distance between the first gate electrode and the second gate electrode and the floating diffusion formed in the recess can be increased, and the first gate electrode, the second gate electrode, and the floating diffusion are parasitic. The capacity can be reduced.

According to the above-described method for manufacturing a solid-state imaging device of the present technology, the semiconductor substrate between the first gate electrode and the second gate electrode is dug to form a recess in the semiconductor substrate, and the first gate electrode and A floating diffusion is formed in this recess between the second gate electrodes.
Thereby, it is possible to increase the distance between the floating diffusion formed in the recess and the first gate electrode and the second gate electrode, and the parasitic capacitance between the first gate electrode and the second gate electrode and the floating diffusion. Can be reduced.

  According to the configuration of the electronic apparatus of the present technology described above, since the solid-state imaging device of the present technology is provided, in the solid-state imaging device, the parasitic capacitance between the first gate electrode, the second gate electrode, and the floating diffusion is reduced. It becomes possible to do.

  According to the above-described present technology, the parasitic capacitance between the gate electrode and the floating diffusion can be reduced, so that the conversion efficiency can be improved.

  In addition, since the floating diffusion is formed in the recess in which the semiconductor substrate is dug, the parasitic capacitance can be reduced without separating the gate electrode and the floating diffusion in the horizontal direction. This makes it possible to reduce the parasitic capacitance and improve the conversion efficiency without increasing the area of the floating diffusion portion.

1 is a schematic configuration diagram (plan view) of a solid-state imaging device according to a first embodiment. 2 is an equivalent circuit diagram of a pixel of the solid-state imaging device according to the first embodiment. FIG. 1A to 1C are cross-sectional views of main parts of a solid-state imaging device according to a first embodiment. FIGS. 8A to 8C are process diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIGS. FIGS. 8A to 8C are process diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIGS. FIGS. 8A to 8C are process diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIGS. FIGS. 8A to 8C are process diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIGS. FIGS. 8A to 8C are process diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIGS. A is a plan view of the vicinity of the floating diffusion. B is a cross-sectional view taken along line BB in FIG. 9A. C is a cross-sectional view taken along the line CC of FIG. 9A. FIGS. 8A to 8C are plan views of a mask pattern when the effect of misalignment margin is not considered in the first embodiment. FIGS. FIGS. 9A to 9C are plan views of a mask pattern in the case of considering an effect of a misalignment margin in the first embodiment. FIGS. AC is sectional drawing of the principal part of the solid-state imaging device of 2nd Embodiment. A to C are process diagrams illustrating a method of manufacturing the solid-state imaging device according to the second embodiment. A to C are process diagrams illustrating a method of manufacturing the solid-state imaging device according to the second embodiment. A to C are process diagrams illustrating a method of manufacturing the solid-state imaging device according to the second embodiment. A to C are process diagrams illustrating a method of manufacturing the solid-state imaging device according to the second embodiment. FIGS. 9A to 9C are plan views of mask patterns when the effect of misalignment margin is not considered in the second embodiment. FIGS. FIGS. 9A to 9C are plan views of a mask pattern in the case where the effect of misalignment margin is considered in the second embodiment. FIGS. It is a schematic block diagram (block diagram) of the electronic device of 3rd Embodiment. It is a top view of the floating diffusion vicinity of A conventional structure. B is a cross-sectional view taken along line BB of FIG. 20A. C is a cross-sectional view taken along the line CC of FIG. 20A. It is a figure explaining the floating diffusion in A, B CMOS solid-state imaging device, and its surrounding parasitic capacitance.

The best mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described below.
The description will be given in the following order.
1. First embodiment (solid-state imaging device)
2. Second embodiment (solid-state imaging device)
3. Third embodiment (electronic device)

<1. First Embodiment (Solid-State Imaging Device)>
FIG. 1 shows a schematic configuration diagram (plan view) of the solid-state imaging device according to the first embodiment.
FIG. 2 shows an equivalent circuit diagram of a pixel of the solid-state imaging device according to the first embodiment.
In the present embodiment, the present technology is applied to a CMOS solid-state imaging device (CMOS image sensor).

  As shown in FIG. 1, the solid-state imaging device 1 according to the present embodiment includes a pixel unit 3 in which a large number of pixels 2 including photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate 11 such as a silicon substrate, It is constituted by a solid-state imaging device formed with a peripheral circuit portion including a circuit and the like.

The pixel 2 includes a photoelectric conversion unit and a pixel transistor composed of a MOS transistor.
Examples of the pixel transistor include a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows.
That is, the vertical drive circuit 4 selectively scans the pixels 2 of the pixel unit 3 in the vertical direction sequentially in units of rows, and passes through the vertical signal lines 9 to generate pixel signals based on the signal charges generated according to the amount of light received in each pixel 2 Is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and performs signal processing such as noise removal for each pixel column on a signal output from the pixels for one row.
That is, the column processing circuit 5 performs signal processing such as CDS for removing fixed pattern noise peculiar to the pixel 2, signal amplification, and AD conversion.
A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.
The input / output terminal 12 exchanges signals with the outside.

  As shown in FIG. 2, the pixel 2 in the solid-state imaging device according to the present embodiment includes a photodiode PD serving as a photoelectric conversion unit and a floating diffusion FD. In addition, the pixel 2 includes four transistors: a transfer transistor TR, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

The transfer transistor TR has a source connected to the cathode side of the photodiode PD and a drain connected to the floating diffusion FD. Further, a transfer wiring for supplying a transfer pulse φTR is connected to the transfer gate electrode 13 of the transfer transistor TR.
The signal charge (electrons in this embodiment) photoelectrically converted by the photodiode PD is transferred to the floating diffusion FD by applying a transfer pulse φTR to the transfer gate electrode 13 of the transfer transistor TR.

The reset transistor RST has a drain connected to the power supply voltage VDD and a source connected to the floating diffusion FD. A reset wiring for supplying a reset pulse φRST is connected to the reset gate electrode 14 between the source and drain of the reset transistor RST.
Prior to the transfer of signal charges from the photodiode PD to the floating diffusion FD, a reset pulse φRST is applied to the reset gate electrode 14 of the reset transistor RST. As a result, the potential of the floating diffusion FD is reset to the VDD level by the power supply voltage VDD.

The amplifying transistor AMP has its drain connected to the power supply voltage VDD and its source connected to the drain of the selection transistor SEL. The amplification gate electrode 15 between the source and drain of the amplification transistor AMP is connected to the floating diffusion FD.
The amplification transistor AMP constitutes a source follower circuit using the power supply voltage VDD as a load, and a pixel signal corresponding to the potential change of the floating diffusion FD is output.

The selection transistor SEL has its drain connected to the source of the amplification transistor AMP and its source connected to the vertical signal line 9. A selection wiring for supplying a selection pulse φSEL is connected to the selection gate electrode 16 between the source and drain of the selection transistor SEL.
By supplying the selection pulse φSEL to the selection gate electrode 16 for each pixel 2, the pixel signal amplified by the amplification transistor AMP is output to the vertical signal line 9.

With the above configuration, by supplying the transfer pulse φTR to the transfer gate electrode 12, the signal charge accumulated in the photodiode PD is read out to the floating diffusion FD by the transfer transistor TR.
By reading the signal charge to the floating diffusion FD, the potential of the floating diffusion FD is displaced, and the potential change is transmitted to the amplification gate electrode 15.
Then, the potential supplied to the amplification gate electrode 15 is amplified by the amplification transistor AMP and selectively output to the vertical signal line 9 as a pixel signal by the selection transistor SEL.
Further, by supplying the reset pulse φRST to the reset gate electrode 14, the signal charge read to the floating diffusion FD is reset by the reset transistor RST so as to be the same potential as the potential near the power supply voltage VDD.

  The pixel signal output to the vertical signal line 9 is then output via the column signal processing circuit 5, the horizontal signal line 10, and the output circuit 7 shown in FIG.

In FIG. 2, four pixel transistors are used for the pixel 2, but three pixel transistors other than the selection transistor SEL may be used.
In FIG. 2, four pixel transistors are used for each pixel 2. However, a plurality of pixels 2 may share a pixel transistor other than the transfer transistor TR.

By the way, in a solid-state imaging device (image sensor), in order to improve the conversion efficiency (an index indicating how much voltage one photoelectrically converted electron is converted into by floating diffusion), the following method is used. Can be mentioned.
(1) The junction capacitance in the source region of the floating diffusion and the reset transistor is reduced.
(2) To reduce parasitic capacitance such as fringe capacitance and gate overlap capacitance with circuit elements such as peripheral transistors.
(3) Reducing the capacitance between wirings and improving the modulation degree of the source follower amplifier.

Here, in the CMOS type solid-state imaging device (CMOS image sensor), the floating diffusion FD of the pixel and the parasitic capacitance generated around the pixel will be described with reference to FIGS. 21A and 21B. FIG. 21A shows an equivalent circuit diagram of a pixel of the CMOS solid-state imaging device, and FIG. 21B shows a schematic sectional view of a transistor of the pixel of the CMOS solid-state imaging device.
As shown in FIGS. 21A and 21B, the following parasitic capacitances can be cited as parasitic capacitances that affect the floating diffusion FD.
That is, the parasitic capacitance C1 of the floating diffusion FD and the gate electrode of the transfer gate transistor TR, and the parasitic capacitance C2 of the floating diffusion FD and the gate electrode of the reset transistor RST are included. In addition, floating diffusion and parasitic capacitances C3 and C4 of the source / drain of the amplification transistor AMP can be cited.

This technique reduces the parasitic capacitances C1, C2, C3, and C4 shown in FIGS. 21A and 21B in order to improve the conversion efficiency.
In this embodiment, the parasitic capacitances C1, C2, C3, and C4 shown in FIGS. 21A and 21B are reduced by changing the configuration of the floating diffusion FD and its peripheral transistors from the conventional configuration.

Next, sectional views of main parts of the solid-state imaging device 1 of the present embodiment are shown in FIGS. 3A to 3C.
FIG. 3A shows a cross-sectional view of the amplification transistor AMP and the reset transistor RST of FIG.
FIG. 3B shows a cross-sectional view of the photodiode PD, the transfer transistor TR, and the floating diffusion FD of FIG.
FIG. 3C shows a cross-sectional view of the selection transistor SEL of FIG. 2 and other MOS transistors (for example, transistors in the MOS peripheral circuit section).

As shown in FIG. 3A, the amplification transistor AMP and the reset transistor RST of FIG. 2 are formed in the left and right semiconductor substrates 11 and the amplification gate electrode 14 or the reset gate electrode 15 formed on the gate insulating film 18. Source / drain regions 19.
As shown in FIG. 3B, the transfer transistor TR in FIG. 2 has a transfer gate electrode 13 formed on the gate insulating film 18. A photoelectric conversion unit made of a photodiode PD is formed in the semiconductor substrate 11 on the left side of the transfer gate electrode 13, and a floating diffusion FD is formed in the semiconductor substrate 11 on the right side of the transfer gate electrode 13. . The charges photoelectrically converted by the photodiode PD are transferred to the floating diffusion FD by the transfer gate 13 of the transfer transistor TR.
As shown in FIG. 3C, the selection transistor SEL and other MOS transistors in FIG. 2 are formed in the selection gate electrode 16 or the gate electrode 17 formed on the gate insulating film 18 and in the left and right semiconductor bases 11. Source / drain regions 19.

Examples of the semiconductor substrate 11 include configurations of a single semiconductor substrate, a semiconductor substrate and an epitaxial layer formed thereon, and a semiconductor layer formed on another substrate.
As the semiconductor material of the semiconductor substrate 11, silicon, other semiconductor elements, compound semiconductors, or the like can be used.

In the present embodiment, particularly, as shown in FIGS. 3A and 3B, in the reset transistor, the amplifying transistor, and the transfer transistor, the left and right semiconductor substrates 11 of the gate electrodes 14, 15, and 13 are located below the gate insulating film 18. It becomes the recessed part 11A dug in.
A source / drain region 19, a photodiode PD, and a floating diffusion FD are formed in the recessed portion 11A.
On the other hand, as shown in FIG. 3C, the semiconductor substrate 11 is not dug in the selection transistor and other MOS transistors.

As shown in FIGS. 3A and 3B, the left and right semiconductor substrates 11 of the gate electrodes 14, 15, 13 are recessed portions 11A dug down, so that the gate electrode 13 of the transfer transistor and the floating diffusion FD are formed. A lot of distance can be taken. Further, the distance between the gate electrode 14 and the source region 19 of the reset transistor and the distance between the gate electrode 15 of the amplification transistor and the source / drain region 19 can be increased.
By increasing these distances, it becomes possible to reduce the parasitic capacitance in that portion, so that the conversion efficiency of the solid-state imaging device can be improved.

The configuration of the solid-state imaging device of the present embodiment illustrated in FIGS. 3A to 3C can be manufactured, for example, as described below.
4-8, FIG. A corresponds to FIG. 3A, FIG. B corresponds to FIG. 3B, and FIG. C corresponds to FIG.

First, as shown in FIGS. 4A to 4C, a gate insulating film 18 and an electrode layer (for example, a polycrystalline silicon layer) 31 for forming a gate electrode are sequentially formed on the semiconductor substrate 11.
The steps up to here are the same as the manufacturing steps of a normal CMOS solid-state imaging device.

Next, as shown in FIG. 5A and FIG. 5B, in the reset transistor, amplification transistor, and transfer transistor, the electrode layer 31 is covered with a photoresist 32.
Thereafter, as shown in FIG. 5C, in the selection transistor and other transistors, the electrode layer 31 and the gate insulating film 18 thereunder are patterned to form the gate electrode 16 of the selection transistor and other transistors formed of the electrode layer 31. A gate electrode 17 is formed.

Next, as shown in FIG. 6C, in the selection transistor and other transistors, a photoresist 33 is formed to cover the gate electrodes 16 and 17 and the periphery thereof.
Thereafter, as shown in FIGS. 6A and 6B, in the reset transistor, the amplification transistor, and the transfer transistor, the electrode layer 31 and the gate insulating film 18 thereunder are patterned. As a result, the gate electrodes 14, 15, 13 of the respective transistors, each including the electrode layer 31, are formed.

Subsequently, as shown in FIGS. 7A and 7B, in the reset transistor, the amplifying transistor, and the transfer transistor, the left and right semiconductor substrates 11 of the gate electrodes 14, 15, and 13 are etched. In this etching, the gate electrodes 14, 15 and 13 are also used as etching masks.
Thereby, the recess 11 </ b> A is formed in the semiconductor substrate 11. As shown in FIG. 7C, the selection transistor and other transistors have the same state as that shown in FIG. 6C.

Thereafter, in the selection transistor and other transistors, although not shown, the photoresist 33 covering the gate electrodes 16 and 17 and the periphery thereof is removed.
Next, as shown in FIGS. 8A to 8C, by using the gate electrodes 14, 15, 13, 16, and 17 as a mask, N-type impurities are implanted into the semiconductor substrate 11, thereby forming the source / drain regions 19 of the transistor. And the floating diffusion FD is formed.

Thereafter, an impurity region constituting the photodiode PD is formed in the semiconductor substrate 11 to form the photodiode PD shown in FIG. 3B.
Further, although not shown, a wiring portion composed of a wiring layer and an interlayer insulating layer is formed above the gate electrodes 13 to 17 of the transistor. In addition, a color filter and a microlens are formed on the light incident side.
In this manner, the solid-state imaging device of the present embodiment shown in FIGS. 3A to 3C can be manufactured.

In the manufacturing method described above, the patterning process of the gate electrodes 16 and 17 of the selection transistor and other transistors is performed before the patterning process of the gate electrodes 13, 14, and 15 of the transfer transistor, the reset transistor, and the amplification transistor. It was.
On the other hand, the patterning process of the gate electrodes 13, 14, and 15 of the transfer transistor, the reset transistor, and the amplification transistor can be performed before the patterning process of the gate electrodes 16 and 17 of the selection transistor and the other transistors. is there.
Further, for example, the gate electrode of each transistor may be patterned first, and then a portion where the recess 11A is not formed is covered with a mask, and the recess 11A is formed in the semiconductor substrate 11 by etching.

3 to 8 show cross-sectional views in the width direction of the gate electrode.
In the present embodiment, the floating diffusion FD can be formed in alignment with the active region by defining the longitudinal position of the gate electrode of the mask pattern for forming the recess 11A in the semiconductor substrate 11. become.
The configuration and manufacturing method of the solid-state imaging device in this case will be described in detail below.

FIG. 9A shows a plan view of the vicinity of the floating diffusion when the floating diffusion FD is formed in alignment with the active region in the present embodiment. 9B is a cross-sectional view taken along line BB in FIG. 9A, and FIG. 9C is a cross-sectional view taken along line CC in FIG. 9A.
For comparison, FIG. 20A shows a plan view in the vicinity of the floating diffusion of the conventional configuration, FIG. 20B shows a cross-sectional view taken along line BB in FIG. 20A, and FIG. 20C shows a cross-sectional view taken along CC in FIG. .

In the conventional configuration, it is necessary to prevent the N ⁺ region of the floating diffusion FD from reaching the boundary between the active region and the element isolation region due to misalignment of the mask for ion implantation.
Therefore, as shown in FIG. 20A, the active region 20 is widely formed from the N ⁺ region to the boundary with a misalignment margin x. As a result, as shown in FIGS. 20A and 20C, the floating diffusion N ⁺ region can be formed so as not to cover the element isolation region 21.
However, in the actual manufacturing process, due to thermal diffusion after ion implantation or the like, as indicated by a broken line in FIG. 20A, the N ⁺ region is formed to extend from the initial width w to x ′ on both sides. As a result, the area effective for the capacity is increased by 2 × ′.
In this conventional configuration, as shown in FIGS. 20A and 20B, an N ⁺ region is formed at a distance d from the gate electrode 13 in order to reduce the parasitic capacitance between the floating diffusion and the gate electrode of the transfer transistor. doing.

In the conventional configuration, when the misalignment margin x shown in FIG. 20A is not taken into account, when the misalignment occurs, the element isolation region in which the ion implantation of the floating diffusion is formed by the impurity region having the opposite polarity 21 is also performed.
In this case, the effective floating diffusion area is reduced.

On the other hand, in the configuration shown in FIGS. 9A to 9C, the planar pattern of the active region 20 is the same as the planar pattern of the portion where the recess is formed by etching the semiconductor substrate 11. And the recessed part is formed. Then, an N ⁺ region of the floating diffusion FD is formed at the end of the active region 20 that becomes a concave portion on the gate electrode 13 side.
As a result, as shown in FIG. 9B, the floating diffusion FD is formed separately from the gate electrode 13 below.
As shown in FIG. 9C, in the active region 20, the semiconductor substrate 11 is etched to form a recess, so that the active region 20 and the element isolation region 21 have a step. For this reason, even if the floating diffusion FD is ion-implanted in the element isolation region 21, the effective floating diffusion FD is defined in the active region 20 of the recess. This makes it possible to design with a mask size larger than the conventional one without considering the mask misalignment margin.

FIG. 10A to FIG. 10C are plan views of mask patterns when etching the semiconductor substrate 11 when the effect of misalignment margin is not considered in the configuration of the present embodiment. 10A to 10C are plan views corresponding to the cross-sectional views of FIGS. 3A to 3C.
As shown in FIGS. 10A and 10B, the mask pattern 22 is wider than the width of the active region 20 and the length of the gate electrodes 14, 15 and 13 in the longitudinal direction.
Inside the mask pattern 22, the semiconductor substrate is etched at portions other than the gate electrodes 14, 15, 13 to form recesses.
In this case, with respect to the cross-sectional view shown in FIG. 9C, part of the left and right element isolation regions 21 of the active region 20 (portion in the mask pattern 22) is also etched to form a recess.
As shown in FIG. 10C, the mask pattern 22 is not formed in the portion of the transistor where the semiconductor substrate 11 is not etched.

11A to 11C are plan views of the mask pattern when the semiconductor substrate 11 is etched in the configuration of the present embodiment in consideration of the effect of the misalignment margin. 11A to 11C are plan views corresponding to the cross-sectional views of FIGS. 3A to 3C.
As shown in FIG. 11B, the mask pattern 22 has the same width as the active region 20 in the portion where the floating diffusion is formed.
As shown in FIGS. 11A and 11B, the mask pattern 22 is the same as in FIGS. 10A and 10B in the portion where the semiconductor substrate 11 other than the floating diffusion is etched.
Inside the mask pattern 22, the semiconductor substrate is etched at portions other than the gate electrodes 14, 15, 13 to form recesses.
In this case, in the floating diffusion portion, as in the cross-sectional view shown in FIG. 9C, the left and right element isolation regions 21 of the active region 20 are not etched, and only the active region 20 becomes a recess.
As shown in FIG. 11C, the mask pattern 22 is not formed in the portion of the transistor where the semiconductor substrate 11 is not etched, as in FIG. 10C.

Here, it was estimated how much the parasitic capacitance can be reduced by the configuration of the present embodiment shown in FIGS. 9A to 9C with respect to the conventional configuration shown in FIGS. 20A to 20C.
The capacitance C is obtained from the following equation (1) from the dielectric constant ε, the area S, and the distance d.
C = εS / d (1)
In this embodiment, the depth of digging the semiconductor substrate is the same as the distance d from the gate electrode of the conventional configuration to the N ⁺ region. Then, assuming that the area of the portion serving as the parasitic capacitance with the gate electrode in the conventional configuration is 1, the portion serving as the parasitic capacitance with the gate electrode in the configuration of the present embodiment when the size of x ′ described above is changed. The relative value of the area was obtained by calculation.
Note that the width w of the N ⁺ region shown in FIGS. 9A and 20A was 0.2 μm.

As a result of the calculation, the relative value of the area with respect to each value of x ′ is 0.667 when x ′ = 0.05 μm, 0.5 when x ′ = 0.1 μm, and 0 when x ′ = 0.15 μm. .4.
Therefore, it can be seen that the configuration of the present embodiment to which the present technology is applied reduces the area of the portion serving as the parasitic capacitance and reduces the parasitic capacitance.
It can also be seen that the effect of reducing the parasitic capacitance becomes more significant as x ′ increases.

According to the configuration of the solid-state imaging device of the present embodiment described above, the left and right semiconductor bases 11 of the gate electrodes 14, 15, 13 are recessed portions 11A dug downward. A photodiode PD, a floating diffusion FD, and a source / drain region 19 are formed in the recess 11A.
Thereby, it is possible to increase the distance between the gate electrode 13 of the transfer transistor and the floating diffusion FD. Further, the distance between the gate electrode 14 and the source region 19 of the reset transistor and the distance between the gate electrode 15 of the amplification transistor and the source / drain region 19 can be increased.
By increasing these distances, it becomes possible to reduce the parasitic capacitance in that portion, so that the conversion efficiency of the solid-state imaging device can be improved.

Further, according to the configuration of the present embodiment, since the floating diffusion FD is formed in the recess 11A in which the semiconductor substrate 11 is dug, the parasitic capacitance can be obtained without separating the gate electrode and the floating diffusion FD in the horizontal direction. Can be reduced.
As a result, the parasitic capacitance can be reduced and the conversion efficiency can be improved without increasing the area of the floating diffusion FD, and thus without increasing the pixel size.
Accordingly, it is possible to achieve both the reduction in pixel size and the improvement in conversion efficiency.

Furthermore, as shown in FIGS. 9A to 9C, when the active region 20 and the recess 11A are formed in alignment, it is not necessary to take a misalignment margin between the active region 20 and the floating diffusion FD.
Therefore, the areas of the active region 20 and the floating diffusion FD can be reduced, and the area of the photodiode PD can be increased correspondingly, and the pixel size can be reduced accordingly.

<2. Second Embodiment (Solid-State Imaging Device)>
12A to 12C are cross-sectional views of main parts of the solid-state imaging device according to the second embodiment.
In the present embodiment, as in the first embodiment, the present technology is applied to a CMOS type solid-state imaging device (CMOS image sensor).

In the first embodiment, since the semiconductor substrate 11 in the photodiode PD portion is dug, the semiconductor substrate 11 in the photodiode PD portion is damaged by the dug. The interface state near the surface increases.
Depending on the design conditions such as the pixel size, it is desirable not to dig out the semiconductor substrate 11 of the photodiode PD when the generation of dark current increases due to the increase in the interface state and affects the image quality.

In the present embodiment, as shown in FIG. 12B, the recess 11 </ b> A is not formed in the semiconductor substrate 11 in the portion of the photodiode PD (photoelectric conversion portion). Thereby, it is possible to prevent an increase in the generation of dark current due to the formation of the recess 11A.
Then, as shown in FIGS. 12A to 12C, the configuration other than the photodiode PD is the same as that of the first embodiment shown in FIGS. 3A to 3C. That is, the recess 11A is formed in the semiconductor substrate 11 in the source / drain regions 19 of the reset transistor and the amplifying transistor and the floating diffusion FD, and the recess 11A is not formed in the selection transistor and other transistors.

  Other configurations are the same as those of the first embodiment, and the configuration shown in the plan view of FIG. 1 can be employed.

In this embodiment, as shown in FIG. 12A, the left and right semiconductor bases 11 of the gate electrodes 14 and 15 of the reset transistor and the amplification transistor are recessed 11A that are dug down below the gate insulating film 18. Yes. Further, as shown in FIG. 12B, the semiconductor substrate 11 in the floating diffusion FD portion is a recess 11 </ b> A that is dug below the gate insulating film 18.
A source / drain region 19 and a floating diffusion FD are formed in the recessed portion 11A.
On the other hand, as shown in FIGS. 12B and 12C, the semiconductor substrate 11 is not dug in the photodiode PD, the selection transistor, and other MOS transistors.

As shown in FIGS. 12A and 12B, the left and right semiconductor substrates 11 of the gate electrodes 14 and 15 and the semiconductor substrate 11 in the floating diffusion FD form a recess 11A dug downward. As a result, the distance between the gate electrode 14 and the source region 19 of the reset transistor and the distance between the gate electrode 15 of the amplification transistor and the source / drain region 19 can be increased. In addition, the distance between the gate electrode 13 of the transfer transistor and the floating diffusion FD can be increased.
By increasing these distances, it becomes possible to reduce the parasitic capacitance in that portion, so that the conversion efficiency of the solid-state imaging device can be improved.
Further, since the semiconductor substrate 11 is not dug in the photodiode PD portion, it is possible to prevent an increase in generation of dark current due to the formation of the recess.

The configuration of the solid-state imaging device of the present embodiment shown in FIGS. 12A to 12C can be manufactured, for example, as described below.
13 to 16, FIG. A corresponds to FIG. 12A, FIG. B corresponds to FIG. 12B, and FIG. C corresponds to FIG.

  First, similarly to the steps shown in FIGS. 4A to 4C of the manufacturing method of the first embodiment, the respective steps up to the step of forming the electrode layer 31 for forming the gate electrode are performed.

Next, as shown in FIG. 13A, in the reset transistor and the amplification transistor, the electrode layer 31 is covered with a photoresist 32.
In the transfer transistor, as shown in FIG. 13B, the side where the floating diffusion is formed is covered with the photoresist 32, but the portion where the photodiode is formed surrounded by the broken line is not covered with the photoresist 32.
Thereafter, as shown in FIGS. 13B and 13C, the electrode layer 31 and the gate insulating film 18 thereunder are patterned in the portion where the photodiode is formed and the selection transistor and other transistors. As a result, in the selection transistor and other transistors, the gate electrode 16 of the selection transistor and the gate electrode 17 of the other transistor formed of the electrode layer 31 are formed. Further, the surface of the semiconductor substrate 11 is exposed at the portion where the photodiode is formed.

Next, as shown in FIG. 14B and FIG. 14C, a portion of the photodiode and the transfer transistor where the transfer gate electrode is formed, the gate electrodes 16 and 17 of the selection transistor and other transistors, and the periphery thereof are covered with a photoresist. 33 is formed.
After that, as shown in FIGS. 14A and 14B, the electrode layer 31 and the gate insulating film 18 thereunder are patterned in a portion where the reset transistor, the amplification transistor, and the floating diffusion are formed. As a result, the gate electrodes 14, 15, 13 of the respective transistors, each including the electrode layer 31, are formed.

Subsequently, as shown in FIGS. 15A and 15B, the semiconductor substrate 11 beside the gate electrodes 14, 15, and 13 is etched in a portion where the reset transistor, the amplification transistor, and the floating diffusion are formed. In this etching, the gate electrodes 14, 15 and 13 are also used as etching masks.
Thereby, the recess 11 </ b> A is formed in the semiconductor substrate 11. As shown in FIG. 15C, the selection transistor and other transistors have the same state as that shown in FIG. 14C.

Thereafter, the photoresist 33 covering the gate electrodes 16 and 17 and the periphery thereof is removed from the portion where the photodiode is formed, the selection transistor and other transistors, although not shown.
Next, as shown in FIGS. 16A to 16C, by using the gate electrodes 14, 15, 13, 16, and 17 as a mask, an N-type impurity is implanted into the semiconductor substrate 11, thereby forming a source / drain region 19 of the transistor. And the floating diffusion FD is formed.

Thereafter, an impurity region constituting the photodiode PD is formed in the semiconductor substrate 11, thereby forming the photodiode PD shown in FIG. 12B.
Further, although not shown, a wiring portion composed of a wiring layer and an interlayer insulating layer is formed above the gate electrodes 13 to 17 of the transistor. In addition, a color filter and a microlens are formed on the light incident side.
In this way, the solid-state imaging device of the present embodiment shown in FIGS. 12A to 12C can be manufactured.

In the manufacturing method described above, the patterning process of the gate electrodes 16 and 17 of the selection transistor and other transistors is performed before the patterning process of the gate electrodes 13, 14, and 15 of the transfer transistor, the reset transistor, and the amplification transistor. It was.
On the other hand, the patterning process of the gate electrodes 13, 14, and 15 of the transfer transistor, the reset transistor, and the amplification transistor can be performed before the patterning process of the gate electrodes 16 and 17 of the selection transistor and the other transistors. is there.
Further, for example, the gate electrode of each transistor may be patterned first, and then a portion where the recess 11A is not formed is covered with a mask, and the recess 11A is formed in the semiconductor substrate 11 by etching.

FIG. 17A to FIG. 17C are plan views of mask patterns when etching the semiconductor substrate 11 when the effect of misalignment margin is not considered in the configuration of the present embodiment. 17A to 17C are plan views corresponding to the cross-sectional views of FIGS. 12A to 12C.
As shown in FIGS. 17A and 17B, the mask pattern 22 has a width wider than the length of the gate electrodes 14, 15, 13 in the longitudinal direction. In the case of the present embodiment, since the semiconductor portion is not dug in the photodiode portion, the mask pattern 22 is not formed in the photodiode portion and the gate electrode 13 portion of the transfer transistor.

18A to 18C are plan views of mask patterns when the semiconductor substrate 11 is etched in the configuration of the present embodiment in consideration of the effect of misalignment margin. 18A to 18C are plan views corresponding to the cross-sectional views of FIGS. 12A to 12C.
As shown in FIG. 18B, the mask pattern 22 has the same width as the active region 20 in the portion where the floating diffusion is formed.
As shown in FIG. 18A, the mask pattern 22 is the same as that in FIG. 17A in the portion where the semiconductor substrate 11 other than the floating diffusion is etched. Inside the mask pattern 22, the semiconductor substrate is etched at portions other than the gate electrodes 14 and 15 to form recesses.
In this case, in the floating diffusion portion, as in the cross-sectional view shown in FIG. 9C, the left and right element isolation regions 21 of the active region 20 are not etched, and only the active region 20 becomes a recess.
As shown in FIGS. 18B and 18C, the mask pattern 22 is not formed in the portion where the photodiode is formed or the portion of the transistor where the semiconductor substrate 11 is not etched, as in FIGS. 17B and 17C.

According to the configuration of the solid-state imaging device of the present embodiment described above, the semiconductor substrate 11 on the right side of the transfer gate electrode 13 and the recesses 11A in which the left and right semiconductor substrates 11 of the gate electrodes 14 and 15 are dug down are provided. It has become. A floating diffusion FD and source / drain regions 19 are formed in the recess 11A.
Thereby, it is possible to increase the distance between the gate electrode 13 of the transfer transistor and the floating diffusion FD. Further, the distance between the gate electrode 14 and the source region 19 of the reset transistor and the distance between the gate electrode 15 of the amplification transistor and the source / drain region 19 can be increased.
By increasing these distances, it becomes possible to reduce the parasitic capacitance in that portion, so that the conversion efficiency of the solid-state imaging device can be improved.

Further, according to the configuration of the present embodiment, since the floating diffusion FD is formed in the recess 11A in which the semiconductor substrate 11 is dug, the parasitic capacitance can be obtained without separating the gate electrode and the floating diffusion FD in the horizontal direction. Can be reduced.
As a result, the parasitic capacitance can be reduced and the conversion efficiency can be improved without increasing the area of the floating diffusion FD, and thus without increasing the pixel size.
Accordingly, it is possible to achieve both the reduction in pixel size and the improvement in conversion efficiency.

  Furthermore, in this embodiment, since the recess 11A is not formed in the photodiode PD, the generation of dark current due to the increase in the interface state due to the formation of the recess 11A by etching can be prevented. .

  Furthermore, also in the present embodiment, as in FIGS. 9A to 9C of the first embodiment, when the active region 20 and the recess 11A are formed in alignment, the active region 20 and the floating diffusion are formed. The area of the FD can be reduced. Accordingly, the area of the photodiode PD can be increased and the pixel size can be reduced accordingly.

In each of the above-described embodiments, the present technology is applied to the CMOS type solid-state imaging device.
The present technology can be similarly applied to a CCD solid-state imaging device.
For example, in a CCD solid-state imaging device in which pixels are arranged in a matrix, a floating diffusion is provided at the tip of a horizontal output gate electrode connected to a horizontal transfer register. In a CCD solid-state imaging device in which pixels are arranged in a line, a floating diffusion is provided at the tip of an output gate electrode connected to a transfer register. These horizontal output gate electrode and output gate electrode are gate electrodes that transfer charges to the floating diffusion.
Further, a reset gate electrode and a reset drain are provided in the subsequent stage of the floating diffusion in order to reset the charge of the floating diffusion. Further, the gate electrode of the amplification transistor is electrically connected to the floating diffusion. This amplification transistor constitutes a source follower circuit and outputs a voltage corresponding to the amount of charge accumulated in the floating diffusion.
When applied to a CCD solid-state imaging device, if a floating diffusion portion (portion from the output gate electrode at the previous stage to the reset gate electrode at the subsequent stage) is dug to form a recess and a floating diffusion is formed in the recess Good. Similarly, the semiconductor substrate may be dug to form a recess in the region that becomes the reset drain ahead of the reset gate electrode and the source / drain region of the amplification transistor whose gate is connected to the floating diffusion.

In each of the above-described embodiments, electrons are used as signal carriers. The floating diffusion FD is an N-type region and the element isolation region 21 is a P-type region.
The present technology can be similarly applied to a configuration in which holes are used as signal carriers, the floating diffusion FD is a P-type region, and the element isolation region is an N-type, which are all of a reverse conductivity type. is there.

In the above-described embodiments, the semiconductor substrate is dug to form the recesses in the floating diffusion FD and the left and right source / drain regions of the gate electrodes of the reset transistor and the amplification transistor.
The present technology is not limited to the configuration in which the recess is formed by digging the semiconductor substrate only in all of these portions. It is possible to have a configuration in which a recess is formed in a part of these portions, or to further increase the number of portions in which the recess is formed.
In this technique, at least in the floating diffusion FD (the portion between the first gate electrode that transfers charge to the FD and the second gate electrode that resets the charge on the FD), the semiconductor substrate is dug into the recess. Form. Thereby, in the case of a CMOS type solid-state imaging device, at least the parasitic capacitances of C1 and C2 among the parasitic capacitances C1 to C4 shown in FIGS. 21A and 21B can be reduced.

  In addition, the present technology provides a surface irradiation type structure in which a circuit forming surface for forming circuit elements such as transistors and a light incident surface on which light is incident are both on the same side with respect to a semiconductor substrate, It can be applied to any of the back-illuminated structures.

  The solid-state imaging device according to the present technology can be applied to various electronic devices such as a camera system such as a digital camera and a video camera, a mobile phone having an imaging function, and other devices having an imaging function.

<3. Third Embodiment (Electronic Device)>
FIG. 19 shows a schematic configuration diagram (block diagram) of an electronic apparatus according to the seventh embodiment.
As illustrated in FIG. 19, the electronic device 121 includes a solid-state imaging device 122, an optical system 123, a shutter device 124, a drive circuit 125, and a signal processing circuit 126.

The optical system 123 includes an optical lens and the like, and forms image light (incident light) from the subject on the pixel portion of the solid-state imaging device 122. Thereby, signal charges are accumulated in the solid-state imaging device 122 for a certain period. The optical system 123 may be an optical lens system including a plurality of optical lenses.
As the solid-state imaging device 122, the solid-state imaging device according to the present technology, such as the solid-state imaging device according to each of the embodiments described above, is used.
The shutter device 124 controls a light irradiation period and a light shielding period for the solid-state imaging device 122.
The drive circuit 125 supplies a drive signal for controlling the transfer operation of the solid-state imaging device 122 and the shutter operation of the shutter device 124. Signal transfer of the solid-state imaging device 122 is performed by a drive signal (timing signal) supplied from the drive circuit 125.
The signal processing circuit 126 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory, or is output to a monitor.

  According to the configuration of the electronic device 121 according to the above-described embodiment, the solid-state imaging device 122 can be obtained by using the solid-state imaging device according to the present technology, such as the solid-state imaging device according to each embodiment described above, as the solid-state imaging device 122. In this case, it is possible to reduce the parasitic capacitance and improve the conversion efficiency.

  In the present technology, the configuration of the imaging device is not limited to the configuration illustrated in FIG. 19, and the configuration other than that illustrated in FIG. 19 is used as long as the configuration uses the solid-state imaging device according to the present technology. Is also possible.

In addition, this indication can also take the following structures.
(1) A semiconductor substrate, a photoelectric conversion portion made of a photodiode formed on the semiconductor substrate, a floating diffusion formed on the semiconductor substrate, and a first gate electrode for transferring electric charge to the floating diffusion And a second gate electrode that resets the charge of the floating diffusion, and at least a portion of the floating diffusion, than the semiconductor substrate under the first gate electrode and the second gate electrode, A solid-state imaging device including a recess formed by digging the semiconductor substrate.
(2) The floating diffusion is provided for each pixel, a transfer transistor including the photoelectric conversion unit and the first gate electrode, a reset transistor including the second gate electrode, and a gate electrode connected to the floating diffusion. The solid-state imaging device according to (1), further including an amplified transistor.
(3) The solid-state imaging device according to (2), wherein the recess is formed in the semiconductor substrate in a source / drain region of the reset transistor and the amplification transistor.
(4) The solid-state imaging device according to any one of (1) to (3), wherein in the floating diffusion, the concave portion is formed in alignment with an active region.
(5) In the photoelectric conversion unit, the solid-state imaging device according to any one of (1) to (4), wherein the recess is not formed in the semiconductor substrate.
(6) A method of manufacturing a solid-state imaging device in which a photoelectric conversion unit made of a photodiode and a floating diffusion are formed on a semiconductor substrate, wherein a first gate electrode and a second gate electrode are formed on the semiconductor substrate. Forming a recess in the semiconductor substrate, digging the semiconductor substrate between the first gate electrode and the second gate electrode, and forming the first gate of the semiconductor substrate. A method of manufacturing a solid-state imaging device, comprising: forming the floating diffusion in the recess between the electrode and the second gate electrode; and forming the photoelectric conversion unit on the semiconductor substrate.
(7) A source / drain region of a reset transistor including the second gate electrode and an amplification transistor having a gate electrode connected to the floating diffusion in the step of forming the floating diffusion for each pixel and forming the recess. The manufacturing method of the solid-state imaging device according to (6), wherein a concave portion is simultaneously formed in the semiconductor substrate in the portion to be.
(8) The method for manufacturing a solid-state imaging device according to (6) or (7), wherein the portion where the floating diffusion is formed is formed by aligning the concave portion with an active region.
(9) An electronic apparatus including an optical system, the solid-state imaging device according to any one of (1) to (5), and a signal processing circuit that processes an output signal of the solid-state imaging device.

  The present technology is not limited to the above-described embodiments, and various other configurations can be taken without departing from the gist of the present technology.

1,122 solid-state imaging device, 2 pixels, 3 pixel units, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8 control circuit, 9 vertical signal line, 10 horizontal signal line, 11 semiconductor Substrate, 11A recess, 12 input / output terminal, 13 transfer gate electrode, 14 reset gate electrode, 15 amplification gate electrode, 16 selection gate electrode, 17 gate electrode, 18 gate insulating film, 19 source / drain region, 20 active region, 21 Element isolation region, 22 mask pattern, 31 electrode layer, 32, 33 photoresist, 121 electronic device, 123 optical system, 124 shutter device, 125 drive circuit, 126 signal processing circuit, PD photodiode, FD floating diffusion, TR transfer transistor , RST reset transaction Star, AMP priest's garb transistor, SEL selection transistor, φTR transfer pulse, φRST reset pulse, φSEL selection pulse

Claims (9)

A semiconductor substrate;
A photoelectric conversion portion formed of a photodiode formed on the semiconductor substrate;
A floating diffusion formed on the semiconductor substrate;
A first gate electrode for transferring charge to the floating diffusion;
A second gate electrode that resets the charge of the floating diffusion;
A solid-state imaging device including at least a portion of the floating diffusion and a recess formed by digging the semiconductor substrate rather than the semiconductor substrate below the first gate electrode and the second gate electrode; apparatus.   Amplification in which the floating diffusion is provided for each pixel, the transfer transistor including the photoelectric conversion unit and the first gate electrode, the reset transistor including the second gate electrode, and the gate electrode connected to the floating diffusion The solid-state imaging device according to claim 1, further comprising a transistor.   The solid-state imaging device according to claim 2, wherein the recess is formed in the semiconductor substrate in a source / drain region of the reset transistor and the amplification transistor.   The solid-state imaging device according to claim 1, wherein in the floating diffusion, the concave portion is formed in alignment with an active region.   The solid-state imaging device according to claim 1, wherein the recess is not formed in the semiconductor substrate in the photoelectric conversion unit. A method of manufacturing a solid-state imaging device in which a photoelectric conversion portion made of a photodiode and a floating diffusion are formed on a semiconductor substrate,
Forming a first gate electrode and a second gate electrode on the semiconductor substrate;
Digging the semiconductor substrate between the first gate electrode and the second gate electrode to form a recess in the semiconductor substrate;
Forming the floating diffusion in the recess of the semiconductor substrate between the first gate electrode and the second gate electrode;
A method for manufacturing a solid-state imaging device, comprising: forming the photoelectric conversion unit on the semiconductor substrate. Forming the floating diffusion for each pixel;
In the step of forming the recess, a recess is also formed in the semiconductor substrate at the same time in a portion that becomes a source / drain region of a reset transistor including the second gate electrode and an amplification transistor having a gate electrode connected to the floating diffusion. The manufacturing method of the solid-state imaging device according to claim 6 formed.   The method for manufacturing a solid-state imaging device according to claim 6, wherein in the portion where the floating diffusion is formed, the concave portion is formed in alignment with the active region. Optical system,
A semiconductor substrate, a photoelectric conversion portion made of a photodiode formed on the semiconductor substrate, a floating diffusion formed on the semiconductor substrate, a first gate electrode for transferring charge to the floating diffusion, and The semiconductor substrate including at least a portion of the second gate electrode and the floating diffusion that resets the charge of the floating diffusion, and the semiconductor substrate below the first gate electrode and the second gate electrode. A solid-state imaging device including a recess formed by digging
An electronic apparatus including a signal processing circuit that processes an output signal of the solid-state imaging device.

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