JP2008016542A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of inhibiting reduction in the maximum electric charge which can be stored irrespective of reduction in an area of a photoelectric converter. <P>SOLUTION: The solid-state imaging apparatus includes a photo diode 101 which generates and stores signal charge in response to incident light. The photo diode 101 is constituted of a p-type well 121 formed on an Si substrate 120 serving as an n-type substrate, and a charge storage layer 122 formed on the p-type well 121 and having polarity different from that of the p-type well 121. The charge storage layer 122 is formed of a plurality of horizontal charge storage layers 112 placed at predetermined intervals in the depthwise direction of the Si substrate 120 and extending in a direction approximately parallel to the surface of the Si substrate 120, and a vertical charge storage layer 113 extending in a direction approximately orthogonal to the surface of the Si substrate 120 and connecting the plurality of horizontal charge storage layers 112. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  2. Description of the Related Art Conventionally, a solid-state imaging device that employs an amplification type imaging device that amplifies and outputs an electric signal generated according to incident light is known (see the following publication).

This solid-state imaging device includes a photodiode, a transfer switch for transferring the photoelectric charge to each pixel, a source follower having a floating diffusion portion, a reset switch for resetting the floating diffusion portion, and a selection switch connected to the drain of the source follower. And have. In addition, a drive circuit that drives each switch, a drive signal line, a power supply line, and a vertical output line and a horizontal output line for outputting a signal from each pixel are provided.
Japanese Patent Application Laid-Open No. 11-196331

  In recent years, the size of an image sensor tends to be reduced due to a demand for downsizing of a solid-state imaging device.

  However, when the size of the image sensor is reduced, the area of the light receiving surface is also reduced, so that the maximum charge amount that can be accumulated is reduced.

  The present invention has been made in view of such circumstances, and a problem thereof is to provide a solid-state imaging device capable of suppressing a decrease in the maximum charge amount that can be accumulated despite a decrease in the area of the photoelectric conversion unit. It is.

  In order to solve the above-described problem, the invention described in claim 1 is a solid-state imaging device including a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and the photoelectric conversion unit is formed on a semiconductor substrate. The second conductivity type region is formed in the first conductivity type region and has a polarity different from that of the first conductivity type region, and the second conductivity type region extends in the depth direction of the semiconductor substrate. A plurality of horizontal diffusion portions arranged at predetermined intervals and extending in a direction substantially parallel to the surface of the semiconductor substrate, and a vertical diffusion portion extending in a direction substantially orthogonal to the surface of the semiconductor substrate and connecting the plurality of horizontal diffusion portions It is characterized by having.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the horizontal diffusion portions are arranged to face each other in the depth direction of the semiconductor substrate.

  According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect, the vertical diffusion portion is disposed in the vicinity of the transfer gate electrode formed on the first conductivity type region. To do.

  According to the present invention, it is possible to suppress a decrease in the maximum amount of charge that can be accumulated despite a decrease in the area of the photoelectric conversion unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 1 is a plan view showing the minimum elements of the solid-state imaging device.

  The solid-state imaging device includes a photodiode (light conversion unit) 101, a transfer switch 102, a source follower 103, a reset switch 105, a row selection switch 104, a power supply line Vdd, and a vertical output line 106. This solid-state imaging device is a CMOS (Complementary Metal Oxide Semiconductor) type area sensor.

  The photodiode 101 performs photoelectric conversion.

  The transfer switch 102 transfers the photocharge generated by the photodiode 101 to the floating diffusion portion 103a. The gate electrode of the transfer switch 102 is connected to the transfer terminal ΦTX (n, n + 1) of the vertical scanning circuit 107.

  The source follower 103 has a floating diffusion portion 103a.

  The reset switch 105 resets the floating diffusion unit 103a. The gate of the reset switch 105 is connected to the reset terminal ΦRES (n, n + 1) of the vertical scanning circuit 107.

  The source of the row selection switch 104 is connected to the drain of the source follower 103. The gate electrode of the selection switch 104 is connected to the select terminal ΦSEL (n, n + 1) of the vertical scanning circuit 107.

  During the accumulation of the light amount charge, the transfer switch 102 is in an OFF state, and the charge generated in the photodiode 101 is not transferred to the gate of the source follower 103 constituting the pixel amplifier. Note that the reset switch 105 is turned on before the accumulation is started, and an appropriate voltage is applied to the gate of the source follower 103 to initialize it (dark level).

  When the row selection switch 104 is turned on, a circuit composed of the load current source 108 and the source follower 103 enters an operating state. When the transfer switch 102 is turned on, the charge accumulated in the photodiode 101 is transferred to the gate of the source follower 103.

  Here, the output of the selected row is generated on the vertical output line 106. The output of the selected row is temporarily stored in the signal storage unit 110 via the transfer gates 109a and 109b. The output of the selected row accumulated in the signal accumulation unit 110 is sequentially read out from the output unit V0 by the horizontal scanning circuit 111.

  FIG. 4 is a conceptual diagram showing a cross section taken along line IV-IV in FIG.

  The photodiode 101 is formed in a P-type well (first conductivity type region) 121 formed on a Si substrate (semiconductor substrate) 120 that is an N-type substrate, and in a P-type well 121, and has a polarity different from that of the P-type well 121. A charge storage layer (second conductivity type region) 122.

  The charge storage layer 122 includes three horizontal charge storage layers (horizontal diffusion portions) 112 extending in a direction substantially parallel to the surface of the Si substrate 120 and a vertical charge storage layer (vertical diffusion) connecting the three charge storage layers 112. Part) 113. The three horizontal charge storage layers 112 are arranged to face each other at a predetermined interval in the depth direction of the Si substrate 120 (the vertical direction in the drawing of FIG. 4). The vertical charge storage layer 113 extends in a direction substantially orthogonal to the surface of the Si substrate 120.

  An LOCOS oxide film 125 for element isolation, a polysilicon gate electrode (transfer gate electrode) 126, and the like are formed on the upper surface of the P-type well 121.

  FIG. 3 is a conceptual diagram showing a cross section of a photodiode according to a comparative example.

  The photodiode 501 includes a P-type well 521 formed in an Si substrate 520 which is an N-type substrate, and a charge storage layer 512 formed in the P-type well 521 and having a polarity different from that of the P-type well 521. The charge storage layer 512 extends in a direction substantially parallel to the surface of the Si substrate 520.

  When the capacitance of the charge storage layer is Cj, the depletion layer width of the PN junction is W, and the PN junction area is Aj, the capacitance Cj of the charge storage layer, the depletion layer width W of the PN junction, and the PN junction area Aj There is a relationship.

Cj = Ksε0Aj / W (Formula 1)
Where Ks: dielectric constant of silicon and ε0: vacuum dielectric constant.

  From Equation 1, it can be seen that as the PN junction area Aj increases, the capacitance Cj of the charge storage layer increases and more charges can be stored.

  Therefore, since the PN junction area Aj of the photodiode 101 of this embodiment is larger than that of the comparative example, it can be seen that the photodiode 101 can store more charge than the photodiode 501.

  Next, a method for manufacturing a solid-state imaging device will be described with reference to FIGS.

  5 to 9 are conceptual diagrams showing cross sections of the manufacturing process of the solid-state imaging device.

  First, a P-type well 121 is formed on the surface of an Si substrate 120 which is an N-type substrate (see FIG. 5).

Next, a LOCOS oxide film 125 and a polysilicon gate electrode 126 are formed on the P-type well 121 (see FIG. 6).
Thereafter, the photoresist 130A is patterned by, for example, photolithography, the P-type well 121 is covered using the photoresist 130A and the polysilicon gate electrode 126 as a mask, ³¹ P ⁺ 140 is implanted, and N on the P-type well 121 is formed. A horizontal charge storage layer 112 made of a type diffusion layer is formed. At this time, by changing the acceleration energy of the ions 140, the three horizontal charge storage layers 112 made of an N-type diffusion layer are formed (see FIG. 7). As described above, the three horizontal charge storage layers 112 are opposed to each other at a predetermined interval in the depth direction, and extend in a direction substantially parallel to the surface of the Si substrate 120.

The horizontal charge storage layer 112 is formed, the photoresist 130A is peeled off, the photoresist 130B is patterned, the P-type well 121 is covered with the photoresist 130B and the polysilicon gate electrode 126 as a mask, and ³¹ P ⁺ 140 is formed. Implantation is performed to form a vertical charge storage layer 113 made of an N-type diffusion layer (see FIG. 8). The vertical charge storage layer 113 extends in a direction substantially orthogonal to the surface of the Si substrate 120. Three horizontal charge storage layers 112 are connected by the vertical charge storage layer 113. The charge storage layer 113 is disposed in the vicinity of the polysilicon gate electrode 126.

After the vertical charge storage layer 113 is formed and the photoresist 130B is peeled off, the photoresist 130C is patterned, the P-type well 121 is covered with the photoresist 130C and the polysilicon gate electrode 126 as a mask, and ¹¹ B ⁺ 140 is formed. The depletion prevention layer (P ⁺ region) 128 is formed on the three horizontal charge storage layers 112 (see FIG. 9).

Next, a photoresist (not shown) is patterned, and the P-type well 121 is covered using the photoresist and the polysilicon gate electrode 126 as a mask, and ⁷⁵ As ⁺ 140 is implanted to form a floating diffusion layer. A mold diffusion layer 127 is formed.

  Thereafter, although not shown, a protective film is formed on the surface of the P-type well 121, and a protective film of an electrode pattern for extraction is opened to the outside. Furthermore, wiring is performed through the opening to complete the solid-state imaging device.

  According to this embodiment, the capacity of the charge storage layer 122 can be increased and the amount of stored charge can be increased, so that the decrease in the maximum amount of charge that can be stored despite the area reduction of the photodiode 101 is suppressed. be able to. Further, the horizontal charge storage layer 112 is different only in the position in the depth direction, and the ions 140 can be implanted using the same mask, so that the manufacturing cost can be reduced. Furthermore, since the charge storage layer 122 is disposed in the vicinity of the polysilicon gate electrode 126, charges can be transferred promptly.

FIG. 1 is a plan view of the minimum element of the solid-state imaging device. FIG. 2 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention. FIG. 3 is a conceptual diagram showing a cross section of a photodiode according to a comparative example. FIG. 4 is a conceptual diagram showing a cross section taken along line IV-IV in FIG. FIG. 5 is a conceptual diagram showing a cross section of the manufacturing process of the solid-state imaging device. FIG. 6 is a conceptual diagram showing a cross section of the manufacturing process of the solid-state imaging device. FIG. 7 is a conceptual diagram showing a cross section of the manufacturing process of the solid-state imaging device. FIG. 8 is a conceptual diagram showing a cross section of the manufacturing process of the solid-state imaging device. FIG. 9 is a conceptual diagram showing a cross section of the manufacturing process of the solid-state imaging device.

Explanation of symbols

  101: Photodiode (light conversion unit), 112: Horizontal charge storage layer (horizontal diffusion unit), 113: Vertical charge storage layer (vertical diffusion unit), 120: Si substrate (semiconductor substrate), 121: P-type well (first well) 1 conductivity type region) 122: charge storage layer (second conductivity type region), 126: polysilicon gate electrode (gate electrode).

Claims (3)

In a solid-state imaging device including a photoelectric conversion unit that generates and accumulates signal charges according to incident light,
The photoelectric conversion unit is formed in a first conductivity type region formed on a semiconductor substrate, and has a second conductivity type region having a polarity different from that of the first conductivity type region,
The second conductivity type regions are arranged at a predetermined interval in the depth direction of the semiconductor substrate, and have a plurality of horizontal diffusion portions extending in a direction substantially parallel to the surface of the semiconductor substrate, and substantially orthogonal to the surface of the semiconductor substrate. A solid-state imaging device, wherein the solid-state imaging device has a vertical diffusion portion extending in a direction to connect the plurality of horizontal diffusion portions.   The solid-state imaging device according to claim 1, wherein the horizontal diffusion portions are arranged to face each other in a depth direction of the semiconductor substrate.   3. The solid-state imaging device according to claim 1, wherein the vertical diffusion portion is disposed in the vicinity of a transfer gate electrode formed on the first conductivity type region.

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