JP2012151369A - Solid state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor in which gate breakdown of an amplifier transistor can be reduced even when a voltage applied to a photoelectric conversion film is high.SOLUTION: The solid state image sensor comprises a plurality of pixel unit cells 11 and a vertical signal line 17, where the pixel unit cell 11 has a photoelectric conversion film 13, a pixel electrode 7, a transparent electrode 9 applied with a positive voltage, and an amplifier transistor 5 formed in a silicon substrate 1, having a gate electrode connected with the pixel electrode 7 and outputting a signal voltage corresponding to the potential of the pixel electrode 7, and a reset transistor 6 formed in the silicon substrate 1, having a drain region connected with the pixel electrode 7 and resetting the potential of the gate electrode of the amplifier transistor 5 to a reset voltage. In the silicon substrate 1, a parasitic diode is formed by the drain region of the reset transistor 6, and the breakdown voltage of the parasitic diode is lower than or equal to the gate breakdown voltage of the amplifier transistor 5.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a stacked solid-state imaging device.

  In recent years, a photodiode is provided inside a silicon substrate, a CCD (Charge Coupled Device) or a MOS (Metal Oxide Semiconductor) is used as a scanning circuit, a CCD image sensor (solid-state imaging device) or a MOS that photoelectrically converts incident light and reads an electrical signal The miniaturization of pixel unit cells of a type image sensor is rapidly progressing. About such a pixel unit cell, the cell size of 3 μm □ was exceeded around 2000, and the cell size of 2 μm □ was exceeded in 2007. An image sensor with a cell size of 1.4 μm □ is scheduled to be commercialized in 2010, and if the pixel unit cell is miniaturized at this pace, a cell size of 1 μm □ is required in recent years. .

  On the other hand, in recent years, a multilayer image sensor as disclosed in Patent Documents 1 and 2 has attracted attention. In a stacked image sensor, an image sensor having characteristics that could not be realized with silicon can be obtained by selecting a material other than silicon as the type of photoelectric conversion film to be stacked on a pixel circuit formed on a silicon substrate. . For example, it is conceivable to apply a sensor having a higher sensitivity by selecting a material having a light absorption coefficient higher than that of silicon. If a photoelectric conversion film having sensitivity of far infrared rays that is not sensitive to silicon is laminated, a far infrared sensor capable of detecting the temperature of the subject can be realized.

  In addition, the stacked sensor has high sensitivity and is effective for miniaturization of the pixel unit cell described above.

Japanese Patent Laid-Open No. 55-120182 JP 2008-252004 A

  By the way, the voltage applied to the photoelectric conversion film in the stacked image sensor depends on the type of the photoelectric conversion film, but the chalcogenide film, the antimony trisulfide film and the amorphous silicon film disclosed in Patent Document 1, and recently attracted attention. In the organic photoconductive film shown in Patent Document 2 that has been developed, the voltage is 10V to 100V. Since this voltage is higher than the breakdown voltage (gate breakdown voltage) and power supply voltage of the gate insulating film of the transistor constituting the pixel circuit formed on the silicon substrate, the gate of the amplification transistor is destroyed due to the operating conditions, and the sensor is destroyed. There is a problem of not working. For example, the voltage applied to the photoelectric conversion film exceeds the gate breakdown voltage (4.5 to 5 V), and the gate breakdown of the amplification transistor occurs.

  Therefore, in view of such a problem, an object of the present invention is to provide a solid-state imaging device capable of suppressing gate breakdown of an amplification transistor even when a voltage applied to a photoelectric conversion film is high.

  In order to achieve the above object, a solid-state imaging device according to one aspect of the present invention is provided corresponding to a plurality of pixel unit cells arranged in a two-dimensional manner and a column of the pixel unit cells. A vertical signal line that transmits a signal voltage of the pixel unit cell, the pixel unit cell being formed above a semiconductor substrate, photoelectrically converting incident light, and the semiconductor of the photoelectric conversion film A pixel electrode formed on a surface on the substrate side, a transparent electrode formed on a surface opposite to the pixel electrode of the photoelectric conversion film to which a positive voltage is applied, and a transistor formed in the semiconductor substrate. An amplifying transistor having a gate electrode connected to the pixel electrode and outputting a signal voltage corresponding to the potential of the pixel electrode; and a transistor formed in the semiconductor substrate, wherein the transistor is connected to the pixel electrode. Was A source region connected to the pixel electrode of the reset transistor in the semiconductor substrate, the source region having a source region or a drain region, and a reset transistor for resetting the potential of the gate electrode of the amplification transistor to a reset voltage Alternatively, a parasitic diode is formed by the drain region, and a breakdown voltage of the parasitic diode is lower than a gate breakdown voltage of the amplification transistor.

  Here, the threshold voltage of the reset transistor may be higher than the threshold voltage of the amplification transistor.

  The pixel unit cell further includes an address transistor that is a transistor formed in the semiconductor substrate and outputs a signal voltage from the pixel unit cell to the vertical signal line, and a threshold voltage of the reset transistor. May be higher than a threshold voltage of the address transistor.

  According to this aspect, even when the voltage applied to the photoelectric conversion film is high and strong incident light enters the transparent electrode when the reset transistor is turned off, the parasitic diode is in a breakdown state, and the gate breakdown of the amplification transistor is caused. It can be suppressed.

  The solid-state imaging device further includes a row scanning circuit that applies a reset signal for controlling on / off of the reset transistor to a gate electrode of the reset transistor, and a low level voltage of the reset signal is a break voltage of the parasitic diode. It may be a voltage with a down voltage equal to or lower than the gate breakdown voltage.

  According to this aspect, the gate breakdown of the amplification transistor can be suppressed without adding a new configuration such as a circuit.

  The semiconductor substrate has a breakdown diffusion region having a conductivity type opposite to that of a source region or a drain region connected to a pixel electrode of the reset transistor and forming the parasitic diode, and the breakdown diffusion region is formed. The region may be in contact with a source region or a drain region connected to the pixel electrode of the reset transistor, and may have a higher impurity concentration than the semiconductor substrate.

  According to this aspect, the breakdown voltage of the parasitic diode can be further lowered to improve the gate breakdown protection capability of the amplification transistor.

  The breakdown diffusion region may be formed so as to overlap with a source region or a drain region of the reset transistor.

  According to this aspect, since the breakdown voltage of the parasitic diode can be further reduced, the gate breakdown protection capability can be improved.

  The breakdown diffusion region may be located below the gate electrode of the reset transistor.

  According to this aspect, since the parasitic diode is easily affected by the gate voltage, the breakdown voltage of the parasitic diode can be lowered while reducing the impurity concentration in the breakdown diffusion region and suppressing the increase in noise.

  The breakdown diffusion region may be continuously formed so as to connect the source region and the drain region of the reset transistor.

  According to this aspect, it is possible to realize a sensor having a large dynamic range by increasing the threshold voltage of the reset transistor.

  The reset voltage of the reset transistor may be equal to or lower than the gate breakdown voltage.

  According to this aspect, since the reset voltage is introduced to the gate of the amplification transistor when the reset transistor is on, the gate breakdown of the amplification transistor when the reset transistor is on can be suppressed.

  A solid-state imaging device according to one embodiment of the present invention is provided corresponding to a plurality of pixel unit cells arranged in a two-dimensional manner and a column of the pixel unit cells, and the pixel unit cells of the corresponding column A vertical signal line for transmitting a signal voltage, and the pixel unit cell is formed above the semiconductor substrate, and is formed on a surface of the photoelectric conversion film on the semiconductor substrate side of the photoelectric conversion film that photoelectrically converts incident light. A pixel electrode, a transparent electrode formed on a surface opposite to the pixel electrode of the photoelectric conversion film, to which a positive voltage is applied, and a transistor formed in the semiconductor substrate, the pixel electrode and An amplifying transistor having a connected gate electrode and outputting a signal voltage corresponding to the potential of the pixel electrode; and a transistor formed in the semiconductor substrate, the source region or drain connected to the pixel electrode A reset transistor that resets the potential of the gate electrode of the amplification transistor, and a protection diode that is connected to the gate of the amplification transistor and whose breakdown voltage is equal to or lower than the gate breakdown voltage of the amplification transistor. Features.

  According to this aspect, even when a high voltage is applied to the photoelectric conversion film and strong incident light enters the transparent electrode, the protective diode is turned on and gate breakdown of the amplification transistor is suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, even when the voltage applied to a photoelectric converting film is high, the reliable lamination type image sensor which can suppress gate destruction of an amplification transistor can be provided. As a result, a highly reliable camera that can be used for a long time in a product equipped with this sensor can be provided.

1 is a circuit diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention. 2 is a cross-sectional view illustrating a detailed structure of one pixel unit cell in the solid-state imaging device according to the embodiment. FIG. It is a figure which shows the electric potential in the pixel unit cell (part along the XY line of FIG. 2) concerning the embodiment. 2 is a cross-sectional view of a reset transistor according to the same embodiment. FIG. It is a figure which shows the current-voltage characteristic of the parasitic diode which concerns on the same embodiment. 3 is a flowchart showing a basic imaging operation of the solid-state imaging device according to the embodiment. 10 is a flowchart showing a modification of the basic imaging operation of the solid-state imaging device according to the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 1 of the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 2 of the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 3 of the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 4 of the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 5 of the embodiment. It is a figure which shows the structure of the reset transistor of the solid-state imaging device which concerns on the modification 6 of the embodiment. It is a circuit diagram which shows the structure of the pixel unit cell of the solid-state imaging device which concerns on the 2nd Embodiment of this invention.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

  In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numerical values described below are all exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numerical values. Furthermore, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this.

(First embodiment)
FIG. 1 is a circuit diagram illustrating a configuration of a solid-state imaging device according to the present embodiment.

  This solid-state imaging device is a stacked solid-state imaging device, and is a photosensitive region composed of a plurality of pixel unit cells 11 arranged two-dimensionally, a vertical scanning unit (row scanning circuit) 15, a photoelectric conversion film. Control line 16, vertical signal line (vertical signal line wiring) 17, load section 18, column signal processing section (row signal storage section) 19, horizontal signal readout section (column scanning circuit) 20, power supply wiring (source follower power supply) 21 And an inverting amplifier (feedback amplifier) 23 and a feedback line 24, and a drive circuit unit that sequentially drives the pixel unit cells 11 and extracts signals.

  The pixel unit cell 11 includes an address transistor (row selection transistor) 4, an amplification transistor 5, a reset transistor 6, and a photoelectric conversion film unit 8.

  The photoelectric conversion film unit 8 photoelectrically converts incident light, and generates and accumulates signal charges corresponding to the amount of incident light. The amplification transistor 5 outputs a signal voltage corresponding to the signal charge amount generated by the photoelectric conversion film unit 8. The reset transistor 6 resets (initializes) the potential of the photoelectric conversion film unit 8, in other words, the gate electrode of the amplification transistor 5. The address transistor 4 selectively outputs a signal voltage from the pixel unit cell 11 in a predetermined row to the vertical signal line 17.

  The vertical scanning unit 15 scans the row of the pixel unit cell 11 in the vertical direction (column direction) by applying a row selection signal for controlling on / off of the address transistor 4 to the gate electrode of the address transistor 4, thereby generating a vertical signal line. 17 selects a row of pixel unit cells 11 for outputting a signal voltage. The vertical scanning unit 15 applies a reset signal for controlling on / off of the reset transistor 6 to the gate electrode of the reset transistor 6 to select a row of the pixel unit cells 11 on which the reset operation is performed.

  The photoelectric conversion film control line 16 is commonly connected to all the pixel unit cells 11 and applies the same positive constant voltage to all the photoelectric conversion film units 8.

  The vertical signal lines 17 are provided corresponding to the columns of the pixel unit cells 11 and transmit the signal voltages of the pixel unit cells 11 in the corresponding columns in the column direction (vertical direction).

  The load unit 18 is provided corresponding to each vertical signal line 17 and connected to the corresponding vertical signal line 17. The load unit 18 constitutes a source follower circuit together with the amplification transistor 5.

  The column signal processing unit 19 performs noise suppression signal processing typified by correlated double sampling, AD conversion (analog-digital conversion), and the like. The column signal processing unit 19 is provided corresponding to each vertical signal line 17 and connected to the corresponding vertical signal line 17.

  The horizontal signal reading unit 20 sequentially reads signals from a plurality of column signal processing units 19 arranged in the horizontal direction (row direction) to a horizontal common signal line (not shown).

  The power supply wiring 21 is connected to the drain regions of the amplification transistor 5 and the reset transistor 6, and is wired in the vertical direction (up and down direction in the drawing of FIG. 1) in the arrangement region (imaging region) of the pixel unit cell 11. This is because since the pixel unit cell 11 is addressed for each column, if the drain wiring is wired in the column direction (vertical direction), all the pixel drive currents in one column flow through one wiring, and the voltage drop increases. is there. The power supply wiring 21 applies a source follower power supply voltage in common to the amplification transistors 5 of all the pixel unit cells 11.

  The inverting amplifier 23 is provided corresponding to the column of the pixel unit cells 11. The output of the inverting amplifier 23 is connected to the source region of the reset transistor 6. When the address transistor 4 and the reset transistor 6 are in a conductive state, the output of the address transistor 4 is received and the gate potential of the amplification transistor 5 is constant. The feedback operation is performed so that the feedback voltage (the output voltage of the inverting amplifier 23) becomes equal to the feedback voltage. At this time, the output voltage of the inverting amplifier 23 is 0V or a positive voltage near 0V.

  The feedback line 24 is provided corresponding to the column of the pixel unit cell 11 and feeds back the output signal of the inverting amplifier 23 to the pixel unit cell 11 of the corresponding column.

  In the solid-state imaging device having the above structure, in the pixel unit cell 11 in the row selected by the vertical scanning unit 15, the signal charge photoelectrically converted by the photoelectric conversion film unit 8 is amplified by the amplification transistor 5 and passed through the address transistor 4. It is output to the vertical signal line 17. The output signal is stored as an electrical signal in the column signal processing unit 19 and then selected and output by the horizontal signal reading unit 20. Thereafter, the signal charge in the pixel unit cell 11 that has output the signal is discharged by turning on the reset transistor 6. At this time, the reset transistor 6 generates a large noise called kTC noise, which remains even when the reset transistor 6 is turned off and signal charge accumulation is started. Therefore, in order to suppress the kTC noise, the noise output is inverted and amplified by the inverting amplifier 23 and fed back to the source region of the reset transistor 6 by the feedback line 24.

  FIG. 2 is a cross-sectional view showing a detailed structure of one pixel unit cell 11 in the solid-state imaging device according to the present embodiment.

  The pixel unit cell 11 is formed by sequentially stacking a pixel circuit including three transistors, that is, an address transistor 4, an amplification transistor 5, and a reset transistor 6 formed in a p-type silicon substrate 1 as a semiconductor substrate, on the silicon substrate 1. It has an interlayer insulating film 14, a pixel electrode 7, a photoelectric conversion film 13, and a photoelectric conversion film portion 8 composed of a transparent electrode 9.

  In the pixel unit cell 11, a reset transistor 6 is formed from n-type diffusion layer regions 10 </ b> A and 10 </ b> B formed in the silicon substrate 1 and a gate electrode 3 </ b> A formed on the silicon substrate 1. Similarly, an amplification transistor 5 is formed from n-type diffusion layer regions 10C and 10D formed in the silicon substrate 1 and a gate electrode 3B formed on the silicon substrate 1. Further, an address transistor 4 is formed from n-type diffusion layer regions 10D and 10E formed in the silicon substrate 1 and a gate electrode 3C formed on the silicon substrate 1.

  An element isolation region 12 that electrically isolates the pixel unit cells 11 is formed in the silicon substrate 1 between the pixel unit cells 11.

  The n-type diffusion layer region 10 A functions as the source region of the reset transistor 6, and the n-type diffusion layer region 10 B functions as the drain region of the reset transistor 6. The n-type diffusion layer region 10 </ b> C functions and functions as a drain region of the amplification transistor 5. The n-type diffusion layer region 10D functions as the source region of the amplification transistor 5 and the drain region of the address transistor 4, and the n-type diffusion layer region 10E functions as the source region of the address transistor 4.

For example, the impurity concentration of the silicon substrate 1 is 1 × 10 ¹⁷ cm ⁻³ , and the impurity concentrations of the n-type diffusion layer regions 10A, 10B, 10C, 10D, and 10E are 1 × 10 ²⁰ to 10 ²² cm ⁻³ , The thickness of the gate insulating film below the gate electrodes 3A, 3B, and 3C is 6.5 to 10 nm.

  The photoelectric conversion film 13 is made of amorphous silicon or the like, is formed above the silicon substrate 1, and photoelectrically converts incident light. The pixel electrode 7 is formed on the surface of the photoelectric conversion film 13 on the silicon substrate 1 side, is in contact with the photoelectric conversion film 13, and collects signal charges generated in the photoelectric conversion film 13. The transparent electrode 9 is formed on the surface of the photoelectric conversion film 13 opposite to the surface on the silicon substrate 1 side (pixel electrode 7), and in order to read the signal charge of the photoelectric conversion film 13 to the pixel electrode 7, the photoelectric conversion film A positive constant voltage is applied to the photoelectric conversion film 13 via the control line 16.

  The amplification transistor 5 is a MOS transistor formed below the pixel electrode 7 in the silicon substrate 1, and has a gate electrode 3 </ b> B connected to the pixel electrode 7, and a signal voltage corresponding to the potential of the pixel electrode 7. Output. The reset transistor 6 is a MOS transistor formed below the pixel electrode 7 in the silicon substrate 1, has a drain region connected to the pixel electrode 7, and sets the potential of the gate electrode 3 B of the amplification transistor 5 to the reset voltage. Reset to (Feedback voltage). The address transistor 4 is a MOS transistor formed below the pixel electrode 7 in the silicon substrate 1. The address transistor 4 is provided between the amplification transistor 5 and the vertical signal line 17, and extends from the pixel unit cell 11 to the vertical signal line 17. Output signal voltage. The address transistor 4 is inserted between the source region of the amplification transistor 5 and the vertical signal line 17, but may be inserted between the drain region of the amplification transistor 5 and the power supply wiring 21.

  The pixel electrode 7 is connected to the gate electrode 3B of the amplification transistor 5 and the drain region (n-type diffusion layer region 10B) of the reset transistor 6 through a contact. A pn junction between the n-type diffusion layer region 10B connected to the pixel electrode 7 and the silicon substrate 1 forms a parasitic diode (storage diode) that stores signal charges.

  FIG. 3 is a diagram showing a potential at a portion along line XY in FIG.

  When a positive voltage is applied to the transparent electrode 9 and there is no signal (reset state), the potential of the n-type diffusion layer region 10B, which is a parasitic diode, is approximately 0V. Light incident from above the transparent electrode 9 passes through the transparent electrode 9 and enters the photoelectric conversion film 13 where it is converted into electron-hole pairs. Electrons of the converted electron-hole pairs are transferred to the transparent electrode 9 side and flow to the power supply wiring 21 connected to the transparent electrode 9. On the other hand, the holes are transferred to the n-type diffusion layer region 10B side and accumulated therein. For this reason, the potential of the n-type diffusion layer region 10 </ b> B changes in the + direction, and a voltage is applied between the n-type diffusion layer region 10 </ b> B and the silicon substrate 1.

  The voltage changed to the + side by the holes accumulated in the n-type diffusion layer region 10B is transmitted to the gate electrode 3B of the amplification transistor 5, and the signal amplified by the amplification transistor 5 passes through the address transistor 4 and passes through the pixel unit cell. 11 is output to the outside, that is, the vertical signal line 17. Thereafter, the signal charge accumulated in the n-type diffusion layer region 10B is discharged by turning on the reset transistor 6. At this time, the voltage is reset to a voltage lower than the voltage applied to the transparent electrode 9.

  Here, when strong incident light enters the transparent electrode 9, the potential of the n-type diffusion layer region 10 </ b> B rises and finally becomes substantially the same potential as the voltage applied to the transparent electrode 9. The voltage applied to the transparent electrode 9 is about 10 to 100 V as described above, and is larger than the withstand voltage limit (˜5 V) of the MOS transistor. Therefore, there is a high possibility that the MOS transistor connected to the n-type diffusion layer region 10B, that is, the amplification transistor 5, is destroyed. Specifically, there is a high possibility that the gate insulating film between the gate electrode 3B of the amplification transistor 5 and the silicon substrate 1 is broken. However, since the breakdown voltage of the parasitic diode of the reset transistor 6 formed in the silicon substrate 1 is set to be equal to or lower than the gate breakdown voltage of the amplification transistor 5, the parasitic diode functions as a protection diode, and thus the breakdown is suppressed. be able to. This is realized by setting the value of the low level voltage of the reset signal to 0 V or less, for example, so that the breakdown voltage of the parasitic diode is not more than the gate breakdown voltage of the amplification transistor 5. This will be described in detail below.

  FIG. 4 is a cross-sectional view of the reset transistor 6.

  A feedback voltage is applied from the inverting amplifier 23 to the source region of the reset transistor 6, that is, the n-type diffusion layer region 10A as shown in FIG. A reverse bias voltage is applied between the drain region of the reset transistor 6, that is, the n-type diffusion layer region 10 </ b> B and the silicon substrate 1. When strong incident light enters the transparent electrode 9 and the voltage of the n-type diffusion layer region 10B increases, the parasitic diode breaks down, and a voltage higher than a certain voltage is not applied to the n-type diffusion layer region 10B.

  FIG. 5 is a diagram showing current-voltage characteristics of the parasitic diode. In FIG. 5, the horizontal axis indicates the voltage of the n-type diffusion layer region 10B, and the vertical axis indicates the current flowing between the n-type diffusion layer region 10B and the silicon substrate 1. Graphs A, B, and C show characteristics when the gate voltages of the different reset transistors 6 are different, and the gate voltage of the reset transistor 6 increases in the order of graphs A, B, and C.

  In any of graphs A, B, and C, when the applied voltage of the n-type diffusion layer region 10B is large and exceeds the breakdown voltage 26, the current increases rapidly and no further voltage is applied. In general, this voltage is greater than the gate breakdown voltage 27 of the transistor. The reason is that if this voltage is lowered, the operating range of the transistor is narrowed.

  However, the breakdown voltage 26 depends on the voltage applied to the gate electrode when the gate electrode exists in the vicinity of the pn junction. As shown in FIG. 5, when the gate voltage of the reset transistor 6 decreases, the electric field strength applied to the pn junction of the parasitic diode increases, so that the breakdown voltage 26 decreases. As a result, the breakdown voltage 26 of the parasitic diode becomes the gate breakdown voltage 27 or less (graph A), and the gate breakdown of the amplification transistor 5 electrically connected to the n-type diffusion layer region 10B does not occur.

  Here, when the gate voltage of the reset transistor 6 is low, the gate of the amplification transistor 5 can be protected in this way. However, since a pulse voltage is applied to the reset transistor 6, a low low voltage is applied to the gate electrode 3A of the reset transistor 6. Both a level voltage (eg, 0V) and a high high level voltage (eg, 3.3V) are applied. When a high-level pulse voltage is applied, the breakdown voltage 26 between the n-type diffusion layer region 10B and the silicon substrate 1 exceeds the gate breakdown voltage 27 and has no gate protection function. However, in this case, the reset transistor 6 is on, and the voltage of the n-type diffusion layer region 10B becomes equal to the voltage of the n-type diffusion layer region 10A. Therefore, if the feedback voltage is set to the gate breakdown voltage 27 or less. Destruction does not occur. Accordingly, the reset voltage of the reset transistor 6 is set to be equal to or lower than the gate breakdown voltage, for example, 0V.

  FIG. 6A is a flowchart illustrating a basic imaging operation of the solid-state imaging device according to the present embodiment. In FIG. 6A, SEL1 indicates a row selection signal applied to the pixel unit cell 11 in the first row. RST1 indicates a reset signal applied to the pixel unit cell 11 in the first row. SEL2 and RST2 are the same except that the corresponding rows are different. One horizontal cycle is a period from when the row selection signal becomes valid until the row selection signal of the next row becomes valid (from the rising edge of SEL1 to the rising edge of SEL2), and the pixel unit cells 11 for one row. This is the period required to read the signal voltage from. One vertical cycle is a period required to read out signal voltages from the pixel unit cells 11 in all rows.

  The feedback operation occurs when the row selection signal and the reset signal are enabled at the same time. That is, it occurs when the address transistor 4 and the reset transistor 6 are simultaneously turned on. As shown in FIG. 6A, the vertical scanning unit 15 performs control so that a reset operation (feedback operation) is performed after signal reading from the pixel unit cell 11. Specifically, first, a high level row selection signal is applied to the gate electrode of the address transistor 4, thereby causing the output signal of the amplification transistor 5 to be output to the vertical signal line 17, and then the row selection signal becomes high level. After that, the output of the inverting amplifier 23 is fed back to the pixel electrode 7 by setting the reset signal to a high level after a certain delay.

  By this feedback operation, reset noise generated when the reset transistor 6 resets the signal charge is suppressed, and it is reduced that the reset noise is superimposed on the next signal charge, so that random noise can be suppressed. .

  Note that, as shown in FIG. 6B, the rising edge and the falling edge of the reset pulse of the reset signal may be inclined so that the amplitude of the reset pulse is small. Thereby, generation | occurrence | production of the random noise resulting from a falling edge can be suppressed. Further, since the amplitude of the reset signal is small and the edge is inclined, the resistance value of the reset transistor 6 continuously changes from on to off, not as a simple switch having two states of on and off. It can be operated as a switch.

  As described above, according to the solid-state imaging device of the present embodiment, the pixel unit cell 11 has a function of protecting the gate insulating film of the amplification transistor 5 therein. That is, when the breakdown voltage of the parasitic diode is smaller than the gate breakdown voltage of the amplification transistor 5, the voltage applied to the photoelectric conversion film 13 is high, and strong incident light enters the transparent electrode 9 when the reset transistor 6 is turned off. However, the parasitic diode is in a breakdown state, and the gate breakdown of the amplification transistor 5 is suppressed. Further, since the feedback voltage applied to the reset transistor 6 is smaller than the gate breakdown voltage and the feedback voltage is introduced to the gate of the amplification transistor 5 when the reset transistor 6 is on, the gate of the amplification transistor 5 when the reset transistor 6 is on. Destruction is also suppressed.

(Modification 1)
FIG. 7 is a diagram showing the structure of the reset transistor 6 of the solid-state imaging device according to this modification. FIG. 7A is a cross-sectional view of the reset transistor 6, and FIG. 7B is a top view of the reset transistor 6.

  The solid-state imaging device of this modification is the embodiment in that the pixel unit cell 11 includes a breakdown region 29 for controlling the breakdown voltage and breakdown current of the parasitic diode in the channel region in the silicon substrate 1. Different from the solid-state imaging device of

Breakdown diffusion region 29 has a conductivity type opposite to the drain region (n-type diffusion layer region 10B) connected to pixel electrode 7 of reset transistor 6, that is, the same conductivity type (p-type) as that of silicon substrate 1, and is parasitic. A diode is formed. Breakdown diffusion region 29 is in contact with n-type diffusion layer region 10B, has an impurity concentration higher than that of silicon substrate 1, for example, an impurity concentration of 1 × 10 ¹⁸ cm ^{−3 that} is one digit higher, and further has an impurity concentration lower than that of the drain region. Have Therefore, the threshold voltage of the amplification transistor 5 and the threshold voltage of the address transistor 4 are equal, but the threshold voltage of the reset transistor 6 is higher than the threshold voltages of the amplification transistor 5 and the address transistor 4.

  The breakdown diffusion region 29 is located below the gate electrode 3A of the reset transistor 6 and sandwiched between the drain region (n-type diffusion layer region 10B) and the source region (n-type diffusion layer region 10A) of the reset transistor 6.

  As described above, according to the solid-state imaging device according to this modification, the breakdown diffusion region having a high impurity concentration and a conductivity type opposite to the drain region is in contact with the drain region of the reset transistor 6 forming the parasitic diode. 29 is provided. Therefore, the breakdown voltage of the parasitic diode can be lowered and the gate breakdown protection capability of the amplification transistor 5 can be improved. At this time, the breakdown diffusion region 29 is constituted only by a partial region of the reset transistor 6 and thus does not greatly affect the characteristics of the reset transistor 6.

  Further, according to the solid-state imaging device according to this modification, the breakdown diffusion region 29 is provided below the gate electrode 3A of the reset transistor 6, so that the parasitic diode is affected by the gate voltage and the breakdown voltage is reduced. It becomes easy to fall. Therefore, the breakdown voltage of the parasitic diode can be lowered while reducing the impurity concentration in the breakdown diffusion region and suppressing the increase in noise.

(Modification 2)
FIG. 8 is a diagram showing the structure of the reset transistor 6 of the solid-state imaging device according to this modification. 8A is a cross-sectional view of the reset transistor 6, and FIG. 8B is a top view of the reset transistor 6.

  The solid-state imaging device of this modification includes a breakdown diffusion region 29 in the silicon substrate 1 having the same width as the drain region (n-type diffusion layer region 10B) and source region (n-type diffusion layer region 10A) of the reset transistor 6. This is different from the solid-state imaging device of Modification 1.

  As described above, according to the solid-state imaging device according to the present modification, the gate breakdown protection capability of the amplification transistor 5 can be improved for the same reason as in the first modification.

(Modification 3)
FIG. 9 is a diagram illustrating the structure of the reset transistor 6 of the solid-state imaging device according to this modification. FIG. 9A is a cross-sectional view of the reset transistor 6, and FIG. 9B is a top view of the reset transistor 6.

  The solid-state imaging device according to the present modification has a breakdown diffusion region 29 below the drain region (n-type diffusion layer region 10B) of the reset transistor 6 in the silicon substrate 1, that is, outside the channel region. Different from solid-state imaging device.

  As described above, according to the solid-state imaging device according to the present modification, the gate breakdown protection capability of the amplification transistor 5 can be improved for the same reason as in the first modification.

(Modification 4)
FIG. 10 is a diagram illustrating the structure of the reset transistor 6 of the solid-state imaging device according to this modification. 10A is a cross-sectional view of the reset transistor 6, and FIG. 10B is a top view of the reset transistor 6.

  The solid-state imaging device according to the present modification has breakdown diffusion in the silicon substrate 1 to the left of the drain region (n-type diffusion layer region 10B) of the reset transistor 6 (the side where the source region is not provided), that is, outside the channel region. It differs from the solid-state imaging device of the modification 1 in that the region 29 is provided.

  As described above, according to the solid-state imaging device according to the present modification, the gate breakdown protection capability of the amplification transistor 5 can be improved for the same reason as in the first modification.

(Modification 5)
FIG. 11 is a diagram showing the structure of the reset transistor 6 of the solid-state imaging device according to this modification. 11A is a cross-sectional view of the reset transistor 6, and FIG. 11B is a plan view of the reset transistor 6.

  The solid-state imaging device of this modification is different from the solid-state imaging device of Modification 1 in that the breakdown diffusion region 29 is formed so as to overlap the drain region (n-type diffusion layer region 10B) of the reset transistor 6. Such a configuration is formed, for example, by implanting p-type impurities into the drain region of the reset transistor 6 and the region below the gate electrode 3A in the silicon substrate 1.

  As described above, according to the solid-state imaging device according to the present modification, the breakdown diffusion region 29 is formed so as to protrude from the drain region of the reset transistor 6. Ability can be improved.

(Modification 6)
FIG. 12 is a diagram illustrating the structure of the reset transistor 6 of the solid-state imaging device according to this modification. 12A is a cross-sectional view of the reset transistor 6, and FIG. 12B is a plan view of the reset transistor 6.

  In the solid-state imaging device of this modification, the breakdown diffusion region 29 is continuously formed so as to connect the source region (n-type diffusion layer region 10A) and the drain region (n-type diffusion layer region 10B) of the reset transistor 6. This is different from the solid-state imaging device according to the first modification.

  The voltage applied to the source region of the reset transistor 6 is often set low. The reason for this is that when a signal is accumulated in the drain region of the reset transistor 6 in FIG. 3, the voltage of the drain region shifts in the positive direction. This is because a sensor with a wide dynamic range and a wide dynamic range can be realized. In this case, the reset transistor 6 operates even if the threshold voltage is increased. Therefore, according to the solid-state imaging device according to the present modification, the breakdown diffusion region 29 having a high impurity concentration is formed as a threshold voltage adjusting diffusion layer on the entire surface of the silicon substrate 1 under the gate electrode 3A of the reset transistor 6. A sensor having a large dynamic range can be realized by increasing the threshold voltage of the reset transistor 6.

(Second Embodiment)
FIG. 13 is a circuit diagram illustrating a configuration of the pixel unit cell 11 of the solid-state imaging device according to the present embodiment.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the first embodiment in that a protection transistor 32 is provided inside the pixel unit cell 11.

  The gate electrode and drain region of the protection transistor 32 are connected to the gate electrode of the amplification transistor 5, and the source region of the protection transistor 32 is connected to the protection voltage 33. Since the protection transistor 32 is turned on at a voltage lower than the gate breakdown voltage of the amplification transistor 5, the protection transistor 32 is turned on when the signal increases due to incident light and the gate voltage of the protection transistor 32 increases. As a result, the voltage of the protection voltage source 33 is applied to the gate electrode of the amplification transistor 5, and even if the signal further increases, the voltage does not increase any more and the gate breakdown of the amplification transistor 5 is suppressed.

  As described above, according to the solid-state imaging device of the present embodiment, the pixel unit cell 11 has a function of protecting the gate insulating film of the amplification transistor 5 therein. That is, since the pixel unit cell 11 further includes the protection transistor 32 that is turned on at or below the gate breakdown voltage of the amplification transistor 5, the voltage applied to the photoelectric conversion film 13 is high, and strong incident light enters the transparent electrode 9. However, the protection transistor 32 is turned on, and the gate breakdown of the amplification transistor 5 is suppressed. Further, since the feedback voltage applied to the reset transistor 6 is smaller than the gate breakdown voltage and the feedback voltage is introduced to the gate of the amplification transistor 5 when the reset transistor 6 is on, the gate of the amplification transistor 5 when the reset transistor 6 is on. Destruction is also suppressed.

  Note that the solid-state imaging device according to the present embodiment requires wiring for introducing the protection transistor 32 and the protection voltage 33 as compared with the solid-state imaging device according to the first embodiment. Is effective.

  While the solid-state imaging device of the present invention has been described based on the embodiments, the present invention is not limited to these embodiments. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  For example, in the above embodiment, the conductivity type of the silicon substrate 1 is p-type and each transistor of the pixel circuit is an n-channel type. However, the conductivity type of the silicon substrate 1 is n-type, and Each transistor may be a p-channel type.

  In this case, the sign of the voltage potential is reversed. For example, the source region of the reset transistor 6 is connected to the pixel electrode 7 to function as a storage diode, and the breakdown diffusion region is formed in contact with (overlapping) the source electrode with a conductivity type opposite to that of the source region of the reset transistor 6. Is done.

  In the above embodiments, each transistor constituting the pixel circuit is a MOS transistor. However, the present invention is not limited to this as long as it is a field effect transistor (FET).

  In the above embodiment, the protection transistor 32 is provided in the pixel unit cell 11. However, a protection diode connected to the gate electrode of the amplification transistor 5 and having a breakdown voltage equal to or lower than the gate breakdown voltage of the amplification transistor 5 is provided. It may be provided instead.

  In the above embodiment, a parasitic diode is formed by the drain region of the reset transistor 6 and the silicon substrate 1. However, when a p-type well region is formed in the silicon substrate 1 and the pixel circuit is formed in the well region, a parasitic diode is formed by the drain region and the well region of the reset transistor 6.

  The present invention can be used for a solid-state imaging device, and in particular, for a small-sized image pickup device.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3A, 3B, 3C Gate electrode 4 Address transistor 5 Amplification transistor 6 Reset transistor 7 Pixel electrode 8 Photoelectric conversion film | membrane part 9 Transparent electrode 10A, 10B, 10C, 10D, 10E n-type diffused layer area | region 11 Pixel unit cell 12 Element Separation region 13 Photoelectric conversion film 14 Interlayer insulating film 15 Vertical scanning section 16 Photoelectric conversion film control line 17 Vertical signal line 18 Load section 19 Column signal processing section 20 Horizontal signal readout section 21 Power supply wiring 23 Inverting amplifier 24 Feedback line 26 Breakdown voltage 27 Gate breakdown voltage 29 Breakdown diffusion region 32 Protection transistor 33 Protection voltage source

Claims (10)

A plurality of pixel unit cells arranged two-dimensionally;
A vertical signal line provided corresponding to a column of the pixel unit cell and transmitting a signal voltage of the pixel unit cell of the corresponding column;
The pixel unit cell is:
A photoelectric conversion film formed above the semiconductor substrate for photoelectrically converting incident light;
A pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side;
A transparent electrode formed on the surface of the photoelectric conversion film opposite to the pixel electrode, to which a positive voltage is applied;
An amplifying transistor which is formed in the semiconductor substrate and has a gate electrode connected to the pixel electrode and outputs a signal voltage corresponding to the potential of the pixel electrode;
A transistor formed in the semiconductor substrate, having a source region or a drain region connected to the pixel electrode, and having a reset transistor for resetting the potential of the gate electrode of the amplification transistor to a reset voltage;
In the semiconductor substrate, a parasitic diode is formed by a source region or a drain region connected to the pixel electrode of the reset transistor,
A breakdown voltage of the parasitic diode is equal to or lower than a gate breakdown voltage of the amplification transistor. The solid-state imaging device further includes a row scanning circuit that applies a reset signal for controlling on / off of the reset transistor to the gate electrode of the reset transistor,
The solid-state imaging device according to claim 1, wherein the low-level voltage of the reset signal is a voltage that causes a breakdown voltage of the parasitic diode to be equal to or lower than the gate breakdown voltage. The solid-state imaging device according to claim 1, wherein a threshold voltage of the reset transistor is higher than a threshold voltage of the amplification transistor. The pixel unit cell further includes a transistor formed in the semiconductor substrate, the address unit outputting a signal voltage from the pixel unit cell to the vertical signal line,
The solid-state imaging device according to claim 1, wherein a threshold voltage of the reset transistor is higher than a threshold voltage of the address transistor. The semiconductor substrate has a conductivity type opposite to that of a source region or a drain region connected to a pixel electrode of the reset transistor, and a breakdown diffusion region for forming the parasitic diode is formed.
The solid-state imaging according to claim 1, wherein the breakdown diffusion region is in contact with a source region or a drain region connected to a pixel electrode of the reset transistor and has a higher impurity concentration than the semiconductor substrate. apparatus. The solid-state imaging device according to claim 5, wherein the breakdown diffusion region is formed so as to overlap a source region or a drain region of the reset transistor. The solid-state imaging device according to claim 5, wherein the breakdown diffusion region is located below a gate electrode of the reset transistor. The solid-state imaging device according to claim 7, wherein the breakdown diffusion region is continuously formed so as to connect a source region and a drain region of the reset transistor. The solid-state imaging device according to claim 1, wherein a reset voltage of the reset transistor is equal to or lower than the gate breakdown voltage. A plurality of pixel unit cells arranged two-dimensionally;
A vertical signal line provided corresponding to a column of the pixel unit cell and transmitting a signal voltage of the pixel unit cell of the corresponding column;
The pixel unit cell is:
A photoelectric conversion film formed above the semiconductor substrate for photoelectrically converting incident light;
A pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side;
A transparent electrode formed on the surface of the photoelectric conversion film opposite to the pixel electrode, to which a positive voltage is applied;
An amplifying transistor which is formed in the semiconductor substrate and has a gate electrode connected to the pixel electrode and outputs a signal voltage corresponding to the potential of the pixel electrode;
A transistor formed in the semiconductor substrate, having a source region or a drain region connected to the pixel electrode, and resetting a potential of the gate electrode of the amplification transistor;
A solid-state imaging device, comprising: a protection diode connected to the gate of the amplification transistor and having a breakdown voltage equal to or lower than a gate breakdown voltage of the amplification transistor.

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