JP2008263086A - Photodiode and solid-state imaging element using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an S/N by reducing a dark current that is generated on a silicon surface from flowing into a charge accumulation layer of a photoelectric conversion section. <P>SOLUTION: A photodiode 15 includes an N-type charge accumulation layer 53 formed on a P-type well 52, a P type depletion preventive layer 54 disposed on the charge accumulation layer 53, and an N-type top layer 55 disposed on the depletion preventive layer 54. The photodiode 15 comprises a charge discharging transistor 40 for discharging charges in the top layer 55. The charge discharging transistor 40 is an MOS transistor with the top layer 55 as a source and with a power supply diffusion section 33 to which a power supply voltage is applied as a drain. A gate 41 of the charge discharging transistor 40 is configured so as to be integrally consecutive with a gate of a source follower transistor constituting an amplification transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a photodiode and a solid-state imaging device using the photodiode.

  In recent years, video cameras, electronic still cameras, and the like have been widely used. In these cameras, a CCD type solid-state imaging device or an amplification type solid-state imaging device is used. In the solid-state imaging device, a plurality of pixels each having a photoelectric conversion unit are arranged in a matrix, and a signal charge is generated by the photoelectric conversion unit of each pixel.

  The amplification type solid-state imaging device guides signal charges generated and accumulated in the photoelectric conversion unit of the pixel to an amplification unit provided in the pixel, and outputs a signal amplified by the amplification unit from the pixel. In an amplification type solid-state imaging device, generally, each pixel includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a charge-voltage conversion unit that receives the signal charges and converts the signal charges into a voltage, An amplification unit that outputs a signal corresponding to the potential of the charge-voltage conversion unit, a charge transfer unit that transfers charge from the photoelectric conversion unit to the charge-voltage conversion unit, and a reset unit that resets the potential of the charge-voltage conversion unit have.

  As such an amplification type solid-state imaging device, a solid-state imaging device using a junction field effect transistor (JFET) in an amplification unit (Patent Document 1), or a solid-state imaging device using a MOS transistor in an amplification unit (Patent Document 2). ) Etc. have been proposed. In a solid-state imaging device using a JFET for the amplifying unit, the gate region of the JFET serves as the charge voltage conversion unit. In a solid-state imaging device using a MOS transistor as an amplification unit, a floating diffusion is the charge-voltage conversion unit.

Since dangling bonds exist on the silicon surface, electron-hole pairs are generated. The photodiode forming the photoelectric conversion unit is formed by a PN junction. However, when the depletion layer reaches the surface, charges generated on the silicon surface are accumulated as a dark current in the charge storage layer of the photoelectric conversion unit. In order to prevent this phenomenon, on the silicon surface, a conductive diffusion region opposite to the charge storage layer of the photoelectric conversion unit (if the charge storage layer of the photoelectric conversion unit is N type, a P type diffusion region, a charge storage layer of the photoelectric conversion unit In most cases, an embedded photodiode in which an N-type diffusion region is formed as a depletion prevention layer is used as a photoelectric conversion portion of a pixel (Patent Document 1).
JP-A-11-177076 JP 2002-43557 A

  However, since the charge moves due to diffusion of concentration and thermal energy, there is a component that flows into the charge storage layer of the photoelectric conversion unit as a dark current even if the depletion layer of the photoelectric conversion unit does not reach the silicon surface. Therefore, even if an embedded photodiode is used as a photoelectric conversion unit of a pixel as in the conventional solid-state imaging device described above, a reduction in the SN ratio due to dark current is inevitable.

  In addition to solid-state image sensors, photodiodes are used for light detection, for example, in various measuring devices, but photodiodes for applications other than solid-state image sensors also flow into the charge storage layer of the photoelectric conversion unit. Needless to say, it is preferable to increase the SN ratio by reducing the dark current.

  The present invention has been made in view of such circumstances, and can further reduce the flow of dark current generated on the silicon surface into the charge storage layer of the photoelectric conversion unit, thereby further increasing the SN ratio. It is an object of the present invention to provide a photodiode that can be used and a solid-state imaging device using the same.

  In order to solve the above problems, a photodiode according to a first aspect of the present invention is disposed on a charge accumulation layer of a first conductivity type that accumulates a signal charge generated according to incident light, and the charge accumulation layer. A depletion prevention layer of the second conductivity type, a semiconductor layer of the first conductivity type disposed on the depletion prevention layer, and a charge discharging unit for discharging charges of the semiconductor layer at least for a predetermined period. It is provided.

  The photodiode according to a second aspect of the present invention is the photodiode according to the first aspect, wherein the charge discharging unit is a transistor having the semiconductor layer as one of a source and a drain, and a semiconductor region to which a predetermined potential is applied. A transistor which is the other of the source and the drain is included.

  The photodiode according to a third aspect of the present invention is the photodiode according to the first aspect, wherein the charge discharging unit is a semiconductor region of the first conductivity type to which a predetermined potential is applied, and is continuous with the semiconductor layer. It is an area.

  A solid-state imaging device according to a fourth aspect of the present invention is a solid-state imaging device including a plurality of pixels each having a photoelectric conversion unit that generates and accumulates charges according to incident light, and the photoelectric conversion unit is the first photoelectric conversion unit. Or a photodiode according to any one of the third to third aspects.

  A solid-state imaging device according to a fifth aspect of the present invention includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a charge-voltage conversion unit that receives the signal charges and converts the signal charges into a voltage, the charge An amplification transistor that outputs a signal according to the potential of the voltage conversion unit; a charge transfer unit that transfers charge from the photoelectric conversion unit to the charge voltage conversion unit; and a reset transistor that resets the potential of the charge voltage conversion unit A solid-state imaging device including a plurality of pixels, wherein the photoelectric conversion unit is a photodiode according to the first aspect.

  The solid-state imaging device according to a sixth aspect of the present invention is the solid-state imaging device according to the fifth aspect, wherein the charge discharging unit is a transistor having the semiconductor layer as one of a source and a drain, and is a source or drain of the amplification transistor. It includes a transistor having a semiconductor region to which a predetermined potential is applied as the other of the source and the drain, and the gate of the transistor in the charge discharging portion is electrically connected to the gate of the amplification transistor.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to the fifth aspect, wherein the charge discharging unit is a transistor having the semiconductor layer as one of a source and a drain, and serves as a source or a drain of the reset transistor. It includes a transistor having a semiconductor region to which a predetermined potential is applied as the other of the source and the drain, and the gate of the transistor in the charge discharging portion is electrically connected to the gate of the reset transistor.

  The solid-state imaging device according to an eighth aspect of the present invention is the solid-state imaging device according to the fifth aspect, wherein the charge discharging unit is a semiconductor region of the first conductivity type to which a predetermined potential is applied, and is continuous with the semiconductor layer. It is a semiconductor region.

  According to the present invention, it is possible to further reduce the dark current component generated through the interface state of the silicon surface from flowing into the charge storage layer of the photoelectric conversion unit, and thereby to further increase the S / N ratio. A diode and a solid-state imaging device using the diode can be provided.

  Hereinafter, a photodiode according to the present invention and a solid-state imaging device using the same will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic configuration diagram showing a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 is configured as a CMOS type solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device 1 includes a vertical scanning circuit 2, a horizontal scanning circuit 3, and a plurality of unit pixels 4 arranged in a two-dimensional manner, like a general CMOS solid-state imaging device. And a read circuit 5 including a known CDS circuit and the like, and an output amplifier 6. An electric signal output from a photodiode 15 (not shown in FIG. 1; see FIG. 2 described later) of each pixel 4 is taken out by the vertical scanning circuit 2 to the reading circuit 5 in units of rows, and is output by the horizontal scanning circuit 3 in units of columns. An image signal is output to the output terminal 7 via the output amplifier 6. Thus, the vertical scanning circuit 2 and the horizontal scanning circuit 3 constitute a circuit for driving the pixel 4. A region where the pixels 4 are two-dimensionally arranged is a pixel region 10. In the solid-state imaging device 1, the vertical scanning circuit 2, the horizontal scanning circuit 3, the readout circuit 5, and the output amplifier 6 constitute a peripheral circuit. The area where the peripheral circuit is arranged is the peripheral circuit area. The peripheral circuit area is arranged around the pixel area 10.

  FIG. 2 is a circuit diagram showing the unit pixel 4 in FIG. As shown in FIG. 2, each pixel 4 includes a selection transistor 11, an amplification transistor 12, a reset transistor 13, a transfer transistor 14, and a photo-electric conversion unit that generates and accumulates signal charges according to incident light. It has a diode 15 and a floating diffusion 16 as a charge-voltage converter that receives the signal charge and converts the signal charge into a voltage. The amplification transistor 12 outputs a signal corresponding to the potential of the floating diffusion 16, and is a source follower transistor in the present embodiment. The transfer transistor 14 transfers charges from the photodiode 15 to the floating diffusion 16. The reset transistor 13 resets the potential of the floating diffusion 16. In FIG. 2, VDD is a power supply. In FIG. 2, illustration of a charge discharging transistor 40 described later is omitted.

  As shown in FIGS. 1 and 2, the gate of the selection transistor 11 of the pixel 4 is commonly connected to the selection line 20 for each row. The gate of the reset transistor 13 of the pixel 4 is commonly connected to the reset line 21 for each row. The gate of the transfer transistor 14 of the pixel 4 is commonly connected to the transfer line 22 for each row. The source of the selection transistor 11 of the pixel 4 is commonly connected to the vertical signal line 23 for each column. The selection line 20, the reset line 21 and the transfer line 22 are connected to the vertical scanning circuit 2. The vertical signal line 23 is connected to the readout circuit 5.

  FIG. 3 is a schematic plan view schematically showing the unit pixel 4 in FIG. FIG. 4 is a schematic cross-sectional view along the line A-A ′ in FIG. 3. In FIG. 3 and FIG. 4, some wiring layers and the like are omitted. In practice, a color filter and a microlens are arranged above the photodiode 15, but are omitted here.

  In FIG. 3, reference numeral 30 denotes an active region (a region where the field oxide film 56 is not formed). Reference numerals 31 to 33 denote N-type impurity diffusion regions formed in a P-type well 52 (see FIG. 4) formed on the N-type silicon substrate 51. The floating diffusion 16 is also an N-type impurity diffusion region formed in the P-type well 52. Instead of the P-type well 52, a P-type epitaxial growth layer may be formed. Further, the diffusion region (semiconductor region) 33 is a power supply diffusion portion to which a power supply voltage VDD as a predetermined potential is applied by a wiring (not shown). Reference numerals 34 to 37 denote gates (electrodes) of the transistors made of polysilicon.

  As shown in FIG. 4, the photodiode 15 has an N-type charge storage layer 53 formed in a P-type well 52, and a depletion prevention layer 54 made of a high-concentration P-type layer on the substrate surface side of the charge storage layer 53. And a surface layer (semiconductor layer) 55 made of an N-type layer is added to the substrate surface side of the depletion preventing layer 54. Although not shown in FIG. 3, the depletion prevention layer 54 is formed so as to cover the charge storage layer 53. FIG. 5 is a diagram showing potentials at respective depth positions in the region of the photodiode 15 of the solid-state imaging device 1 according to the present embodiment. The photodiode 15 photoelectrically converts incident light and accumulates the generated charges in the charge accumulation layer 53. The charges accumulated in the charge accumulation layer 53 of the photodiode 15 are transferred to the floating diffusion 16 when the transfer transistor 14 is turned on.

  In the present embodiment, as shown in FIGS. 3 and 4, the photodiode 15 is provided with a charge discharging transistor 40 as a charge discharging unit that discharges the charge of the surface layer 55. The charge discharging transistor 40 is a MOS transistor having the surface layer 55 as a source and the power supply diffusion portion 33 as a drain. The gate 41 of the charge discharging transistor 40 is made of polysilicon and is continuously formed integrally with the gate 36 of the amplification transistor 12. As a result, the gate 41 of the charge discharging transistor 40 is electrically connected to the gate 36 of the amplification transistor 12. The amplification transistor 12 is a source follower transistor and always operates in the saturation region. Accordingly, the charge discharging transistor 40 is also configured to always operate in the saturation region. Therefore, the charge discharging transistor 40 is always in the on state, and the charge on the surface layer 55 is discharged to the power supply diffusion portion 33.

  The transfer transistor 14 is a MOS transistor having the charge storage layer 53 of the photodiode 15 as a source and the floating diffusion 16 as a drain. The transfer transistor 14 is driven by a drive signal applied to its gate 34.

  The amplification transistor 12 is a MOS transistor having the power source diffusion portion 33 as a drain and the diffusion region 32 as a source. The gate 36 of the amplification transistor 12 is electrically connected to the floating diffusion 16 by a wiring 45. The amplification transistor 12 outputs an electric signal corresponding to the voltage of the gate 36. Therefore, the amplification transistor 12 outputs an electrical signal corresponding to the amount of charge generated and accumulated by the photodiode 15.

  The selection transistor 11 is a MOS transistor having the diffusion region 32 as a drain and the diffusion region 31 as a source. When the selection transistor 11 is turned on, the output of the amplification transistor 12 is output to the vertical signal line 23. That is, the amplifying transistor 12 and the selection transistor 11 can be read by the source follower.

  The reset transistor 13 is a MOS transistor having the power diffusion unit 33 as a drain and the floating diffusion 16 as a source. The reset transistor 13 resets the electric charge accumulated in the floating diffusion 16 by being turned on.

  In FIG. 4, 56 is a field oxide film formed by LOCOS, 57 is a high concentration P-type element isolation region, and 58 is an oxide film. Although not shown in the drawing, an interlayer insulating film, wiring, and the like are formed on the field oxide film 56 and the oxide film 58, and further, a color filter, a microlens, and the like are provided thereon as necessary. .

  FIG. 6 is a timing chart showing an example of the operation of the solid-state imaging device 1 according to the present embodiment. Since the solid-state imaging device 1 according to the present embodiment is driven in the same manner as a general CMOS solid-state imaging device as shown in FIG. 6, detailed description thereof is omitted. In FIG. 6, only the nth row is shown. In FIG. 6, the accumulation period is a period during which a mechanical shutter (not shown) is open. The readout circuit 5 reads out the dark level in period 1 (circled number 1) in FIG. 6, and reads out the level in which the dark level is superimposed on the true optical signal level in period 2 (circled number 2) in FIG. . Then, the readout circuit 5 performs correlated double sampling processing for obtaining a true optical signal level by taking the difference between these two levels.

  In order to facilitate understanding of the ON period of the charge discharging transistor 40 (that is, the period during which the charge of the surface layer 55 is discharged), FIG. 6 shows the potential of the floating diffusion (FD) 16 (= source follower). The gate potential of the transistor (amplification transistor) 12 = the gate potential of the charge discharging transistor 40 is also shown. The charge discharging transistors 40 in each row are designed to operate in a saturated state even during the period 2 (circled number 2), and are always on.

  In the present embodiment, as described above, in the photodiode 15, the surface layer 55 is disposed on the substrate surface side of the depletion preventing layer 54. The photodiode 15 is provided with a charge discharging transistor 40. As described above, the charge discharging transistor 40 is always on. Therefore, the surface layer 55 and the power supply diffusion portion 33 are always in conduction, and the surface layer 55 is in a depleted state. Therefore, as shown in FIG. 5, the potential of the surface layer 55 becomes higher than the potential of the depletion preventing layer 54 that is the P-type region below the surface layer 55. Therefore, the dark current component generated through the interface state on the silicon surface is attracted to the surface layer 55. By such an effect, it is possible to prevent dark current from being mixed with signal charges. Furthermore, since the charges sucked to the surface layer 55 are discharged to the power source diffusion portion 33 having a higher potential, the surface layer 55 does not overflow with dark current components.

  As described above, according to the present embodiment, the dark current generated on the silicon surface is discharged to the power supply diffusion portion 33 without being stored in the charge storage layer 53, so that a high SN ratio can be obtained. .

  Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 1 according to the present embodiment will be described with reference to FIGS. This comparative example corresponds to a conventional solid-state imaging device. FIG. 7 is a schematic plan view schematically showing a unit pixel of the solid-state imaging device according to this comparative example, and corresponds to FIG. FIG. 8 is a schematic cross-sectional view along the line B-B ′ in FIG. 7 and corresponds to FIG. 4. FIG. 9 is a diagram showing potentials at respective depth positions in the region of the photodiode 15 of the solid-state imaging device according to this comparative example, and corresponds to FIG. 7 to 9, the same or corresponding elements as those in FIGS. 3 to 5 are denoted by the same reference numerals, and redundant description thereof is omitted.

  This comparative example is different from the present embodiment only in the points described below. In the present embodiment, the surface layer 55 is arranged on the substrate surface side of the depletion preventing layer 54 in the photodiode 15, whereas in this comparative example, the surface layer 55 is not formed in the photodiode 15 and is depleted. An anti-oxidation layer 54 appears on the silicon surface. That is, the photodiode 15 in this comparative example is configured as a normal embedded photodiode. Accordingly, in this comparative example, the charge discharging transistor 40 provided in the present embodiment is removed, and the gate electrode 41 of the charge discharging transistor 40 and the active region serving as the discharge path are removed.

  Therefore, in this comparative example, the potential distribution on the silicon surface side is as shown in FIG. For this reason, the dark current component generated through the interface state of the silicon surface flows into the charge storage layer 53, the dark current is mixed with the signal charge, and the SN ratio is lowered.

  On the other hand, in the present embodiment, as described above, the surface layer 55 and the charge discharging transistor 40 can prevent the dark current from being mixed with the signal charge, and a high SN ratio can be obtained. is there.

  [Second Embodiment]

  FIG. 10 is a schematic plan view schematically showing a unit pixel of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. FIG. 11 is a schematic cross-sectional view taken along line C-C ′ in FIG. 10 and corresponds to FIG. 4. 10 and 11, elements that are the same as or correspond to those in FIGS. 3 and 4 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the first embodiment only in the points described below. In the present embodiment, instead of the charge discharging transistor 40 provided in the first embodiment, a charge discharging transistor 60 is provided as a charge discharging portion for discharging the charge of the surface layer 55. . Similarly to the charge discharging transistor 40, the charge discharging transistor 60 is also a MOS transistor having the surface layer 55 as a source and the power source diffusion portion 33 as a drain. However, while the gate 41 of the charge discharging transistor 40 is integrally formed continuously with the gate 36 of the amplification transistor 12, the gate 61 of the charge discharging transistor 60 is separated from the gate 36 of the amplification transistor 12. The reset transistor 13 is continuously formed integrally with the gate 37. As a result, the gate 61 of the charge discharging transistor 60 is electrically connected to the gate 37 of the reset transistor 13. Therefore, the charge discharging transistor 60 is turned on / off simultaneously with the reset transistor 13.

  The solid-state imaging device according to the present embodiment is also driven in the same manner as a general CMOS type solid-state imaging device, as shown in FIG. 6, similarly to the solid-state imaging device 1 according to the first embodiment. As can be seen from FIG. 6, the charge discharging transistors 60 in each row are in the on state during most of the period excluding the reading period of the row.

  Also in the present embodiment, as in the first embodiment, dark current generated on the silicon surface is discharged to the power supply diffusion portion 33 without being stored in the charge storage layer 53, and thus has a high SN ratio. Can be obtained.

  [Third Embodiment]

  FIG. 12 is a schematic plan view schematically showing a unit pixel of the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. FIG. 13 is a schematic cross-sectional view taken along line D-D ′ in FIG. 12 and corresponds to FIG. 4. 12 and 13, elements that are the same as or correspond to those in FIGS. 3 and 4 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the first embodiment only in the points described below. In the present embodiment, the charge discharging transistor 40 provided in the first embodiment is removed, and the gate electrode 41 of the charge discharging transistor 40 is removed. In the present embodiment, as shown in FIGS. 12 and 13, a part of the surface layer 55 is extended so as to reach the power supply diffusion portion 33. Thus, in the present embodiment, the power supply diffusion portion 33 is continuously connected to the surface layer 55, and the power supply diffusion portion 33 serves as a charge discharge portion that always discharges the charge of the surface layer 55.

  Also in the present embodiment, as in the first embodiment, dark current generated on the silicon surface is discharged to the power supply diffusion portion 33 without being stored in the charge storage layer 53, and thus has a high SN ratio. Can be obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, the conductivity type of each semiconductor layer or the like may be the opposite conductivity type from the example described above.

  In addition, each of the above embodiments is an example in which the photodiode according to the present invention is used in a solid-state imaging device. However, the photodiode according to the present invention is also used in applications other than the solid-state imaging device, for example, various measuring apparatuses. be able to.

  Further, the present invention can also be applied to a solid-state imaging device using a junction field effect transistor in the amplifying unit as disclosed in Patent Document 1. The present invention can also be applied to a CCD type solid-state imaging device.

1 is a schematic configuration diagram illustrating a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows the unit pixel in FIG. FIG. 2 is a schematic plan view schematically showing a unit pixel in FIG. 1. FIG. 4 is a schematic cross-sectional view along the line A-A ′ in FIG. 3. It is a figure which shows the electric potential of each depth position in the area | region of the photodiode of the solid-state image sensor by the 1st Embodiment of this invention. It is a timing chart which shows an example of operation | movement of the solid-state image sensor by the 1st Embodiment of this invention. It is a schematic plan view which shows typically the unit pixel of the solid-state image sensor by a comparative example. FIG. 8 is a schematic sectional view taken along line B-B ′ in FIG. 7. It is a figure which shows the electric potential of each depth position in the area | region of the photodiode of the solid-state image sensor by the comparative example shown in FIG. It is a schematic plan view which shows typically the unit pixel of the solid-state image sensor by the 2nd Embodiment of this invention. It is a schematic sectional drawing in alignment with the C-C 'line in FIG. It is a schematic plan view which shows typically the unit pixel of the solid-state image sensor by the 3rd Embodiment of this invention. FIG. 13 is a schematic cross-sectional view along the line D-D ′ in FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 4 Unit pixel 12 Amplification transistor 13 Reset transistor 14 Transfer transistor 15 Photodiode 16 Floating diffusion 33 Power supply diffusion part 40,60 Charge discharge transistor 53 Charge storage layer 54 Depletion prevention layer 55 Surface layer

Claims (8)

A charge storage layer of a first conductivity type that stores signal charges generated in response to incident light;
A depletion preventing layer of a second conductivity type disposed on the charge storage layer;
A semiconductor layer of the first conductivity type disposed on the depletion prevention layer;
A charge discharging unit for discharging charges of the semiconductor layer at least for a predetermined period;
A photodiode characterized by comprising:   2. The charge discharging unit includes a transistor having the semiconductor layer as one of a source and a drain, and a transistor having a semiconductor region to which a predetermined potential is applied as the other of the source and the drain. The photodiode described.   2. The photodiode according to claim 1, wherein the charge discharging unit is a semiconductor region of the first conductivity type to which a predetermined potential is applied and is continuous with the semiconductor layer.   4. A solid-state imaging device including a plurality of pixels each having a photoelectric conversion unit that generates and accumulates charges according to incident light, wherein the photoelectric conversion unit is the photodiode according to claim 1. A solid-state imaging device characterized by the above. A photoelectric conversion unit that generates and accumulates signal charge according to incident light, a charge-voltage conversion unit that receives the signal charge and converts the signal charge into voltage, and an amplifier that outputs a signal according to the potential of the charge-voltage conversion unit A solid-state imaging device comprising a plurality of transistors, a pixel having a charge transfer unit that transfers charges from the photoelectric conversion unit to the charge-voltage conversion unit, and a reset transistor that resets the potential of the charge-voltage conversion unit,
The solid-state imaging device, wherein the photoelectric conversion unit is a photodiode according to claim 1. The charge discharging unit is a transistor having the semiconductor layer as one of a source and a drain, and a transistor having a semiconductor region that is a source or a drain of the amplification transistor and a predetermined potential is applied to the other as a source and a drain. Including
The solid-state imaging device according to claim 5, wherein the gate of the transistor of the charge discharging unit is electrically connected to the gate of the amplification transistor. The charge discharging unit is a transistor having the semiconductor layer as one of a source and a drain, and a transistor having a semiconductor region that is a source or a drain of the reset transistor and a predetermined potential is applied to the other as a source and a drain. Including
The solid-state imaging device according to claim 5, wherein a gate of the transistor of the charge discharging unit is electrically connected to a gate of the reset transistor.   The solid-state imaging device according to claim 5, wherein the charge discharging unit is a semiconductor region of the first conductivity type to which a predetermined potential is applied and is continuous with the semiconductor layer.

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