JP2009071310A - Image sensor, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image sensor and a manufacturing method thereof such that the sensitivity of the image sensor can be improved by joining a crystalline substrate where a photodiode is formed to a substrate where a circuit including lower interconnection is formed and improving dark characteristics. <P>SOLUTION: The manufacturing method of the image sensor includes the stages of: preparing a first substrate 100 where interconnection and a readout circuit are formed; forming the photodiode including a first impurity region 71 and a second impurity region in a crystalline region; and forming a first contact 81 and a second contact 82 which penetrate the photodiode 70 to connect with the interconnection and are formed apart from each other, the first contact 81 being in contact with the first impurity region 71 and the second contact 82 being in contact with the second impurity region 72. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image sensor and a manufacturing method thereof.

  Generally, an image sensor is roughly divided into a charge coupled device and a CMOS image sensor as a semiconductor device that converts an optical image into an electrical signal.

  In the conventional technique, a photodiode is formed on a substrate by an ion implantation method. However, with the aim of increasing the number of pixels without increasing the chip size, the image quality tends to deteriorate due to the reduction in the photosensitive area due to the decrease in the size of the photodiode. Yes.

  Also, the stacking height is not reduced as much as the area of the light receiving portion is reduced, and the number of photons incident on the light receiving portion tends to decrease due to a light diffraction phenomenon called an Airy disk.

  As an alternative to solve this, a photodiode is vapor-deposited with amorphous silicon, or a readout circuit is formed on a silicon substrate by a method such as wafer-to-wafer bonding, Attempts have been made to form the photodiode on the readout circuit (hereinafter referred to as “three-dimensional image sensor”). The photodiode and the readout circuit are connected through wiring.

  According to the prior art, since both the source and drain at both ends of the transfer transistor are doped with a high concentration of N-type, there is a problem that a charge sharing phenomenon occurs. When the charge sharing phenomenon occurs, the sensitivity of the output image may decrease, and an image error may occur.

  In addition, according to the prior art, the photo charge cannot be smoothly moved between the photodiode and the readout circuit, dark current is generated, saturation and sensitivity are reduced. It has occurred.

  The present invention relates to an image sensor capable of improving the sensitivity of an image sensor by improving a dark characteristic by bonding a crystalline substrate on which a photodiode is formed to a substrate on which a circuit including a lower wiring is formed. And a method for manufacturing the same.

  According to an aspect of the present invention, there is provided a method of manufacturing an image sensor, comprising: preparing a first substrate on which wirings and a readout circuit are formed; Forming a plurality of first contacts and second contacts formed through the photodiode and connected to the wiring and spaced apart from each other. The first contact may be in contact with the first impurity region, and the second contact may be in contact with the second impurity region.

  An image sensor according to an aspect of the present invention includes a semiconductor substrate on which wiring and readout circuits are formed, and a photo formed on the semiconductor substrate and including a first impurity region and a second impurity region in a crystalline region. A plurality of first contacts and second contacts that are connected to the wiring through the photodiode and spaced apart from each other; the first contact being in contact with the first impurity region; The contact includes contacting the second impurity region.

  The image sensor and the manufacturing method thereof according to the present invention improve the dark characteristics by bonding the crystalline substrate on which the photodiode is formed to the substrate on which the circuit including the lower wiring is formed, thereby improving the sensitivity of the image sensor. Can be improved.

(First embodiment)
Hereinafter, an image sensor and a manufacturing method thereof according to embodiments will be described in detail with reference to the accompanying drawings.

  The present invention is not limited to a CMOS image sensor, but can be applied to an image sensor that requires a photodiode.

  5a and 5b are cross-sectional views of the image sensor according to the first embodiment.

  As shown in FIGS. 5a and 5b, the image sensor according to the first embodiment includes a first circuit layer 20, a metal wiring layer 30, a photodiode 70, and first and second contacts 81 and 82 formed thereon. A substrate 100 is included.

  FIG. 5 a shows a side sectional view of the first substrate 100 including the circuit layer 20, the metal wiring layer 30 and the photodiode 70, and FIG. 5 b shows the circuit layer 20 and the metal wiring layer 30. It is a detailed view regarding the 1st board | substrate 100 in which the wiring 150 was formed.

  The circuit layer 20 includes a circuit including a readout circuit 120, and the metal wiring layer 30 includes a wiring 150 connected to the circuit.

  The photodiode 70 is formed on a crystalline substrate and may be formed of first, second and third impurity regions 71, 72 and 73.

  The first impurity region 71 is formed by p-type impurities, the second impurity region 72 is formed by high-concentration n-type impurities, and the third impurity region 73 is formed by low-concentration n-type impurities. It is formed.

  At this time, the second impurity region 72 may be formed for ohmic contact.

  In this embodiment, the photodiode 70 is formed of the first, second and third impurity regions 71, 72, 73. However, the present invention is not limited to this, and the photodiode 70 includes the first impurity region 71 and The second impurity region 72 may be formed only.

  The first contact 81 penetrates the first impurity region 71, and the second contact 82 penetrates the second impurity region 72.

  At this time, the photodiode 70 is disposed between the first and second contacts 81, 82, and is adjacent to the photodiode 70 formed between the first and second contacts 81, 82. Can be formed symmetrically.

  The second contact 82 in contact with the first impurity region 71 can remove holes existing in the first impurity region 71, and the first contact 81 in contact with the second impurity region 72 The signal generated by the diode 70 can be transmitted to the circuit area.

  Although not shown in the drawing, a color filter array and a micro lens may be further formed on the photodiode 70.

  1A to 5B are process cross-sectional views of an image sensor manufacturing method according to an embodiment.

  First, as shown in FIGS. 1a and 1b, a first substrate 100 including a circuit layer 20 and a metal wiring layer 30 is prepared.

  FIG. 1 a shows a side sectional view of the first substrate 100 including the circuit layer 20 and the metal wiring layer 30, and FIG. 1 b shows that the wiring 150 a of the circuit layer 20 and the metal wiring layer 30 is formed. FIG. 3 is a detailed view related to the first substrate 100 formed.

  The circuit layer 20 includes a read circuit 120, and the metal wiring layer 30 includes a wiring 150a connected to the circuit.

  First, as shown in FIG. 1B, the first substrate 100 on which the wiring 150a and the readout circuit 120 are formed is prepared. For example, the device isolation layer 110 is formed on the second conductivity type first substrate 100 to define the active region, and the read circuit 120 including a transistor is formed in the active region. For example, the read circuit 120 can be formed to include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. Thereafter, the ion implantation region 130 including the floating diffusion region 131 and the source and drain regions 133, 135, and 137 for the transistors can be formed. In addition, according to the embodiment, a noise removal circuit (not shown) can be added to improve sensitivity.

  The step of forming the readout circuit 120 on the first substrate 100 includes the step of forming an electrical junction region 140 on the first substrate 100 and a first conductivity type connection region 147 connected to the wiring 150a on the electrical junction region 140. Can be included.

  For example, the electrical junction region 140 may be a PN junction, but is not limited thereto. For example, the electrical junction region 140 is formed on the first conductivity type ion implantation layer 143 and the first conductivity type ion implantation layer 143 formed on the second conductivity type well 141 or the second conductivity type epi layer. A second conductivity type ion implantation layer 145 may be included. For example, the PN junction 140 may be a PO145 / N-143 / P-141 junction as shown in FIG. 1B, but is not limited thereto. The first substrate 100 may be conductive to the second conductivity type, but is not limited thereto.

  According to the embodiment, the device is designed so that there is a potential difference between the source and the drain at both ends of the transfer transistor, thereby enabling complete dumping of the photocharge. As a result, the photocharge generated in the photodiode is damped to the floating diffusion region, so that the output image sensitivity can be increased.

  That is, in the embodiment, as shown in FIG. 1B, by forming an electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed, a potential difference is generated between the source and drain at both ends of the transfer transistor 121. Allows complete dumping of photocharges.

  Hereinafter, the photo charge damping structure of the embodiment will be described in detail.

  In the embodiment, unlike the floating diffusion region 131 node which is an N + junction, the P / N / P junction 140 which is the electrical junction region 140 is pinched off at a predetermined voltage without transmitting all applied voltages. This voltage is called a pinning voltage, and the pinning voltage depends on the doping concentrations of PO145 and N-143.

  Specifically, the electrons generated by the photodiode 70 move to the P0 / N− / P− junction 140, and are transferred to the FD 131 node and converted into a voltage when the transfer transistor 121 is on.

  Since the maximum voltage value of the P0 / N- / P-junction 140 is a pinning voltage and the maximum voltage value of the FD131 node is Vdd-RxVth, the charge sharing phenomenon does not occur due to the potential difference between both ends of the transfer transistor 121. In addition, electrons generated in the photodiode 70 on the chip can be completely damped to the FD 131 node.

  That is, in the embodiment, the reason why the P0 / N− / P well junction which is not the N + / P well junction is formed on the silicon substrate which is the first substrate 100 is that the 4-Tr APS (Active pixel sensor) reset operation is performed. Since the + voltage is applied to N-143 of the P0 / N− / P well junction and the ground voltage is applied to the PO 145 and the P well 141, the P0 / N− / P well double is applied above the predetermined voltage. As in the case where the junction has a bipolar junction transistor (BJT) structure, pinch-off occurs. This is called a pinning voltage. Therefore, a potential difference is generated between the source and drain at both ends of the transfer transistor 121, and a charge sharing phenomenon during the on / off operation of the transfer transistor can be prevented.

  Therefore, unlike the case where the photodiode is simply connected to the N + J junction as in the prior art, according to the embodiment, problems such as saturation and reduction in sensitivity can be prevented.

  Next, according to the embodiment, the first conductivity type connection region 147 is formed between the photodiode and the readout circuit to provide a smooth movement path of the photocharge, thereby minimizing the dark current source, Saturation color saturation reduction and sensitivity reduction can be prevented.

  To this end, in the first embodiment, the first conductive type connection region 147 for the ohmic contact can be formed on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to penetrate the PO 145 and contact the N-143.

  Meanwhile, the width of the first conductivity type connection region 147 can be minimized in order to minimize the occurrence of the first conductivity type connection region 147 as a leakage source. For this reason, the embodiment can perform plug implant after the etching of the first metal contact 151a, but is not limited thereto. For example, in another example, an ion implantation pattern (not shown) may be formed, and the first conductivity type connection region 147 may be formed using the ion implantation pattern as an ion implantation mask.

  That is, the reason why the N + doping is locally applied only to the contact forming portion as in the first embodiment is to facilitate the ohmic contact formation while minimizing the dark signal. When the entire transfer transistor source portion is N + doped as in the prior art, a dark signal may increase due to dangling bonds on the substrate surface.

  Next, an interlayer insulating layer 160 may be formed on the first substrate 100 to form a wiring 150a. The wiring 150a may include a first metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but is not limited thereto.

  Subsequently, as shown in FIG. 2, a first impurity region 71 is formed in the second substrate 50.

  The second substrate 50 may be formed of n-type crystalline silicon doped with low-concentration n-type impurities, and an oxide film may be further formed on the second substrate 50.

  The first impurity region 71 is formed by forming a first photoresist pattern 61 on the second substrate 50 and performing a first ion implantation process on a p-type impurity.

  Subsequently, the first photoresist pattern 61 is removed, and a second photoresist pattern 62 is formed on the second substrate 50 as shown in FIG. 3, and a second ion implantation process is performed. A second impurity region 72 is formed on the second substrate 50.

  The second impurity region 72 may be formed by implanting a high concentration n-type impurity.

  At this time, since the second substrate 50 is n-type crystalline silicon, a third impurity region 73 into which low-concentration n-type impurities are implanted is disposed between the first impurity region 71 and the second impurity region 72. Thus, the photodiode 70 can be formed.

  At this time, the second impurity region 72 may be formed for ohmic contact.

  A heat treatment process may be performed to activate the first, second, and third impurity regions 71, 72, and 73.

  In the present embodiment, the second substrate 50 is formed of n-type crystalline silicon. However, the present invention is not limited to this, and the second substrate 50 may be formed of p-type crystalline silicon.

  When the second substrate 50 is an n-type substrate as in this embodiment, the first impurity region 71 and the second impurity region 72 are formed by an ion implantation process. In the case of a type substrate, the photodiode 70 is formed by forming a third impurity region 73 into which low-concentration n-type impurities are implanted and a second impurity region 72 into which high-concentration n-type impurities are implanted. be able to.

  In this embodiment, the photodiode 70 includes the first impurity region 71 implanted with p-type impurities, the third impurity region 73 implanted with low-concentration n-type impurities, and high-concentration n-type impurities. The photodiode 70 may be formed of only the first impurity region 71 and the third impurity region 73, but is not limited thereto.

  Subsequently, the second photoresist pattern 62 is removed, and the second substrate 50 including the photodiode 70 is bonded to the first substrate 100 as shown in FIG.

  Therefore, the photodiode 70 is formed on the metal wiring layer 30.

  In the present embodiment, the photodiode 70 is formed on the entire second substrate 50, but when the photodiode 70 is formed only on a part of the second substrate 50, the photodiode 70 on the second substrate 50 is formed. The area except for can be removed.

  Then, as shown in FIG. 5, a first contact 81 and a second contact 82 are formed through the photodiode 70 and connected to the wiring M3.

  FIG. 5 a shows a side sectional view of the first substrate 100 including the circuit layer 20, the metal wiring layer 30 and the photodiode 70, and FIG. 5 b shows the circuit layer 20, the metal wiring layer 30. FIG. 6 is a detailed view of the first substrate 100 on which the wiring 150a is formed.

  The first and second contacts 81 and 82 are etched to form a via hole that penetrates the photodiode 70, and then the via hole is made of tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum. It can be formed by filling with a metal material such as (Al).

  The first contact 81 is formed through the first impurity region 71, and the second contact 82 is formed through the second impurity region 72.

  At this time, when forming the first and second contacts 81 and 82, the second contact 82 not only penetrates the second impurity region 72 but also penetrates a part of the metal wiring layer 30 to form a metal wiring. Can connect with M3.

  The photodiode 70 is disposed between the first and second contacts 81 and 82, and the photodiode formed adjacent to the photodiode 70 formed between the first and second contacts 81 and 82 is It can be formed symmetrically.

  The second contact 82 in contact with the first impurity region 71 can remove holes existing in the first impurity region 71 and includes the first contact 81 in contact with the second impurity region 72. 150 can transmit the signal generated by the photodiode 70 to the circuit area.

  Subsequently, although not shown, an electrode, a color filter array, and a micro lens can be formed on the photodiode 70.

(Second embodiment)
FIG. 6 is a detailed view of the first substrate on which the wiring 150 is formed as a cross-sectional view of the image sensor according to the second embodiment.

  The second embodiment can employ the technical features of the first embodiment.

  For example, according to the second embodiment, the device is designed so that there is a potential difference between the source and the drain at both ends of the transfer transistor, and the photocharge can be completely dumped.

  In addition, according to the embodiment, a charge coupling region is formed between the photodiode and the readout circuit to provide a smooth movement path of the photocharge, thereby minimizing the dark current source, saturation color saturation and A decrease in sensitivity can be prevented.

  On the other hand, unlike the first embodiment, the second embodiment is an example in which a first conductivity type connection region 148 is formed on one side of the electrical junction region 140.

  According to the embodiment, the N + connection region 148 for the ohmic contact can be formed at the P0 / N− / P− junction 140. At this time, the formation process of the N + connection region 148 and the M1C contact 151a is a leakage. May be a source. This is because the reverse voltage is applied to the P0 / N− / P− junction 140, and an electric field may be generated on the substrate surface. In such an electric field, crystal defects generated during the contact formation process become a leakage source.

  In addition, when the N + connection region 148 is formed on the surface of the P0 / N− / P− junction 140, an electric field due to the N + / P0 junction 148/145 is added, which may also be a leakage source.

  Accordingly, the second embodiment presents a layout in which the first contact plug 151a is formed in the active region formed of the N + connection region 148 without doping the P0 layer, and the first contact plug 151a is connected to the N-junction 143. .

According to the second embodiment, since the electric field on the substrate surface is not generated, this can contribute to the reduction of the dark current of the 3-D Integrated CIS.
(Third embodiment)

  FIG. 7 is a detailed view of the first substrate on which the wiring 150 is formed as a cross-sectional view of the image sensor according to the third embodiment.

  The third embodiment can employ the technical features of the first embodiment.

  For example, according to the third embodiment, the device is designed such that there is a potential difference between the source and the drain at both ends of the transfer transistor, so that the photocharge can be completely dumped.

  In addition, according to the embodiment, a charge coupling region is formed between the photodiode and the readout circuit to provide a smooth movement path of the photocharge, thereby minimizing the dark current source, saturation color saturation and A decrease in sensitivity can be prevented.

  Meanwhile, in the third embodiment, the step of forming the read circuit 120 on the first substrate 100 will be described in more detail.

  First, a first transistor 121a and a second transistor 121b are formed on the first substrate 100. For example, the first transistor 121a and the second transistor 121b may be a first transfer transistor and a second transfer transistor, respectively, but are not limited thereto. The first transistor 121a and the second transistor 121b may be formed simultaneously or sequentially.

  Thereafter, an electrical junction region 140 is formed between the first transistor 121a and the second transistor 121b. For example, the electrical junction region 140 may be a PN junction 40, but is not limited thereto.

  For example, the PN junction 140 according to the embodiment includes a first conductivity type ion implantation layer 143 formed on the second conductivity type epi (or well) 141, and a second conductivity type formed on the first conductivity type ion implantation layer 143. A conductive ion implantation layer 145 may be included.

  For example, the PN junction 140 may be a PO145 / N-143 / P-141 junction as shown in FIG. 1B, but is not limited thereto.

  Thereafter, a high-concentration first conductivity type connection region 131b connected to the wiring 150 is formed on one side of the second transistor 121b. The high-concentration first conductivity type connection region 131b can serve as the second floating diffusion region 131b as a high-concentration N + ion implantation region, but is not limited thereto.

  In the embodiment, the readout circuit unit includes a part for moving electrons generated by the photodiode on the chip to the N + junction 131b of the substrate on which the circuit is formed, and an electron at the N + junction 131b and the N− junction 143. 4Tr operation becomes possible.

  In the third embodiment, the reason why the P0 / N− / P− junction 140 and the N + junction 131b are formed separately as shown in FIG. 7 is as follows.

  For example, if N + doping and contact are formed at P / N / P junction 140 of P0 / N- / P-Epi 140, dark current will be generated due to damage of N + junction 131b and contact etching, thus preventing this. For this purpose, the N + junction 131b, which is a contact forming portion, is separated from the P / N / P junction 140.

  That is, if N + doping and contact etching are performed on the surface of the P / N / P junction 140, it becomes a leakage source, and in order to prevent this, a contact is formed at the N + / P-Epi junction 131b.

At the time of signal reading (Signal Readout), the gate of the second transistor 121b is turned on, so that electrons generated by the photodiode 70 on the top of the chip pass through the P0 / N- / P-Epi junction 140 and pass through the first floating diffusion. Since it is moved to the area 131a node, CDS (Correlated Double Sampling) becomes possible.

  As described above, according to the image sensor manufacturing method of the embodiment, the crystalline second substrate on which the photodiode is formed is bonded to the first substrate on which the circuit including the lower wiring is formed. The characteristics of the image sensor can be improved and the sensitivity of the image sensor can be improved.

It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example. It is process sectional drawing of the manufacturing method of the image sensor by an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit layer, 30 Metal wiring layer, 50 2nd board | substrate, 61 1st photoresist pattern, 62 2nd photoresist pattern, 70 Photodiode, 71 1st impurity region, 72 2nd impurity region, 73 3rd impurity region, 81 first contact, 82 second contact, 100 first substrate, 110 element isolation film, 120 readout circuit, 121 transfer transistor, 121a first transistor, 121b second transistor, 123 reset transistor, 125 drive transistor, 127 select transistor, 130 ion implantation region, 131 floating diffusion region, 131a first floating diffusion region, 131b N + junction, 133, 135, 137 source and drain region, 140 Electrical junction region, 141 Second conductivity type well, 143 First conductivity type ion implantation layer, 145 Second conductivity type ion implantation layer, 147 First conductivity type connection region, 150, 150a wiring, 151 First metal, 151a First Metal contact, 152 2nd metal, 153 3rd metal

Claims (18)

Preparing a first substrate on which wiring and readout circuits are formed;
Forming a photodiode formed on the first substrate including a first impurity region and a second impurity region in a crystalline region;
Forming a plurality of first contacts and second contacts formed through the photodiode and connected to the wiring and spaced apart from each other, wherein the first contact is in contact with the first impurity region; A method of manufacturing an image sensor, wherein two contacts are in contact with the second impurity region. Forming the photodiode formed in the crystalline region on the first substrate;
Forming a photodiode on a crystalline second substrate;
The method according to claim 1, further comprising bonding the photodiode on the first substrate.   The photodiode includes a third impurity region formed between the first impurity region and the second impurity region, and the third impurity region is formed by implanting a low concentration n-type impurity. The manufacturing method of the image sensor of Claim 1 containing.   The method according to claim 1, wherein the first impurity region and the second impurity region formed in the photodiode are formed symmetrically with respect to adjacent pixels.   The step of preparing the first substrate on which the wiring and the readout circuit are formed includes the step of forming the readout circuit on the first substrate, and forming an electrical junction region on the first substrate so as to be electrically connected to the readout circuit. The method according to claim 1, further comprising: forming a wiring on the first substrate so as to be electrically connected to the electrical junction region.   The step of forming an electrical junction region on the first substrate includes forming a first conductivity type ion implantation region on the first substrate, and forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. The manufacturing method of the image sensor of Claim 5 including the step of forming.   The method of claim 5, further comprising forming a first conductivity type connection region between the electrical junction region and the wiring, wherein the first conductivity type connection region is electrically connected to the wiring. Manufacturing method of image sensor.   The method of manufacturing an image sensor according to claim 5, wherein an ion implantation concentration in the electrical junction region is lower than an ion implantation concentration in the floating diffusion region.   The readout circuit of the first substrate includes a first transistor and a second transistor formed on the first substrate, and the electrical junction region is formed between the first transistor and the second transistor. The manufacturing method of the image sensor of Claim 5 containing.   A semiconductor substrate on which wiring and readout circuits are formed; a photodiode formed on the semiconductor substrate and including a first impurity region and a second impurity region in a crystalline region; and penetrating the photodiode A plurality of first and second contacts connected to the wiring and spaced apart from each other, wherein the first contact is in contact with the first impurity region, and the second contact is in contact with the second impurity region; Including image sensor.   The image sensor according to claim 10, further comprising an oxide film formed between the semiconductor substrate on which wiring and a readout circuit are formed and the photodiode.   The image sensor according to claim 10, wherein the first impurity region is formed by implanting p-type impurities, and the second impurity region is formed by implanting n-type impurities.   The image sensor according to claim 10, wherein the first impurity region and the second impurity region formed in the photodiode are formed symmetrically with respect to adjacent pixels.   The photodiode includes a third impurity region formed between the first impurity region and the second impurity region, and the third impurity region is formed by implanting a low concentration n-type impurity. The image sensor according to claim 10.   The readout circuit includes an electrical junction region formed in the semiconductor substrate, and the electrical junction region is formed on the first conductivity type ion implantation region and the first conductivity type ion implantation region formed in the semiconductor substrate. The image sensor according to claim 10, further comprising a formed second conductivity type ion implantation region.   The image sensor according to claim 15, further comprising a first conductivity type connection region formed between the electric junction region and the wiring, wherein the first conductivity type connection region is electrically connected to the wiring. .   The image sensor according to claim 10, wherein the readout circuit includes a potential difference between a source and a drain on both sides of the transistor.   The image sensor according to claim 17, wherein the transistor is a transfer transistor, and an ion implantation concentration of a source of the transistor is lower than an ion implantation concentration of a floating diffusion region.

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