KR20100079266A - Image sensor and method for manufacturing thereof - Google Patents

Image sensor and method for manufacturing thereof Download PDF

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Publication number
KR20100079266A
KR20100079266A KR1020080137695A KR20080137695A KR20100079266A KR 20100079266 A KR20100079266 A KR 20100079266A KR 1020080137695 A KR1020080137695 A KR 1020080137695A KR 20080137695 A KR20080137695 A KR 20080137695A KR 20100079266 A KR20100079266 A KR 20100079266A
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South Korea
Prior art keywords
light sensing
conductive
wiring
sensing unit
forming
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KR1020080137695A
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Korean (ko)
Inventor
한창훈
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주식회사 동부하이텍
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Priority to KR1020080137695A priority Critical patent/KR20100079266A/en
Publication of KR20100079266A publication Critical patent/KR20100079266A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The image sensor according to the embodiment includes a readout circuitry formed on the first substrate; Wiring formed on the first substrate; A light sensing device including a first conductive conductive layer and a second conductive conductive layer on the wiring; A contact plug connecting the light sensing unit and the wiring; An interlayer separation layer formed on the light sensing unit; And a ground line formed on the inter-pixel separation layer and connected to the light sensing unit.

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is divided into a charge coupled device (CCD) and a CMOS image sensor (CIS). do.

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor").

Meanwhile, according to the related art, in connection with the separation of electrons and holes generated by light in the upper photo diode in the three-dimensional structure, the movement path of the electron is longer than that of the conventional two-dimensional structure, and thus it is not smooth. However, there is a problem of recombination with each other resulting in loss of signal.

In addition, according to the related art, since both the source and the drain of the both ends of the transfer transistor are doped with a high concentration of N-type, charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide an image sensor and a method of manufacturing the same that can optimize the formation of a signal line in order to minimize light loss.

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can increase the charge factor (Charge Sharing) does not occur.

In addition, the embodiment of the present invention provides an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a manufacturing method.

The image sensor according to the embodiment includes a readout circuitry formed on the first substrate; Wiring formed on the first substrate; A light sensing device including a first conductive conductive layer and a second conductive conductive layer on the wiring; A contact plug connecting the light sensing unit and the wiring; An interlayer separation layer formed on the light sensing unit; And a ground line formed on the inter-pixel separation layer and connected to the light sensing unit.

In addition, the manufacturing method of the image sensor according to the embodiment comprises the steps of forming a readout circuitry (Readout Circuitry) on the first substrate; Forming a wire on the first substrate; Forming a light sensing device including a first conductive conductive layer and a second conductive conductive layer on the wiring; Forming a contact plug connecting the light sensing unit and the wiring; Forming an inter-pixel separation layer on the light sensing unit; And forming a ground line connected to the light sensing unit on the inter-pixel separation layer.

According to the image sensor and the manufacturing method according to the embodiment, it is possible to prevent the loss of light due to the ground line formation in the three-dimensional image sensor, and to effectively improve the sensitivity by separating the electrons and holes have.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and may be applied to an image sensor requiring a photodiode.

(First embodiment)

1 is a cross-sectional view of an image sensor according to a first embodiment. 2A is a cross-sectional view taken along line AA ′ of the image sensor according to the first embodiment, and FIG. 2B is a cross-sectional view taken along line BB ′ of the image sensor according to the first embodiment.

The image sensor according to the first embodiment includes a readout circuitry 120 formed on the first substrate 100; A wiring 150 formed on the substrate; A light sensing device 210 including a first conductivity type conductive layer 214 and a second conductivity type conductive layer 216 on the wiring 150; A contact plug 240 connecting the light sensing unit 210 and the wiring 150; An inter pixel separation layer 220 formed on the light sensing unit 210; And a ground line 260 formed on the inter-pixel separation layer 220 and connected to the light sensing unit 210.

The light sensing unit 210 may be a photodiode, but is not limited thereto. The photodetector 210 may be a photogate, a combination of a photodiode and a photogate, and the like. On the other hand, the embodiment is an example in which the photodiode is formed in the crystalline semiconductor layer, but is not limited thereto, and includes the one formed in the amorphous semiconductor layer. Unexplained reference numerals among the reference numerals of FIG. 1 will be described in the following manufacturing method.

According to the image sensor and the manufacturing method according to the embodiment, it is possible to prevent the loss of light due to the ground line formation in the three-dimensional image sensor, and to effectively improve the sensitivity by separating the electrons and holes have.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Hereinafter, a manufacturing method of an image sensor according to an exemplary embodiment will be described with reference to FIGS. 2A, 2B, and 3.

First, as shown in FIG. 2A, the interlayer insulating layer 160 is formed on the first substrate 100, and the wiring 150 is formed on the interlayer insulating layer 160.

Hereinafter, a process of forming the lead-out circuit 120, the electrical junction region 140, the wiring 150, and the like on the first substrate 100 will be described in detail with reference to FIG. 3.

First, as shown in FIG. 3, the first substrate 100 on which the readout circuit 120 is formed is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. In addition, according to the embodiment, the noise can be improved by adding a noise removing circuit (not shown).

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the embodiment, as shown in FIG. 3, the voltage difference between the source / drain across the transfer transistor (Tx) 121 is formed by forming the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / P-well junction, not the N + / P-well junction, is formed in the silicon sub, which is the first substrate 100, is P0 during the 4-Tr APS Reset operation. In / N- / P-well junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and P-well (141), so P0 / N- / P-well Double above a certain voltage Junction is Pinch-Off as in BJT structure. This is called pinning voltage. Therefore, a voltage difference occurs at the source / drain at both ends of the Tx 121, and thus, photocharge is fully dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation ( Saturation) can be prevented and degradation of sensitivity.

To this end, the first embodiment may form an n + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, as another example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but is not limited thereto.

Next, referring to FIG. 2A, an optical sensing unit 210 is formed on the wiring 150.

For example, a high concentration first conductive type conductive layer 212, first conductive type conductive layer 214, and second conductive type conductive layer 216 are formed in a crystalline semiconductor layer, and the wiring ( After bonding on 150, the photosensitive unit 210 is left and the crystalline semiconductor layer is removed.

Next, a contact plug 240 connecting the light sensing unit 210 and the wiring 150 is formed. For example, the photodetector 210 is partially etched to form a first trench (not shown) that exposes the top metal of the wiring 150, for example, the third metal M3. Thereafter, a first metal layer (not shown) filling the first trench may be formed, and the contact plug 240 may be formed by etching out the first metal layer.

The contact plug 240 is prevented from shorting by not coming into contact with the second conductive conductive layer 216 of the light sensing unit 210, and a short circuit prevention layer 232 is formed on the contact plug 240 by an oxide film or the like. ) Can be further formed.

In addition, an interpixel separation layer 220 filled with an insulating film such as an oxide film may be formed by removing the light sensing unit at the pixel boundary. The interpixel separation layer 220 may be formed by a second conductivity type ion implantation, for example, a P type ion implantation.

Thereafter, the second insulating layer 235 may be formed on the light sensing unit 210 by an oxide film or the like.

Next, a ground line 260 connected to the light sensing unit 210 is formed on the inter-pixel separation layer 220.

For example, as shown in FIG. 2B, a portion of the pixel isolation layer 220 is removed to expose the second conductivity type conductive layer 216 of the light sensing unit to form a third trench (not shown). The trench may be filled with a metal layer to form a ground contact 264 in contact with the second conductivity type conductive layer.

Thereafter, an upper ground line 262 may be formed by the metal layer on the ground contact 264.

Thereafter, a color filter (not shown) process, a microlens (not shown) process, a pad (not shown) opening process, and the like may be performed.

According to the image sensor and the manufacturing method according to the embodiment, it is possible to prevent the loss of light due to the ground line formation in the three-dimensional image sensor, and to effectively improve the sensitivity by separating the electrons and holes have.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

(2nd Example)

4 is a cross-sectional view of an image sensor according to a second embodiment.

The second embodiment can employ the technical features of the first embodiment.

The second embodiment may further include forming a second conductivity type ion implantation layer 250 between the second conductivity type conductive layer 216 and the ground contact 264 of the light sensing unit 210. have.

According to the second embodiment, by forming the second conductivity type ion implantation layer 250, holes can be more efficiently escaped, and dark current is reduced by inducing recombination with electrons, which are dark current components generated at the pixel separation interface. It also works.

(Third Embodiment)

FIG. 5 is a cross-sectional view of the image sensor according to the third embodiment, which is a detailed view of a first substrate on which a readout circuit 120, a wiring 150, and the like are formed.

The third embodiment can employ the technical features of the first embodiment.

Meanwhile, unlike the first embodiment, the third embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, wherein the Ricky is formed in a process of forming the N + connection region 148 and the M1C contact 151a. A Leakage Source may occur. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the third embodiment, a first contact plug 151a is formed in an active region formed of an N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a to the N-junction 143 is provided. present.

According to the third embodiment, the E-Field of the Si surface is not generated, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a plan view of an image sensor according to a first embodiment;

2A and 2B are sectional views of the image sensor according to the first embodiment;

3 is a sectional view of an image sensor according to a first embodiment;

4 is a sectional view of an image sensor according to a second embodiment;

5 is a sectional view of an image sensor according to a third embodiment;

Claims (18)

A readout circuitry formed on the first substrate; Wiring formed on the first substrate; A light sensing device including a first conductive conductive layer and a second conductive conductive layer on the wiring; A contact plug connecting the light sensing unit and the wiring; An interlayer separation layer formed on the light sensing unit; And And a ground line formed on the inter-pixel separation layer and connected to the light sensing unit. According to claim 1, The ground line is, A ground contact in contact with the second conductive conductive layer of the light sensing unit; And And an upper ground line on the ground contact. The method of claim 2, And a second conductivity type ion implantation layer formed between the second conductivity type conductive layer and the ground contact of the light sensing unit. According to claim 1, The contact plug is formed between the first conductive conductive layer of the light sensing unit and the top metal of the wiring. An image sensor, characterized in that the short-circuit prevention layer is further formed on the contact plug. According to claim 1, The readout circuit includes a transistor, And a potential difference between the source and the drain of both sides of the transistor. 6. The method of claim 5, The transistor is a transfer transistor, And an ion implantation concentration of the transistor source is lower than an ion implantation concentration of a floating diffusion region which is a drain. According to claim 1, And an electrical junction region electrically connected to the lead-out circuit on the first substrate. And a first conductivity type connection region formed between the electrical junction region and the wiring. The method of claim 7, wherein The first conductivity type connection region And an image sensor electrically connected to the wiring on the upper portion of the junction region. The method of claim 7, wherein The first conductivity type connection region An image sensor, characterized in that formed on one side of the electrical junction region is electrically connected to the wiring. Forming a readout circuitry on the first substrate; Forming a wire on the first substrate; Forming a light sensing device including a first conductive conductive layer and a second conductive conductive layer on the wiring; Forming a contact plug connecting the light sensing unit and the wiring; Forming an inter-pixel separation layer on the light sensing unit; And forming a ground line connected to the light sensing unit on the inter-pixel separation layer. The method of claim 10, In the step of forming the ground line, Forming a ground contact in contact with the second conductive type conductive layer of the light sensing unit; And forming an upper ground line on the ground contact. The method of claim 11, wherein In the step of forming the ground line, And forming a second conductive ion implantation layer between the second conductive conductive layer and the ground contact of the light sensing unit. The method of claim 10, The contact plug is formed between the first conductive conductive layer of the light sensing unit and the top metal of the wiring. The manufacturing method of the image sensor, characterized in that the short-circuit prevention layer is further formed on the contact plug. The method of claim 10, The readout circuit includes a transistor, And a potential difference between the source and the drain of both sides of the transistor. 15. The method of claim 14, The transistor is a transfer transistor, And an ion implantation concentration of the transistor source is lower than an ion implantation concentration of the floating diffusion region, the drain. The method of claim 10, Forming an electrical junction region electrically connected to the lead-out circuit on the first substrate, And forming a first conductive connection region between the electrical junction region and the wiring. The method of claim 16, The first conductivity type connection region And an electrical connection with the wirings formed on the electrical junction region. The method of claim 16, The first conductivity type connection region And an electrical connection with the wiring on one side of the electrical bonding region.
KR1020080137695A 2008-12-31 2008-12-31 Image sensor and method for manufacturing thereof KR20100079266A (en)

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