WO2019009023A1 - Imaging device - Google Patents

Imaging device Download PDF

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Publication number
WO2019009023A1
WO2019009023A1 PCT/JP2018/022308 JP2018022308W WO2019009023A1 WO 2019009023 A1 WO2019009023 A1 WO 2019009023A1 JP 2018022308 W JP2018022308 W JP 2018022308W WO 2019009023 A1 WO2019009023 A1 WO 2019009023A1
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WO
WIPO (PCT)
Prior art keywords
voltage
transistor
impurity region
signal
potential
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PCT/JP2018/022308
Other languages
French (fr)
Japanese (ja)
Inventor
嘉晃 佐藤
翔太 山田
雅史 村上
廣瀬　裕
Original Assignee
パナソニックＩｐマネジメント株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to JP2018554794A priority Critical patent/JP6474014B1/en
Priority to CN201880002381.3A priority patent/CN109429559B/en
Publication of WO2019009023A1 publication Critical patent/WO2019009023A1/en
Priority to US16/377,855 priority patent/US11233958B2/en
Priority to US17/551,720 priority patent/US11678083B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14665—Imagers using a photoconductor layer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present disclosure relates to an imaging device.
  • a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor are widely used in digital still cameras and digital cameras. As well known, these image sensors have photodiodes formed on a semiconductor substrate.
  • CCD charge coupled device
  • CMOS complementary metal oxide semiconductor
  • a structure in which a photoelectric conversion portion having a photoelectric conversion layer is disposed above a semiconductor substrate has been proposed (for example, Patent Document 1).
  • An imaging device having such a structure may be referred to as a stacked imaging device.
  • a stacked imaging device is a node having an electrical connection with a photoelectric conversion unit, and has a floating node that temporarily accumulates one of positive and negative charges generated by photoelectric conversion as a signal charge.
  • the floating node typically has a diffusion region formed on a semiconductor substrate supporting the photoelectric conversion unit, and a conductive structure electrically connecting the photoelectric conversion unit and the diffusion region to each other.
  • the semiconductor substrate is provided with a CCD circuit or a CMOS circuit, and a signal corresponding to the amount of charge stored in the floating node is read out via the CCD circuit or the CMOS circuit.
  • a leak current from an impurity region that accumulates charges generated by photoelectric conversion or to an impurity region may cause degradation in an image obtained. Therefore, it is useful to be able to reduce such leakage current.
  • the leak current from the impurity region which accumulates the charge generated by photoelectric conversion or to the impurity region may be simply referred to as “dark current”.
  • a semiconductor substrate having a first impurity region of n-type conductivity, a photoelectric conversion unit electrically connected to the first impurity region, and converting light into electric charge; a first terminal and a second terminal;
  • the first terminal includes a capacitive element electrically connected to the first impurity region, and a voltage supply circuit electrically connected to the second terminal, wherein the voltage supply circuits are different from each other in the first A voltage and a second voltage are supplied to the second terminal, and the first impurity region stores positive charge among charges generated in the photoelectric conversion unit.
  • the general or specific aspects may be realized in an element, a device, a module, a system or a method. Also, the comprehensive or specific aspects may be realized by any combination of elements, devices, apparatuses, modules, systems and methods.
  • a dark current suppressed imaging device is provided.
  • FIG. 1 is a diagram schematically illustrating an exemplary configuration of an imaging device according to a first embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view schematically showing an exemplary device structure of the pixel 10.
  • FIG. 3 is a view schematically showing a typical example of the circuit configuration of the pixel 10A shown in FIG.
  • FIG. 4A is a timing chart for explaining an exemplary operation of the pixel 10A having the circuit configuration shown in FIG.
  • FIG. 4B is a timing chart for explaining an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10A.
  • FIG. 4C is a timing chart for explaining another example of the operation of the pixels 10A, 10Ap and 10Aq.
  • FIG. 5 is a view schematically showing an example of another circuit configuration of the pixel 10.
  • FIG. 6 is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 7A is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 7B is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 8 is a timing chart for explaining an exemplary operation of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B.
  • FIG. 9A is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 9B is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 10 is a timing chart for explaining an exemplary operation of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B.
  • FIG. 11A is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 11B is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 11C is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 12 is a diagram schematically illustrating an example of a circuit configuration of the pixel 10B included in the imaging device according to the second embodiment of the present disclosure.
  • FIG. 13 is a diagram showing a more specific example to which the circuit configuration shown in FIG. 12 is applied.
  • FIG. 11A is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 11B is a view schematically showing an example of still another circuit configuration of the pixel 10.
  • FIG. 11C is a view schematically showing an example of still another circuit
  • FIG. 14A is a timing chart for describing an exemplary operation of the pixel 10Bf having the circuit configuration shown in FIG.
  • FIG. 14B is a timing chart for describing an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf.
  • FIG. 15 is a view showing a modified example of the imaging device according to the second embodiment of the present disclosure.
  • FIG. 16 is a diagram showing another modified example of the imaging device according to the second embodiment of the present disclosure.
  • FIG. 17A is a timing chart for illustrating an exemplary operation of the pixel 10Br having the circuit configuration shown in FIG. FIG.
  • FIG. 17B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Br and electrons are used as signal charges.
  • FIG. 18 is a diagram showing still another modified example of the imaging device according to the second embodiment of the present disclosure.
  • FIG. 19A is a diagram schematically illustrating an example of a circuit configuration of a pixel included in an imaging device according to a third embodiment of the present disclosure.
  • FIG. 19B is a view schematically showing another example of the circuit configuration of the pixel included in the imaging device according to the third embodiment of the present disclosure.
  • FIG. 20 is a timing chart for illustrating an exemplary operation of the pixel 10D having the circuit configuration shown in FIG. 19A.
  • FIG. 21 is a diagram schematically illustrating an example of a circuit configuration of a pixel included in an imaging device according to a fourth embodiment of the present disclosure.
  • FIG. 22A is a timing chart for describing an exemplary operation of the pixel 10C having the circuit configuration shown in FIG.
  • FIG. 22B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10C and electrons are used as signal charges.
  • FIG. 23 is a view showing a modified example of the imaging device according to the fourth embodiment of the present disclosure.
  • FIG. 24 is a functional block diagram schematically illustrating an exemplary camera system according to a fifth embodiment of the present disclosure.
  • This specification discloses an imaging device described in the following items.
  • the imaging device according to claim 1, wherein the first impurity region stores positive charge among charges generated in the photoelectric conversion unit.
  • the first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
  • the voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off.
  • the first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
  • the voltage supply circuit supplies the first voltage to the second terminal during a first period in which the positive charge is accumulated in the first impurity region, and the first transistor is turned on after the first period.
  • the semiconductor substrate has a second impurity region
  • the first transistor includes the second impurity region as the other of a source and a drain,
  • a semiconductor substrate having a first impurity region of p-type conductivity; A photoelectric conversion unit electrically connected to the first impurity region to convert light into charge; A capacitive element having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first impurity region; A voltage supply circuit electrically connected to the second terminal; The voltage supply circuit supplies first and second voltages different from each other to the second terminal,
  • the imaging device according to claim 1, wherein the first impurity region stores negative charge among charges generated in the photoelectric conversion unit.
  • the first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
  • the voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off.
  • the first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
  • the voltage supply circuit supplies the first voltage to the second terminal in a first period in which the negative charge is accumulated in the first impurity region, and the first transistor is turned on after the first period.
  • the semiconductor substrate has a second impurity region
  • the first transistor includes the second impurity region as the other of a source and a drain,
  • the capacitive element and the first impurity region are at least a part of a charge storage node that stores charges of one polarity among charges generated in the photoelectric conversion unit,
  • the imaging device according to any one of Items 1 to 10, wherein a capacitance value of the capacitive element is smaller than a capacitance value of a portion other than the capacitive element in the charge storage node.
  • the photoelectric conversion unit is A first electrode, A second electrode facing the first electrode; A photoelectric conversion layer located between the first electrode and the second electrode; 12.
  • the imaging device according to any one of items 1 to 11, wherein the first electrode is electrically connected to the first impurity region.
  • a semiconductor substrate having a first impurity region and a second impurity region; A photoelectric conversion unit electrically connected to the first impurity region; A first transistor including a first impurity region as one of a source region and a drain region and including a second impurity region as the other of the source region and the drain region; And a voltage supply circuit electrically connected to the second impurity region, The voltage supply circuit applies a first voltage to the second impurity region in a first period in which the first transistor is on, and after the first period and in a second period in which the first transistor is off, An imaging device applying a different second voltage to the second impurity region.
  • the configuration of the item 1 it is possible to prevent the occurrence of dark current due to forward bias applied to the pn junction between the first impurity region and the periphery thereof when the first transistor is turned off.
  • a voltage with a smaller voltage difference can be applied as the first voltage and the second voltage.
  • a voltage with a smaller voltage difference can be applied as the first voltage and the second voltage.
  • the first transistor is n-type, The imaging device according to any one of Items 1 to 10, wherein the second voltage is higher than the first voltage.
  • the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor can be avoided from being lower than the substrate potential of the semiconductor substrate.
  • the first transistor is p-type, The imaging device according to any one of Items 1 to 10, wherein the second voltage is lower than the first voltage.
  • the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor exceeds the substrate potential of the semiconductor substrate.
  • the reset transistor is n-type, 14.
  • the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor becomes lower than the substrate potential of the semiconductor substrate.
  • the influence of dark current on a signal corresponding to the voltage level of the charge storage node after reset can be suppressed.
  • the reset transistor is p-type, 14.
  • the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor exceeds the substrate potential of the semiconductor substrate.
  • the charge storage node includes an n-type first impurity region formed in the semiconductor substrate, 19.
  • the charge storage node includes a p-type first impurity region formed in the semiconductor substrate, 19.
  • the photoelectric converter is A first electrode supported on a semiconductor substrate; A second electrode, Further comprising a photoelectric conversion layer located between the first electrode and the second electrode; The imaging device according to any one of Items 1 to 17 or any one of Items 19 to 22, wherein the first electrode is electrically connected to the first impurity region.
  • An imaging device comprising a plurality of pixels, wherein Each pixel of the plurality of pixels is A photoelectric conversion unit that generates charges by photoelectric conversion; A charge storage node for storing charge; A reset transistor electrically connected to the charge storage node and resetting the potential of the charge storage node to a reference potential; An amplification transistor electrically connected to the charge storage node and outputting a signal voltage according to the charge stored in the charge storage node; A capacitive element having one end electrically connected to the charge storage node and the other end connected to a voltage source; Equipped with A first voltage is applied to the other end of the capacitive element in the exposure period in which charge is stored in the charge storage node, and the other end of the capacitive element is different from the first voltage in the reset period in the non-exposure period other than the exposure period. 2 voltage is applied, An imaging device, wherein the reset period is a part of a non-exposure period, and a reset transistor resets the potential of the charge storage node to
  • an imaging device capable of reducing leakage current is provided.
  • the potential of the charge storage node is set to a low potential in the exposure period, and the potential of the charge storage node is high in the non-exposure period. By setting the potential, the dark current can be reduced without deteriorating the circuit characteristics.
  • the voltage change of the control signal applied to the other end of the capacitive element can be applied to the FD node through the capacitive element.
  • any control signal in the pixel can be used also as a control signal given to the capacitive element, so the number of control signal lines used can be reduced.
  • a switch transistor electrically connected between one end of the capacitive element and the charge storage node, or between the voltage source and the other end, for switching connection / disconnection of the capacitive element and the charge storage node, item 26 27.
  • the imaging device described in Item 29 it is possible to selectively use the FD potential control mode for controlling the potential of the charge storage node and the high gain mode for efficiently converting the signal charge.
  • the charge is a hole, The imaging device according to any one of items 25 to 29, wherein the second voltage is higher than the first voltage.
  • imaging device described in Item 30 it is possible to provide an imaging device that can reduce leakage current and that uses holes as signal charges.
  • the charge is an electron, The imaging device according to any one of items 25 to 29, wherein the second voltage is lower than the first voltage.
  • imaging device described in Item 32 it is possible to provide an imaging device that can reduce leakage current and that uses electrons as signal charges.
  • the imaging device described in Item 35 it is possible to suppress the power supply noise of the control signal applied to the capacitive element from being mixed into the charge storage node.
  • a high output can be obtained from the amplification transistor even for the potential of the charge storage node at a low level, so that the voltage range necessary for the operation of the current source of the source follower circuit can be secured. It becomes possible.
  • the photoelectric converter is A first electrode, A second electrode facing the first electrode; A photoelectric conversion film located between the first electrode and the second electrode and generating charges by photoelectric conversion;
  • the imaging device according to any one of Items 25 to 36, having:
  • an imaging device including a photoelectric conversion unit having a photoelectric conversion film, which can reduce the leakage current.
  • FIG. 1 schematically shows an exemplary configuration of an imaging device according to a first embodiment of the present disclosure.
  • An imaging device 100 illustrated in FIG. 1 includes a pixel array 110 including a plurality of pixels 10 and a peripheral circuit 120.
  • the pixel array 110 includes a plurality of pixels 10 arranged, for example, in a matrix of m rows and n columns.
  • m and n are natural numbers.
  • the pixels 10 are two-dimensionally arranged on the semiconductor substrate 60, for example, to form an imaging region.
  • the number and arrangement of the pixels 10 in the pixel array 110 are not limited to the illustrated example.
  • the number of pixels 10 included in the imaging device 100 may be one.
  • the imaging device 100 can be used as a line sensor.
  • Each pixel 10 includes a photoelectric conversion unit that receives light and generates a charge.
  • the photoelectric conversion portion of each pixel 10 has a structure including a buried photodiode formed on the semiconductor substrate 60 or a part of the photoelectric conversion layer disposed above the region corresponding to the imaging region in the semiconductor substrate 60. obtain.
  • terms such as “upper” and “lower” are used only to designate the mutual arrangement between members, and are not intended to limit the posture when using the imaging device 100.
  • the peripheral circuit 120 has a predetermined voltage applied to the vertical scanning circuit 122, the signal holding circuit 123, the horizontal scanning circuit 124, the output stage amplifier 126, and each pixel 10 in the pixel array 110. And a voltage supply circuit 128 for supplying the voltage.
  • the peripheral circuit 120 is provided on the semiconductor substrate 60 on which the pixel array 110 described above is formed.
  • the arrangement of peripheral circuit 120 is not limited to this example, and part or all of peripheral circuit 120 may be arranged on another substrate different from semiconductor substrate 60.
  • the vertical scanning circuit 122 is also referred to as a row scanning circuit, and has, for example, a connection with an address signal line and a reset signal line provided corresponding to each row of the plurality of pixels 10.
  • the vertical scanning circuit 122 can execute accumulation and readout of signal charges in the pixels 10 and reset of the accumulated signal charges on a row basis by supplying predetermined signals to the address signal line and the reset signal line. it can.
  • the peripheral circuit 120 may have two or more vertical scanning circuits 122. In FIG. 1, in order to avoid complication of the drawing, illustration of various signal lines such as address signal lines and reset signal lines is omitted. Arrows in FIG. 1 schematically indicate the flow of signals supplied to various signal lines such as address signal lines and reset signal lines.
  • the signal holding circuit 123 is connected to a vertical signal line (not shown) provided corresponding to each column of the plurality of pixels 10, and has a function of temporarily holding a signal output to the vertical signal line.
  • the signal may be held in the form of analog values or in the form of digital values subjected to analog-to-digital conversion.
  • the signal holding circuit 123 outputs, to the horizontal scanning circuit 124, the difference between the signal read from the pixel 10 after accumulation of the signal charge and the signal read from the pixel 10 after reset of the signal charge. .
  • the operations between the signals may be performed in analog or digital form.
  • the horizontal scanning circuit 124 also referred to as a column scanning circuit, typically includes an analog-to-digital converter circuit in part.
  • the horizontal scanning circuit 124 has a function of reading out the difference signal obtained by the signal holding circuit 123 for each row of the plurality of pixels 10 to the output stage amplifier 126.
  • the voltage supply circuit 128 is electrically connected to each pixel 10, and is configured to switch and supply two or more predetermined voltages to each pixel 10 when the imaging device 100 operates.
  • the second voltage V B is a voltage different from the first voltage V A.
  • the voltage supply circuit 128 may be configured to be capable of applying a predetermined voltage to each pixel 10 when the imaging device 100 operates, and is not limited to a specific power supply circuit.
  • the voltage supply circuit 128 may be a circuit that generates a predetermined voltage, or may be a circuit that converts a voltage supplied from another power supply into a predetermined voltage.
  • the voltage supply circuit 128 may be part of the vertical scanning circuit 122.
  • the voltage applied from the voltage supply circuit 128 to each pixel 10 is not limited to two different voltages.
  • the voltage supply circuit 128 may be configured to be able to switch between three or more different voltages and supply them to each pixel 10.
  • FIG. 2 schematically illustrates a cross section of an exemplary device structure of the pixel 10.
  • FIG. 2 schematically shows the shape, size and arrangement of each part in the pixel 10, and the shape, size and arrangement of each part shown in FIG. 2 do not necessarily reflect the shape, size and arrangement in a real device. The same applies to the other drawings of the present disclosure.
  • the pixel 10A illustrated in FIG. 2 is an example of the above-described pixel 10.
  • the pixel 10A roughly includes a part of the semiconductor substrate 60 and the photoelectric conversion unit 50A supported by the interlayer insulating layer 40 covering the semiconductor substrate 60.
  • the photoelectric conversion unit 50 ⁇ / b> A includes the photoelectric conversion layer 54 located above the region corresponding to the imaging region in the semiconductor substrate 60. That is, a stacked imaging device is illustrated as the imaging device 100 here.
  • the semiconductor substrate 60 includes a support substrate 60S and one or more semiconductor layers formed on the support substrate 60S.
  • a p-type silicon substrate is illustrated as the support substrate 60S.
  • Impurity regions 60 a to 60 e and an element isolation region 65 are provided in the semiconductor substrate 60.
  • Each of impurity regions 60a to 60e is typically an n-type diffusion region.
  • the photoelectric conversion unit 50A supported by the semiconductor substrate 60 includes the pixel electrode 52 on the interlayer insulating layer 40, the counter electrode 56 positioned farther from the semiconductor substrate 60 than the pixel electrode 52, and the pixel The photoelectric conversion layer 54 located between the electrode 52 and the counter electrode 56 is provided.
  • the pixel electrode 52 is an electrode formed of metal such as aluminum or copper, metal nitride, or polysilicon to which conductivity is imparted by doping an impurity.
  • the pixel electrode 52 is electrically separated from the pixel electrode 52 in another adjacent pixel 10A by being spatially separated.
  • the counter electrode 56 is formed of a transparent conductive material such as ITO.
  • transparent means transmitting at least a portion of light in the wavelength range to be detected, and it is not essential to transmit light over the entire wavelength range of visible light.
  • the counter electrode 56 may be formed across the plurality of pixels 10A, while the pixel electrode 52 is separated between the pixel electrodes 52 in other adjacent pixels 10A.
  • the counter electrode 56 is typically disposed above the semiconductor substrate 60 in the form of a single continuous electrode.
  • the photoelectric conversion layer 54 is formed of an organic material or an inorganic material such as amorphous silicon.
  • the photoelectric conversion layer 54 is formed, for example, by vacuum evaporation, and may have a thickness of about 500 nm.
  • the photoelectric conversion layer 54 may have a layer composed of an organic material and a layer composed of an inorganic material.
  • the photoelectric conversion layer 54 receives light incident through the counter electrode 56 and generates positive and negative charges by photoelectric conversion. Similar to the counter electrode 56, the photoelectric conversion layer 54 may also be disposed above the semiconductor substrate 60 in the form of a single continuous layer across the plurality of pixels 10A.
  • a voltage line connected to a power supply (not shown) is connected to the counter electrode 56, and the counter electrode 56 has a predetermined bias voltage when the imaging device 100 operates. Receive the supply. By controlling the potential of the counter electrode 56 by application of a predetermined bias voltage, one of the positive and negative charges generated by photoelectric conversion can be collected by the pixel electrode 52 as a signal charge.
  • the bias voltage applied to the counter electrode 56 may be supplied from the voltage supply circuit 128 described above.
  • a bias voltage that is higher than the pixel electrode 52 may be applied to the counter electrode 56.
  • positive charge Typical of positive charges as signal charges are holes. It is of course possible to use a negative charge, eg an electron, as the signal charge.
  • a bias voltage that is lower than that of the pixel electrode 52 may be applied to the counter electrode 56.
  • the pixel 10A includes the connection portion 42 disposed in the interlayer insulating layer 40. As schematically shown in FIG. 2, one end of the connection portion 42 is connected to the pixel electrode 52 of the photoelectric conversion unit 50.
  • the connection unit 42 includes a plurality of wiring layers and a plurality of plugs, and electrically connects the photoelectric conversion unit 50A to a circuit formed on the semiconductor substrate 60.
  • the plurality of wiring layers and the plurality of plugs are typically formed of a metal such as copper or tungsten or a metal compound such as metal nitride or metal oxide.
  • the signal detection transistor 72, the address transistor 74, and the reset transistor 76 are formed on the semiconductor substrate 60.
  • an n-channel field effect transistor represented by an n-channel MOS is exemplified as the signal detection transistor 72, the address transistor 74, and the reset transistor 76.
  • a p-type transistor instead of the n-type transistor.
  • an n-type silicon substrate may be used as the support substrate 60S, and the p-type is selected as the conductivity type of the impurity regions 60a to 60e.
  • the reset transistor 76 includes the impurity region 60a formed in the semiconductor substrate 60 as one of the drain region and the source region, and includes the impurity region 60b as the other of the drain region and the source region.
  • the connection portion 42 has a connection with the impurity region 60a, and therefore, the impurity region 60a is electrically connected to the pixel electrode 52 of the photoelectric conversion portion 50A through the connection portion 42. It is connected.
  • a reset voltage line for supplying a reset voltage which is a reference voltage for reset is connected to the impurity region 60b.
  • the reset transistor 76 is switched on and off to switch supply and cutoff of the reset voltage supplied from the reset voltage line to the impurity region 60a.
  • which of the impurity region 60a and the impurity region 60b functions as the drain region of the reset transistor 76 is determined by the potential of the impurity region 60a and the impurity region 60b.
  • the impurity region 60a and the impurity region 60b will be described as the drain region and the source region, respectively.
  • the drain region and the source region may be interchanged.
  • the imaging device 100 includes another transistor connected in series to the reset transistor 76, the same applies to the other transistors connected in series to the reset transistor 76.
  • the signal detection transistor 72 includes a gate insulating layer 72g on the semiconductor substrate 60, a gate electrode 72e on the gate insulating layer 72g, an impurity region 60c as a drain region, and an impurity region 60d as a source region.
  • a power supply line (not shown) is connected to the impurity region 60c, and a power supply voltage of, for example, 3.3 V is applied to the impurity region 60c from the power supply line when the imaging device 100 operates.
  • connection portion 42 is also connected to the gate electrode 72 e of the signal detection transistor 72. That is, the gate electrode 72 e of the signal detection transistor 72 is electrically connected to the pixel electrode 52 of the photoelectric conversion unit 50 A through the connection unit 42.
  • address transistor 74 includes an impurity region 60d as a drain region and an impurity region 60e as a source region.
  • the address transistor 74 is electrically connected to the signal detection transistor 72 by sharing the impurity region 60 d with the signal detection transistor 72.
  • a vertical signal line (not shown) is connected to impurity region 60e.
  • the circuit in the pixel 10A is electrically separated from the circuit in the other adjacent pixel 10A by the element isolation region 65.
  • the element isolation region 65 is also provided between the signal detection transistor 72 and the reset transistor 76.
  • connection portion 42 has a connection with the pixel electrode 52.
  • the impurity region 60 a and the gate electrode 72 e of the signal detection transistor 72 are electrically connected to the pixel electrode 52 through the connection portion 42.
  • the pixel electrode 52, the connection portion 42, the impurity region 60a, and the gate electrode 72e function as a charge storage node that temporarily holds the signal charge collected by the pixel electrode 52.
  • the pixel 10A further includes a control line 81 electrically connected to the connection portion 42.
  • the control line 81 is a signal line connected to the voltage supply circuit 128 described above. That is, here, the impurity region 60a has an electrical connection with the voltage supply circuit 128 described above. As described later, a capacitive element or the like may be interposed between the impurity region 60 a and the voltage supply circuit 128.
  • a voltage supply circuit 128 to the connecting portion 42 which constitutes a part of the charge storage nodes are electrically connected, switches the output of the voltage supply circuit 128 between the first voltage V A and the second voltage V B. This makes it possible, for example, to temporarily change the potential of the charge storage node after reset.
  • the semiconductor substrate 60 has one or more semiconductor layers on the support substrate 60S.
  • the semiconductor layer on the support substrate 60S includes a first p-type semiconductor layer 61p, an n-type semiconductor layer 61n, and a second p-type semiconductor layer 62p.
  • the above-described impurity regions 60a to 60e and the element isolation region 65 are formed in the second p-type semiconductor layer 62p as ap well.
  • the n-type semiconductor layer 61 n is located between the first p-type semiconductor layer 61 p and the second p-type semiconductor layer 62 p, and via an unshown well contact provided outside the imaging region when the imaging device 100 operates. The potential is controlled.
  • the n-type semiconductor layer 61 n suppresses the inflow of minority carriers from the support substrate 60S or the peripheral circuit 120 to the charge storage node for storing signal charges.
  • the semiconductor substrate 60 is a p-type provided between the second p-type semiconductor layer 62p and the support substrate 60S so as to penetrate the first p-type semiconductor layer 61p and the n-type semiconductor layer 61n. It has a region 63.
  • the p-type region 63 has a relatively high impurity concentration, and electrically connects the second p-type semiconductor layer 62p and the support substrate 60S to each other.
  • a substrate contact (not shown) is provided outside the imaging region, and the potential of the support substrate 60S and the second p-type semiconductor layer 62p is controlled via the substrate contact when the imaging device 100 operates. In other words, when the imaging device 100 operates, the substrate potential of the semiconductor substrate 60 is controlled via the substrate contact.
  • the voltage supply circuit 128 described above may be configured to supply the substrate potential of the semiconductor substrate 60 via the substrate contact.
  • an n-type transistor is applied as the signal detection transistor 72, the address transistor 74, and the reset transistor 76 as in the example described here, the substrate potential is typically ground.
  • impurity region 60a constitutes a part of the charge storage node that temporarily stores the signal charge generated by photoelectric conversion unit 50A. This is because the junction capacitance formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p functions as a capacitance for accumulating at least a part of the signal charge.
  • the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p produces a depletion layer.
  • lattice defects are present, and in particular, various lattice defects caused by impurities, dangling bonds, etc. exist on the surface of the semiconductor substrate 60. If a lattice defect exists in the depletion layer, for example, mixing of a charge different from the original signal charge into the impurity region 60a is likely to occur. In other words, lattice defects located in the depletion layer can cause dark current. Dark current results in a reduction in the signal-to-noise ratio and degrades the quality of the obtained image. If the depletion layer in the semiconductor substrate 60 can be reduced as much as possible to reduce lattice defects located in the depletion layer among lattice defects, it is useful because deterioration in image quality due to dark current is suppressed.
  • the impurity region 60a in order to reduce the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p, the impurity region 60a after discharging the signal charge from the impurity region 60a. It is effective to make the potential of V close to the substrate potential as much as possible. That is, it is effective to make the potential of the impurity region 60a after reset as close as possible to the substrate potential. For example, when the signal charge is a hole and the substrate potential is ground, it is useful to apply a voltage as low as possible, which is close to 0 V, as the reset voltage.
  • the potential of impurity region 60a is increased by electrical coupling through a circuit element such as a transistor connected to impurity region 60a. If it fluctuates, the potential of the impurity region 60a may fall below the substrate potential.
  • a field effect transistor when a field effect transistor is connected to an n-type impurity region in a floating node that stores signal charge, the transistor is turned on and on due to the effect of electrical coupling via parasitic capacitance between the source and drain.
  • the potential of the impurity region may decrease due to the switching off.
  • forward bias is applied to the pn junction between the impurity region and the surrounding p well, and from the p-type silicon substrate as a support substrate Holes will flow into the impurity region. That is, there is a possibility that dark current occurs and the image quality of the obtained image is degraded.
  • the present inventors have repeated studies in view of the above, for example, by varying the potential of the charge storage node after the reset by switching the first voltage V A and the second voltage V B, impurities accumulate signal charge region It has been found that it is possible to prevent the charge different from the original signal charge from being mixed in the impurity region with the switching on and off of the connected transistor.
  • FIG. 3 schematically shows a typical example of the circuit configuration of the pixel 10A shown in FIG. Note that, in FIG. 2, illustration of voltage lines for supplying a predetermined bias voltage to the counter electrode 56 of the photoelectric conversion unit 50A is omitted in FIG. 2 in order to prevent the drawing from becoming excessively complicated. Likewise, in the following drawings, illustration of voltage lines for supplying a predetermined bias voltage to the counter electrode 56 is omitted.
  • the gate of the signal detection transistor 72 is connected to the photoelectric conversion unit 50A. It can be said that the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 corresponds to a charge storage node. A voltage corresponding to the signal charge stored in the node FDa is applied to the gate of the signal detection transistor 72. As shown, the drain of the signal detection transistor 72 is connected to a power supply line 82 as a source follower power supply for supplying the power supply voltage Vdd, and the source of the signal detection transistor 72 is a vertical signal via the address transistor 74. Line 89 is connected. That is, the signal detection transistor 72 and the address transistor 74 form a source follower.
  • An address signal line 84 connected to the vertical scanning circuit 122 is connected to the gate of the address transistor 74.
  • the vertical scanning circuit 122 can read out the signal from the pixel 10 A to the vertical signal line 89 by controlling the address signal selsel applied to the address signal line 84.
  • the reset transistor 76 is also connected to the node FDa.
  • the side of the source and drain of the reset transistor 76 which is not connected to the node FDa is connected to the reset voltage line 85.
  • a predetermined reset voltage Vr is applied to the reset voltage line 85.
  • the reset signal line 86 connected to the vertical scanning circuit 122 is connected to the gate of the reset transistor 76. Under control of the reset signal ⁇ rst applied to the reset signal line 86, the vertical scanning circuit 122 can turn on the reset transistor 76 and apply the reset voltage Vr to the charge storage node. As described with reference to FIG.
  • the reset transistor 76 includes the impurity region 60a forming a part of the charge storage node as a drain region or a source region. When the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node, and the potential of the charge storage node is reset.
  • the voltage supply circuit 128 is further electrically connected to the node FDa.
  • the capacitive element C1 is interposed between the node FDa and the control line 81 connected to the voltage supply circuit 128.
  • the node FDa is connected to one of the two terminals of the capacitive element C1. That is, in this example, one terminal of the capacitive element C1 is electrically connected to the impurity region 60a.
  • the voltage supply circuit 128 is connected to the other of the two terminals of the capacitive element C1.
  • the capacitive element C1 may have, for example, a metal-insulator-semiconductor (MIS) structure disposed in the interlayer insulating layer 40, or may be a depression-type MOS (DMOS) capacitor. Alternatively, it may be a MIM (metal-insulator-metal) structure. Adopting the MIM structure makes it easy to obtain a larger capacity value.
  • MIS metal-insulator-semiconductor
  • DMOS depression-type MOS
  • MIM metal-insulator-metal
  • voltage supply circuit 128 has switching elements 128a and 128b configured of field effect transistors or the like. That is, here, the voltage supply circuit 128, the switching by switching the switching elements 128a and 128b on and off, the voltage Vc applied to the control line 81 between the first voltage V A and the second voltage V B It is possible.
  • FIG. 4A is a timing chart for explaining an exemplary operation of the pixel 10A having the circuit configuration shown in FIG.
  • the top chart in FIG. 4A shows pulses of the horizontal synchronization signal HD.
  • the period from the rise of a certain pulse to the rise of the next pulse corresponds to 1 H which is one horizontal scanning period.
  • the reset of the pixels 10A belonging to one certain row among the plurality of pixels 10A included in the pixel array 110 and the readout of the signal from the pixels 10A are performed.
  • the double arrow SEL in FIG. 4A indicates a selection period in which the address transistor 74 of the pixel of interest is turned on, and the arrow ACC indicates a non-selection period in which the address transistor 74 is turned off.
  • the bottom chart in FIG. 4A shows temporal changes of the potential of the node FDa, ie, the potential V FD of the impurity region 60a, and the second chart from the bottom is applied from the voltage supply circuit 128 to the control line 81.
  • the temporal change of voltage Vc is shown.
  • the first voltage V A is applied to the control line 81.
  • the address signal selsel After accumulation of signal charges by exposure, the address signal selsel is set to high level at time T1. By setting the address signal selsel to a high level, a first signal of a voltage level corresponding to the signal charge stored in the charge storage node is read out to the vertical signal line 89 through the signal detection transistor 72 and the address transistor 74. The read first signal is temporarily held by the signal holding circuit 123 shown in FIG.
  • the reset signal rstrst is set to the high level, and the reset transistor 76 is turned on.
  • the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node, and the potential of the charge storage node is reset.
  • the potential V FD of the impurity regions 60a by the reset voltage Vr is applied to the node FDa falls to Vr.
  • a voltage higher than the substrate potential Vsub is used as the reset voltage Vr. Therefore, here, Vr> Vsub.
  • the substrate potential Vsub is 0 V, a positive voltage near 0 V is used as the reset voltage Vr.
  • the reset signal rstrst is set to low level, and the reset transistor 76 is turned off.
  • the reset transistor 76 includes the impurity region 60 a as a drain region or a source region. Therefore, when the reset transistor 76 is turned off, the potential V FD of the impurity region 60a may be further lowered from Vr due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76. As described above, at this time, if the potential V FD falls below the substrate potential Vsub, extra holes flow into the impurity region 60a.
  • the potential V FD of the impurity region 60a immediately after the reset transistor 76 is off is V1a satisfying the relationship of Vr>V1a> Vsub.
  • V1a may be about 0.2V. That is, the second voltage V B and appropriate selection, by switching between the output from the voltage supply circuit 128 of the first voltage V A and the second voltage V B, the potential V FD is the substrate potential Vsub of the impurity regions 60a It is prevented that it falls below.
  • a potential difference of 0.2 V can be secured at the potential V FD of the impurity region 60 a with reference to the substrate potential. That is, the inflow of unnecessary holes to the impurity region 60a due to the potential V FD falling below the substrate potential Vsub is prevented. In other words, dark current is suppressed.
  • V B the source of the reset transistor 76 - in consideration of the magnitude of the parasitic capacitance between the drain potential V FD when off the reset transistor 76 satisfies the relation of V1a> Vsub It is sufficient to select a voltage that will
  • a second signal corresponding to the voltage level of the charge storage node after discharge of the signal charge is transmitted through the address transistor 74 during a period until time T4 when the next pulse of the horizontal synchronization signal HD And read out to the vertical signal line 89.
  • the signal holding circuit 123 outputs the difference ⁇ between the first signal and the second signal to the horizontal scanning circuit 124 as a signal representing an image.
  • the address transistor 74 is turned off, and accumulation of signal charge of the next frame is started.
  • the voltage supply circuit 128 applies the first voltage V A to the impurity region 60 a during the first period from time T2 to T3 in which the reset transistor 76 is turned on. It followed, in the second period of time T3 ⁇ T4, and is configured to switch the voltage applied to the impurity regions 60a to a second voltage V B.
  • the potential V FD of the impurity regions 60a with the off of the reset transistor 76 is possible to prevent that fall below the substrate potential Vsub. Therefore, it is possible to suppress the dark current generated by the flow of extra holes into impurity region 60a.
  • capacitive element C1 since capacitive element C1 has an electrical connection with node FDa, at least one of the charge storage nodes for temporarily holding the signal charge, like impurity region 60a. Make up the department. In other words, the connection of capacitive element C1 to node FDa increases the capacitance value of the entire charge storage node. It is advantageous for the capacitance value of the capacitive element C1 to be as small as possible for the following two reasons.
  • the first reason is that an increase in the capacitance value of the entire charge storage node results in a decrease in conversion gain. If the conversion gain is lowered, the influence of noise in the subsequent stage circuit becomes large, and there is a possibility that the SN ratio may be lowered. Therefore, from the viewpoint of avoiding the decrease in the SN ratio, it is useful that the capacitance value of the capacitive element C1 be as small as possible.
  • the second reason is that if the capacitive element C1 has a relatively large capacitance value, the influence of noise mixing on the control line 81 via the capacitive element C1 to the node FDa may increase.
  • Noise included in the voltage applied to control line 81 can be mixed in node FDa by electrical coupling via capacitive element C1.
  • the configuration in which the voltage supplied to control line 81 is commonly applied to the charge storage nodes of the pixels belonging to the same row via the capacitive element C1 in other words, the first voltage V A
  • the noise on the control line 81 may appear on the image as a horizontal line noise. It is useful to be able to suppress the horizontal noise because the horizontal noise tends to be easily recognized by the viewer of the image as compared to the random noise in units of pixels.
  • capacitance value of capacitance element C1 is C 1 and the capacitance value of a portion other than capacitance element C1 of the charge storage nodes is C FD
  • the magnitude of the voltage variation transmitted to node FDa is the voltage variation of control line 81 It is represented by the product of C 1 / (C 1 + C FD )). Therefore, in terms of horizontal noise suppression, capacitance value C 1 of the capacitor C1 is advantageously as small as possible.
  • the capacitance value C 1 of the capacitor element C1, the capacitance value of the portions other than the capacitor element C1 of the charge storage node is beneficial to be smaller than C FD. It is made smaller than the capacitance value C FD portion other than the capacitive element C1 of the charge storage node capacitance value C 1 of the capacitor C1, the reduction in the SN ratio caused by connecting a capacitor C1 to the node FDa The degree may be smaller than the degree of reduction of the SN ratio when the F value is increased by one level.
  • the capacitance value C 1 of the capacitor element C1 with the degree less than half of the capacitance value C FD, the degree of reduction of the SN ratio caused by connecting a capacitor C1 to node FDa, converted to F value
  • the change can be limited to about (1/2) or less.
  • the reset voltage Vr Since a larger positive voltage is used as the reset voltage Vr, the influence of the reduction in the potential V FD of the impurity region 60a due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76 accompanying the turning off of the reset transistor 76 is small. It can be said. However, when using electrons as signal charges, it is necessary to use a higher voltage as the reset voltage Vr in order to improve the number of saturated electrons, and from the viewpoint of securing the number of saturated electrons sufficient for the required dynamic range, It is more advantageous to use holes as the charge.
  • the conductivity type of each region in the semiconductor substrate 60 may be switched between n-type and p-type.
  • the p-type transistor as the reset transistor 76 as described below, as the second voltage V B, using a voltage lower than the first voltage V A.
  • FIG. 4B is a timing chart for explaining an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10A.
  • a p-type transistor is applied to the reset transistor 76
  • a higher voltage is used as a substrate potential Vsub than when an n-type transistor is applied to the reset transistor 76.
  • Substrate potential Vsub may be, for example, about 3.3V.
  • the effect of the change in the potential V FD of the impurity region 60a due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76 is better when holes are used as signal charges. Is small. This is because of the same reason as in the case where an n-type transistor is applied to the reset transistor 76 and electrons are used as signal charges. However, in order to secure a sufficient number of saturated electrons, it is necessary to secure a sufficient potential difference between the substrate potential and the potential V FD of the impurity region 60a. On the other hand, if the signal charge is an electron, a voltage near 3.3 V which is the substrate potential may be used as the reset voltage Vr. When a p-type transistor is applied to the reset transistor 76, the signal charge is Using electrons is easier to secure a sufficient number of saturated electrons in the required dynamic range while avoiding circuit complexity.
  • FIG. 4B shows an example of operation in the case where a p-type transistor is applied to the reset transistor 76 and electrons are used as signal charges.
  • the reset transistor 76 is a p-type transistor and electrons are used as signal charges
  • the signal detection transistor 72 and the address transistor 74 are also formed on the semiconductor substrate 60 as p-type transistors.
  • the potential V FD of the impurity region 60a gradually decreases due to the accumulation of the signal charge due to the exposure.
  • the address signal selsel is set to low level at time T1 to turn on the address transistor 74, and the first signal is read out to the vertical signal line 89.
  • the reset signal rstrst is set to low level, and the reset transistor 76 is turned on.
  • the potential V FD of the impurity region 60a rises to Vr.
  • the reset voltage Vr at this time for example, a voltage of 2.8 V which is near the substrate potential Vsub and lower than the substrate potential Vsub is used.
  • the reset signal rstrst is set to the high level, and the reset transistor 76 is turned off.
  • the electrical coupling caused by the parasitic capacitance of the reset transistor 76 may further increase the potential V FD of the impurity region 60a from Vr.
  • V FD exceeds the substrate potential Vsub
  • a forward bias is applied to the pn junction between the impurity region 60a and the periphery thereof, and an n-type silicon substrate as a support substrate is redundantly connected to the impurity region 60a. Electrons flow in. In other words, dark current occurs.
  • the time T3 only a reset signal ⁇ rst a high level, and switches the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to lower than the first voltage V A second voltage V B .
  • the potential of the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 can be reduced via the capacitive element C1, As shown in FIG. 4B, the potential V FD of the impurity region 60a can be prevented from exceeding the substrate potential Vsub.
  • the potential V FD of the impurity region 60a immediately after the reset transistor 76 is turned off is V1b which satisfies the relationship Vsub>V1b> Vr.
  • V1b may be about 3.1V.
  • the reset transistor 76 After the reset transistor 76 is turned off, the second signal corresponding to the voltage level of the charge storage node after discharging the signal charge is read out to the vertical signal line 89, and the absolute value of the difference ⁇ between the first signal and the second signal is obtained. Obtained as an image signal. After obtaining the second signal, the address transistor 74 is turned off, and accumulation of signal charge of the next frame is started.
  • control line 81 is connected between the exposure period for accumulating signal charges in the charge accumulation node and the period for resetting in a non-exposure period other than the exposure period of one frame period.
  • the voltages supplied may be different from each other.
  • FIG. 4C is a timing chart for explaining another example of the operation of the pixels 10A, 10Ap and 10Aq. Similar to the example shown in FIGS. 4A and 4B, in the operation example shown in FIG. 4C, the exposure period for accumulating the signal charge in the charge storage node and the non-exposure period other than the exposure period are alternately repeated.
  • the non-exposure period includes, in part, a reset period for resetting the potential of the charge storage node to a predetermined potential.
  • the pixel 10A shown in FIG. 3 is illustrated.
  • the address signal selsel is made high.
  • ⁇ V FD (V B ⁇ V A ) (C 1 / (C 1 + C FD )) (1)
  • the potential of the node FDa at this time is read out to the vertical signal line 89 through the signal detection transistor 72 and the address transistor 74 as a first signal expressing a voltage level corresponding to the signal charge stored in the charge storage node.
  • the reset signal rstrst is made high. Thereby, the signal charge is discharged from the charge storage node through the reset transistor 76, and the potential of the charge storage node is reset to the reset voltage Vr.
  • the reset signal rstrst is set to low level, and the reset transistor 76 is turned off. From time T3 to time T4 at which the next pulse of horizontal synchronization signal HD rises, the second signal corresponding to the voltage level of the charge storage node after discharge of the signal charge is made vertical via address transistor 74. Read on line 89.
  • the difference ⁇ between the first signal read from time T1 to time T2 and the second signal read from time T3 to time T4 represents an image. It becomes a true pixel signal.
  • the voltage applied to the control line 81 is returned to the first voltage V A again.
  • the potential of the node FDa drops from Vr to V1c due to capacitive coupling via the capacitive element C1.
  • the fluctuation amount of the potential of the node FDa at this time (Vr ⁇ V1c) is equal to the above-described ⁇ V FD .
  • the fluctuation amount ⁇ V FD is controlled by determining the first voltage V A and the second voltage V B based on the above equation (1). be able to.
  • the desired ⁇ V FD can be achieved by the following procedure. First, at the time of product design, the capacitance ratio between the capacitive element C1 and a portion of the charge storage node other than the capacitive element C1 is determined from the total capacitance value of the target charge storage node. Then, the amplitude of the voltage applied to the control line 81 during actual operation, i.e., a specific voltage value of the first voltage V A and the second voltage V B is determined based on equation (1) above.
  • either the first voltage VA or the second voltage VB is at ground (0 V). Since the ground side is generally low impedance, it is possible to suppress the mixing of power supply noise from the voltage supply circuit 128 connected to the control line 81 into the charge storage node. For example, when the second voltage V B is grounded, the first voltage V A is a negative level voltage.
  • the voltage supply circuit 128, the control line 81, and supplies the first voltage V A to the exposure period for accumulating the signal charges impurity regions 60a to charge storage node includes in its part.
  • a second voltage V B different from the first voltage V A is supplied.
  • control may be employed to differ between at least the reset period and the other periods after the exposure period. According to such control, for example, the potential of the charge storage node can be temporarily reduced compared to the reset voltage Vr.
  • the potential difference between the impurity region 60a and the second p-type semiconductor layer 62p located around it and grounded, for example, can be reduced.
  • the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p is reduced, and the reduction of dark current is realized. That is, by setting the potential of the charge storage node to a low potential in the exposure period, an effect of dark current reduction can be expected.
  • the potential of the charge storage node is raised by the potential difference amount between the second voltage V B and the first voltage V A. Therefore, by adjusting this potential difference, it is possible to set the source-drain voltage of the signal detection transistor 72 and the transistor of the subsequent stage circuit within the voltage range in which these transistors can operate. Therefore, the signal detection transistor 72 and the rear stage circuit can normally read out the pixel signal or the reference signal.
  • FIG. 5 schematically shows an example of another circuit configuration of the pixel 10.
  • the pixel 10Ap illustrated in FIG. 5 includes a photoelectric conversion unit 50B instead of the photoelectric conversion unit 50A.
  • the photoelectric conversion unit 50B is, for example, a buried photodiode formed in the semiconductor substrate 60.
  • the photoelectric conversion unit 50B is connected to the gate of the signal detection transistor 72.
  • the node FDb between the photoelectric conversion unit 50B and the signal detection transistor 72 corresponds to a charge storage node.
  • the pn junction in the embedded photodiode as the photoelectric conversion unit 50B, the impurity region 60a and the gate electrode 72e function as charge storage nodes for temporarily holding the charge generated by the photoelectric conversion unit 50B.
  • Impurity region 60a may be part of a pn junction in the buried photodiode.
  • the same operation as the operation described with reference to FIGS. 4A and 4B can be applied to the imaging device 100 having the pixel 10Ap.
  • the reset signal ⁇ rst a low level
  • to switch the voltage Vc applied to the control line 81 from the voltage supply circuit 128 from the first voltage V A higher than the first voltage V A second voltage V B the potential of the node FDb can be increased through the capacitive element C1.
  • the second voltage V B the potential V FD of the impurity regions 60a is avoided that below the substrate potential Vsub, can suppress dark current.
  • the reset transistor 76 or the like is a p-type transistor and electrons are stored as signal charges, which is more advantageous because a larger dynamic range can be obtained.
  • FIG. 6 schematically shows an example of still another circuit configuration of the pixel 10.
  • the pixel 10Aq illustrated in FIG. 6 further includes the transfer transistor 79 connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
  • the transfer transistor 79 transfers the signal charge obtained by the photoelectric conversion unit 50B to a node FDc between the gate of the signal detection transistor 72 and the transfer transistor 79 at a predetermined timing.
  • the transfer transistor 79 is, for example, an n-channel MOS.
  • the transfer transistor 79 may share the impurity region 60 a with the reset transistor 76 as one of a source region and a drain region.
  • the circuit configuration shown in FIG. 6 similar to the pixel 10Ap shown in FIG. 5, by switching the voltage Vc from the first voltage V A to the second voltage V B, the potential of a floating node node FDc, capacitance
  • the potential V FD of the impurity region 60a can be avoided, for example, from rising below the substrate potential Vsub through the element C1.
  • Switching of the voltage Vc from the first voltage V A to the second voltage V B is performed, for example, at the timing of turning off the reset transistor 76 after discharging the signal charge transferred to the node FDc by turning on the reset transistor 76. Be done.
  • FIG. 7A and 7B schematically show an example of still another circuit configuration of the pixel 10.
  • the pixel 10Ar shown in FIG. 7A has a signal detection transistor 72d of a depletion type instead of the signal detection transistor 72.
  • a depletion type transistor as the signal detection transistor 72d, a high output can be obtained from the signal detection transistor 72d even when the potential of the node FDa is at a low level. Therefore, it becomes easier to secure the voltage range necessary for the operation of the current source configured of the load circuit and the like connected to the vertical signal line 89.
  • the pixel 10As shown in FIG. 7B has a configuration in which the photoelectric conversion unit 50A of the pixel 10Ar shown in FIG. 7A is replaced with a photoelectric conversion unit 50B.
  • the photoelectric conversion unit 50B is, for example, a buried photodiode formed in the semiconductor substrate 60. Even in the configuration using a photodiode, a depletion type transistor can be used as the signal detection transistor 72d.
  • FIG. 8 is a timing chart for explaining an exemplary operation of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B.
  • the waveform of the voltage Vc in the non-exposure period is different from the waveform in the operation sequence illustrated in FIG. 4C.
  • FIG. 8 wherein, in the non-exposure period, a short period of relatively high second voltage V B voltage Vc to be applied to the control line 81 from the voltage supply circuit 128.
  • the voltage Vc is switched from the first voltage V A to the relatively high second voltage V B at the rise timing of the reset signal rstrst at time T 2, and the reset signal rstrst is low at time T 3 After being switched to the level, it is returned to the first voltage V A.
  • the reset transistor 76 After the reset transistor 76 is turned off, the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the first voltage VA , thereby contributing all changes in the voltage Vc to the change in the potential of the charge storage node. It becomes possible.
  • the potential of the charge storage node drops from the reset voltage Vr by ⁇ V FD represented by the formula (1).
  • the potential of the charge storage node can be lowered to a potential V1d lower than Vr.
  • the true pixel signal representing the image of the subject is given by the difference between the first signal corresponding to the potential of the charge storage node at time T1 and the second signal corresponding to the potential of the charge storage node at time T4. .
  • the first signal is read out to the vertical signal line 89 between time T1 and time T2, and the second signal is read out to the vertical signal line 89 between time T4 and time T5. That is, in this example, when the first voltage V A is applied to the control line 81, readout of the pixel signal and the reference signal is performed. Similarly, in this example, by using a voltage of 0V as the first voltage V A, it is possible to suppress the contamination of the noise nodes FDa or node FDb in voltage output from the voltage supply circuit 128.
  • FIG. 9A and 9B schematically show an example of still another circuit configuration of the pixel 10.
  • the pixel 10At shown in FIG. 9A is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74 and the reset transistor 76 in the circuit configuration shown in FIG.
  • a pixel 10Au shown in FIG. 9B is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74 and the reset transistor 76 in the circuit configuration shown in FIG.
  • electrons are typically used as signal charges.
  • a p-type transistor is applied to the reset transistor 76, using electrons as the signal charge secures a sufficient number of saturated electrons in the required dynamic range while avoiding complication of the circuit. Cheap.
  • FIG. 10 is a timing chart for explaining an exemplary operation of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B.
  • the address signal ⁇ sel from the high level to the low level, switching the voltage Vc applied to the control line 81 to the relatively low from the first voltage V A second voltage V B .
  • the address signal selsel is maintained at the low level in the non-exposure period.
  • the potential of the charge storage node is obtained by capacitive coupling via the capacitive element C1. Decreases.
  • the variation amount ⁇ V FD of the potential at this time is expressed by the above-mentioned equation (1) by the capacitance ratio between the capacitive element C1 and the portion of the charge storage node other than the capacitive element C1. From time T1 to time T2, a signal corresponding to the voltage V FD at this time is read out to the vertical signal line 89 as a first signal.
  • the reset is performed by setting the reset signal rstrst to low level. That is, when the reset signal rstrst is set to low level, the reset transistor 76 is turned on, the signal charge stored in the node FDa or FDb is discharged through the reset transistor 76, and the potential of the charge storage node becomes the voltage Vr. It is reset.
  • the reset signal rstrst is set to the high level to turn off the reset transistor 76.
  • the second signal corresponding to the reset voltage Vr is read out to the vertical signal line 89 from time T3 to time T4.
  • the difference between the first signal read from time T1 to time T2 and the second signal read from time T3 to time T4. are output as true pixel signals.
  • the signal detection transistor 72, the address transistor 74, and the reset transistor 76 be p-type transistors.
  • the reset transistor 76 is an n-channel MOS, for example, 0 V is used as the substrate potential Vsub.
  • the reset transistor 76 is a p-channel MOS, and 0 V is adopted as the substrate potential Vsub.
  • voltage V FD is lowered along with accumulation of electrons which are signal charges in the charge storage node, so that the voltage is applied to the pn junction between impurity region 60a and the periphery thereof. It is necessary to reset the potential of the charge storage node to a potential higher than the substrate potential Vsub prior to the accumulation of the signal charge in order to avoid the forward bias of the output voltage.
  • the signal charge is an electron
  • a voltage of 3.3 V can be used as the reset voltage Vr.
  • the potential of the charge storage node drops from, for example, 3.3 V at the start of the exposure, and the potential difference between it and the substrate potential Vsub decreases. Therefore, the depletion layer width is reduced, and the effect of dark current reduction can be expected.
  • the potential V FD of impurity region 60a is set to the substrate potential Vsub to prevent the applied voltage from becoming forward bias. It can not be raised more than that.
  • the potential V FD of the impurity region 60a rises. Therefore, prior to the accumulation of the signal charge, the potential of the charge storage node is reset to a potential of, for example, 0 V lower than the substrate potential Vsub. In this case, the difference between the potential of the charge storage node at the start of exposure and the substrate potential Vsub is enlarged as compared with the case where an n-channel MOS is used as the reset transistor 76.
  • 11A and 11B schematically show an example of still another circuit configuration of the pixel 10.
  • the pixel 10Av shown in FIG. 11A further includes a transistor 71 connected between the capacitive element C and the control line 81.
  • the difference between the pixel 10Av shown in FIG. 11A and the pixel 10Aw shown in FIG. 11B is that in the pixel 10Aw, the transistor 71 is connected between the node FDa and the capacitive element C1.
  • the transistor 71 in the pixel 10Av illustrated in FIG. 11A has a function as a switching element that switches connection and disconnection between the capacitive element C1 and the voltage supply circuit 128.
  • the transistor 71 in the pixel 10Aw illustrated in FIG. 11B has a function as a switching element that switches connection and disconnection between the node FDa and the capacitive element C1.
  • the capacitance value of the entire charge storage node can be reduced.
  • capacitive element C1 can be electrically disconnected from node FDa.
  • capacitive element C1 is connected to node FDa or node FDb, and the voltage supplied to control line 81 is switched to control the potential of the charge storage node via capacitive element C1. It becomes possible. However, since the capacitance value of the entire charge storage node is increased as a result of connecting the capacitive element C1, the conversion gain at the time of converting the signal charge into a voltage may be reduced.
  • a transistor 71 may be interposed between the capacitive element C1 and the voltage supply circuit 128, or between the node FDa or the node FDb and the capacitive element C1.
  • the on / off switching of the transistor 71 can change the capacitance value of the entire charge storage node.
  • the FD potential control mode in which the potential of the charge storage node is controlled via the capacitive element C1 by switching on and off of the transistor 71, and the high gain mode in which the signal charge is efficiently converted into a voltage signal. It becomes possible to use properly.
  • the FD potential control mode is a mode in which the transistor 71 is turned on to electrically couple the voltage supply circuit 128 to the charge storage node via the capacitive element C1. In the high gain mode, the transistor 71 is turned off and the entire charge storage node is turned off. Is a mode in which the capacitance value of
  • the mode switching may be automatically performed using an exposure time or an operating temperature as a criterion that has a large influence on dark current, or may be performed based on a user's instruction.
  • the FD potential control mode may be selected for imaging under a long second exposure for over 1 second or a high temperature environment for over 80 degrees.
  • the operation sequence in the FD potential control mode may be the same as the operation sequence described with reference to FIG. 4A, FIG. 4B, FIG. 4C, FIG. 8 or FIG.
  • FIG. 11C schematically shows an example of still another circuit configuration of the pixel 10.
  • the imaging device 100 includes a load transistor 73 connected to the vertical signal line 89.
  • the load transistor 73 is, for example, an n-channel MOS, and functions as a current source 94.
  • the imaging device 100 includes a feedback circuit 90x.
  • the feedback circuit 90x includes an inverting amplifier 92 whose inverting input terminal is connected to the vertical signal line 89.
  • the inverting amplifier 92 is provided for each column of the pixels 10Ax corresponding to the vertical signal line 89, and here, the reset voltage line 85 is connected to the output terminal thereof.
  • the signal detection transistor 72, the address transistor 74, the inverting amplifier 92, and the reset transistor 76 form a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion unit 50A.
  • a voltage Vref of, for example, 1 V or near 1 V is supplied to the non-inverting input terminal of the inverting amplifier 92.
  • the voltage Vref any voltage within the range of the power supply voltage Vdd and the ground can be used.
  • the feedback loop is formed, the voltage of the vertical signal line 89 converges to the voltage Vref input to the non-inverting input terminal of the inverting amplifier 92.
  • the potential of the node FDa can be reset to a potential at which the voltage of the vertical signal line 89 becomes Vref.
  • the first signal and the second signal are read out to the vertical signal line 89 by the source follower formed by the signal detection transistor 72 and the current source 94.
  • the potential of the node FDa at the time of signal reading is low, the voltage appearing on the vertical signal line 89 via the signal detection transistor 72 is also low, and the source-drain voltage necessary for operation in the saturation region can not be secured.
  • the load transistor 73 may operate in the linear region. As a result, the source follower may not operate properly and the linearity of the signal may be degraded.
  • the current value obtained by the current source 94 is set small, it is possible to operate the load transistor 73 in the saturation region, but in this case, a problem such as a reduction in the speed required for reading out a signal may occur. Further, the voltage drop of the vertical signal line 89 may cause the input signal to the inverting amplifier 92 to be out of the operating range, and the feedback circuit 90x may not operate properly. That is, there is a possibility that the potential of the node FDa can not be reset to such a potential that the voltage of the vertical signal line 89 becomes Vref.
  • the operation sequence described with reference to FIG. 4C, FIG. 8 or FIG. 10 can be applied.
  • the potential of the charge storage node in at least a part of the period of non-exposure period, through the capacitor C1 Temporarily raise or lower.
  • the potential of the charge storage node is selectively raised in a non-exposure period other than the exposure period by switching the voltage applied from the voltage supply circuit 128 to the control line 81.
  • the load transistor 73 By setting the potential of the charge storage node to a high potential selectively in the non-exposure period, the load transistor 73 is prevented from operating in the linear region, and the first signal and the second signal are normally output from the pixel. It is possible to read out. Since the signal read operation and the feedback operation are performed during the non-exposure period, there is no problem even if the potential of the charge storage node is low such that the load transistor 73 operates in the linear region during the exposure period. Absent. By setting the potential of the charge storage node to a low potential in the exposure period, it is possible to obtain an effect that the dark current can be suppressed without deteriorating the circuit characteristics.
  • FIG. 12 schematically illustrates an example of the circuit configuration of the pixel 10B included in the imaging device according to the second embodiment of the present disclosure. Similar to the pixel 10A shown in FIG. 3, the pixel 10B shown in FIG. 12 is an example of the pixel 10 described above. The main difference between the pixel 10B shown in FIG. 12 and the pixel 10A described with reference to FIG. 3 is that the pixel 10B is not connected to the node FDa among the source and drain of the reset transistor 76. It is the point which further has the transistor 78 connected. Also, the voltage supply circuit 128 is electrically connected to a node RD between the reset transistor 76 and the transistor 78. In this example, voltage supply circuit 128 is electrically connected to impurity region 60 a via reset transistor 76.
  • each pixel 10 of the imaging device 100 may have a circuit configuration further including a transistor 78 connected to the reset transistor 76.
  • the transistor 78 is, for example, an n-channel MOS, and can include an impurity region 60 b as a source region or a drain region of the reset transistor 76 as a drain region or a source region.
  • the reset voltage line 85 is connected to the side not connected to the reset transistor 76. For example, when the imaging device 100 operates, a predetermined reset is performed. A voltage Vr is applied to the transistor 78.
  • the gate of the transistor 78 is connected to a signal line 88 for supplying the transistor 78 with a signal fb fb for controlling the on and off of the transistor 78.
  • the signal line 88 has, for example, a connection with the vertical scanning circuit 122, and the vertical scanning circuit 122 can be configured to control the potential of the signal line 88.
  • voltage supply circuit 128 is connected to a node RD between reset transistor 76 and transistor 78 via capacitive element C2. That is, in this example, the voltage supply circuit 128 is connected not to the impurity region 60a side of the reset transistor 76 but to the impurity region 60b side via the capacitive element C2.
  • the capacitive element C2 connected between the control line 81 and the impurity region 60b can have the same configuration as the above-mentioned capacitive element C1.
  • FIG. 13 shows a more specific example to which the circuit configuration shown in FIG. 12 is applied.
  • the pixel 10 ⁇ / b> Bf illustrated in FIG. 13 is an example of the pixel 10 ⁇ / b> B illustrated in FIG. 12 and includes a feedback circuit 90.
  • the feedback circuit 90 includes an inverting amplifier 92 whose inverting input terminal is connected to the vertical signal line 89, as in the example described with reference to FIG. 11C.
  • the pixel 10 ⁇ / b> Bf includes a capacitive element C ⁇ b> 3 connected in parallel to the reset transistor 76.
  • the feedback circuit 90 forms a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion unit 50A.
  • the feedback loop includes transistor 78 in part.
  • thermal noise called kTC noise occurs when the transistor is turned on or off. After resetting the potential of the node FDa, simply turning off the reset transistor 76 causes kTC noise generated by turning off the reset transistor 76 to remain at the charge storage node before the signal charge is stored.
  • the kTC noise generated with the turning off of the reset transistor can be reduced by using negative feedback as described in WO 2012/147302. The entire disclosure of WO 2012/147302 is incorporated herein by reference.
  • this node RD is a floating node.
  • the transistor 78 can include the impurity region 60b, for example, as a drain region. Therefore, when the transistor 78 is turned off, there is a possibility that the potential of the impurity region 60b may fall below the substrate potential due to electrical coupling caused by the parasitic capacitance of the transistor 78. When the potential of the impurity region 60b is lower than the substrate potential, the inflow of unnecessary holes from the p well causes an unintended fluctuation of the potential in the impurity region 60b, which may lower the SN ratio.
  • the voltage supply circuit 128 is electrically connected to the impurity region 60 b. As described below, by switching the voltage Vc to be applied to the control line 81 from the voltage supply circuit 128 between the first voltage V A and the second voltage V B, the potential of the impurity region 60b is lower than the substrate potential Can be prevented.
  • FIG. 14A is a timing chart for describing an exemplary operation of the pixel 10Bf having the circuit configuration shown in FIG.
  • the second chart from the bottom in FIG. 14A shows temporal changes in the potential of the node RD, ie, the potential V RD of the impurity region 60b.
  • Vc the potential of the node RD
  • V A the potential of the impurity region 60b.
  • the address signal selsel is set to the high level. At this time, the first signal of the voltage level corresponding to the signal charge stored in the charge storage node is read out.
  • the reset signal rstrst and the signal fbfb are set to the high level. That is, the reset transistor 76 and the transistor 78 are turned on. The turning on of the reset transistor 76 and the transistor 78 forms a feedback loop. The formation of the feedback loop resets the potential of the node FDa.
  • the potential of the node FDa is lowered to the voltage V2a such that the voltage of the vertical signal line 89 becomes Vref.
  • a voltage that satisfies the relationship of V2a> Vsub is used as the voltage Vref applied to the non-inversion amplification terminal of the inversion amplifier 92.
  • the potential V RD of the node RD with the ON of the reset transistor 76 and the transistor 78 is increased to V3.
  • the voltage V3 satisfies the relationship of V3> Vsub.
  • the reset signal rstrst is set to low level, and the reset transistor 76 is turned off.
  • the potential V FD of the impurity region 60a is lowered from V2a to V4a as the reset transistor 76 is turned off.
  • the potential V FD falls below the substrate potential Vsub, extra holes flow into the impurity region 60a.
  • the relationship of V4a> Vsub is satisfied by properly selecting the voltage Vref. From the viewpoint of reducing the depletion layer as much as possible, it is useful that V4a be as close as possible to Vsub as long as the relationship of V4a> Vsub is satisfied.
  • the capacitive element C3 is interposed between the node FDa and the node RD, and while the transistor 78 is not turned off, a feedback loop including the capacitive element C3 in its path is formed. Condition will continue. Therefore, the signal output from the transistor 78 is attenuated by the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa itself.
  • the signal fbfb is set to low level, and the transistor 78 is turned off.
  • the time T4 just off the reset transistor 76, which switches the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to a second voltage V B.
  • the electrical coupling caused by the parasitic capacitance of the transistor 78 lowers the potential V RD of the impurity region 60b.
  • the potential V RD decreases from V3 to V5a as the transistor 78 is turned off. At this time, if V5a ⁇ Vsub, extra holes causing noise will flow into the impurity region 60b.
  • the voltage supply circuit 128 at the timing of switching off the transistor 78 from ON, than the first voltage V A voltage Vc from the first voltage V A and it is configured to switch to a higher second voltage V B.
  • the voltage Vc from the first voltage V A to the second voltage V B it is possible to increase the potential V RD of the node RD via the capacitor C2, the potential V RD falls below the substrate potential It can prevent.
  • the potential of the signal line 88 may be gradually lowered from the high level to the low level so as to cross the threshold voltage of the transistor 78.
  • the resistance of the transistor 78 is gradually increased.
  • the operating band of the transistor 78 narrows, and the frequency range of the signal to be fed back narrows.
  • the transistor 78 When the voltage of the signal line 88 reaches a low level, the transistor 78 is turned off and the formation of the feedback loop is eliminated. At this time, if the operating band of the transistor 78 is a band sufficiently lower than the operating band of the signal detection transistor 72, the thermal noise generated in the transistor 78 is suppressed by 1 / (1 + AB) 1/2 by the feedback circuit 90. Be done.
  • a in the equation is the gain of the feedback circuit 90
  • B is the attenuation factor of the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa.
  • the transistor 78 is off means that when the transistor 78 is an n-type transistor, the voltage of the signal line 88 is set to a low level lower than the threshold voltage of the transistor 78.
  • the transistor 78 is a p-type transistor, it indicates that the voltage of the signal line 88 is at a high level higher than the threshold voltage of the transistor 78.
  • a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises. Similar to the first example described with reference to FIGS. 4A and 4B, the difference ⁇ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
  • the voltage supply circuit 128 applies the first voltage V A to the impurity region 60b during the first period in which the reset transistor 76 is on. Further, the voltage supply circuit 128, the reset transistor 76 is a transistor 78 even after having been turned off within a second time period which is switched off, and the second voltage V B is applied to the impurity regions 60b.
  • the potential V2a of the impurity region 60a when the reset transistor 76 and the transistor 78 are turned on, and the potential V4a of the impurity region 60a when the transistor 78 is further turned off are the substrate potential Vsub. It is possible to make the potential as low as possible close to the substrate potential Vsub while suppressing that Further, with respect to impurity region 60b, the potential V3 when transistor 78 is turned on and the potential V5a when transistor 78 is turned off thereafter are suppressed to the substrate potential Vsub while being suppressed below the substrate potential Vsub. The potential can be as close as possible. Therefore, generation of dark current due to fluctuation of potential V RD due to electrical coupling via transistor 78 can be suppressed, and an image signal in which image quality deterioration due to dark current is suppressed can be obtained. .
  • FIG. 14B is a timing chart for describing an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf. Similar to the example described with reference to FIG. 4B, an example using electrons as signal charges will be described here. In this case, the signal detection transistor 72 and the address transistor 74 are also typically p-type transistors.
  • the address signal selsel is set to low level, and the first signal is read out.
  • the reset transistor 76 and the transistor 78 are turned on to form a feedback loop.
  • the potential of the node FDa is reset to the voltage V2b such that the voltage of the vertical signal line 89 becomes Vref.
  • a voltage that satisfies the relationship of V2b ⁇ Vsub is used as the voltage Vref.
  • the potential V RD of the node RD rises to V 3 as the reset transistor 76 and the transistor 78 are turned on.
  • the voltage V3 satisfies the relationship of V3 ⁇ Vsub.
  • the reset transistor 76 is turned off.
  • the potential V FD of the impurity region 60a is raised from V2b to V4b. Since the potential V FD is caused dark current when outweighs the substrate potential Vsub, so that the potential V FD does not exceed the substrate potential Vsub, proper selection of voltage Vref applied to the non-inverting amplifier terminal of the inverting amplifier 92 Do. From the viewpoint of reducing the depletion layer as much as possible, it is useful that V4b be as close as possible to Vsub as long as the relationship of V4b ⁇ Vsub is satisfied.
  • the transistor 78 is turned off at time T4. At this time, the transistor 78 may be turned off by gradually raising the potential of the signal line 88 from low level to high level so as to cross the threshold voltage of the transistor 78.
  • the electrical coupling due to the parasitic capacitance of the transistor 78 may increase the potential V RD of the impurity region 60b. In this example, the potential V RD rises from V3 to V5 b as the transistor 78 is turned off.
  • a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises.
  • the difference ⁇ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
  • FIG. 15 shows a modification of the imaging device according to the second embodiment of the present disclosure.
  • the pixel 10Bp illustrated in FIG. 15 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10B illustrated in FIG. 12 is replaced with a photoelectric conversion unit 50B.
  • the operation of the imaging device 100 having the pixel 10Bp may be similar to, for example, the operation described with reference to FIG. 14A or 14B. That is, the first period the reset transistor 76 is on, the first voltage V A is applied to the impurity region 60b, the reset transistor 76 is a transistor 78 even after having been turned off is switched off 2 the period may apply operations such as applying a second voltage V B to the impurity regions 60b.
  • the potential of the node RD is floating node, capacitance It can be raised, for example, via element C2. Therefore, the dark current can be suppressed by preventing the potential V RD of the impurity region 60b from being lower than the substrate potential Vsub due to the turning off of the transistor 78.
  • a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
  • FIG. 16 shows another modified example of the imaging device according to the second embodiment of the present disclosure.
  • the pixel 10Br illustrated in FIG. 16 is also an example of the above-described pixel 10.
  • the main difference between the pixel 10Br shown in FIG. 16 and the pixel 10B described with reference to FIG. 12 is that in the pixel 10Br, the source of the transistor 78, not the node RD between the transistor 78 and the reset transistor 76.
  • the voltage supply circuit 128 is electrically connected to the side of the drain and the drain not connected to the reset transistor 76. That is, in the example shown in FIG. 16, the control line 81 connected to the voltage supply circuit 128 is connected to the side of the source and the drain of the transistor 78 which is not connected to the reset transistor 76.
  • FIG. 17A is a timing chart for illustrating an exemplary operation of the pixel 10Br having the circuit configuration shown in FIG. Compared to the operation example described with reference to FIG. 14A, the operation example shown in FIG. 17A, unlike the timing of switching the voltage applied to the control line 81 between the first voltage V A and the second voltage V B There is.
  • the address signal selsel is set to high level, and a first signal at a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read out.
  • the reset signal rstrst and the signal fbfb are set to high level, and the reset transistor 76 and the transistor 78 are turned on.
  • the voltage supply circuit 128 applies the first voltage V A to the control line 81 at time T2. Therefore, when the reset transistor 76 and the transistor 78 are turned on, the potential V FD of the impurity region 60 a and the potential V RD of the impurity region 60 b change to V A.
  • substrate potential Vsub By applying a voltage higher than the voltage applied to the substrate contact to apply substrate potential Vsub as first voltage V A , potential V FD of impurity region 60 a and potential V RD of impurity region 60 b are substrates of semiconductor substrate 60. It is possible to avoid falling below the potential Vsub.
  • the reset transistor 76 is turned off.
  • the electric potential V FD of the impurity region 60a may drop from V A due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76.
  • the potential V FD of the impurity region 60a falls below the substrate potential Vsub due to the turning off of the reset transistor 76, extra holes flow into the impurity region 60a.
  • the voltage supply circuit 128 are switched from the first voltage V A at the timing of the off the reset transistor 76 a voltage applied to the control line 81 to a second voltage V B.
  • the transistor 78 is turned on, as shown in FIG. 17A, the potential V RD impurity region 60b is changed to V B.
  • the field effect transistor has a parasitic capacitance between the source and drain, and functions as a capacitance in the off state. Therefore, by raising the voltage applied to control line 81 from first voltage V A to second voltage V B , potential V FD of impurity region 60 a can be raised via reset transistor 76 in the off state. It is. By appropriate selection of the specific value of the first voltage V A and the second voltage V B, can be reduced or offset the decreased amount of the potential V FD accompanying off the reset transistor 76, as a result, impurity regions 60a It can be avoided that the potential V FD falls below the substrate potential Vsub. In this example, the potential V FD of the impurity region 60a is changed to V6a satisfying the relationship of V6a> Vsub.
  • the transistor 78 is turned off at time T4.
  • the electrical coupling through the transistor 78 may lower the potential V RD of the impurity region 60 b due to the turning off of the transistor 78.
  • the potential V RD of the impurity region 60 b is lowered from V B to V 7 a.
  • the potential V RD of the impurity region 60 b immediately before the transistor 78 is turned off is V B. Since the transistor 78 in a state that is higher than the first voltage V A closer to the substrate potential Vsub second voltage V B is applied is turned off, the potential V RD may avoids falls below the substrate potential Vsub . As shown in FIG. 17A, the relationship of V7a> Vsub is established here.
  • the second voltage V B may be used voltage as satisfied relationship V7a> Vsub. With lowest possible voltage as the second voltage V B as long as the relationship V7a> Vsub is satisfied, it is advantageous to a reduction in the depletion layer.
  • the time T4 may be also be continuously applied to the second voltage V B to the control line 81 or later.
  • the parasitic capacitance between the source and drain of reset transistor 76 is relatively small, so that even if the potential V RD of impurity region 60 b decreases from V B to V 7 a, it has almost no effect on the potential V FD of impurity region 60 a. It does not occur.
  • a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises.
  • the difference ⁇ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
  • the voltage supply circuit 128 applies the first voltage V A to the impurity region 60b during the first period in which the reset transistor 76 is on is described with reference to FIG. 14A.
  • Such control can also prevent the potential V RD of the impurity region 60 b from falling below the substrate potential Vsub. Further, it is possible to suppress the generation of dark current due to the fluctuation of the potential V FD of the impurity region 60 a due to the electrical coupling through the reset transistor 76 in the off state.
  • the transistor 78 is off after time T4 and the source-drain is non-conductive, but since the parasitic capacitance is provided between the source and drain, the transistor 78 functions as a capacitance. That is, the electrical coupling due to the parasitic capacitance of the transistor 78 can be used to control the potential V RD of the impurity region 60 b.
  • the potential V.sub.RD is prevented from falling below the substrate potential V.sub.sub with the turning off of the transistor 78, thereby preventing extra holes from flowing into the impurity region 60b. obtain.
  • the transistor 78 after being turned off can exhibit the same function as the capacitive element C2 shown in FIG.
  • the capacitance value of the source-drain parasitic capacitance is generally relatively small. Therefore, as the circuit configuration illustrated in FIG. 12, a voltage supply circuit 128 through the capacitor C2 having a greater capacitance who connected to the node RD is, as the first voltage V A and the second voltage V B
  • the potential V RD of the impurity region 60b can be changed more largely while applying a smaller voltage difference voltage.
  • the circuit configuration shown in FIG. 12 can more effectively reduce the drop in potential V RD accompanying turning off of the transistor 78 than the circuit configuration shown in FIG. it is possible to use as the first voltage V a.
  • FIG. 17B illustrates an exemplary operation when a p-type transistor is applied to the reset transistor 76, the transistor 78, the signal detection transistor 72, and the address transistor 74 of the pixel 10Br, and electrons are used as signal charges.
  • the timing of switching the voltage applied to the control line 81 between the first voltage V A and the second voltage V B has been described with reference to FIG. 17A operation Common to the example.
  • the second voltage V B using a voltage lower than the first voltage V A.
  • the address transistor 74 is turned on, and a first signal of a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read.
  • the reset signal rstrst and the signal fbfb are set to low level, and the reset transistor 76 and the transistor 78 are turned on.
  • voltage supply circuit 128 applies first voltage V A to control line 81 at time T 2, so potential V FD of impurity region 60 a and potential V RD of impurity region 60 b are set to V A. Change.
  • the first voltage V A, the potential V FD and the potential V RD is so as not to exceed the substrate potential Vsub, using a voltage lower than the voltage giving the substrate potential Vsub.
  • the reset transistor 76 is turned off.
  • the electrical coupling caused by the parasitic capacitance of the reset transistor 76 may cause the potential V FD of the impurity region 60 a to rise from V A.
  • V A the voltage applied to the control line 81 at the timing of the off reset transistor 76 is lower than the first voltage V A second voltage V B.
  • Potential V RD of impurity region 60 b changes to V B.
  • the potential V FD of the impurity region 60 a can be reduced via the reset transistor 76 in the off state.
  • the transistor 78 as well as off the time T4, at the timing of the off-transistor 78, and returns the voltage applied to the control line 81 from the second voltage V B to the first voltage V A.
  • electrical coupling via the transistor 78 can increase the potential V RD of the impurity region 60 b.
  • the transistor 78 in a state that is lower than the first voltage V A closer to the substrate potential Vsub second voltage V B is applied to the control line 81 are turned off, the impurity regions immediately off of the transistor 78 Assuming that the potential V RD of 60b is V7b, the relationship of V7b ⁇ Vsub is established. That is avoided potential V RD will exceed the substrate potential Vsub.
  • a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises.
  • the difference ⁇ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
  • the potential V RD of the impurity region 60 b can be avoided from exceeding the substrate potential Vsub. Further, it is possible to suppress the generation of dark current due to the fluctuation of the potential V FD of the impurity region 60 a due to the electrical coupling through the reset transistor 76 in the off state.
  • the reset transistor 76 When p-type transistors are applied to the reset transistor 76, the transistor 78, the signal detection transistor 72, and the address transistor 74 of the pixel 10Br shown in FIG. 16 and electrons are used as the signal charge, the description will be given with reference to FIG. The same control as in the example given can also be applied.
  • FIG. 18 shows still another modified example of the imaging device according to the second embodiment of the present disclosure.
  • the pixel 10Bq illustrated in FIG. 18 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10Br illustrated in FIG. 16 is replaced with a photoelectric conversion unit 50B.
  • the operation of the imaging device 100 having the pixel 10Bq may be similar to the operation described with reference to FIG. 17A or 17B. That is, of the period during which the transistor 78 is turned on, a period excluding the first period the reset transistor 76 is on, may the second voltage V B is applied to operation as applied to the impurity regions 60b. According to such control, for example, the potential V RD of the impurity region 60 b can be avoided from falling below the substrate potential Vsub.
  • a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
  • Third Embodiment 19A and 19B schematically illustrate an example of a circuit configuration of a pixel included in an imaging device according to a third embodiment of the present disclosure.
  • the imaging device 140 shown in FIG. 19A has a pixel 10D. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10D has three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the pixel 10D.
  • the pixel 10Dp illustrated in FIG. 19B has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10D illustrated in FIG. 19A is replaced with a photoelectric conversion unit 50B.
  • the main difference between the pixel 10D shown in FIG. 19A and the pixel 10A described with reference to FIG. 3 is that in the pixel 10D, the voltage supply circuit 128 is not connected to the node FDa, and the node FDa and the address The point is that the signal line 84 is electrically coupled via the capacitive element C1.
  • the pixel 10D may have the same device structure as the device structure described with reference to FIG. 2 except that the control line 81 is not disposed in the interlayer insulating layer 40.
  • the terminal of the capacitive element C1 not connected to the node FDb is connected to the address signal line 84 as in the pixel 10D shown in FIG. 19A.
  • An address signal selsel is input to a terminal connected to the address signal line 84 among the terminals of the capacitive element C1. Therefore, these exemplary circuits have a configuration capable of controlling the potential of node FDa or node FDb by control of address signal selsel.
  • the address signal line 84 is connected to one of the terminals of the capacitive element C1.
  • the terminal on the side opposite to the side connected to the node FDa or the node FDb in the capacitive element C1 has a high level during the reset period, and the row is selected It is only necessary to input a control signal which is low level in a period other than the above.
  • there may be a configuration in which the reset signal rstrst or another control signal is input to a terminal of the capacitive element C1 opposite to the side connected to the node FDa or the node FDb.
  • FIG. 20 is a timing chart for illustrating an exemplary operation of the pixel 10D having the circuit configuration shown in FIG. 19A.
  • the address signal ⁇ sel is, in FIG. 20 also serve voltage Vc shown in FIG. 4C
  • Vc shown in FIG. 4C
  • [Phi H is the high level It represents the signal ⁇ H
  • ⁇ L represents the low level signal ⁇ L.
  • the low level signal ⁇ L corresponds to the first voltage V A
  • the high level signal ⁇ H corresponds to the second voltage V B.
  • the node FDa is capacitively coupled to the address signal line 84 via the capacitive element C1. Therefore, the potential of the node FDa can be raised by setting the address signal selsel to high level at time T1.
  • the variation amount ⁇ V FD of the potential at this time is expressed by the following equation (2).
  • ⁇ V FD ( ⁇ H ⁇ L ) (C 1 / (C 1 + C FD )) (2)
  • the second normal operation is normally performed within the voltage range operable in the circuit following the signal detection transistor 72. It is possible to carry out a readout of the signal.
  • the capacitive element C1 is not limited to the element having the above-described MIS structure, MIM structure, or the like.
  • the capacitive element C1 may be realized by a parasitic capacitance between wires.
  • the capacitive element C1 may be realized by a parasitic capacitance between the gate of the signal detection transistor 72 and a wiring such as a signal line.
  • FIG. 21 schematically illustrates an example of a circuit configuration of a pixel included in an imaging device according to a fourth embodiment of the present disclosure.
  • the imaging device 150 shown in FIG. 21 has a pixel 10C. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10C has three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the pixel 10C.
  • the three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 constitute a detection circuit 95 that detects the signal charge stored in the node FDa electrically connected to the photoelectric conversion unit 50A.
  • the voltage supply circuit 128 is not connected to the node FDa of the pixel 10C shown in FIG.
  • the pixel 10C may have the same device structure as the device structure described with reference to FIG. 2 except that the control line 81 is not disposed in the interlayer insulating layer 40.
  • FIG. 22A is a timing chart for describing an exemplary operation of the pixel 10C having the circuit configuration shown in FIG.
  • the address transistor 74 is turned on at time T1 after signal charge storage by exposure, and the first signal at the voltage level corresponding to the signal charge stored in the charge storage node is read out. . Thereafter, similarly to the first example, at time T2, the reset signal ⁇ ⁇ rst is set to the high level, the reset transistor 76 is turned on, and the signal charge is discharged from the charge storage node through the reset transistor 76. At this time, the potential V FD of the impurity region 60a changes to Vr. Here, Vr> Vsub.
  • the reset signal rstrst is set to low level, and the reset transistor 76 is turned off.
  • the electrical coupling caused by the parasitic capacitance of the reset transistor 76 causes the potential V FD of the impurity region 60a to drop from Vr.
  • Vr is a voltage close to the substrate potential Vsub, for example, the potential V FD after the reset transistor 76 is turned off may fall below the substrate potential Vsub.
  • the potential V FD of the impurity region 60a is lowered from Vr to V8a where V8a ⁇ Vsub.
  • the reset signal rstrst applied to the gate of the reset transistor 76 is lower than the high level signal H H and higher than the low level signal L L.
  • the voltage level signal M M is switched.
  • a voltage level that maintains the reset transistor 76 in the off state is used.
  • the reset signal rstrst By raising the reset signal rstrst from the low level to the signal M M at an intermediate voltage level while maintaining the off state of the reset transistor 76, an electrical cup due to the parasitic capacitance between the gate and the drain of the reset transistor 76 utilizing a ring, it is possible to raise the potential V FD of the impurity regions 60a to a potential higher than the substrate potential Vsub.
  • the potential V FD of the impurity region 60a is raised to V9a satisfying V9a> Vsub by raising the reset signal rstrst from the low level signal LL to an intermediate voltage level signal> M. .
  • the reset signal rstrst is raised from the low level signal L L to an intermediate voltage level signal M M , after discharge of the signal charge, ie, until time T5 when the next pulse of the horizontal synchronization signal HD rises, ie, , And reads the second signal corresponding to the voltage level of the charge storage node after reset. That is, in this example, the reading of the second signal is performed in a state where the potential V FD of the impurity region 60a is higher than the substrate potential Vsub.
  • the potential V FD of the impurity region 60 a may be temporarily lower than the substrate potential Vsub between the reading of the first signal and the reading of the second signal.
  • an intermediate voltage applied to the reset signal line 86 so that the potential V FD exceeds the substrate potential Vsub. Determine the voltage level.
  • the potential V FD of the impurity regions 60a is a short time only a period below the substrate potential Vsub, is higher than the potential V FD is the substrate potential Vsub of the impurity regions 60a after reset, the voltage level of the charge storage node after the reset The influence of dark current on the corresponding second signal can be suppressed.
  • FIG. 22B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10C shown in FIG. 21 and electrons are used as signal charges.
  • a p-type transistor is applied to the signal detection transistor 72, the address transistor 74, and the reset transistor 76 instead of the n-type transistor and electrons are used as signal charges, for example, the following operation can be applied.
  • the address transistor 74 is turned on at time T1, and a first signal of a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read out.
  • the reset signal rstrst is set to low level to turn on the reset transistor 76, and the signal charge is discharged from the charge storage node.
  • the potential V FD of the impurity region 60 a is Vr, and in this example, Vr ⁇ Vsub.
  • the reset signal rstrst is set to a high level signal ⁇ H , and the reset transistor 76 is turned off.
  • the potential V FD of the impurity region 60a is raised from Vr to V8b where V8b> Vsub.
  • the reset signal ⁇ rst applied to the gate of the reset transistor 76 is switched to the signal [Phi M of intermediate voltage level between the signal of a low level [Phi L and a high-level signal [Phi H.
  • the intermediate voltage level signal M M is higher than the low level signal L L and lower than the high level signal ⁇ H.
  • an intermediate voltage level a voltage level which keeps the reset transistor 76 in the off state is used.
  • the potential V FD of the impurity region 60 a is lower than the substrate potential Vsub at the time of reading of the second signal.
  • the potential V FD of the impurity regions 60a is lower than the substrate potential Vsub, the potential V FD of the impurity regions 60a during the period from the reading of the first signal to the read of the second signal May temporarily exceed the substrate potential Vsub.
  • the potential V FD of the impurity regions 60a is a short time only a period in excess of the substrate potential Vsub, is lower than the potential V FD is the substrate potential Vsub of the impurity regions 60a after reset, the voltage level of the charge storage node after the reset The influence of dark current on the corresponding second signal can be suppressed.
  • the vertical scanning circuit 122 includes a first level signal for turning on the reset transistor 76, a second level signal for turning off the reset transistor 76, and an intermediate level signal for the reset transistor 76.
  • the potential of the impurity region 60a is reset by sequentially applying to the gate.
  • the voltage corresponding to the intermediate level signal M M is between the voltage corresponding to the first level signal and the voltage corresponding to the second level signal so that the reset transistor 76 can maintain the off state. It is a voltage.
  • potential V FD of impurity region 60a is higher than substrate potential Vsub when intermediate level signal M M is applied to the gate of reset transistor 76, as described with reference to FIG. 22A.
  • the influence of the dark current on the second signal corresponding to the voltage level of the charge storage node after reset can be suppressed to avoid the deterioration of the image quality.
  • the potential V FD of the impurity region 60 a may be temporarily lower than the substrate potential Vsub when the signal of the second level is applied to the gate of the reset transistor 76.
  • the fourth embodiment it is possible to prevent the deterioration of the image quality due to the dark current while avoiding the circuit becoming excessively complicated.
  • the potential V FD of the impurity region 60a at the time of reading of the second signal corresponding to the voltage level of the charge storage node after reset can be set as low as possible, for example, close to the substrate potential Vsub, generation of dark current Can be effectively suppressed.
  • FIG. 23 shows a modification of the imaging device according to the fourth embodiment of the present disclosure.
  • the pixel 10Cp illustrated in FIG. 23 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10C illustrated in FIG. 21 is replaced with a photoelectric conversion unit 50B.
  • the operation of the imaging device 100 having the pixel 10Cp may be similar to the operation described with reference to FIGS. 22A and 22B.
  • a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
  • the depletion layer formed can be reduced to reduce the number of lattice defects located in the depletion layer.
  • peripheral circuit 120 including voltage supply circuit 128 or the like may be performed based on an instruction from a control circuit mounted on semiconductor substrate 60 or another substrate different from semiconductor substrate 60.
  • Each circuit included in the imaging device may be realized by an integrated circuit such as an LSI, or some or all of them may be integrated in one chip as a single circuit.
  • Each circuit included in the imaging device may be realized as an FPGA (field-programmable gate array) or may be a reconfigurable processor or the like.
  • Each circuit included in the imaging apparatus may be realized as a circuit directed to a specific process, or may be realized by a combination of a general-purpose processing circuit and a program in which the process as described in the above embodiment is described. It may be realized.
  • This program may be stored in a memory or the like formed on the semiconductor substrate 60 or another substrate.
  • FIG. 24 schematically shows functional blocks of a camera system according to a fifth embodiment of the present disclosure.
  • a camera system 200 illustrated in FIG. 24 includes an optical system 201, an imaging device 100, a signal processing circuit 203, a system controller 204, and a display device 205.
  • Camera system 200 may be, for example, a smartphone, a digital camera, a video camera, and the like.
  • the optical system 201 has, for example, a lens group including an optical zoom and a lens for autofocus and a stop.
  • a lens group including an optical zoom and a lens for autofocus and a stop.
  • any of the imaging devices described in the first to fourth embodiments can be applied.
  • the signal processing circuit 203 is, for example, a DSP (Digital Signal Processor).
  • the signal processing circuit 203 receives output data from the imaging device 100, and performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance.
  • the imaging device 100 and the signal processing circuit 203 may be realized as a single semiconductor device.
  • the semiconductor device may be, for example, a so-called SoC (System on a Chip). According to such a configuration, the electronic device including the imaging device 100 as a part thereof can be further miniaturized.
  • a system controller 204 controls the entire camera system 200.
  • the system controller 204 is typically a semiconductor integrated circuit, and is, for example, a CPU (Central Processing Unit).
  • the display device 205 is, for example, a liquid crystal display or an organic EL display.
  • the display device 205 may include an input interface such as a touch panel.
  • the user can execute selection and control of the processing content of the signal processing circuit 203 and setting of imaging conditions through the input interface using the touch pen.
  • Each of the signal detection transistor 72, the address transistor 74, the reset transistor 76, the transistor 71, the transistor 78, the load transistor 73, and the transfer transistor 79 described above may be a p-channel MOS. As described above, when these transistors are p-channel MOSs, a voltage lower than the first voltage can be applied as the second voltage.
  • the signal detection transistor 72, the address transistor 74, the reset transistor 76, the transistor 71, the transistor 78, the load transistor 73, and the transfer transistor 79 need not all be unified into either n channel MOS or p channel MOS. As these transistors, besides field effect transistors, bipolar transistors can also be used.
  • an imaging device capable of imaging with high image quality by suppressing the influence of dark current.
  • the imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, and the like.
  • the imaging device of the present disclosure can be used as a camera for a mobile device, a medical camera, a camera for a robot, a security camera, a camera mounted on a vehicle, and the like.

Abstract

An imaging device which is provided with: a semiconductor substrate which comprises a first impurity region having an n-type conductivity; a photoelectric conversion unit which is electrically connected to the first impurity region and converts light into charges; a capacitive element which has a first terminal and a second terminal, with the first terminal being electrically connected to the first impurity region; and a voltage supply circuit which is electrically connected to the second terminal. The voltage supply circuit supplies a first voltage and a second voltage, which are different from each other, to the second terminal; and the first impurity region stores positive charges among the charges produced in the photoelectric conversion unit.

Description

撮像装置Imaging device
　本開示は、撮像装置に関する。 The present disclosure relates to an imaging device.
　デジタルスチルカメラ、デジタルカメラなどにＣＣＤ（Charge Coupled Device）イメージセンサおよびＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサが広く用いられている。よく知られているように、これらのイメージセンサは、半導体基板に形成されたフォトダイオードを有する。 A charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor are widely used in digital still cameras and digital cameras. As well known, these image sensors have photodiodes formed on a semiconductor substrate.
　他方、光電変換層を有する光電変換部を半導体基板の上方に配置した構造が提案されている（例えば特許文献１）。このような構造を有する撮像装置は、積層型の撮像装置と呼ばれることがある。積層型の撮像装置は、光電変換部との電気的な接続を有するノードであって、光電変換によって生成された正および負の電荷の一方を信号電荷として一時的に蓄積する浮遊ノードを有する。この浮遊ノードは、典型的には、光電変換部を支持する半導体基板に形成された拡散領域と、光電変換部と拡散領域とを互いに電気的に接続する導電構造とを有する。半導体基板には、ＣＣＤ回路またはＣＭＯＳ回路が設けられ、浮遊ノードに蓄積された電荷量に応じた信号がＣＣＤ回路またはＣＭＯＳ回路を介して読み出される。 On the other hand, a structure in which a photoelectric conversion portion having a photoelectric conversion layer is disposed above a semiconductor substrate has been proposed (for example, Patent Document 1). An imaging device having such a structure may be referred to as a stacked imaging device. A stacked imaging device is a node having an electrical connection with a photoelectric conversion unit, and has a floating node that temporarily accumulates one of positive and negative charges generated by photoelectric conversion as a signal charge. The floating node typically has a diffusion region formed on a semiconductor substrate supporting the photoelectric conversion unit, and a conductive structure electrically connecting the photoelectric conversion unit and the diffusion region to each other. The semiconductor substrate is provided with a CCD circuit or a CMOS circuit, and a signal corresponding to the amount of charge stored in the floating node is read out via the CCD circuit or the CMOS circuit.
国際公開第２０１２／１４７３０２号International Publication No. 2012/147302
　撮像装置の分野では、ノイズ低減の要求がある。撮像装置では、光電変換によって発生した電荷を蓄積する不純物領域からの、または、不純物領域へのリーク電流により、得られる画像に劣化が生じることがある。したがって、このようなリーク電流を低減できると有益である。以下では、光電変換によって発生した電荷を蓄積する不純物領域からの、または、不純物領域へのリーク電流を単に「暗電流」と呼ぶことがある。 In the field of imaging devices, there is a need for noise reduction. In an imaging device, a leak current from an impurity region that accumulates charges generated by photoelectric conversion or to an impurity region may cause degradation in an image obtained. Therefore, it is useful to be able to reduce such leakage current. Hereinafter, the leak current from the impurity region which accumulates the charge generated by photoelectric conversion or to the impurity region may be simply referred to as “dark current”.
　本開示の限定的ではないある例示的な実施形態によれば、以下が提供される。 According to one non-limiting exemplary embodiment of the present disclosure, the following is provided.
　ｎ型の導電型の第１不純物領域を有する半導体基板と、前記第１不純物領域に電気的に接続され、光を電荷に変換する光電変換部と、第１端子および第２端子を有し、前記第１端子が前記第１不純物領域に電気的に接続された容量素子と、前記第２端子に電気的に接続された電圧供給回路とを備え、前記電圧供給回路は、互いに異なる第１の電圧および第２の電圧を前記第２端子に供給し、前記第１不純物領域は、前記光電変換部で生じた電荷のうち正電荷を蓄積する、撮像装置。 a semiconductor substrate having a first impurity region of n-type conductivity, a photoelectric conversion unit electrically connected to the first impurity region, and converting light into electric charge; a first terminal and a second terminal; The first terminal includes a capacitive element electrically connected to the first impurity region, and a voltage supply circuit electrically connected to the second terminal, wherein the voltage supply circuits are different from each other in the first A voltage and a second voltage are supplied to the second terminal, and the first impurity region stores positive charge among charges generated in the photoelectric conversion unit.
　包括的または具体的な態様は、素子、デバイス、モジュール、システムまたは方法で実現されてもよい。また、包括的または具体的な態様は、素子、デバイス、装置、モジュール、システムおよび方法の任意の組み合わせによって実現されてもよい。 The general or specific aspects may be realized in an element, a device, a module, a system or a method. Also, the comprehensive or specific aspects may be realized by any combination of elements, devices, apparatuses, modules, systems and methods.
　開示された実施形態の追加的な効果および利点は、明細書および図面から明らかになる。効果および／または利点は、明細書および図面に開示の様々な実施形態または特徴によって個々に提供され、これらの１つ以上を得るために全てを必要とはしない。 Additional advantages and benefits of the disclosed embodiments will become apparent from the description and the drawings. The advantages and / or advantages may be individually provided by the various embodiments or features disclosed in the description and the drawings, and not all may be required to obtain one or more of these.
　本開示の実施形態によれば、暗電流の抑制された撮像装置が提供される。 According to an embodiment of the present disclosure, a dark current suppressed imaging device is provided.
図１は、本開示の第１の実施形態による撮像装置の例示的な構成を模式的に示す図である。FIG. 1 is a diagram schematically illustrating an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. 図２は、画素１０の例示的なデバイス構造を模式的に示す断面図である。FIG. 2 is a cross-sectional view schematically showing an exemplary device structure of the pixel 10. 図３は、図２に示す画素１０Ａの回路構成の典型例を模式的に示す図である。FIG. 3 is a view schematically showing a typical example of the circuit configuration of the pixel 10A shown in FIG. 図４Ａは、図３に示す回路構成を有する画素１０Ａの例示的な動作を説明するためのタイミングチャートである。FIG. 4A is a timing chart for explaining an exemplary operation of the pixel 10A having the circuit configuration shown in FIG. 図４Ｂは、画素１０Ａのリセットトランジスタ７６にｐ型のトランジスタを適用したときの例示的な動作を説明するためのタイミングチャートである。FIG. 4B is a timing chart for explaining an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10A. 図４Ｃは、画素１０Ａ、１０Ａｐおよび１０Ａｑの動作の他の例を説明するためのタイミングチャートである。FIG. 4C is a timing chart for explaining another example of the operation of the pixels 10A, 10Ap and 10Aq. 図５は、画素１０の他の回路構成の例を模式的に示す図である。FIG. 5 is a view schematically showing an example of another circuit configuration of the pixel 10. 図６は、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 6 is a view schematically showing an example of still another circuit configuration of the pixel 10. 図７Ａは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 7A is a view schematically showing an example of still another circuit configuration of the pixel 10. 図７Ｂは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 7B is a view schematically showing an example of still another circuit configuration of the pixel 10. 図８は、図７Ａに示す画素１０Ａｒまたは図７Ｂに示す画素１０Ａｓの例示的な動作を説明するためのタイミングチャートである。FIG. 8 is a timing chart for explaining an exemplary operation of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B. 図９Ａは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 9A is a view schematically showing an example of still another circuit configuration of the pixel 10. 図９Ｂは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 9B is a view schematically showing an example of still another circuit configuration of the pixel 10. 図１０は、図９Ａに示す画素１０Ａｔまたは図９Ｂに示す画素１０Ａｕの例示的な動作を説明するためのタイミングチャートである。FIG. 10 is a timing chart for explaining an exemplary operation of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B. 図１１Ａは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 11A is a view schematically showing an example of still another circuit configuration of the pixel 10. 図１１Ｂは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 11B is a view schematically showing an example of still another circuit configuration of the pixel 10. 図１１Ｃは、画素１０のさらに他の回路構成の例を模式的に示す図である。FIG. 11C is a view schematically showing an example of still another circuit configuration of the pixel 10. 図１２は、本開示の第２の実施形態による撮像装置が有する画素１０Ｂの回路構成の一例を模式的に示す図である。FIG. 12 is a diagram schematically illustrating an example of a circuit configuration of the pixel 10B included in the imaging device according to the second embodiment of the present disclosure. 図１３は、図１２に示す回路構成が適用された、より具体的な例を示す図である。FIG. 13 is a diagram showing a more specific example to which the circuit configuration shown in FIG. 12 is applied. 図１４Ａは、図１３に示す回路構成を有する画素１０Ｂｆの例示的な動作を説明するためのタイミングチャートである。FIG. 14A is a timing chart for describing an exemplary operation of the pixel 10Bf having the circuit configuration shown in FIG. 図１４Ｂは、画素１０Ｂｆのリセットトランジスタ７６およびトランジスタ７８にｐ型のトランジスタを適用したときの例示的な動作を説明するためのタイミングチャートである。FIG. 14B is a timing chart for describing an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf. 図１５は、本開示の第２の実施形態による撮像装置の変形例を示す図である。FIG. 15 is a view showing a modified example of the imaging device according to the second embodiment of the present disclosure. 図１６は、本開示の第２の実施形態による撮像装置の他の変形例を示す図である。FIG. 16 is a diagram showing another modified example of the imaging device according to the second embodiment of the present disclosure. 図１７Ａは、図１６に示す回路構成を有する画素１０Ｂｒの例示的な動作を説明するためのタイミングチャートである。FIG. 17A is a timing chart for illustrating an exemplary operation of the pixel 10Br having the circuit configuration shown in FIG. 図１７Ｂは、画素１０Ｂｒのリセットトランジスタ７６およびトランジスタ７８にｐ型のトランジスタを適用し、信号電荷として電子を用いたときの例示的な動作を説明するためのタイミングチャートである。FIG. 17B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Br and electrons are used as signal charges. 図１８は、本開示の第２の実施形態による撮像装置のさらに他の変形例を示す図である。FIG. 18 is a diagram showing still another modified example of the imaging device according to the second embodiment of the present disclosure. 図１９Ａは、本開示の第３の実施形態による撮像装置が有する画素の回路構成の一例を模式的に示す図である。FIG. 19A is a diagram schematically illustrating an example of a circuit configuration of a pixel included in an imaging device according to a third embodiment of the present disclosure. 図１９Ｂは、本開示の第３の実施形態による撮像装置が有する画素の回路構成の他の一例を模式的に示す図である。FIG. 19B is a view schematically showing another example of the circuit configuration of the pixel included in the imaging device according to the third embodiment of the present disclosure. 図２０は、図１９Ａに示す回路構成を有する画素１０Ｄの例示的な動作を説明するためのタイミングチャートである。FIG. 20 is a timing chart for illustrating an exemplary operation of the pixel 10D having the circuit configuration shown in FIG. 19A. 図２１は、本開示の第４の実施形態による撮像装置が有する画素の回路構成の一例を模式的に示す図である。FIG. 21 is a diagram schematically illustrating an example of a circuit configuration of a pixel included in an imaging device according to a fourth embodiment of the present disclosure. 図２２Ａは、図２１に示す回路構成を有する画素１０Ｃの例示的な動作を説明するためのタイミングチャートである。FIG. 22A is a timing chart for describing an exemplary operation of the pixel 10C having the circuit configuration shown in FIG. 図２２Ｂは、画素１０Ｃのリセットトランジスタ７６にｐ型のトランジスタを適用し、信号電荷として電子を用いたときの例示的な動作を説明するためのタイミングチャートである。FIG. 22B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10C and electrons are used as signal charges. 図２３は、本開示の第４の実施形態による撮像装置の変形例を示す図である。FIG. 23 is a view showing a modified example of the imaging device according to the fourth embodiment of the present disclosure. 図２４は、本開示の第５の実施形態による例示的なカメラシステムを模式的に示す機能ブロック図である。FIG. 24 is a functional block diagram schematically illustrating an exemplary camera system according to a fifth embodiment of the present disclosure.
　本明細書は、以下の項目に記載の撮像装置を開示している。 This specification discloses an imaging device described in the following items.
　［項目１］
　ｎ型の導電型の第１不純物領域を有する半導体基板と、
　前記第１不純物領域に電気的に接続され、光を電荷に変換する光電変換部と、
　第１端子および第２端子を有し、前記第１端子が前記第１不純物領域に電気的に接続された容量素子と、
　前記第２端子に電気的に接続された電圧供給回路と
を備え、
　前記電圧供給回路は、互いに異なる第１の電圧および第２の電圧を前記第２端子に供給し、
　前記第１不純物領域は、前記光電変換部で生じた電荷のうち正電荷を蓄積する、撮像装置。 [Item 1]
a semiconductor substrate having a first impurity region of n-type conductivity;
A photoelectric conversion unit electrically connected to the first impurity region to convert light into charge;
A capacitive element having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first impurity region;
A voltage supply circuit electrically connected to the second terminal;
The voltage supply circuit supplies first and second voltages different from each other to the second terminal,
The imaging device according to claim 1, wherein the first impurity region stores positive charge among charges generated in the photoelectric conversion unit.
　［項目２］
　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
　前記電圧供給回路は、前記第１トランジスタがオンである第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオフである第２期間に前記第２電圧を前記第２端子に供給する、項目１に記載の撮像装置。 [Item 2]
The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off The imaging device according to item 1, wherein the second voltage is supplied to the second terminal.
　［項目３］
　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
　前記電圧供給回路は、前記正電荷を前記第１不純物領域に蓄積する第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオンである第２期間に前記第２電圧を前記第２端子に供給する、項目１に記載の撮像装置。 [Item 3]
The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
The voltage supply circuit supplies the first voltage to the second terminal during a first period in which the positive charge is accumulated in the first impurity region, and the first transistor is turned on after the first period. The imaging device according to Item 1, wherein the second voltage is supplied to the second terminal in a second period.
　［項目４］
　前記半導体基板は、第２不純物領域を有し、
　前記第１トランジスタは、前記第２不純物領域をソースおよびドレインの他方として含み、
　前記第１端子は、前記第２不純物領域に接続されている、項目２または３に記載の撮像装置。 [Item 4]
The semiconductor substrate has a second impurity region,
The first transistor includes the second impurity region as the other of a source and a drain,
The imaging device according to Item 2 or 3, wherein the first terminal is connected to the second impurity region.
　［項目５］
　前記第２電圧は、前記第１電圧よりも高い、項目２から４のいずれか一項に記載の撮像装置。 [Item 5]
The imaging device according to any one of Items 2 to 4, wherein the second voltage is higher than the first voltage.
　［項目６］
　ｐ型の導電型の第１不純物領域を有する半導体基板と、
　前記第１不純物領域に電気的に接続され、光を電荷に変換する光電変換部と、
　第１端子および第２端子を有し、前記第１端子が前記第１不純物領域に電気的に接続された容量素子と、
　前記第２端子に電気的に接続された電圧供給回路と
を備え、
　前記電圧供給回路は、互いに異なる第１の電圧および第２の電圧を前記第２端子に供給し、
　前記第１不純物領域は、前記光電変換部で生じた電荷のうち負電荷を蓄積する、撮像装置。 [Item 6]
a semiconductor substrate having a first impurity region of p-type conductivity;
A photoelectric conversion unit electrically connected to the first impurity region to convert light into charge;
A capacitive element having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first impurity region;
A voltage supply circuit electrically connected to the second terminal;
The voltage supply circuit supplies first and second voltages different from each other to the second terminal,
The imaging device according to claim 1, wherein the first impurity region stores negative charge among charges generated in the photoelectric conversion unit.
　［項目７］
　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
　前記電圧供給回路は、前記第１トランジスタがオンである第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオフである第２期間に前記第２電圧を前記第２端子に供給する、項目６に記載の撮像装置。 [Item 7]
The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off The imaging device according to Item 6, wherein the second voltage is supplied to the second terminal.
　［項目８］
　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
　前記電圧供給回路は、前記負電荷を前記第１不純物領域に蓄積する第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオンである第２期間に前記第２電圧を前記第２端子に供給する、項目６に記載の撮像装置。 [Item 8]
The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the negative charge is accumulated in the first impurity region, and the first transistor is turned on after the first period. The imaging device according to Item 6, wherein the second voltage is supplied to the second terminal in a second period.
　［項目９］
　前記半導体基板は、第２不純物領域を有し、
　前記第１トランジスタは、前記第２不純物領域をソースおよびドレインの他方として含み、
　前記第１端子は、前記第２不純物領域に接続されている、項目７または８に記載の撮像装置。 [Item 9]
The semiconductor substrate has a second impurity region,
The first transistor includes the second impurity region as the other of a source and a drain,
The imaging device according to Item 7 or 8, wherein the first terminal is connected to the second impurity region.
　［項目１０］
　前記第２電圧は、前記第１電圧よりも低い、項目７から９のいずれか一項に記載の撮像装置。 [Item 10]
The imaging device according to any one of items 7 to 9, wherein the second voltage is lower than the first voltage.
　［項目１１］
　前記容量素子および前記第１不純物領域は、前記光電変換部で生じた電荷のうち一方の極性の電荷を蓄積する電荷蓄積ノードの少なくとも一部であり、
　前記容量素子の容量値は、前記電荷蓄積ノードのうち前記容量素子以外の部分の容量値よりも小さい、項目１から１０のいずれか一項に記載の撮像装置。 [Item 11]
The capacitive element and the first impurity region are at least a part of a charge storage node that stores charges of one polarity among charges generated in the photoelectric conversion unit,
The imaging device according to any one of Items 1 to 10, wherein a capacitance value of the capacitive element is smaller than a capacitance value of a portion other than the capacitive element in the charge storage node.
　［項目１２］
　前記光電変換部は、
　　第１電極と、
　　前記第１電極に対向する第２電極と、
　　前記第１電極および前記第２電極の間に位置する光電変換層と
　を有し、
　前記第１電極は、前記第１不純物領域に電気的に接続されている、項目１から１１のいずれか一項に記載の撮像装置。 [Item 12]
The photoelectric conversion unit is
A first electrode,
A second electrode facing the first electrode;
A photoelectric conversion layer located between the first electrode and the second electrode;
12. The imaging device according to any one of items 1 to 11, wherein the first electrode is electrically connected to the first impurity region.
　［項目１３］
　前記光電変換部は、埋め込みフォトダイオードである、項目１から４および６から９のいずれか一項に記載の撮像装置。 [Item 13]
The imaging device according to any one of Items 1 to 4 and 6 to 9, wherein the photoelectric conversion unit is an embedded photodiode.
　また、本明細書は、以下の項目に記載の撮像装置を開示している。 Further, the present specification discloses an imaging device described in the following items.
　［項目１］
　第１不純物領域および第２不純物領域を有する半導体基板と、
　第１不純物領域に電気的に接続された光電変換部と、
　第１不純物領域をソース領域およびドレイン領域の一方として含み、第２不純物領域をソース領域およびドレイン領域の他方として含む第１トランジスタと、
　第２不純物領域に電気的に接続された電圧供給回路と
を備え、
　電圧供給回路は、第１トランジスタがオンである第１期間に第１電圧を第２不純物領域に印加し、第１期間の後かつ第１トランジスタがオフである第２期間に第１電圧とは異なる第２電圧を第２不純物領域に印加する、撮像装置。 [Item 1]
A semiconductor substrate having a first impurity region and a second impurity region;
A photoelectric conversion unit electrically connected to the first impurity region;
A first transistor including a first impurity region as one of a source region and a drain region and including a second impurity region as the other of the source region and the drain region;
And a voltage supply circuit electrically connected to the second impurity region,
The voltage supply circuit applies a first voltage to the second impurity region in a first period in which the first transistor is on, and after the first period and in a second period in which the first transistor is off, An imaging device applying a different second voltage to the second impurity region.
　項目１の構成によれば、第１トランジスタのオフに伴って第１不純物領域とその周囲との間のｐｎ接合に順方向バイアスがかかることによって暗電流が生じてしまうことを防止し得る。 According to the configuration of the item 1, it is possible to prevent the occurrence of dark current due to forward bias applied to the pn junction between the first impurity region and the periphery thereof when the first transistor is turned off.
　［項目２］
　第２不純物領域と電圧供給回路との間に接続された容量素子をさらに備える、項目１に記載の撮像装置。 [Item 2]
The imaging device according to Item 1, further comprising a capacitive element connected between the second impurity region and the voltage supply circuit.
　項目２の構成によれば、第１電圧および第２電圧として、より電圧差の小さな電圧を適用し得る。 According to the configuration of item 2, a voltage with a smaller voltage difference can be applied as the first voltage and the second voltage.
　［項目３］
　ソース領域およびドレイン領域の一方が第２不純物領域に電気的に接続された第２トランジスタをさらに備える、項目２に記載の撮像装置。 [Item 3]
The imaging device according to Item 2, further comprising a second transistor in which one of the source region and the drain region is electrically connected to the second impurity region.
　［項目４］
　ソース領域およびドレイン領域の一方が第２不純物領域に電気的に接続された第２トランジスタをさらに備え、
　電圧供給回路は、第２トランジスタのソース領域およびドレイン領域の他方に接続されている、項目１に記載の撮像装置。 [Item 4]
And a second transistor in which one of the source region and the drain region is electrically connected to the second impurity region,
The imaging device according to Item 1, wherein the voltage supply circuit is connected to the other of the source region and the drain region of the second transistor.
　項目４の構成によれば、第２トランジスタのオフに伴って第２不純物領域とその周囲との間のｐｎ接合に順方向バイアスがかかることによって暗電流が生じてしまうことを防止し得る。 According to the configuration of item 4, it is possible to prevent the occurrence of dark current due to forward bias applied to the pn junction between the second impurity region and the periphery thereof when the second transistor is turned off.
　［項目５］
　第２期間は、第２トランジスタがオンである期間のうち、第１期間を除く期間である、項目３または４に記載の撮像装置。 [Item 5]
The imaging device according to Item 3 or 4, wherein the second period is a period excluding the first period among the periods in which the second transistor is on.
　項目５の構成によれば、第１トランジスタを介したカップリングによる、第１不純物領域の電位の変動に起因した暗電流の発生を抑制し得る。 According to the configuration of the item 5, it is possible to suppress the generation of dark current due to the fluctuation of the potential of the first impurity region due to the coupling via the first transistor.
　［項目６］
　第２期間は、第２トランジスタがオンからオフに切り替えられた時点から開始する、項目３または４に記載の撮像装置。 [Item 6]
The imaging device according to Item 3 or 4, wherein the second period starts from the time when the second transistor is switched from on to off.
　項目６の構成によれば、第２トランジスタを介したカップリングによる、第２不純物領域の電位の変動に起因した暗電流の発生を抑制し得る。 According to the configuration of the item 6, generation of dark current due to fluctuation of the potential of the second impurity region due to coupling via the second transistor can be suppressed.
　［項目７］
　第１不純物領域を有する半導体基板と、
　第１不純物領域に電気的に接続された光電変換部と、
　第１不純物領域をソース領域およびドレイン領域の一方として含み、第１不純物領域へのリセット電圧の供給および遮断を切り替える第１トランジスタと、
　第１不純物領域に電気的に接続された電圧供給回路と
を備え、
　電圧供給回路は、第１トランジスタがオンである第１期間に第１電圧を第１不純物領域に印加し、第１期間に続く、第１トランジスタがオフとされた第２期間に第１電圧とは異なる第２電圧を第１不純物領域に印加する、撮像装置。 [Item 7]
A semiconductor substrate having a first impurity region,
A photoelectric conversion unit electrically connected to the first impurity region;
A first transistor that includes a first impurity region as one of a source region and a drain region and switches supply and shutoff of a reset voltage to the first impurity region;
A voltage supply circuit electrically connected to the first impurity region;
The voltage supply circuit applies a first voltage to the first impurity region in a first period in which the first transistor is on, and continues to the first voltage in a second period in which the first transistor is turned off. An imaging device for applying different second voltages to the first impurity region;
　項目７の構成によれば、第１トランジスタのオフに伴って第１不純物領域とその周囲との間のｐｎ接合に順方向バイアスがかかることによって暗電流が生じてしまうことを防止し得る。 According to the configuration of item 7, it is possible to prevent the occurrence of dark current due to forward bias applied to the pn junction between the first impurity region and the periphery thereof when the first transistor is turned off.
　［項目８］
　第１不純物領域と電圧供給回路との間に接続された容量素子をさらに備える、項目７に記載の撮像装置。 [Item 8]
The imaging device according to Item 7, further comprising a capacitive element connected between the first impurity region and the voltage supply circuit.
　項目８の構成によれば、第１電圧および第２電圧として、より電圧差の小さな電圧を適用し得る。 According to the configuration of item 8, a voltage with a smaller voltage difference can be applied as the first voltage and the second voltage.
　［項目９］
　ソース領域およびドレイン領域の一方が第１トランジスタのソース領域およびドレイン領域の他方に電気的に接続された第２トランジスタをさらに備え、
　電圧供給回路は、第１トランジスタを介して第１不純物領域に接続されている、項目７または８に記載の撮像装置。 [Item 9]
And a second transistor in which one of the source region and the drain region is electrically connected to the other of the source region and the drain region of the first transistor,
9. The imaging device according to item 7 or 8, wherein the voltage supply circuit is connected to the first impurity region via the first transistor.
　［項目１０］
　第２トランジスタを含み、光電変換部で発生した電気信号を負帰還させるフィードバック回路をさらに備える、項目３、４、５、６または９に記載の撮像装置。 [Item 10]
10. The imaging device according to Item 3, 4, 5, 6 or 9, further comprising a feedback circuit that includes a second transistor and negatively feeds back an electrical signal generated by the photoelectric conversion unit.
　項目１０の構成によれば、負帰還を利用してｋＴＣノイズを縮小することが可能である。 According to the configuration of item 10, it is possible to reduce kTC noise using negative feedback.
　［項目１１］
　第１トランジスタは、ｎ型であり、
　第２電圧は、第１電圧よりも高い、項目１から１０のいずれかに記載の撮像装置。 [Item 11]
The first transistor is n-type,
The imaging device according to any one of Items 1 to 10, wherein the second voltage is higher than the first voltage.
　項目１１の構成によれば、第１不純物領域の電位および／または第１トランジスタと第２トランジスタとの間のノードの電位が半導体基板の基板電位を下回ってしまうことを回避し得る。 According to the configuration of item 11, the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor can be avoided from being lower than the substrate potential of the semiconductor substrate.
　［項目１２］
　第１トランジスタは、ｐ型であり、
　第２電圧は、第１電圧よりも低い、項目１から１０のいずれかに記載の撮像装置。 [Item 12]
The first transistor is p-type,
The imaging device according to any one of Items 1 to 10, wherein the second voltage is lower than the first voltage.
　項目１２の構成によれば、第１不純物領域の電位および／または第１トランジスタと第２トランジスタとの間のノードの電位が半導体基板の基板電位を上回ってしまうことを回避し得る。 According to the configuration of item 12, it can be avoided that the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor exceeds the substrate potential of the semiconductor substrate.
　［項目１３］
　第１不純物領域を有する半導体基板と、
　第１不純物領域に電気的に接続された光電変換部と、
　第１不純物領域をソース領域およびドレイン領域の一方として含み、第１不純物領域へのリセット電圧の供給および遮断を切り替えるリセットトランジスタと、
　リセットトランジスタのゲートに接続された駆動回路と
を備え、
　駆動回路は、リセットトランジスタがオンとなる第１電圧、リセットトランジスタがオフとなる第２電圧、および、第１電圧と第２電圧の間の第３電圧をゲートに順次に印加することにより、第１不純物領域の電位のリセットを実行する、撮像装置。 [Item 13]
A semiconductor substrate having a first impurity region,
A photoelectric conversion unit electrically connected to the first impurity region;
A reset transistor that includes a first impurity region as one of a source region and a drain region and switches supply and shutoff of a reset voltage to the first impurity region;
And a drive circuit connected to the gate of the reset transistor,
The drive circuit sequentially applies to the gate a first voltage at which the reset transistor is turned on, a second voltage at which the reset transistor is turned off, and a third voltage between the first voltage and the second voltage. 1) An imaging device that executes resetting of the potential of an impurity region.
　項目１３の構成によれば、回路が過度に複雑となることを避けながら、暗電流による画質の劣化を防止し得る。 According to the configuration of the item 13, it is possible to prevent the deterioration of the image quality due to the dark current while avoiding the circuit becoming excessively complicated.
　［項目１４］
　リセットトランジスタは、ｎ型であり、
　第３電圧は、第１電圧よりも低く第２電圧よりも高い、項目１３に記載の撮像装置。 [Item 14]
The reset transistor is n-type,
14. The imaging device according to item 13, wherein the third voltage is lower than the first voltage and higher than the second voltage.
　項目１４の構成によれば、第１不純物領域の電位および／または第１トランジスタと第２トランジスタとの間のノードの電位が半導体基板の基板電位を下回ってしまうことを回避し得る。 According to the configuration of the item 14, it can be avoided that the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor becomes lower than the substrate potential of the semiconductor substrate.
　［項目１５］
　第３電圧は、駆動回路からゲートに第３電圧が印加されている状態において、第１不純物領域の電位が半導体基板の基板電位よりも高くなる電圧である、項目１３または１４に記載の撮像装置。 [Item 15]
The imaging device according to Item 13 or 14, wherein the third voltage is a voltage at which the potential of the first impurity region becomes higher than the substrate potential of the semiconductor substrate in a state where the third voltage is applied to the gate from the drive circuit. .
　項目１５の構成によれば、リセット後の電荷蓄積ノードの電圧レベルに対応する信号への暗電流の影響を抑制し得る。 According to the configuration of item 15, the influence of dark current on a signal corresponding to the voltage level of the charge storage node after reset can be suppressed.
　［項目１６］
　リセットトランジスタは、ｐ型であり、
　第３電圧は、第１電圧よりも高く第２電圧よりも低い、項目１３に記載の撮像装置。 [Item 16]
The reset transistor is p-type,
14. The imaging device according to item 13, wherein the third voltage is higher than the first voltage and lower than the second voltage.
　項目１６の構成によれば、第１不純物領域の電位および／または第１トランジスタと第２トランジスタとの間のノードの電位が半導体基板の基板電位を上回ってしまうことを回避し得る。 According to the configuration of the item 16, it is possible to avoid that the potential of the first impurity region and / or the potential of the node between the first transistor and the second transistor exceeds the substrate potential of the semiconductor substrate.
　［項目１７］
　第３電圧は、駆動回路からゲートに第３電圧が印加されている状態において、第１不純物領域の電位が半導体基板の基板電位よりも低くなる電圧である、項目１３または１６に記載の撮像装置。 [Item 17]
The imaging device according to Item 13 or 16, wherein the third voltage is a voltage at which the potential of the first impurity region becomes lower than the substrate potential of the semiconductor substrate in a state where the third voltage is applied to the gate from the drive circuit. .
　項目１７の構成によれば、リセット後の電荷蓄積ノードの電圧レベルに対応する信号への暗電流の影響を抑制し得る。 According to the configuration of item 17, it is possible to suppress the influence of dark current on the signal corresponding to the voltage level of the charge storage node after reset.
　［項目１８］
　光電変換部と、光電変換部に電気的に接続された電荷蓄積ノードと、電荷蓄積ノードに蓄積された信号電荷を検出する検出回路と、信号電荷を排出するリセットトランジスタとを備える撮像装置の駆動方法であって、
　リセットトランジスタのゲートに、リセットトランジスタがオンとなる第１電圧、リセットトランジスタがオフとなる第２電圧、および、第１電圧と第２電圧の間の第３電圧を順次に印加することにより、電荷蓄積ノードの電位のリセットを実行する、撮像装置の駆動方法。 [Item 18]
Driving of an imaging device including a photoelectric conversion unit, a charge storage node electrically connected to the photoelectric conversion unit, a detection circuit detecting a signal charge stored in the charge storage node, and a reset transistor discharging the signal charge Method,
The charge is applied sequentially to the gate of the reset transistor by applying a first voltage at which the reset transistor is turned on, a second voltage at which the reset transistor is turned off, and a third voltage between the first voltage and the second voltage. A driving method of an imaging device, which performs reset of a potential of a storage node.
　項目１８の構成によれば、回路が過度に複雑となることを避けながら、暗電流による画質の劣化を防止し得る。 According to the configuration of the item 18, it is possible to prevent the deterioration of the image quality due to the dark current while avoiding the circuit becoming excessively complicated.
　［項目１９］
　電荷蓄積ノードは、半導体基板に形成されたｎ型の第１不純物領域を含み、
　第３電圧は、第１電圧よりも低く第２電圧よりも高い、項目１８に記載の撮像装置。 [Item 19]
The charge storage node includes an n-type first impurity region formed in the semiconductor substrate,
19. The imaging device according to item 18, wherein the third voltage is lower than the first voltage and higher than the second voltage.
　［項目２０］
　電荷蓄積ノードの電位が半導体基板の基板電位よりも低くなる電圧を第２電圧として印加する、項目１９に記載の撮像装置の駆動方法。 [Item 20]
20. A method of driving an imaging device according to item 19, wherein a voltage at which the potential of the charge storage node becomes lower than the substrate potential of the semiconductor substrate is applied as a second voltage.
　［項目２１］
　電荷蓄積ノードは、半導体基板に形成されたｐ型の第１不純物領域を含み、
　第３電圧は、第１電圧よりも高く第２電圧よりも低い、項目１８に記載の撮像装置。 [Item 21]
The charge storage node includes a p-type first impurity region formed in the semiconductor substrate,
19. The imaging device according to item 18, wherein the third voltage is higher than the first voltage and lower than the second voltage.
　［項目２２］
　電荷蓄積ノードの電位が半導体基板の基板電位よりも高くなる電圧を第２電圧として印加する、項目２１に記載の撮像装置の駆動方法。 [Item 22]
22. A driving method of an imaging device according to item 21, wherein a voltage at which the potential of the charge storage node becomes higher than the substrate potential of the semiconductor substrate is applied as a second voltage.
　［項目２３］
　光電変換部は、
　　半導体基板に支持された第１電極と、
　　第２電極と、
　　第１電極および第２電極の間に位置する光電変換層と
　をさらに含み、
　第１電極は、第１不純物領域に電気的に接続されている、項目１から１７のいずれか、または、項目１９から２２のいずれかに記載の撮像装置。 [Item 23]
The photoelectric converter is
A first electrode supported on a semiconductor substrate;
A second electrode,
Further comprising a photoelectric conversion layer located between the first electrode and the second electrode;
The imaging device according to any one of Items 1 to 17 or any one of Items 19 to 22, wherein the first electrode is electrically connected to the first impurity region.
　［項目２４］
　光電変換部は、埋め込みフォトダイオードである、項目１から２３のいずれかに記載の撮像装置。 [Item 24]
24. The imaging device according to any one of items 1 to 23, wherein the photoelectric conversion unit is a buried photodiode.
　［項目２５］
　複数の画素を備える撮像装置であって、
　複数の画素のそれぞれの画素は、
　　光電変換により電荷を生成する光電変換部と、
　　電荷を蓄積する電荷蓄積ノードと、
　　電荷蓄積ノードに電気的に接続され、電荷蓄積ノードの電位を基準電位にリセットするリセットトランジスタと、
　　電荷蓄積ノードに電気的に接続され、電荷蓄積ノードに蓄積された電荷に応じた信号電圧を出力する増幅トランジスタと、
　　一端が電荷蓄積ノードに電気的に接続され、他端が電圧源に接続される容量素子と、
　を備え、
　電荷を電荷蓄積ノードに蓄積する露光期間において、容量素子の他端には第１電圧が印加され、露光期間以外の非露光期間中のリセット期間において、他端には第１電圧とは異なる第２電圧が印加され、
　リセット期間は、非露光期間の一部であり、リセットトランジスタが電荷蓄積ノードの電位を基準電位にリセットする期間である、撮像装置。 [Item 25]
An imaging device comprising a plurality of pixels, wherein
Each pixel of the plurality of pixels is
A photoelectric conversion unit that generates charges by photoelectric conversion;
A charge storage node for storing charge;
A reset transistor electrically connected to the charge storage node and resetting the potential of the charge storage node to a reference potential;
An amplification transistor electrically connected to the charge storage node and outputting a signal voltage according to the charge stored in the charge storage node;
A capacitive element having one end electrically connected to the charge storage node and the other end connected to a voltage source;
Equipped with
A first voltage is applied to the other end of the capacitive element in the exposure period in which charge is stored in the charge storage node, and the other end of the capacitive element is different from the first voltage in the reset period in the non-exposure period other than the exposure period. 2 voltage is applied,
An imaging device, wherein the reset period is a part of a non-exposure period, and a reset transistor resets the potential of the charge storage node to a reference potential.
　項目２５に記載の撮像装置によると、リーク電流を低減することが可能となる撮像装置が提供される。 According to the imaging device described in Item 25, an imaging device capable of reducing leakage current is provided.
　［項目２６］
　非露光期間の全体において、容量素子の他端に第２電圧が印加される、項目２５に記載の撮像装置。 [Item 26]
26. The imaging device according to Item 25, wherein a second voltage is applied to the other end of the capacitive element throughout the non-exposure period.
　項目２６に記載の撮像装置によると、例えば信号電荷として正孔を用いる場合、露光期間では、電荷蓄積ノードの電位を低電位に設定し、かつ、非露光期間では、電荷蓄積ノードの電位を高電位に設定することにより、回路特性を劣化させることなく、暗電流を低減することができる。 According to the imaging device described in Item 26, for example, when holes are used as signal charges, the potential of the charge storage node is set to a low potential in the exposure period, and the potential of the charge storage node is high in the non-exposure period. By setting the potential, the dark current can be reduced without deteriorating the circuit characteristics.
　［項目２７］
　容量素子は、増幅トランジスタのゲートに電気的に接続される、項目２５または２６に記載の撮像装置。 [Item 27]
27. The imaging device according to Item 25 or 26, wherein the capacitive element is electrically connected to the gate of the amplification transistor.
　項目２７に記載の撮像装置によると、容量素子の他端に印加される制御信号の電圧変化を容量素子を介してＦＤノードに与えることができる。 According to the imaging device described in Item 27, the voltage change of the control signal applied to the other end of the capacitive element can be applied to the FD node through the capacitive element.
　［項目２８］
　増幅トランジスタに電気的に接続され、信号電圧を選択的に出力する選択トランジスタをさらに備え、
　選択トランジスタの制御信号が、容量素子の他端に接続される、項目２６または２７に記載の撮像装置。 [Item 28]
And a selection transistor electrically connected to the amplification transistor and selectively outputting the signal voltage,
The imaging device according to Item 26 or 27, wherein a control signal of the selection transistor is connected to the other end of the capacitive element.
　項目２８に記載の撮像装置によると、画素内の任意の制御信号を、容量素子に与える制御信号としても用いることができるので、使用する制御信号線の数を減らすことができる。 According to the imaging device described in Item 28, any control signal in the pixel can be used also as a control signal given to the capacitive element, so the number of control signal lines used can be reduced.
　［項目２９］
　容量素子の一端と電荷蓄積ノードとの間、または、電圧源と他端との間に電気的に接続され、容量素子および電荷蓄積ノードの接続・非接続を切替えるスイッチトランジスタをさらに備える、項目２６または２７に記載の撮像装置。 [Item 29]
A switch transistor electrically connected between one end of the capacitive element and the charge storage node, or between the voltage source and the other end, for switching connection / disconnection of the capacitive element and the charge storage node, item 26 27. The imaging device according to 27.
　項目２９に記載の撮像装置によると、例えば、電荷蓄積ノードの電位を制御するＦＤ電位制御モード、および、信号電荷を効率的に変換する高ゲインモードを使い分けることが可能となる。 According to the imaging device described in Item 29, for example, it is possible to selectively use the FD potential control mode for controlling the potential of the charge storage node and the high gain mode for efficiently converting the signal charge.
　［項目３０］
　電荷は、正孔であり、
　第２電圧は第１電圧よりも高い、項目２５から２９のいずれかに記載の撮像装置。 [Item 30]
The charge is a hole,
The imaging device according to any one of items 25 to 29, wherein the second voltage is higher than the first voltage.
　項目３０に記載の撮像装置によると、リーク電流を低減することが可能な、信号電荷として正孔を用いる撮像装置を提供できる。 According to the imaging device described in Item 30, it is possible to provide an imaging device that can reduce leakage current and that uses holes as signal charges.
　［項目３１］
　リセットトランジスタおよび増幅トランジスタはＮ型トランジスタである、項目３０に記載の撮像装置。 [Item 31]
The imaging device according to Item 30, wherein the reset transistor and the amplification transistor are N-type transistors.
　項目３１に記載の撮像装置によると、信号電荷として正孔を用いる場合、リーク電流を適切に低減することが可能となる。 According to the imaging device described in Item 31, when holes are used as the signal charges, it is possible to appropriately reduce the leak current.
　［項目３２］
　電荷は、電子であり、
　第２電圧は第１電圧よりも低い、項目２５から２９のいずれかに記載の撮像装置。 [Item 32]
The charge is an electron,
The imaging device according to any one of items 25 to 29, wherein the second voltage is lower than the first voltage.
　項目３２に記載の撮像装置によると、リーク電流を低減することが可能な、信号電荷として電子を用いる撮像装置を提供できる。 According to the imaging device described in Item 32, it is possible to provide an imaging device that can reduce leakage current and that uses electrons as signal charges.
　［項目３３］
　リセットトランジスタおよび増幅トランジスタはＰ型トランジスタである、項目３２に記載の撮像装置。 [Item 33]
The imaging device according to Item 32, wherein the reset transistor and the amplification transistor are P-type transistors.
　項目３３に記載の撮像装置によると、信号電荷として電子を用いる場合、リーク電流を適切に低減することが可能となる。 According to the imaging device described in Item 33, when using electrons as the signal charge, it is possible to appropriately reduce the leak current.
　［項目３４］
　第１電圧はグランド電圧である、項目３０に記載の撮像装置。 [Item 34]
The imaging device according to Item 30, wherein the first voltage is a ground voltage.
　項目３４に記載の撮像装置によると、容量素子に印加される制御信号の電源ノイズが電荷蓄積ノードに混入することを抑制することが可能となる。 According to the imaging device described in Item 34, it is possible to suppress that the power supply noise of the control signal applied to the capacitive element is mixed in the charge storage node.
　［項目３５］
　第２電圧はグランド電圧である、項目３０に記載の撮像装置。 [Item 35]
The imaging device according to Item 30, wherein the second voltage is a ground voltage.
　項目３５に記載の撮像装置によると、容量素子に印加される制御信号の電源ノイズが電荷蓄積ノードに混入することを抑制することが可能となる。 According to the imaging device described in Item 35, it is possible to suppress the power supply noise of the control signal applied to the capacitive element from being mixed into the charge storage node.
　［項目３６］
　増幅トランジスタは、デプレッション型のトランジスタである、項目２５から３５のいずれかに記載の撮像装置。 [Item 36]
36. The imaging device according to any one of items 25 to 35, wherein the amplification transistor is a depletion type transistor.
　項目３６に記載の撮像装置によると、低レベルの電荷蓄積ノードの電位に対しても増幅トランジスタから高い出力が得られるため、ソースフォロア回路の電流源の動作に必要な電圧レンジを確保することが可能となる。 According to the imaging device described in Item 36, a high output can be obtained from the amplification transistor even for the potential of the charge storage node at a low level, so that the voltage range necessary for the operation of the current source of the source follower circuit can be secured. It becomes possible.
　［項目３７］
　光電変換部は、
　第１電極と、
　第１電極に対向する第２電極と、
　第１電極と第２電極との間に位置し、光電変換によって電荷を発生させる光電変換膜と、
を有する、項目２５から３６のいずれかに記載の撮像装置。 [Item 37]
The photoelectric converter is
A first electrode,
A second electrode facing the first electrode;
A photoelectric conversion film located between the first electrode and the second electrode and generating charges by photoelectric conversion;
The imaging device according to any one of Items 25 to 36, having:
　項目３７に記載の撮像装置によると、リーク電流を低減することが可能となる、光電変換膜を有する光電変換部を備える撮像装置が提供される。 According to the imaging device described in Item 37, there is provided an imaging device including a photoelectric conversion unit having a photoelectric conversion film, which can reduce the leakage current.
　以下、図面を参照しながら、本開示の実施形態を詳細に説明する。なお、以下で説明する実施形態は、いずれも包括的または具体的な例を示す。以下の実施形態で示される数値、形状、材料、構成要素、構成要素の配置および接続形態、ステップ、ステップの順序などは、一例であり、本開示を限定する主旨ではない。本明細書において説明される種々の態様は、矛盾が生じない限り互いに組み合わせることが可能である。また、以下の実施形態における構成要素のうち、最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。以下の説明において、実質的に同じ機能を有する構成要素は共通の参照符号で示し、説明を省略することがある。 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below all show comprehensive or specific examples. Numerical values, shapes, materials, components, arrangement and connection of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. The various aspects described herein can be combined with one another as long as no contradiction arises. Moreover, among the components in the following embodiments, components not described in the independent claim showing the highest level concept are described as optional components. In the following description, components having substantially the same function are denoted by the same reference numerals, and the description may be omitted.
　（第１の実施形態）
　図１は、本開示の第１の実施形態による撮像装置の例示的な構成を模式的に示す。図１に示す撮像装置１００は、複数の画素１０を含む画素アレイ１１０と、周辺回路１２０とを有する。 First Embodiment
FIG. 1 schematically shows an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. An imaging device 100 illustrated in FIG. 1 includes a pixel array 110 including a plurality of pixels 10 and a peripheral circuit 120.
　画素アレイ１１０は、例えばｍ行ｎ列のマトリクス状に配置された複数の画素１０を含む。ここで、ｍ、ｎは、自然数である。画素１０は、半導体基板６０に例えば２次元に配列されることにより、撮像領域を形成する。画素アレイ１１０中の画素１０の数および配置は、図示する例に限定されない。例えば、撮像装置１００に含まれる画素１０の数は、１つであってもよい。画素アレイ１１０中の画素１０の配列が一次元である場合、撮像装置１００をラインセンサとして利用することができる。 The pixel array 110 includes a plurality of pixels 10 arranged, for example, in a matrix of m rows and n columns. Here, m and n are natural numbers. The pixels 10 are two-dimensionally arranged on the semiconductor substrate 60, for example, to form an imaging region. The number and arrangement of the pixels 10 in the pixel array 110 are not limited to the illustrated example. For example, the number of pixels 10 included in the imaging device 100 may be one. When the array of the pixels 10 in the pixel array 110 is one-dimensional, the imaging device 100 can be used as a line sensor.
　各画素１０は、光の入射を受けて電荷を生成する光電変換部を含む。各画素１０の光電変換部は、半導体基板６０に形成された埋め込みフォトダイオード、または、半導体基板６０のうち撮像領域に対応する領域の上方に配置された光電変換層の一部を含む構造であり得る。なお、本明細書において、「上方」、「下方」などの用語は、あくまでも部材間の相互の配置を指定するために用いており、撮像装置１００の使用時における姿勢を限定する意図ではない。 Each pixel 10 includes a photoelectric conversion unit that receives light and generates a charge. The photoelectric conversion portion of each pixel 10 has a structure including a buried photodiode formed on the semiconductor substrate 60 or a part of the photoelectric conversion layer disposed above the region corresponding to the imaging region in the semiconductor substrate 60. obtain. In the present specification, terms such as “upper” and “lower” are used only to designate the mutual arrangement between members, and are not intended to limit the posture when using the imaging device 100.
　図１に例示する構成において、周辺回路１２０は、垂直走査回路１２２と、信号保持回路１２３と、水平走査回路１２４と、出力段アンプ１２６と、画素アレイ１１０中の各画素１０に所定の電圧を供給する電圧供給回路１２８とを含む。ここでは、周辺回路１２０は、上述の画素アレイ１１０が形成された半導体基板６０上に設けられている。しかしながら、周辺回路１２０の配置はこの例に限定されず、周辺回路１２０の一部または全部が、半導体基板６０とは異なる他の基板上に配置されてもかまわない。 In the configuration illustrated in FIG. 1, the peripheral circuit 120 has a predetermined voltage applied to the vertical scanning circuit 122, the signal holding circuit 123, the horizontal scanning circuit 124, the output stage amplifier 126, and each pixel 10 in the pixel array 110. And a voltage supply circuit 128 for supplying the voltage. Here, the peripheral circuit 120 is provided on the semiconductor substrate 60 on which the pixel array 110 described above is formed. However, the arrangement of peripheral circuit 120 is not limited to this example, and part or all of peripheral circuit 120 may be arranged on another substrate different from semiconductor substrate 60.
　垂直走査回路１２２は、行走査回路とも呼ばれ、例えば、複数の画素１０の各行に対応して設けられたアドレス信号線およびリセット信号線との接続を有する。垂直走査回路１２２は、アドレス信号線およびリセット信号線に所定の信号を供給することにより、画素１０における信号電荷の蓄積および読み出し、ならびに、蓄積された信号電荷のリセットを行単位で実行することができる。周辺回路１２０は、２以上の垂直走査回路１２２を有していてもよい。なお、図１では、図面が複雑になることを避けるために、アドレス信号線、リセット信号線などの各種の信号線の図示は省略されている。図１中の矢印は、アドレス信号線、リセット信号線などの各種の信号線に供給される信号の流れを模式的に示している。 The vertical scanning circuit 122 is also referred to as a row scanning circuit, and has, for example, a connection with an address signal line and a reset signal line provided corresponding to each row of the plurality of pixels 10. The vertical scanning circuit 122 can execute accumulation and readout of signal charges in the pixels 10 and reset of the accumulated signal charges on a row basis by supplying predetermined signals to the address signal line and the reset signal line. it can. The peripheral circuit 120 may have two or more vertical scanning circuits 122. In FIG. 1, in order to avoid complication of the drawing, illustration of various signal lines such as address signal lines and reset signal lines is omitted. Arrows in FIG. 1 schematically indicate the flow of signals supplied to various signal lines such as address signal lines and reset signal lines.
　信号保持回路１２３は、複数の画素１０の各列に対応して設けられる不図示の垂直信号線に接続されており、垂直信号線に出力される信号を一時的に保持する機能を有する。信号は、アナログ値の形で保持されてもよいし、アナログ－デジタル変換の施されたデジタル値の形で保持されてもよい。信号保持回路１２３は、例えば、信号電荷の蓄積後に画素１０から読み出された信号と、信号電荷のリセット後にその画素１０から読み出された信号との間の差分を水平走査回路１２４に出力する。信号間の演算は、アナログ、デジタルのいずれの形で実行されてもよい。水平走査回路１２４は、列走査回路とも呼ばれ、典型的には、その一部にアナログ－デジタル変換回路を含む。水平走査回路１２４は、信号保持回路１２３によって複数の画素１０の行単位で得られた、差分の信号を出力段アンプ１２６に読み出す機能を有する。 The signal holding circuit 123 is connected to a vertical signal line (not shown) provided corresponding to each column of the plurality of pixels 10, and has a function of temporarily holding a signal output to the vertical signal line. The signal may be held in the form of analog values or in the form of digital values subjected to analog-to-digital conversion. For example, the signal holding circuit 123 outputs, to the horizontal scanning circuit 124, the difference between the signal read from the pixel 10 after accumulation of the signal charge and the signal read from the pixel 10 after reset of the signal charge. . The operations between the signals may be performed in analog or digital form. The horizontal scanning circuit 124, also referred to as a column scanning circuit, typically includes an analog-to-digital converter circuit in part. The horizontal scanning circuit 124 has a function of reading out the difference signal obtained by the signal holding circuit 123 for each row of the plurality of pixels 10 to the output stage amplifier 126.
　電圧供給回路１２８は、各画素１０に電気的に接続されており、撮像装置１００の動作時に各画素１０に２以上の所定の電圧を切り替えて供給するように構成される。電圧供給回路１２８は、例えば、第１電圧ＶAおよび第２電圧ＶBを切り替えて各画素１０に供給する。ここで、第２電圧ＶBは、第１電圧ＶAとは異なる電圧である。 The voltage supply circuit 128 is electrically connected to each pixel 10, and is configured to switch and supply two or more predetermined voltages to each pixel 10 when the imaging device 100 operates. Voltage supply circuit 128, for example, supplies by switching the first voltage V A and the second voltage V B to the pixels 10. Here, the second voltage V B is a voltage different from the first voltage V A.
　電圧供給回路１２８は、撮像装置１００の動作時に各画素１０に所定の電圧を印加可能に構成されていればよく、特定の電源回路に限定されない。電圧供給回路１２８は、所定の電圧を生成する回路であってもよいし、他の電源から供給された電圧を所定の電圧に変換する回路であってもよい。電圧供給回路１２８は、垂直走査回路１２２の一部であってもよい。電圧供給回路１２８から各画素１０に印加される電圧は、互いに異なる２つの電圧に限定されない。電圧供給回路１２８は、互いに異なる３つ以上の電圧を切り替えて各画素１０に供給可能に構成されてもよい。 The voltage supply circuit 128 may be configured to be capable of applying a predetermined voltage to each pixel 10 when the imaging device 100 operates, and is not limited to a specific power supply circuit. The voltage supply circuit 128 may be a circuit that generates a predetermined voltage, or may be a circuit that converts a voltage supplied from another power supply into a predetermined voltage. The voltage supply circuit 128 may be part of the vertical scanning circuit 122. The voltage applied from the voltage supply circuit 128 to each pixel 10 is not limited to two different voltages. The voltage supply circuit 128 may be configured to be able to switch between three or more different voltages and supply them to each pixel 10.
　（画素１０のデバイス構造）
　図２は、画素１０の例示的なデバイス構造の断面を模式的に示す。図２は、画素１０における各部の形状、寸法および配置をあくまで模式的に示し、図２中に示される各部の形状、寸法および配置は、必ずしも現実のデバイスにおける形状、寸法および配置を反映しない。本開示の他の図面についても同様である。 (Device structure of pixel 10)
FIG. 2 schematically illustrates a cross section of an exemplary device structure of the pixel 10. FIG. 2 schematically shows the shape, size and arrangement of each part in the pixel 10, and the shape, size and arrangement of each part shown in FIG. 2 do not necessarily reflect the shape, size and arrangement in a real device. The same applies to the other drawings of the present disclosure.
　図２に示す画素１０Ａは、上述の画素１０の一例である。画素１０Ａは、概略的には、半導体基板６０の一部と、半導体基板６０を覆う層間絶縁層４０に支持された光電変換部５０Ａとを含む。図２に示す例では、光電変換部５０Ａは、半導体基板６０のうち撮像領域に対応する領域の上方に位置する光電変換層５４を含んでいる。すなわち、ここでは、撮像装置１００として積層型の撮像装置を例示する。 The pixel 10A illustrated in FIG. 2 is an example of the above-described pixel 10. The pixel 10A roughly includes a part of the semiconductor substrate 60 and the photoelectric conversion unit 50A supported by the interlayer insulating layer 40 covering the semiconductor substrate 60. In the example illustrated in FIG. 2, the photoelectric conversion unit 50 </ b> A includes the photoelectric conversion layer 54 located above the region corresponding to the imaging region in the semiconductor substrate 60. That is, a stacked imaging device is illustrated as the imaging device 100 here.
　図２に模式的に示すように、半導体基板６０は、支持基板６０Ｓと、支持基板６０Ｓ上に形成された１以上の半導体層とを含む。ここでは、支持基板６０Ｓとして、ｐ型シリコン基板を例示する。半導体基板６０には、不純物領域６０ａ～６０ｅおよび素子分離領域６５が設けられている。不純物領域６０ａ～６０ｅのそれぞれは、典型的には、ｎ型の拡散領域である。 As schematically shown in FIG. 2, the semiconductor substrate 60 includes a support substrate 60S and one or more semiconductor layers formed on the support substrate 60S. Here, a p-type silicon substrate is illustrated as the support substrate 60S. Impurity regions 60 a to 60 e and an element isolation region 65 are provided in the semiconductor substrate 60. Each of impurity regions 60a to 60e is typically an n-type diffusion region.
　図２に示すように、半導体基板６０に支持された光電変換部５０Ａは、層間絶縁層４０上の画素電極５２と、画素電極５２よりも半導体基板６０から遠くに位置する対向電極５６と、画素電極５２および対向電極５６の間に位置する光電変換層５４とを有する。画素電極５２は、アルミニウム、銅などの金属、金属窒化物、または、不純物がドープされることにより導電性が付与されたポリシリコンなどから形成される電極である。画素電極５２は、空間的に分離されることにより、隣接する他の画素１０Ａ中の画素電極５２から電気的に分離される。対向電極５６は、ＩＴＯなどの透明な導電性材料から形成される。本明細書における「透明」は、検出しようとする波長範囲の光の少なくとも一部を透過することを意味し、可視光の波長範囲全体にわたって光を透過することは必須ではない。画素電極５２が、隣接する他の画素１０Ａ中の画素電極５２との間で分離されることに対し、対向電極５６は、複数の画素１０Ａにわたって形成され得る。対向電極５６は、典型的には、連続した単一の電極の形で半導体基板６０の上方に配置される。 As shown in FIG. 2, the photoelectric conversion unit 50A supported by the semiconductor substrate 60 includes the pixel electrode 52 on the interlayer insulating layer 40, the counter electrode 56 positioned farther from the semiconductor substrate 60 than the pixel electrode 52, and the pixel The photoelectric conversion layer 54 located between the electrode 52 and the counter electrode 56 is provided. The pixel electrode 52 is an electrode formed of metal such as aluminum or copper, metal nitride, or polysilicon to which conductivity is imparted by doping an impurity. The pixel electrode 52 is electrically separated from the pixel electrode 52 in another adjacent pixel 10A by being spatially separated. The counter electrode 56 is formed of a transparent conductive material such as ITO. As used herein, "transparent" means transmitting at least a portion of light in the wavelength range to be detected, and it is not essential to transmit light over the entire wavelength range of visible light. The counter electrode 56 may be formed across the plurality of pixels 10A, while the pixel electrode 52 is separated between the pixel electrodes 52 in other adjacent pixels 10A. The counter electrode 56 is typically disposed above the semiconductor substrate 60 in the form of a single continuous electrode.
　光電変換層５４は、有機材料またはアモルファスシリコンなどの無機材料から形成される。光電変換層５４は、例えば、真空蒸着によって形成され、５００ｎｍ程度の厚さを有し得る。光電変換層５４が、有機材料から構成される層と無機材料から構成される層とを有していてもよい。光電変換層５４は、対向電極５６を介して入射した光を受けて、光電変換により正および負の電荷を生成する。対向電極５６と同様に、光電変換層５４も、複数の画素１０Ａにわたって連続した単一の層の形で半導体基板６０の上方に配置され得る。 The photoelectric conversion layer 54 is formed of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 54 is formed, for example, by vacuum evaporation, and may have a thickness of about 500 nm. The photoelectric conversion layer 54 may have a layer composed of an organic material and a layer composed of an inorganic material. The photoelectric conversion layer 54 receives light incident through the counter electrode 56 and generates positive and negative charges by photoelectric conversion. Similar to the counter electrode 56, the photoelectric conversion layer 54 may also be disposed above the semiconductor substrate 60 in the form of a single continuous layer across the plurality of pixels 10A.
　図２において図示が省略されているが、対向電極５６には、不図示の電源に接続された電圧線が接続されており、対向電極５６は、撮像装置１００の動作時、所定のバイアス電圧の供給を受ける。所定のバイアス電圧の印加によって対向電極５６の電位を制御することにより、光電変換によって生成された正および負の電荷のうちの一方を信号電荷として画素電極５２によって収集することができる。 Although not shown in FIG. 2, a voltage line connected to a power supply (not shown) is connected to the counter electrode 56, and the counter electrode 56 has a predetermined bias voltage when the imaging device 100 operates. Receive the supply. By controlling the potential of the counter electrode 56 by application of a predetermined bias voltage, one of the positive and negative charges generated by photoelectric conversion can be collected by the pixel electrode 52 as a signal charge.
　対向電極５６に印加されるバイアス電圧は、上述の電圧供給回路１２８から供給されてもよい。信号電荷として正の電荷を利用する場合には、画素電極５２よりも高電位となるようなバイアス電圧を対向電極５６に印加すればよい。以下では、特に断りの無い限り、信号電荷として正の電荷を利用する例を説明する。信号電荷としての正の電荷の典型的は、正孔である。信号電荷として負の電荷、例えば電子を利用することももちろん可能である。信号電荷として負の電荷を利用する場合には、画素電極５２よりも低電位となるようなバイアス電圧を対向電極５６に印加すればよい。 The bias voltage applied to the counter electrode 56 may be supplied from the voltage supply circuit 128 described above. When a positive charge is used as the signal charge, a bias voltage that is higher than the pixel electrode 52 may be applied to the counter electrode 56. In the following, unless otherwise noted, an example of using positive charge as signal charge will be described. Typical of positive charges as signal charges are holes. It is of course possible to use a negative charge, eg an electron, as the signal charge. When a negative charge is used as the signal charge, a bias voltage that is lower than that of the pixel electrode 52 may be applied to the counter electrode 56.
　画素１０Ａは、層間絶縁層４０中に配置された接続部４２を含む。図２に模式的に示すように、接続部４２の一端は、光電変換部５０の画素電極５２に接続されている。接続部４２は、複数の配線層および複数のプラグを含み、光電変換部５０Ａを、半導体基板６０に形成された回路に電気的に接続する。複数の配線層および複数のプラグは、典型的には、銅もしくはタングステンなどの金属、または、金属窒化物もしくは金属酸化物などの金属化合物から形成される。この例では、半導体基板６０に、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６が形成されている。 The pixel 10A includes the connection portion 42 disposed in the interlayer insulating layer 40. As schematically shown in FIG. 2, one end of the connection portion 42 is connected to the pixel electrode 52 of the photoelectric conversion unit 50. The connection unit 42 includes a plurality of wiring layers and a plurality of plugs, and electrically connects the photoelectric conversion unit 50A to a circuit formed on the semiconductor substrate 60. The plurality of wiring layers and the plurality of plugs are typically formed of a metal such as copper or tungsten or a metal compound such as metal nitride or metal oxide. In this example, the signal detection transistor 72, the address transistor 74, and the reset transistor 76 are formed on the semiconductor substrate 60.
　以下、特に断りの無い限り、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６として、ｎチャンネルＭＯＳに代表されるｎチャンネルの電界効果トランジスタを例示する。後述するように、ｎ型のトランジスタに代えてｐ型のトランジスタを適用することも可能である。この場合、支持基板６０Ｓとしてｎ型シリコン基板を用いればよく、不純物領域６０ａ～６０ｅの導電型としてｐ型が選ばれる。 Hereinafter, unless otherwise specified, an n-channel field effect transistor represented by an n-channel MOS is exemplified as the signal detection transistor 72, the address transistor 74, and the reset transistor 76. As described later, it is also possible to apply a p-type transistor instead of the n-type transistor. In this case, an n-type silicon substrate may be used as the support substrate 60S, and the p-type is selected as the conductivity type of the impurity regions 60a to 60e.
　リセットトランジスタ７６は、例えば、半導体基板６０に形成された不純物領域６０ａをドレイン領域およびソース領域の一方として含み、不純物領域６０ｂをドレイン領域およびソース領域の他方として含む。図２に模式的に示すように、接続部４２は、不純物領域６０ａとの接続を有し、したがって、不純物領域６０ａは、接続部４２を介して光電変換部５０Ａの画素電極５２に電気的に接続されている。 For example, the reset transistor 76 includes the impurity region 60a formed in the semiconductor substrate 60 as one of the drain region and the source region, and includes the impurity region 60b as the other of the drain region and the source region. As schematically shown in FIG. 2, the connection portion 42 has a connection with the impurity region 60a, and therefore, the impurity region 60a is electrically connected to the pixel electrode 52 of the photoelectric conversion portion 50A through the connection portion 42. It is connected.
　図２においては図示が省略されているが、不純物領域６０ｂには、リセットの基準電圧であるリセット電圧を供給するリセット電圧線が接続される。リセットトランジスタ７６は、オンおよびオフが切り替えられることにより、リセット電圧線から供給されるリセット電圧の不純物領域６０ａへの供給および遮断を切り替える。なお、不純物領域６０ａおよび不純物領域６０ｂのいずれがリセットトランジスタ７６のドレイン領域として機能するかは、不純物領域６０ａおよび不純物領域６０ｂの電位によって決まる。以下では、便宜上、不純物領域６０ａおよび不純物領域６０ｂがそれぞれドレイン領域およびソース領域であるとして説明する。ただし、撮像装置１００の使用状況によっては、ドレイン領域およびソース領域が入れ替わることもあり得る。撮像装置１００が、リセットトランジスタ７６に直列に接続される他のトランジスタを有する場合、リセットトランジスタ７６に直列に接続される他のトランジスタについても同様である。 Although not shown in FIG. 2, a reset voltage line for supplying a reset voltage which is a reference voltage for reset is connected to the impurity region 60b. The reset transistor 76 is switched on and off to switch supply and cutoff of the reset voltage supplied from the reset voltage line to the impurity region 60a. Note that which of the impurity region 60a and the impurity region 60b functions as the drain region of the reset transistor 76 is determined by the potential of the impurity region 60a and the impurity region 60b. Hereinafter, for the sake of convenience, the impurity region 60a and the impurity region 60b will be described as the drain region and the source region, respectively. However, depending on the usage condition of the imaging device 100, the drain region and the source region may be interchanged. When the imaging device 100 includes another transistor connected in series to the reset transistor 76, the same applies to the other transistors connected in series to the reset transistor 76.
　信号検出トランジスタ７２は、半導体基板６０上のゲート絶縁層７２ｇと、ゲート絶縁層７２ｇ上のゲート電極７２ｅと、ドレイン領域としての不純物領域６０ｃと、ソース領域としての不純物領域６０ｄとを含む。不純物領域６０ｃには、不図示の電源線が接続されており、撮像装置１００の動作時、不純物領域６０ｃには、電源線から例えば３．３Ｖの電源電圧が印加される。 The signal detection transistor 72 includes a gate insulating layer 72g on the semiconductor substrate 60, a gate electrode 72e on the gate insulating layer 72g, an impurity region 60c as a drain region, and an impurity region 60d as a source region. A power supply line (not shown) is connected to the impurity region 60c, and a power supply voltage of, for example, 3.3 V is applied to the impurity region 60c from the power supply line when the imaging device 100 operates.
　図２に示すように、接続部４２は、信号検出トランジスタ７２のゲート電極７２ｅにも接続されている。つまり、信号検出トランジスタ７２のゲート電極７２ｅは、接続部４２を介して光電変換部５０Ａの画素電極５２に電気的に接続されている。 As shown in FIG. 2, the connection portion 42 is also connected to the gate electrode 72 e of the signal detection transistor 72. That is, the gate electrode 72 e of the signal detection transistor 72 is electrically connected to the pixel electrode 52 of the photoelectric conversion unit 50 A through the connection unit 42.
　図２に例示する構成において、アドレストランジスタ７４は、ドレイン領域としての不純物領域６０ｄおよびソース領域としての不純物領域６０ｅを含む。ここでは、アドレストランジスタ７４は、信号検出トランジスタ７２との間で不純物領域６０ｄを共有することにより、信号検出トランジスタ７２に電気的に接続されている。不純物領域６０ｅには、不図示の垂直信号線が接続される。なお、画素１０Ａ中の回路は、素子分離領域６５により、隣接する他の画素１０Ａ中の回路から電気的に分離される。図２に示すように、素子分離領域６５は、信号検出トランジスタ７２とリセットトランジスタ７６との間にも設けられる。 In the configuration illustrated in FIG. 2, address transistor 74 includes an impurity region 60d as a drain region and an impurity region 60e as a source region. Here, the address transistor 74 is electrically connected to the signal detection transistor 72 by sharing the impurity region 60 d with the signal detection transistor 72. A vertical signal line (not shown) is connected to impurity region 60e. Note that the circuit in the pixel 10A is electrically separated from the circuit in the other adjacent pixel 10A by the element isolation region 65. As shown in FIG. 2, the element isolation region 65 is also provided between the signal detection transistor 72 and the reset transistor 76.
　上述したように、接続部４２は、画素電極５２との接続を有する。また、不純物領域６０ａ、および、信号検出トランジスタ７２のゲート電極７２ｅは、接続部４２を介して画素電極５２に電気的に接続されている。画素電極５２、接続部４２、不純物領域６０ａおよびゲート電極７２ｅは、画素電極５２によって収集された信号電荷を一時的に保持する電荷蓄積ノードとして機能する。 As described above, the connection portion 42 has a connection with the pixel electrode 52. The impurity region 60 a and the gate electrode 72 e of the signal detection transistor 72 are electrically connected to the pixel electrode 52 through the connection portion 42. The pixel electrode 52, the connection portion 42, the impurity region 60a, and the gate electrode 72e function as a charge storage node that temporarily holds the signal charge collected by the pixel electrode 52.
　図２に例示する構成において、画素１０Ａは、接続部４２に電気的に接続された制御線８１をさらに有する。制御線８１は、上述の電圧供給回路１２８に接続された信号線である。すなわち、ここでは、不純物領域６０ａは、上述の電圧供給回路１２８との間の電気的な接続を有する。なお、後述するように、不純物領域６０ａと電圧供給回路１２８との間には、容量素子などが介在し得る。電荷蓄積ノードの一部を構成する接続部４２に電圧供給回路１２８を電気的に接続し、電圧供給回路１２８の出力を第１電圧ＶAおよび第２電圧ＶB間で切り替える。これによって、例えば、リセット後の電荷蓄積ノードの電位を一時的に変化させることが可能になる。 In the configuration illustrated in FIG. 2, the pixel 10A further includes a control line 81 electrically connected to the connection portion 42. The control line 81 is a signal line connected to the voltage supply circuit 128 described above. That is, here, the impurity region 60a has an electrical connection with the voltage supply circuit 128 described above. As described later, a capacitive element or the like may be interposed between the impurity region 60 a and the voltage supply circuit 128. A voltage supply circuit 128 to the connecting portion 42 which constitutes a part of the charge storage nodes are electrically connected, switches the output of the voltage supply circuit 128 between the first voltage V A and the second voltage V B. This makes it possible, for example, to temporarily change the potential of the charge storage node after reset.
　ここで、半導体基板６０の構成の詳細を説明する。上述したように、半導体基板６０は、支持基板６０Ｓ上に１以上の半導体層を有する。この例では、支持基板６０Ｓ上の半導体層は、第１ｐ型半導体層６１ｐ、ｎ型半導体層６１ｎおよび第２ｐ型半導体層６２ｐを含む。図２に模式的に示すように、上述の不純物領域６０ａ～６０ｅおよび素子分離領域６５は、ｐウェルとしての第２ｐ型半導体層６２ｐ中に形成されている。 Here, the details of the configuration of the semiconductor substrate 60 will be described. As described above, the semiconductor substrate 60 has one or more semiconductor layers on the support substrate 60S. In this example, the semiconductor layer on the support substrate 60S includes a first p-type semiconductor layer 61p, an n-type semiconductor layer 61n, and a second p-type semiconductor layer 62p. As schematically shown in FIG. 2, the above-described impurity regions 60a to 60e and the element isolation region 65 are formed in the second p-type semiconductor layer 62p as ap well.
　ｎ型半導体層６１ｎは、第１ｐ型半導体層６１ｐと第２ｐ型半導体層６２ｐとの間に位置し、撮像装置１００の動作時、撮像領域の外側に設けられた不図示のウェルコンタクトを介してその電位が制御される。ｎ型半導体層６１ｎは、信号電荷を蓄積する電荷蓄積ノードへの支持基板６０Ｓまたは周辺回路１２０からの少数キャリアの流入を抑制する。 The n-type semiconductor layer 61 n is located between the first p-type semiconductor layer 61 p and the second p-type semiconductor layer 62 p, and via an unshown well contact provided outside the imaging region when the imaging device 100 operates. The potential is controlled. The n-type semiconductor layer 61 n suppresses the inflow of minority carriers from the support substrate 60S or the peripheral circuit 120 to the charge storage node for storing signal charges.
　図２に例示する構成において、半導体基板６０は、第１ｐ型半導体層６１ｐおよびｎ型半導体層６１ｎを貫通するようにして第２ｐ型半導体層６２ｐと支持基板６０Ｓとの間に設けられたｐ型領域６３を有する。ｐ型領域６３は、比較的高い不純物濃度を有し、第２ｐ型半導体層６２ｐと支持基板６０Ｓとを互いに電気的に接続する。撮像領域の外側には、不図示の基板コンタクトが設けられ、撮像装置１００の動作時、基板コンタクトを介して、支持基板６０Ｓおよび第２ｐ型半導体層６２ｐの電位が制御される。換言すれば、撮像装置１００の動作時、半導体基板６０の基板電位は、基板コンタクトを介して制御される。上述の電圧供給回路１２８が、基板コンタクトを介して半導体基板６０の基板電位を供給するように構成されていてもよい。ここで説明する例のように、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６としてｎ型のトランジスタを適用する場合、基板電位は、典型的には、接地である。 In the configuration illustrated in FIG. 2, the semiconductor substrate 60 is a p-type provided between the second p-type semiconductor layer 62p and the support substrate 60S so as to penetrate the first p-type semiconductor layer 61p and the n-type semiconductor layer 61n. It has a region 63. The p-type region 63 has a relatively high impurity concentration, and electrically connects the second p-type semiconductor layer 62p and the support substrate 60S to each other. A substrate contact (not shown) is provided outside the imaging region, and the potential of the support substrate 60S and the second p-type semiconductor layer 62p is controlled via the substrate contact when the imaging device 100 operates. In other words, when the imaging device 100 operates, the substrate potential of the semiconductor substrate 60 is controlled via the substrate contact. The voltage supply circuit 128 described above may be configured to supply the substrate potential of the semiconductor substrate 60 via the substrate contact. When an n-type transistor is applied as the signal detection transistor 72, the address transistor 74, and the reset transistor 76 as in the example described here, the substrate potential is typically ground.
　（暗電流の抑制）
　上述したように、不純物領域６０ａは、光電変換部５０Ａによって生成された信号電荷を一時的に蓄積する電荷蓄積ノードの一部を構成する。これは、不純物領域６０ａと第２ｐ型半導体層６２ｐとの間のｐｎ接合によって形成される接合容量が、信号電荷の少なくとも一部を蓄積する容量として機能するからである。 (Suppression of dark current)
As described above, impurity region 60a constitutes a part of the charge storage node that temporarily stores the signal charge generated by photoelectric conversion unit 50A. This is because the junction capacitance formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p functions as a capacitance for accumulating at least a part of the signal charge.
　ただし、不純物領域６０ａと第２ｐ型半導体層６２ｐとの間のｐｎ接合は、空乏層を生じさせる。半導体基板６０中には、格子欠陥が存在し、特に、半導体基板６０の表面には、不純物、ダングリングボンドなどに起因する多様な格子欠陥が存在する。空乏層内に格子欠陥が存在すると、例えば、本来の信号電荷とは異なる電荷の不純物領域６０ａへの混入が生じやすくなる。換言すれば、空乏層内に位置する格子欠陥は、暗電流を生じさせる原因となり得る。暗電流は、ＳＮ比の低下をもたらし、得られる画像の画質を劣化させてしまう。半導体基板６０中の空乏層をなるべく縮小して、格子欠陥のうち、空乏層内に位置する格子欠陥を低減できると、暗電流に起因する画質の劣化が抑制されるので有益である。 However, the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p produces a depletion layer. In the semiconductor substrate 60, lattice defects are present, and in particular, various lattice defects caused by impurities, dangling bonds, etc. exist on the surface of the semiconductor substrate 60. If a lattice defect exists in the depletion layer, for example, mixing of a charge different from the original signal charge into the impurity region 60a is likely to occur. In other words, lattice defects located in the depletion layer can cause dark current. Dark current results in a reduction in the signal-to-noise ratio and degrades the quality of the obtained image. If the depletion layer in the semiconductor substrate 60 can be reduced as much as possible to reduce lattice defects located in the depletion layer among lattice defects, it is useful because deterioration in image quality due to dark current is suppressed.
　本発明者らの検討によると、不純物領域６０ａと第２ｐ型半導体層６２ｐとの間のｐｎ接合によって形成される空乏層の縮小には、不純物領域６０ａから信号電荷を排出した後の不純物領域６０ａの電位をなるべく基板電位に近づけることが有効である。すなわち、リセット後の不純物領域６０ａの電位をなるべく基板電位に近づけることが有効である。例えば信号電荷が正孔であり、かつ、基板電位が接地の場合、０Ｖに近い、なるべく低い電圧をリセット電圧として適用すると有益である。 According to the studies of the present inventors, in order to reduce the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p, the impurity region 60a after discharging the signal charge from the impurity region 60a. It is effective to make the potential of V close to the substrate potential as much as possible. That is, it is effective to make the potential of the impurity region 60a after reset as close as possible to the substrate potential. For example, when the signal charge is a hole and the substrate potential is ground, it is useful to apply a voltage as low as possible, which is close to 0 V, as the reset voltage.
　ただし、リセット後の不純物領域６０ａの電位と基板電位との間の電位差が小さすぎると、不純物領域６０ａに接続されたトランジスタなどの回路要素を介した電気的なカップリングによって不純物領域６０ａの電位が変動した場合に、不純物領域６０ａの電位が基板電位を下回ってしまうおそれがある。 However, if the potential difference between the potential of impurity region 60a after reset and the substrate potential is too small, the potential of impurity region 60a is increased by electrical coupling through a circuit element such as a transistor connected to impurity region 60a. If it fluctuates, the potential of the impurity region 60a may fall below the substrate potential.
　例えば、信号電荷を蓄積する浮遊ノード中のｎ型不純物領域に電界効果トランジスタが接続されていると、ソース－ドレイン間の寄生容量を介した電気的なカップリングの影響によって、そのトランジスタのオンおよびオフの切り替えに起因して不純物領域の電位が低下し得る。このとき、その不純物領域の電位が基板電位を下回ってしまうと、不純物領域とその周囲のｐウェルとの間のｐｎ接合に順方向バイアスがかかることになり、支持基板としてのｐ型シリコン基板から不純物領域に正孔が流入してしまう。すなわち、暗電流が生じ、得られる画像の画質が劣化するおそれがある。 For example, when a field effect transistor is connected to an n-type impurity region in a floating node that stores signal charge, the transistor is turned on and on due to the effect of electrical coupling via parasitic capacitance between the source and drain. The potential of the impurity region may decrease due to the switching off. At this time, if the potential of the impurity region falls below the substrate potential, forward bias is applied to the pn junction between the impurity region and the surrounding p well, and from the p-type silicon substrate as a support substrate Holes will flow into the impurity region. That is, there is a possibility that dark current occurs and the image quality of the obtained image is degraded.
　本発明者らは、上記に鑑み検討を重ね、例えば、第１電圧ＶAおよび第２電圧ＶBの切り替えによってリセット後の電荷蓄積ノードの電位を変化させることにより、信号電荷を蓄積する不純物領域に接続されたトランジスタのオンおよびオフの切り替えに伴ってその不純物領域に本来の信号電荷とは異なる電荷が混入してしまうことを回避し得ることを見出した。 The present inventors have repeated studies in view of the above, for example, by varying the potential of the charge storage node after the reset by switching the first voltage V A and the second voltage V B, impurities accumulate signal charge region It has been found that it is possible to prevent the charge different from the original signal charge from being mixed in the impurity region with the switching on and off of the connected transistor.
　図３は、図２に示す画素１０Ａの回路構成の典型例を模式的に示す。なお、図面が過度に複雑になることを避けるために、図２では、光電変換部５０Ａの対向電極５６に所定のバイアス電圧を供給する電圧線の図示が省略されている。以降の図面についても同様に、対向電極５６に所定のバイアス電圧を供給する電圧線の図示を省略する。 FIG. 3 schematically shows a typical example of the circuit configuration of the pixel 10A shown in FIG. Note that, in FIG. 2, illustration of voltage lines for supplying a predetermined bias voltage to the counter electrode 56 of the photoelectric conversion unit 50A is omitted in FIG. 2 in order to prevent the drawing from becoming excessively complicated. Likewise, in the following drawings, illustration of voltage lines for supplying a predetermined bias voltage to the counter electrode 56 is omitted.
　図３に示すように、信号検出トランジスタ７２のゲートは、光電変換部５０Ａに接続される。光電変換部５０Ａと信号検出トランジスタ７２との間のノードＦＤａが電荷蓄積ノードに相当するといえる。信号検出トランジスタ７２のゲートには、ノードＦＤａに蓄積された信号電荷に対応する電圧が印加される。図示するように、信号検出トランジスタ７２のドレインには、電源電圧Ｖｄｄを供給する、ソースフォロア電源としての電源線８２が接続され、信号検出トランジスタ７２のソースには、アドレストランジスタ７４を介して垂直信号線８９が接続される。すなわち、信号検出トランジスタ７２およびアドレストランジスタ７４は、ソースフォロアを形成する。アドレストランジスタ７４のゲートには、垂直走査回路１２２に接続されたアドレス信号線８４が接続されている。垂直走査回路１２２は、アドレス信号線８４に印加するアドレス信号Φｓｅｌの制御により、画素１０Ａからの信号を垂直信号線８９に読み出すことができる。 As shown in FIG. 3, the gate of the signal detection transistor 72 is connected to the photoelectric conversion unit 50A. It can be said that the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 corresponds to a charge storage node. A voltage corresponding to the signal charge stored in the node FDa is applied to the gate of the signal detection transistor 72. As shown, the drain of the signal detection transistor 72 is connected to a power supply line 82 as a source follower power supply for supplying the power supply voltage Vdd, and the source of the signal detection transistor 72 is a vertical signal via the address transistor 74. Line 89 is connected. That is, the signal detection transistor 72 and the address transistor 74 form a source follower. An address signal line 84 connected to the vertical scanning circuit 122 is connected to the gate of the address transistor 74. The vertical scanning circuit 122 can read out the signal from the pixel 10 A to the vertical signal line 89 by controlling the address signal selsel applied to the address signal line 84.
　ノードＦＤａに注目する。ノードＦＤａには、リセットトランジスタ７６も接続される。リセットトランジスタ７６のソースおよびドレインのうちノードＦＤａに接続されていない側は、リセット電圧線８５に接続されている。撮像装置１００の動作時、リセット電圧線８５には、例えば、所定のリセット電圧Ｖｒが印加される。リセットトランジスタ７６のゲートには、垂直走査回路１２２に接続されたリセット信号線８６が接続されている。垂直走査回路１２２は、リセット信号線８６に印加するリセット信号Φｒｓｔの制御により、リセットトランジスタ７６をオンとして電荷蓄積ノードにリセット電圧Ｖｒを印加することができる。図２を参照して説明したように、リセットトランジスタ７６は、電荷蓄積ノードの一部を構成する不純物領域６０ａをドレイン領域またはソース領域として含む。リセットトランジスタ７６のオンにより、電荷蓄積ノードから信号電荷が排出され、電荷蓄積ノードの電位がリセットされる。 Focus on the node FDa. The reset transistor 76 is also connected to the node FDa. The side of the source and drain of the reset transistor 76 which is not connected to the node FDa is connected to the reset voltage line 85. During operation of the imaging device 100, for example, a predetermined reset voltage Vr is applied to the reset voltage line 85. The reset signal line 86 connected to the vertical scanning circuit 122 is connected to the gate of the reset transistor 76. Under control of the reset signal Φrst applied to the reset signal line 86, the vertical scanning circuit 122 can turn on the reset transistor 76 and apply the reset voltage Vr to the charge storage node. As described with reference to FIG. 2, the reset transistor 76 includes the impurity region 60a forming a part of the charge storage node as a drain region or a source region. When the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node, and the potential of the charge storage node is reset.
　ここでは、ノードＦＤａに電圧供給回路１２８がさらに電気的に接続されている。この例では、ノードＦＤａと、電圧供給回路１２８に接続された制御線８１との間に容量素子Ｃ１が介在している。換言すれば、容量素子Ｃ１が有する２つの端子のうちの一方には、ノードＦＤａが接続されている。すなわち、この例では、容量素子Ｃ１の一方の端子は、不純物領域６０ａに電気的に接続されている。容量素子Ｃ１の２つの端子のうちの他方には、電圧供給回路１２８が接続される。 Here, the voltage supply circuit 128 is further electrically connected to the node FDa. In this example, the capacitive element C1 is interposed between the node FDa and the control line 81 connected to the voltage supply circuit 128. In other words, the node FDa is connected to one of the two terminals of the capacitive element C1. That is, in this example, one terminal of the capacitive element C1 is electrically connected to the impurity region 60a. The voltage supply circuit 128 is connected to the other of the two terminals of the capacitive element C1.
　容量素子Ｃ１の具体的な構成に特に限定はない。容量素子Ｃ１は、例えば、層間絶縁層４０中に配置されたＭＩＳ（metal-insulator-semiconductor）構造であってもよいし、デプレッション型のＭＯＳ（ＤＭＯＳ）容量であってもよい。あるいは、ＭＩＭ（metal-insulator-metal）構造であってもよい。ＭＩＭ構造を採用すると、より大きな容量値を得やすい。 There are no particular limitations on the specific configuration of the capacitive element C1. The capacitive element C1 may have, for example, a metal-insulator-semiconductor (MIS) structure disposed in the interlayer insulating layer 40, or may be a depression-type MOS (DMOS) capacitor. Alternatively, it may be a MIM (metal-insulator-metal) structure. Adopting the MIM structure makes it easy to obtain a larger capacity value.
　図３に例示する構成において、電圧供給回路１２８は、電界効果トランジスタなどから構成されるスイッチング素子１２８ａおよび１２８ｂを有する。つまり、ここでは、電圧供給回路１２８は、スイッチング素子１２８ａおよび１２８ｂのオンおよびオフを切り替えることにより、制御線８１に印加される電圧Ｖｃを第１電圧ＶAおよび第２電圧ＶBの間で切り替え可能である。 In the configuration illustrated in FIG. 3, voltage supply circuit 128 has switching elements 128a and 128b configured of field effect transistors or the like. That is, here, the voltage supply circuit 128, the switching by switching the switching elements 128a and 128b on and off, the voltage Vc applied to the control line 81 between the first voltage V A and the second voltage V B It is possible.
　（撮像装置１００の動作の第１の例）
　次に、図４Ａを参照して、撮像装置１００の動作の一例を説明する。図４Ａは、図３に示す回路構成を有する画素１０Ａの例示的な動作を説明するためのタイミングチャートである。図４Ａ中、一番上のチャートは、水平同期信号ＨＤのパルスを示す。あるパルスの立ち上がりから次のパルスの立ち上がりまでの期間が、１つの水平走査期間である１Ｈに対応する。この１Ｈ期間に、画素アレイ１１０に含まれる複数の画素１０Ａのうち、ある１つの行に属する画素１０Ａのリセットおよび画素１０Ａからの信号の読み出しが実行される。図４Ａ中の両矢印ＳＥＬは、注目した画素のアドレストランジスタ７４がオンとされた選択期間を示し、矢印ＡＣＣは、アドレストランジスタ７４がオフとされた非選択期間を示す。 (First Example of Operation of Imaging Device 100)
Next, an example of the operation of the imaging device 100 will be described with reference to FIG. 4A. FIG. 4A is a timing chart for explaining an exemplary operation of the pixel 10A having the circuit configuration shown in FIG. The top chart in FIG. 4A shows pulses of the horizontal synchronization signal HD. The period from the rise of a certain pulse to the rise of the next pulse corresponds to 1 H which is one horizontal scanning period. During the 1H period, the reset of the pixels 10A belonging to one certain row among the plurality of pixels 10A included in the pixel array 110 and the readout of the signal from the pixels 10A are performed. The double arrow SEL in FIG. 4A indicates a selection period in which the address transistor 74 of the pixel of interest is turned on, and the arrow ACC indicates a non-selection period in which the address transistor 74 is turned off.
　図４Ａ中、一番下のチャートは、ノードＦＤａの電位すなわち不純物領域６０ａの電位ＶFDの時間的変化を示し、下から２番目のチャートは、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃの時間的変化を示す。ここでは、時刻Ｔ１の時点において、制御線８１には第１電圧ＶAが印加されている。 The bottom chart in FIG. 4A shows temporal changes of the potential of the node FDa, ie, the potential V FD of the impurity region 60a, and the second chart from the bottom is applied from the voltage supply circuit 128 to the control line 81. The temporal change of voltage Vc is shown. Here, at time T1, the first voltage V A is applied to the control line 81.
　露光による信号電荷の蓄積後、時刻Ｔ１にアドレス信号Φｓｅｌをハイレベルとする。アドレス信号Φｓｅｌをハイレベルとすることにより、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号が信号検出トランジスタ７２およびアドレストランジスタ７４を介して垂直信号線８９に読み出される。読み出された第１の信号は、図１に示す信号保持回路１２３に一時的に保持される。 After accumulation of signal charges by exposure, the address signal selsel is set to high level at time T1. By setting the address signal selsel to a high level, a first signal of a voltage level corresponding to the signal charge stored in the charge storage node is read out to the vertical signal line 89 through the signal detection transistor 72 and the address transistor 74. The read first signal is temporarily held by the signal holding circuit 123 shown in FIG.
　次に、時刻Ｔ２にリセット信号Φｒｓｔをハイレベルとし、リセットトランジスタ７６をオンとする。リセットトランジスタ７６のオンにより、電荷蓄積ノードから信号電荷が排出され、電荷蓄積ノードの電位がリセットされる。このとき、ノードＦＤａにリセット電圧Ｖｒが印加されることによって不純物領域６０ａの電位ＶFDがＶｒに低下する。リセット電圧Ｖｒとしては、基板電位Ｖｓｕｂよりも高い電圧を用いる。したがって、ここでは、Ｖｒ＞Ｖｓｕｂである。基板電位Ｖｓｕｂが０Ｖである場合、リセット電圧Ｖｒとして０Ｖ付近かつ正の電圧を用いる。 Next, at time T2, the reset signal rstrst is set to the high level, and the reset transistor 76 is turned on. When the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node, and the potential of the charge storage node is reset. At this time, the potential V FD of the impurity regions 60a by the reset voltage Vr is applied to the node FDa falls to Vr. A voltage higher than the substrate potential Vsub is used as the reset voltage Vr. Therefore, here, Vr> Vsub. When the substrate potential Vsub is 0 V, a positive voltage near 0 V is used as the reset voltage Vr.
　次に、時刻Ｔ３にリセット信号Φｒｓｔをローレベルとし、リセットトランジスタ７６をオフとする。図２を参照して説明したように、リセットトランジスタ７６は、不純物領域６０ａをドレイン領域またはソース領域として含む。そのため、リセットトランジスタ７６をオフすると、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、不純物領域６０ａの電位ＶFDがＶｒからさらに低下し得る。既に説明したように、このとき、電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうと、不純物領域６０ａに余計な正孔が流入してしまう。 Next, at time T3, the reset signal rstrst is set to low level, and the reset transistor 76 is turned off. As described with reference to FIG. 2, the reset transistor 76 includes the impurity region 60 a as a drain region or a source region. Therefore, when the reset transistor 76 is turned off, the potential V FD of the impurity region 60a may be further lowered from Vr due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76. As described above, at this time, if the potential V FD falls below the substrate potential Vsub, extra holes flow into the impurity region 60a.
　ただし、ここでは、時刻Ｔ３にリセット信号Φｒｓｔをローレベルとするだけでなく、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃを第２電圧ＶBに切り替えている。ここでは、第２電圧ＶBとして、第１電圧ＶAよりも高い電圧を用いる。 However, in this case, not a time T3 by the reset signal Φrst a low level, and switches the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to a second voltage V B. Here, as the second voltage V B, using a voltage higher than the first voltage V A.
　電圧Ｖｃを第１電圧ＶAから第１電圧ＶAよりも高い第２電圧ＶBに切り替えることにより、容量素子Ｃ１を介してノードＦＤａの電位を上昇させることができる。この例では、リセットトランジスタ７６のオフ直後の不純物領域６０ａの電位ＶFDは、Ｖｒ＞Ｖ１ａ＞Ｖｓｕｂの関係を満たすＶ１ａとなっている。例えばリセット電圧Ｖｒが０．５Ｖのとき、Ｖ１ａは、０．２Ｖ程度であり得る。つまり、第２電圧ＶBを適切に選択し、電圧供給回路１２８からの出力を第１電圧ＶAおよび第２電圧ＶBの間で切り替えることにより、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうことが防止されている。この例では、基板電位を基準として不純物領域６０ａの電位ＶFDに、０．２Ｖの電位差を確保できている。つまり、電位ＶFDが基板電位Ｖｓｕｂを下回ることに起因する、余計な正孔の不純物領域６０ａへの流入が防止される。換言すれば、暗電流が抑制されている。第２電圧ＶBの具体的な値としては、リセットトランジスタ７６のソース－ドレイン間の寄生容量の大きさなどを考慮して、リセットトランジスタ７６のオフ時に電位ＶFDがＶ１ａ＞Ｖｓｕｂの関係を満たすこととなるような電圧を選択すればよい。 By switching the voltage Vc from the first voltage V A higher than the first voltage V A second voltage V B, it can increase the potential of the node FDa through the capacitor C1. In this example, the potential V FD of the impurity region 60a immediately after the reset transistor 76 is off is V1a satisfying the relationship of Vr>V1a> Vsub. For example, when the reset voltage Vr is 0.5V, V1a may be about 0.2V. That is, the second voltage V B and appropriate selection, by switching between the output from the voltage supply circuit 128 of the first voltage V A and the second voltage V B, the potential V FD is the substrate potential Vsub of the impurity regions 60a It is prevented that it falls below. In this example, a potential difference of 0.2 V can be secured at the potential V FD of the impurity region 60 a with reference to the substrate potential. That is, the inflow of unnecessary holes to the impurity region 60a due to the potential V FD falling below the substrate potential Vsub is prevented. In other words, dark current is suppressed. A specific value of the second voltage V B, the source of the reset transistor 76 - in consideration of the magnitude of the parasitic capacitance between the drain potential V FD when off the reset transistor 76 satisfies the relation of V1a> Vsub It is sufficient to select a voltage that will
　リセットトランジスタ７６のオフ後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ４までの期間に、信号電荷の排出後の電荷蓄積ノードの電圧レベルに対応する第２の信号を、アドレストランジスタ７４を介して垂直信号線８９に読み出す。信号保持回路１２３は、第１の信号および第２の信号の差分Δを、画像を表現する信号として水平走査回路１２４に出力する。第２の信号の取得後、アドレストランジスタ７４をオフとし、次のフレームの信号電荷の蓄積を開始する。 After the reset transistor 76 is turned off, a second signal corresponding to the voltage level of the charge storage node after discharge of the signal charge is transmitted through the address transistor 74 during a period until time T4 when the next pulse of the horizontal synchronization signal HD And read out to the vertical signal line 89. The signal holding circuit 123 outputs the difference Δ between the first signal and the second signal to the horizontal scanning circuit 124 as a signal representing an image. After obtaining the second signal, the address transistor 74 is turned off, and accumulation of signal charge of the next frame is started.
　以上に説明した例では、電圧供給回路１２８が、リセットトランジスタ７６がオンとされる、時刻Ｔ２～Ｔ３の第１の期間には第１電圧ＶAを不純物領域６０ａに印加し、第１の期間に続く、時刻Ｔ３～Ｔ４の第２の期間には、不純物領域６０ａに印加する電圧を第２電圧ＶBに切り替えるように構成されている。図４Ａを参照しながら説明したように、電圧供給回路１２８から不純物領域６０ａに印加する電圧をリセットトランジスタ７６のオフのタイミングで、第１電圧ＶAよりも高い第２電圧ＶBに切り替えることにより、リセットトランジスタ７６のオフに伴って不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうことを防止可能である。したがって、不純物領域６０ａに余計な正孔が流入することによって生じる暗電流を抑制できる。 In the example described above, the voltage supply circuit 128 applies the first voltage V A to the impurity region 60 a during the first period from time T2 to T3 in which the reset transistor 76 is turned on. It followed, in the second period of time T3 ~ T4, and is configured to switch the voltage applied to the impurity regions 60a to a second voltage V B. As described with reference to FIG. 4A, in the timing off of the reset transistor 76 a voltage applied to the impurity regions 60a from the voltage supply circuit 128, by switching to higher than the first voltage V A second voltage V B , the potential V FD of the impurity regions 60a with the off of the reset transistor 76 is possible to prevent that fall below the substrate potential Vsub. Therefore, it is possible to suppress the dark current generated by the flow of extra holes into impurity region 60a.
　また、図３に示す例では、制御線８１に印加される電圧Ｖｃを第１電圧ＶAおよび第２電圧ＶBの間で切り替え、容量素子Ｃ１を介してノードＦＤａの電位を変化させている。このように、不純物領域６０ａと電圧供給回路１２８との間に容量素子Ｃ１を介在させることにより、電荷蓄積ノードに蓄積された信号電荷に影響を与えることなく、電荷蓄積ノードの電位を制御することが可能になる。 Further, in the example shown in FIG. 3, switch the voltage Vc applied to the control line 81 between the first voltage V A and the second voltage V B, and changing the potential of the node FDa through the capacitor C1 . Thus, by interposing the capacitive element C1 between the impurity region 60a and the voltage supply circuit 128, the potential of the charge storage node is controlled without affecting the signal charge stored in the charge storage node. Becomes possible.
　ここで、図３を参照すればわかるように、容量素子Ｃ１は、ノードＦＤａとの電気的接続を有するため、不純物領域６０ａと同様に、信号電荷を一時的に保持する電荷蓄積ノードの少なくとも一部を構成する。換言すれば、ノードＦＤａへの容量素子Ｃ１の接続は、電荷蓄積ノード全体の容量値を増大させる。以下の２つの理由から、容量素子Ｃ１の容量値がなるべく小さくされることが有利である。 Here, as can be seen with reference to FIG. 3, since capacitive element C1 has an electrical connection with node FDa, at least one of the charge storage nodes for temporarily holding the signal charge, like impurity region 60a. Make up the department. In other words, the connection of capacitive element C1 to node FDa increases the capacitance value of the entire charge storage node. It is advantageous for the capacitance value of the capacitive element C1 to be as small as possible for the following two reasons.
　第１の理由は、電荷蓄積ノード全体の容量値が増大すると、変換ゲインが低下する結果を招くからである。変換ゲインが低下すると、後段回路でのノイズの影響が大きくなり、ＳＮ比低下のおそれがある。したがって、ＳＮ比の低下を回避する観点からは、容量素子Ｃ１の容量値がなるべく小さくされることが有益である。 The first reason is that an increase in the capacitance value of the entire charge storage node results in a decrease in conversion gain. If the conversion gain is lowered, the influence of noise in the subsequent stage circuit becomes large, and there is a possibility that the SN ratio may be lowered. Therefore, from the viewpoint of avoiding the decrease in the SN ratio, it is useful that the capacitance value of the capacitive element C1 be as small as possible.
　第２の理由は、容量素子Ｃ１が比較的に大きな容量値を有すると、ノードＦＤａへの容量素子Ｃ１を介した制御線８１上のノイズの混入の影響が増大し得るからである。制御線８１に印加される電圧に含まれるノイズは、容量素子Ｃ１を介した電気的なカップリングにより、ノードＦＤａに混入し得る。特に、同一の行に属する画素の電荷蓄積ノードに対して共通して、制御線８１に供給された電圧が容量素子Ｃ１を介して印加されるような構成、換言すれば、第１電圧ＶAと第２電圧ＶBとの間の切り替えが行単位で実行されるような構成では、制御線８１上のノイズが横線ノイズとして画像上に現れ得る。横線ノイズは、画素単位のランダムノイズと比較して画像の観察者に認識されやすい傾向があるため、横線ノイズを抑制できると有益である。 The second reason is that if the capacitive element C1 has a relatively large capacitance value, the influence of noise mixing on the control line 81 via the capacitive element C1 to the node FDa may increase. Noise included in the voltage applied to control line 81 can be mixed in node FDa by electrical coupling via capacitive element C1. In particular, the configuration in which the voltage supplied to control line 81 is commonly applied to the charge storage nodes of the pixels belonging to the same row via the capacitive element C1, in other words, the first voltage V A When the switching as performed row by row configuration between the second voltage V B, the noise on the control line 81 may appear on the image as a horizontal line noise. It is useful to be able to suppress the horizontal noise because the horizontal noise tends to be easily recognized by the viewer of the image as compared to the random noise in units of pixels.
　容量素子Ｃ１の容量値をＣ１、電荷蓄積ノードのうち容量素子Ｃ１以外の部分の容量値をＣＦＤとすると、ノードＦＤａに伝搬する電圧変動の大きさは、制御線８１の電圧変動と（Ｃ１／（Ｃ１＋ＣＦＤ））との積で表される。したがって、横線ノイズ抑制の観点からも、容量素子Ｃ１の容量値Ｃ１はなるべく小さい方が有利である。 Assuming that the capacitance value of capacitance element C1 is C 1 and the capacitance value of a portion other than capacitance element C1 of the charge storage nodes is C FD , the magnitude of the voltage variation transmitted to node FDa is the voltage variation of control line 81 It is represented by the product of C 1 / (C 1 + C FD )). Therefore, in terms of horizontal noise suppression, capacitance value C 1 of the capacitor C1 is advantageously as small as possible.
　また、容量素子Ｃ１の容量値Ｃ１は、電荷蓄積ノードのうち容量素子Ｃ１以外の部分の容量値をＣＦＤよりも小さいと有益である。容量素子Ｃ１の容量値Ｃ１を電荷蓄積ノードのうち容量素子Ｃ１以外の部分の容量値ＣＦＤよりも小さくすることにより、ノードＦＤａに容量素子Ｃ１を接続したことに起因するＳＮ比の低下の程度を、Ｆ値を一段大きな値にしたときのＳＮ比の低下の程度よりも小さくし得る。例えば、容量素子Ｃ１の容量値Ｃ１を容量値ＣＦＤの１／２以下程度とすれば、ノードＦＤａに容量素子Ｃ１を接続したことに起因するＳＮ比の低下の程度を、Ｆ値に換算して（１／２）段程度以下の変化に留め得る。 The capacitance value C 1 of the capacitor element C1, the capacitance value of the portions other than the capacitor element C1 of the charge storage node is beneficial to be smaller than C FD. It is made smaller than the capacitance value C FD portion other than the capacitive element C1 of the charge storage node capacitance value C 1 of the capacitor C1, the reduction in the SN ratio caused by connecting a capacitor C1 to the node FDa The degree may be smaller than the degree of reduction of the SN ratio when the F value is increased by one level. For example, if the capacitance value C 1 of the capacitor element C1 with the degree less than half of the capacitance value C FD, the degree of reduction of the SN ratio caused by connecting a capacitor C1 to node FDa, converted to F value The change can be limited to about (1/2) or less.
　なお、正孔に代えて電子を信号電荷として用いる場合にも、図４Ａを参照して説明した動作と同様の動作を適用し得る。ただし、信号電荷として正孔を用いる場合と比較して、信号電荷として電子を用いる場合、電荷蓄積ノードへの信号電荷量の蓄積に伴って不純物領域６０ａの電位ＶFDが低下する点が異なる。そのため、信号電荷として電子を用いる場合には、基板電位を基準として不純物領域６０ａの電位ＶFDとの間に十分な電位差を確保する観点から、リセット電圧Ｖｒとしてより大きな正の電圧、例えば３．３Ｖ程度の電圧が用いられ得る。 In the case where electrons are used as signal charges instead of holes, the same operation as the operation described with reference to FIG. 4A can be applied. However, when electrons are used as the signal charge, the potential V FD of the impurity region 60a is lowered along with the accumulation of the signal charge amount at the charge storage node, as compared with the case where holes are used as the signal charge. Therefore, in the case of using electrons as the signal charge, from the viewpoint of securing a sufficient potential difference with the potential V FD of the impurity region 60a with reference to the substrate potential, a larger positive voltage, eg 3.V. A voltage of around 3 V can be used.
　リセット電圧Ｖｒとしてより大きな正の電圧を用いるので、リセットトランジスタ７６のオフに伴う、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングによる不純物領域６０ａの電位ＶFDの低下の影響は小さいといえる。しかしながら、信号電荷として電子を用いる場合、飽和電子数を向上させるにはリセット電圧Ｖｒとしてより高い電圧を用いる必要があり、要求されるダイナミックレンジに十分な飽和電子数の確保の観点からは、信号電荷として正孔を用いる方が有利である。 Since a larger positive voltage is used as the reset voltage Vr, the influence of the reduction in the potential V FD of the impurity region 60a due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76 accompanying the turning off of the reset transistor 76 is small. It can be said. However, when using electrons as signal charges, it is necessary to use a higher voltage as the reset voltage Vr in order to improve the number of saturated electrons, and from the viewpoint of securing the number of saturated electrons sufficient for the required dynamic range, It is more advantageous to use holes as the charge.
　リセットトランジスタ７６としてｐ型のトランジスタを適用することも可能である。この場合、半導体基板６０中の各領域の導電型をｎ型とｐ型との間で入れ替えればよい。ただし、リセットトランジスタ７６としてｐ型のトランジスタを適用する場合には、以下に説明するように、第２電圧ＶBとして、第１電圧ＶAよりも低い電圧を用いる。 It is also possible to apply a p-type transistor as the reset transistor 76. In this case, the conductivity type of each region in the semiconductor substrate 60 may be switched between n-type and p-type. However, when applying the p-type transistor as the reset transistor 76, as described below, as the second voltage V B, using a voltage lower than the first voltage V A.
　図４Ｂは、画素１０Ａのリセットトランジスタ７６にｐ型のトランジスタを適用したときの例示的な動作を説明するためのタイミングチャートである。リセットトランジスタ７６にｐ型のトランジスタを適用する場合には、基板電位Ｖｓｕｂとして、リセットトランジスタ７６にｎ型のトランジスタを適用した場合よりも高い電圧が用いられる。基板電位Ｖｓｕｂは、例えば３．３Ｖ程度であり得る。 FIG. 4B is a timing chart for explaining an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10A. When a p-type transistor is applied to the reset transistor 76, a higher voltage is used as a substrate potential Vsub than when an n-type transistor is applied to the reset transistor 76. Substrate potential Vsub may be, for example, about 3.3V.
　リセットトランジスタ７６にｐ型のトランジスタを適用した場合、信号電荷として正孔を用いる方が、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングによる不純物領域６０ａの電位ＶFDの変化の影響は、小さい。これは、リセットトランジスタ７６にｎ型のトランジスタを適用し、かつ、信号電荷として電子を用いた場合と同様の理由による。ただし、十分な飽和電子数を確保するには、基板電位を基準として不純物領域６０ａの電位ＶFDとの間に十分な電位差を確保する必要が生じる。これに対し、信号電荷が電子であれば、リセット電圧Ｖｒとして、基板電位である３．３Ｖ付近の電圧を用いればよく、リセットトランジスタ７６にｐ型のトランジスタを適用した場合には、信号電荷として電子を用いる方が、回路の複雑化を回避しながら、要求されるダイナミックレンジに十分な飽和電子数を確保しやすい。 When a p-type transistor is applied to the reset transistor 76, the effect of the change in the potential V FD of the impurity region 60a due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76 is better when holes are used as signal charges. Is small. This is because of the same reason as in the case where an n-type transistor is applied to the reset transistor 76 and electrons are used as signal charges. However, in order to secure a sufficient number of saturated electrons, it is necessary to secure a sufficient potential difference between the substrate potential and the potential V FD of the impurity region 60a. On the other hand, if the signal charge is an electron, a voltage near 3.3 V which is the substrate potential may be used as the reset voltage Vr. When a p-type transistor is applied to the reset transistor 76, the signal charge is Using electrons is easier to secure a sufficient number of saturated electrons in the required dynamic range while avoiding circuit complexity.
　したがって、ここでは、信号電荷として電子を用いる場合の動作の例を説明する。図４Ｂは、リセットトランジスタ７６にｐ型のトランジスタを適用し、信号電荷として電子を用いる場合の動作の例を示している。リセットトランジスタ７６がｐ型のトランジスタであり、信号電荷として電子を用いる場合、典型的には、信号検出トランジスタ７２およびアドレストランジスタ７４もｐ型のトランジスタとして半導体基板６０に形成される。 Therefore, here, an example of operation in the case of using electrons as signal charges will be described. FIG. 4B shows an example of operation in the case where a p-type transistor is applied to the reset transistor 76 and electrons are used as signal charges. When the reset transistor 76 is a p-type transistor and electrons are used as signal charges, typically, the signal detection transistor 72 and the address transistor 74 are also formed on the semiconductor substrate 60 as p-type transistors.
　図４Ｂに示す例では、時刻Ｔ１までの期間に注目すると、露光による信号電荷の蓄積により、不純物領域６０ａの電位ＶFDが徐々に低下している。信号電荷の蓄積後、時刻Ｔ１にアドレス信号Φｓｅｌをローレベルとしてアドレストランジスタ７４をオンとし、第１の信号を垂直信号線８９に読み出す。 In the example shown in FIG. 4B, focusing on the period up to the time T1, the potential V FD of the impurity region 60a gradually decreases due to the accumulation of the signal charge due to the exposure. After the signal charge is stored, the address signal selsel is set to low level at time T1 to turn on the address transistor 74, and the first signal is read out to the vertical signal line 89.
　次に、時刻Ｔ２にリセット信号Φｒｓｔをローレベルとし、リセットトランジスタ７６をオンとする。図４Ｂに示すように、リセットトランジスタ７６のオンにより、不純物領域６０ａの電位ＶFDは、Ｖｒに上昇する。このときのリセット電圧Ｖｒとしては、基板電位Ｖｓｕｂ付近かつ基板電位Ｖｓｕｂよりも低い、例えば２．８Ｖの電圧が用いられる。 Next, at time T2, the reset signal rstrst is set to low level, and the reset transistor 76 is turned on. As shown in FIG. 4B, when the reset transistor 76 is turned on, the potential V FD of the impurity region 60a rises to Vr. As the reset voltage Vr at this time, for example, a voltage of 2.8 V which is near the substrate potential Vsub and lower than the substrate potential Vsub is used.
　次に、時刻Ｔ３にリセット信号Φｒｓｔをハイレベルとし、リセットトランジスタ７６をオフとする。リセットトランジスタ７６をオフすると、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、不純物領域６０ａの電位ＶFDがＶｒからさらに上昇し得る。このとき、電位ＶFDが基板電位Ｖｓｕｂを上回ってしまうと、不純物領域６０ａとその周囲との間のｐｎ接合に順方向バイアスがかかり、支持基板としてのｎ型シリコン基板から不純物領域６０ａに余計な電子が流入してしまう。換言すれば、暗電流が生じてしまう。 Next, at time T3, the reset signal rstrst is set to the high level, and the reset transistor 76 is turned off. When the reset transistor 76 is turned off, the electrical coupling caused by the parasitic capacitance of the reset transistor 76 may further increase the potential V FD of the impurity region 60a from Vr. At this time, when the potential V FD exceeds the substrate potential Vsub, a forward bias is applied to the pn junction between the impurity region 60a and the periphery thereof, and an n-type silicon substrate as a support substrate is redundantly connected to the impurity region 60a. Electrons flow in. In other words, dark current occurs.
　ここでは、時刻Ｔ３にリセット信号Φｒｓｔをハイレベルとするだけでなく、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃを第１電圧ＶAよりも低い第２電圧ＶBに切り替えている。電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに切り替えることにより、容量素子Ｃ１を介して光電変換部５０Ａと信号検出トランジスタ７２との間のノードＦＤａの電位を低下させることができ、図４Ｂに示すように、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを上回ってしまうことを回避し得る。この例では、リセットトランジスタ７６のオフ直後の不純物領域６０ａの電位ＶFDは、Ｖｓｕｂ＞Ｖ１ｂ＞Ｖｒの関係を満たすＶ１ｂとなっている。Ｖ１ｂは、３．１Ｖ程度であり得る。 Here, not the time T3 only a reset signal Φrst a high level, and switches the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to lower than the first voltage V A second voltage V B . By switching the voltage Vc from the first voltage V A to the second voltage V B , the potential of the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 can be reduced via the capacitive element C1, As shown in FIG. 4B, the potential V FD of the impurity region 60a can be prevented from exceeding the substrate potential Vsub. In this example, the potential V FD of the impurity region 60a immediately after the reset transistor 76 is turned off is V1b which satisfies the relationship Vsub>V1b> Vr. V1b may be about 3.1V.
　リセットトランジスタ７６のオフ後、信号電荷の排出後の電荷蓄積ノードの電圧レベルに対応する第２の信号を垂直信号線８９に読み出し、第１の信号および第２の信号の差分Δの絶対値を画像信号として得る。第２の信号の取得後、アドレストランジスタ７４をオフとし、次のフレームの信号電荷の蓄積を開始する。 After the reset transistor 76 is turned off, the second signal corresponding to the voltage level of the charge storage node after discharging the signal charge is read out to the vertical signal line 89, and the absolute value of the difference Δ between the first signal and the second signal is obtained. Obtained as an image signal. After obtaining the second signal, the address transistor 74 is turned off, and accumulation of signal charge of the next frame is started.
　（撮像装置１００の動作の第２の例）
　本開示の実施形態による撮像装置の動作の例は、図４Ａおよび図４Ｂを参照して説明した例に限られない。例えば、以下に説明するように、信号電荷を電荷蓄積ノードに蓄積する露光期間と、１フレーム期間のうち露光期間以外の非露光期間中のリセットのための期間との間で、制御線８１に供給する電圧を互いに異なる電圧としてもよい。 (Second Example of Operation of Imaging Device 100)
An example of the operation of an imaging device according to an embodiment of the present disclosure is not limited to the example described with reference to FIGS. 4A and 4B. For example, as described below, the control line 81 is connected between the exposure period for accumulating signal charges in the charge accumulation node and the period for resetting in a non-exposure period other than the exposure period of one frame period. The voltages supplied may be different from each other.
　図４Ｃは、画素１０Ａ、１０Ａｐおよび１０Ａｑの動作の他の例を説明するためのタイミングチャートである。図４Ａおよび図４Ｂに示す例と同様に、図４Ｃに示す動作例において、信号電荷を電荷蓄積ノードに蓄積するための露光期間および露光期間以外の非露光期間が交互に繰り返されている。非露光期間は、電荷蓄積ノードの電位を所定の電位にリセットするためのリセット期間をその一部に含む。 FIG. 4C is a timing chart for explaining another example of the operation of the pixels 10A, 10Ap and 10Aq. Similar to the example shown in FIGS. 4A and 4B, in the operation example shown in FIG. 4C, the exposure period for accumulating the signal charge in the charge storage node and the non-exposure period other than the exposure period are alternately repeated. The non-exposure period includes, in part, a reset period for resetting the potential of the charge storage node to a predetermined potential.
　ここでは、図３に示す画素１０Ａを例示する。まず、時刻Ｔ１において、アドレス信号Φｓｅｌをハイレベルにする。また、このとき、制御線８１に印加する電圧を第１電圧ＶAから相対的に高い第２電圧ＶBに切り替える。 Here, the pixel 10A shown in FIG. 3 is illustrated. First, at time T1, the address signal selsel is made high. At this time, switch the voltage applied to the control line 81 to a relatively high from the first voltage V A second voltage V B.
　制御線８１に印加する電圧を第１電圧ＶAから第２電圧ＶBに切り替えることにより、容量素子Ｃ１を介した容量結合によってノードＦＤａの電位が一時的に上昇する。このとき、ノードＦＤａの電位の変動量ΔＶＦＤは、下記の式（１）で表される。 By switching the voltage applied to the control line 81 to a second voltage V B from the first voltage V A, the potential of the node FDa by capacitive coupling through the capacitor C1 is temporarily increased. At this time, the variation amount ΔV FD of the potential of the node FDa is expressed by the following equation (1).
　　ΔＶＦＤ＝（ＶB－ＶA）（Ｃ１／（Ｃ１＋ＣＦＤ））　　　（１）
　このときのノードＦＤａの電位が、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルを表現する第１の信号として信号検出トランジスタ７２およびアドレストランジスタ７４を介して垂直信号線８９に読み出される。 ΔV FD = (V B −V A ) (C 1 / (C 1 + C FD )) (1)
The potential of the node FDa at this time is read out to the vertical signal line 89 through the signal detection transistor 72 and the address transistor 74 as a first signal expressing a voltage level corresponding to the signal charge stored in the charge storage node.
　時刻Ｔ２において、リセット信号Φｒｓｔをハイレベルにする。これにより、リセットトランジスタ７６を介して電荷蓄積ノードから信号電荷が排出され、電荷蓄積ノードの電位がリセット電圧Ｖｒにリセットされる。 At time T2, the reset signal rstrst is made high. Thereby, the signal charge is discharged from the charge storage node through the reset transistor 76, and the potential of the charge storage node is reset to the reset voltage Vr.
　時刻Ｔ３において、リセット信号Φｒｓｔをローレベルとし、リセットトランジスタ７６をオフする。時刻Ｔ３から、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ４までの間に、信号電荷の排出後の電荷蓄積ノードの電圧レベルに対応する第２の信号を、アドレストランジスタ７４を介して垂直信号線８９に読み出す。 At time T3, the reset signal rstrst is set to low level, and the reset transistor 76 is turned off. From time T3 to time T4 at which the next pulse of horizontal synchronization signal HD rises, the second signal corresponding to the voltage level of the charge storage node after discharge of the signal charge is made vertical via address transistor 74. Read on line 89.
　この例では、時刻Ｔ１から時刻Ｔ２までの間に読み出された第１の信号と、時刻Ｔ３から時刻Ｔ４までの間に読み出された第２の信号との差分Δが、画像を表現する真の画素信号となる。 In this example, the difference Δ between the first signal read from time T1 to time T2 and the second signal read from time T3 to time T4 represents an image. It becomes a true pixel signal.
　時刻Ｔ４において、制御線８１に印加する電圧を再び第１電圧ＶAに戻す。容量素子Ｃ１を介した容量結合により、ノードＦＤａの電位は、ＶｒからＶ１ｃに低下する。このときのノードＦＤａの電位の変動量である（Ｖｒ－Ｖ１ｃ）は、上述したΔＶＦＤに等しい。 At time T4, the voltage applied to the control line 81 is returned to the first voltage V A again. The potential of the node FDa drops from Vr to V1c due to capacitive coupling via the capacitive element C1. The fluctuation amount of the potential of the node FDa at this time (Vr−V1c) is equal to the above-described ΔV FD .
　ここで、変動量ΔＶＦＤは、容量値Ｃ１およびＣＦＤが既知であれば、上述の式（１）に基づいて第１電圧ＶAおよび第２電圧ＶBを決定することにより、制御することができる。所望のΔＶＦＤを以下の手順で実現することが可能である。まず、製品設計時において、ターゲットとする電荷蓄積ノードの全体の容量値から、容量素子Ｃ１と、電荷蓄積ノードのうち容量素子Ｃ１以外の部分との間の容量比を決定する。そして、実動作時に制御線８１に印加する電圧の振幅、すなわち、第１電圧ＶAおよび第２電圧ＶBの具体的な電圧値を上述の式（１）に基づき決定する。 Here, if the capacitance values C 1 and C FD are known, the fluctuation amount ΔV FD is controlled by determining the first voltage V A and the second voltage V B based on the above equation (1). be able to. The desired ΔV FD can be achieved by the following procedure. First, at the time of product design, the capacitance ratio between the capacitive element C1 and a portion of the charge storage node other than the capacitive element C1 is determined from the total capacitance value of the target charge storage node. Then, the amplitude of the voltage applied to the control line 81 during actual operation, i.e., a specific voltage value of the first voltage V A and the second voltage V B is determined based on equation (1) above.
　第１電圧ＶAおよび第２電圧ＶBのいずれかが接地（０Ｖ）であると有益である。接地側は一般に低インピーダンスであるので、制御線８１に接続された電圧供給回路１２８からの電源ノイズの電荷蓄積ノードへの混入を抑制し得るからである。例えば第２電圧ＶBを接地とした場合、第１電圧ＶAは、負レベルの電圧となる。 Advantageously , either the first voltage VA or the second voltage VB is at ground (0 V). Since the ground side is generally low impedance, it is possible to suppress the mixing of power supply noise from the voltage supply circuit 128 connected to the control line 81 into the charge storage node. For example, when the second voltage V B is grounded, the first voltage V A is a negative level voltage.
　この例では、電圧供給回路１２８は、制御線８１に対して、不純物領域６０ａをその一部に含む電荷蓄積ノードに信号電荷を蓄積する露光期間に第１電圧ＶAを供給している。他方、行選択時には、第１電圧ＶAとは異なる第２電圧ＶBを供給している。ここでは、特に、非露光期間のうちリセットトランジスタ７６がオンとされるリセット期間中に制御線８１に供給される電圧は、第２電圧ＶBである。このように、露光期間後であって少なくともリセット期間と、その他の期間との間で異ならせるような制御も採用し得る。このような制御によれば、例えば、電荷蓄積ノードの電位をリセット電圧Ｖｒと比較して一時的に低下させることができる。容量素子Ｃ１を介して電荷蓄積ノードの電位を低下させることにより、不純物領域６０ａと、その周囲に位置し、例えば接地とされる第２ｐ型半導体層６２ｐとの間の電位差を縮小できる。これにより、不純物領域６０ａと第２ｐ型半導体層６２ｐとの間のｐｎ接合によって形成される空乏層が縮小され、暗電流の低減が実現される。すなわち、露光期間における電荷蓄積ノードの電位を低電位とすることにより、暗電流低減の効果が期待できる。 In this example, the voltage supply circuit 128, the control line 81, and supplies the first voltage V A to the exposure period for accumulating the signal charges impurity regions 60a to charge storage node includes in its part. On the other hand, at the time of row selection, a second voltage V B different from the first voltage V A is supplied. Here, in particular, the voltage supplied to the control line 81 during the reset period when the reset transistor 76 is turned on among the non-exposure period, the second voltage V B. In this manner, control may be employed to differ between at least the reset period and the other periods after the exposure period. According to such control, for example, the potential of the charge storage node can be temporarily reduced compared to the reset voltage Vr. By reducing the potential of the charge storage node via the capacitive element C1, the potential difference between the impurity region 60a and the second p-type semiconductor layer 62p located around it and grounded, for example, can be reduced. Thereby, the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p is reduced, and the reduction of dark current is realized. That is, by setting the potential of the charge storage node to a low potential in the exposure period, an effect of dark current reduction can be expected.
　図４Ｃに例示する動作においては、行選択時、電荷蓄積ノードの電位は第２電圧ＶBと第１電圧ＶAとの電位差分だけ上昇する。そのため、この電位差を調整することにより、信号検出トランジスタ７２および後段回路のトランジスタのソース－ドレイン電圧を、これらのトランジスタが動作可能な電圧範囲内に設定することができる。したがって、信号検出トランジスタ７２および後段回路により、画素信号または基準信号の読み出しを正常に行うことが可能となる。 In the operation illustrated in FIG. 4C, when the row selection, the potential of the charge storage node is raised by the potential difference amount between the second voltage V B and the first voltage V A. Therefore, by adjusting this potential difference, it is possible to set the source-drain voltage of the signal detection transistor 72 and the transistor of the subsequent stage circuit within the voltage range in which these transistors can operate. Therefore, the signal detection transistor 72 and the rear stage circuit can normally read out the pixel signal or the reference signal.
　（第１の実施形態の変形例）
　本開示の撮像装置１００は、積層型の撮像装置に限られない。図５は、画素１０の他の回路構成の例を模式的に示す。図３を参照して説明した画素１０Ａと比較して、図５に示す画素１０Ａｐは、光電変換部５０Ａに代えて、光電変換部５０Ｂを有する。光電変換部５０Ｂは、例えば半導体基板６０に形成された埋め込みフォトダイオードである。 (Modification of the first embodiment)
The imaging device 100 of the present disclosure is not limited to a stacked imaging device. FIG. 5 schematically shows an example of another circuit configuration of the pixel 10. Compared to the pixel 10A described with reference to FIG. 3, the pixel 10Ap illustrated in FIG. 5 includes a photoelectric conversion unit 50B instead of the photoelectric conversion unit 50A. The photoelectric conversion unit 50B is, for example, a buried photodiode formed in the semiconductor substrate 60.
　図５に示すように、この例では、信号検出トランジスタ７２のゲートに光電変換部５０Ｂが接続される。図５に例示する構成では、光電変換部５０Ｂと信号検出トランジスタ７２との間のノードＦＤｂが電荷蓄積ノードに相当するといえる。換言すれば、光電変換部５０Ｂとしての埋め込みフォトダイオード中のｐｎ接合、不純物領域６０ａおよびゲート電極７２ｅなどが、光電変換部５０Ｂによって生成された電荷を一時的に保持する電荷蓄積ノードとして機能する。不純物領域６０ａが、埋め込みフォトダイオード中のｐｎ接合の一部であってもよい。 As shown in FIG. 5, in this example, the photoelectric conversion unit 50B is connected to the gate of the signal detection transistor 72. In the configuration illustrated in FIG. 5, it can be said that the node FDb between the photoelectric conversion unit 50B and the signal detection transistor 72 corresponds to a charge storage node. In other words, the pn junction in the embedded photodiode as the photoelectric conversion unit 50B, the impurity region 60a and the gate electrode 72e function as charge storage nodes for temporarily holding the charge generated by the photoelectric conversion unit 50B. Impurity region 60a may be part of a pn junction in the buried photodiode.
　画素１０Ａｐを有する撮像装置１００についても、図４Ａおよび図４Ｂを参照して説明した動作と同様の動作を適用することが可能である。例えば、リセット信号Φｒｓｔをローレベルとするタイミングで、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃを第１電圧ＶAから第１電圧ＶAよりも高い第２電圧ＶBに切り替えることにより、容量素子Ｃ１を介してノードＦＤｂの電位を上昇させることができる。第２電圧ＶBを適切に選択することにより、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ることを回避して、暗電流を抑制し得る。なお、光電変換部として埋め込みフォトダイオードを適用する場合、リセットトランジスタ７６などをｐ型のトランジスタとし、信号電荷として電子を蓄積する構成によれば、より大きなダイナミックレンジが得られるのでより有利である。 The same operation as the operation described with reference to FIGS. 4A and 4B can be applied to the imaging device 100 having the pixel 10Ap. For example, at the timing of the reset signal Φrst a low level, to switch the voltage Vc applied to the control line 81 from the voltage supply circuit 128 from the first voltage V A higher than the first voltage V A second voltage V B Thus, the potential of the node FDb can be increased through the capacitive element C1. By suitably selecting the second voltage V B, the potential V FD of the impurity regions 60a is avoided that below the substrate potential Vsub, can suppress dark current. When a buried photodiode is applied as the photoelectric conversion unit, the reset transistor 76 or the like is a p-type transistor and electrons are stored as signal charges, which is more advantageous because a larger dynamic range can be obtained.
　図６は、画素１０のさらに他の回路構成の例を模式的に示す。図５を参照して説明した画素１０Ａｐの回路構成と比較して、図６に示す画素１０Ａｑは、信号検出トランジスタ７２のゲートと光電変換部５０Ｂとの間に接続された転送トランジスタ７９をさらに有する。転送トランジスタ７９は、光電変換部５０Ｂによって得られた信号電荷を、信号検出トランジスタ７２のゲートと転送トランジスタ７９との間のノードＦＤｃに所定のタイミングで転送する。転送トランジスタ７９は、例えばｎチャンネルＭＯＳである。転送トランジスタ７９は、不純物領域６０ａを、ソース領域およびドレイン領域の一方としてリセットトランジスタ７６との間で共有していてもよい。 FIG. 6 schematically shows an example of still another circuit configuration of the pixel 10. Compared to the circuit configuration of the pixel 10Ap described with reference to FIG. 5, the pixel 10Aq illustrated in FIG. 6 further includes the transfer transistor 79 connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B. . The transfer transistor 79 transfers the signal charge obtained by the photoelectric conversion unit 50B to a node FDc between the gate of the signal detection transistor 72 and the transfer transistor 79 at a predetermined timing. The transfer transistor 79 is, for example, an n-channel MOS. The transfer transistor 79 may share the impurity region 60 a with the reset transistor 76 as one of a source region and a drain region.
　図６に示す回路構成によれば、図５に示す画素１０Ａｐと同様に、電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに切り替えることにより、浮遊ノードであるノードＦＤｃの電位を、容量素子Ｃ１を介して例えば上昇させ、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ることを回避し得る。電圧Ｖｃを第１電圧ＶAから第２電圧ＶBへの切り替えは、例えば、ノードＦＤｃに転送された信号電荷をリセットトランジスタ７６のオンによって排出した後の、リセットトランジスタ７６のオフのタイミングで実行される。 According to the circuit configuration shown in FIG. 6, similar to the pixel 10Ap shown in FIG. 5, by switching the voltage Vc from the first voltage V A to the second voltage V B, the potential of a floating node node FDc, capacitance The potential V FD of the impurity region 60a can be avoided, for example, from rising below the substrate potential Vsub through the element C1. Switching of the voltage Vc from the first voltage V A to the second voltage V B is performed, for example, at the timing of turning off the reset transistor 76 after discharging the signal charge transferred to the node FDc by turning on the reset transistor 76. Be done.
　図７Ａおよび図７Ｂは、画素１０のさらに他の回路構成の例を模式的に示す。 7A and 7B schematically show an example of still another circuit configuration of the pixel 10.
　図３を参照して説明した画素１０Ａと比較して、図７Ａに示す画素１０Ａｒは、信号検出トランジスタ７２に代えて、デプレッション型の信号検出トランジスタ７２ｄを有する。信号検出トランジスタ７２ｄとしてデプレッション型のトランジスタを用いることにより、ノードＦＤａの電位が低レベルにある場合であっても、信号検出トランジスタ７２ｄから高い出力が得られる。そのため、垂直信号線８９に接続された負荷回路などから構成される電流源の動作に必要な電圧レンジの確保がより容易になる。 Compared to the pixel 10A described with reference to FIG. 3, the pixel 10Ar shown in FIG. 7A has a signal detection transistor 72d of a depletion type instead of the signal detection transistor 72. By using a depletion type transistor as the signal detection transistor 72d, a high output can be obtained from the signal detection transistor 72d even when the potential of the node FDa is at a low level. Therefore, it becomes easier to secure the voltage range necessary for the operation of the current source configured of the load circuit and the like connected to the vertical signal line 89.
　図７Ｂに示す画素１０Ａｓは、図７Ａに示す画素１０Ａｒの光電変換部５０Ａを光電変換部５０Ｂに置き換えた構成を有する。上述したように、光電変換部５０Ｂは、例えば半導体基板６０に形成された埋め込みフォトダイオードである。フォトダイオードを用いる構成においても、信号検出トランジスタ７２ｄとしてデプレッション型のトランジスタを用いることができる。 The pixel 10As shown in FIG. 7B has a configuration in which the photoelectric conversion unit 50A of the pixel 10Ar shown in FIG. 7A is replaced with a photoelectric conversion unit 50B. As described above, the photoelectric conversion unit 50B is, for example, a buried photodiode formed in the semiconductor substrate 60. Even in the configuration using a photodiode, a depletion type transistor can be used as the signal detection transistor 72d.
　図８は、図７Ａに示す画素１０Ａｒまたは図７Ｂに示す画素１０Ａｓの例示的な動作を説明するためのタイミングチャートである。 FIG. 8 is a timing chart for explaining an exemplary operation of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B.
　図４Ｃを参照して説明した例と比較して、この例では、非露光期間における電圧Ｖｃの波形が、図４Ｃに示す動作シーケンスにおける波形と異なる。図８に示すように、ここでは、非露光期間において、電圧供給回路１２８から制御線８１に印加する電圧Ｖｃを相対的に高い第２電圧ＶBとする期間が短い。図８に例示する動作において、電圧Ｖｃは、時刻Ｔ２におけるリセット信号Φｒｓｔの立ち上がりのタイミングで第１電圧ＶAから相対的に高い第２電圧ＶBに切り替えられ、時刻Ｔ３においてリセット信号Φｒｓｔがローレベルに切り替えられた後に第１電圧ＶAに戻されている。リセットトランジスタ７６をオフにした後に、電圧供給回路１２８から制御線８１に印加する電圧Ｖｃを第１電圧ＶAに切り替えることにより、電圧Ｖｃの変化の全てを電荷蓄積ノードの電位の変動に寄与させることが可能となる。 Compared to the example described with reference to FIG. 4C, in this example, the waveform of the voltage Vc in the non-exposure period is different from the waveform in the operation sequence illustrated in FIG. 4C. As shown in FIG. 8, wherein, in the non-exposure period, a short period of relatively high second voltage V B voltage Vc to be applied to the control line 81 from the voltage supply circuit 128. In the operation illustrated in FIG. 8, the voltage Vc is switched from the first voltage V A to the relatively high second voltage V B at the rise timing of the reset signal rstrst at time T 2, and the reset signal rstrst is low at time T 3 After being switched to the level, it is returned to the first voltage V A. After the reset transistor 76 is turned off, the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the first voltage VA , thereby contributing all changes in the voltage Vc to the change in the potential of the charge storage node. It becomes possible.
　図８に示す例において、時刻Ｔ４における電圧Ｖｃの切り替えにより、電荷蓄積ノードの電位は、リセット電圧Ｖｒから式（１）で表されるΔＶＦＤだけ低下する。その結果、電荷蓄積ノードの電位をＶｒよりも低い電位Ｖ１ｄに低下させることができる。被写体の像を表現する真の画素信号は、時刻Ｔ１における電荷蓄積ノードの電位に対応する第１の信号と、時刻Ｔ４における電荷蓄積ノードの電位に対応する第２の信号との差分で与えられる。 In the example shown in FIG. 8, by switching the voltage Vc at time T4, the potential of the charge storage node drops from the reset voltage Vr by ΔV FD represented by the formula (1). As a result, the potential of the charge storage node can be lowered to a potential V1d lower than Vr. The true pixel signal representing the image of the subject is given by the difference between the first signal corresponding to the potential of the charge storage node at time T1 and the second signal corresponding to the potential of the charge storage node at time T4. .
　第１の信号は、時刻Ｔ１から時刻Ｔ２までの間に垂直信号線８９に読み出され、第２の信号は、時刻Ｔ４から時刻Ｔ５までの間に垂直信号線８９に読み出される。すなわち、この例では、第１電圧ＶAが制御線８１に印加されているときに、画素信号および基準信号の読み出しを実行している。この例でも同様に、０Ｖの電圧を第１電圧ＶAとして用いることにより、電圧供給回路１２８から出力される電圧中のノイズのノードＦＤａまたはノードＦＤｂへの混入を抑制することができる。 The first signal is read out to the vertical signal line 89 between time T1 and time T2, and the second signal is read out to the vertical signal line 89 between time T4 and time T5. That is, in this example, when the first voltage V A is applied to the control line 81, readout of the pixel signal and the reference signal is performed. Similarly, in this example, by using a voltage of 0V as the first voltage V A, it is possible to suppress the contamination of the noise nodes FDa or node FDb in voltage output from the voltage supply circuit 128.
　図９Ａおよび図９Ｂは、画素１０のさらに他の回路構成の例を模式的に示す。図９Ａに示す画素１０Ａｔは、図３に示す回路構成における信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６としてｐ型のトランジスタを適用した例である。図９Ｂに示す画素１０Ａｕは、図５に示す回路構成における信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６としてｐ型のトランジスタを適用した例である。 9A and 9B schematically show an example of still another circuit configuration of the pixel 10. The pixel 10At shown in FIG. 9A is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74 and the reset transistor 76 in the circuit configuration shown in FIG. A pixel 10Au shown in FIG. 9B is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74 and the reset transistor 76 in the circuit configuration shown in FIG.
　図９Ａおよび図９Ｂに例示する構成において、典型的には、信号電荷として電子が用いられる。上述したように、リセットトランジスタ７６にｐ型のトランジスタを適用した場合、信号電荷として電子を用いる方が、回路の複雑化を回避しながら、要求されるダイナミックレンジに十分な飽和電子数を確保しやすい。 In the configuration illustrated in FIGS. 9A and 9B, electrons are typically used as signal charges. As described above, when a p-type transistor is applied to the reset transistor 76, using electrons as the signal charge secures a sufficient number of saturated electrons in the required dynamic range while avoiding complication of the circuit. Cheap.
　図１０は、図９Ａに示す画素１０Ａｔまたは図９Ｂに示す画素１０Ａｕの例示的な動作を説明するためのタイミングチャートである。図１０に示す例では、まず、時刻Ｔ１において、アドレス信号Φｓｅｌをハイレベルからローレベルとし、制御線８１に印加する電圧Ｖｃを第１電圧ＶAから相対的に低い第２電圧ＶBに切り替える。アドレス信号Φｓｅｌをローレベルにすることにより、選択された行の画素から、信号検出トランジスタ７２およびアドレストランジスタ７４を介して第１の信号が垂直信号線８９に読み出される。ここでは、非露光期間においてアドレス信号Φｓｅｌがローレベルに維持される。 FIG. 10 is a timing chart for explaining an exemplary operation of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B. In the example shown in FIG. 10, first, at time T1, the address signal Φsel from the high level to the low level, switching the voltage Vc applied to the control line 81 to the relatively low from the first voltage V A second voltage V B . By setting the address signal selsel to the low level, the first signal is read out to the vertical signal line 89 from the pixels of the selected row via the signal detection transistor 72 and the address transistor 74. Here, the address signal selsel is maintained at the low level in the non-exposure period.
　電圧ＶＦＤのグラフからわかるように、制御線８１に印加する電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに切り替えることにより、容量素子Ｃ１を介した容量結合によって、電荷蓄積ノードの電位が低下する。このときの電位の変動量ΔＶＦＤは、容量素子Ｃ１と、電荷蓄積ノードのうち容量素子Ｃ１以外の部分との間の容量比により、上述の式（１）で表される。時刻Ｔ１から時刻Ｔ２までの間に、このときの電圧ＶＦＤに対応する信号が第１の信号として垂直信号線８９に読み出される。 As can be seen from the graph of the voltage V FD , by switching the voltage V c applied to the control line 81 from the first voltage V A to the second voltage V B , the potential of the charge storage node is obtained by capacitive coupling via the capacitive element C1. Decreases. The variation amount ΔV FD of the potential at this time is expressed by the above-mentioned equation (1) by the capacitance ratio between the capacitive element C1 and the portion of the charge storage node other than the capacitive element C1. From time T1 to time T2, a signal corresponding to the voltage V FD at this time is read out to the vertical signal line 89 as a first signal.
　この例では、時刻Ｔ２において、リセット信号Φｒｓｔをローレベルにすることにより、リセットが実行される。すなわち、リセット信号Φｒｓｔがローレベルとされることによりリセットトランジスタ７６がオンとされ、ノードＦＤａまたはＦＤｂに蓄積された信号電荷がリセットトランジスタ７６を介して排出され、電荷蓄積ノードの電位が電圧Ｖｒにリセットされる。 In this example, at time T2, the reset is performed by setting the reset signal rstrst to low level. That is, when the reset signal rstrst is set to low level, the reset transistor 76 is turned on, the signal charge stored in the node FDa or FDb is discharged through the reset transistor 76, and the potential of the charge storage node becomes the voltage Vr. It is reset.
　次に、時刻Ｔ３において、リセット信号Φｒｓｔをハイレベルとしてリセットトランジスタ７６をオフする。ここでは、時刻Ｔ３から時刻Ｔ４までの間に、リセット電圧Ｖｒに対応する第２の信号を垂直信号線８９に読み出す。図１０中に模式的に示すように、時刻Ｔ１から時刻Ｔ２までの間に読み出された第１の信号と、時刻Ｔ３から時刻Ｔ４までの間に読み出された第２の信号との差分が、真の画素信号として出力される。 Next, at time T3, the reset signal rstrst is set to the high level to turn off the reset transistor 76. Here, the second signal corresponding to the reset voltage Vr is read out to the vertical signal line 89 from time T3 to time T4. As schematically shown in FIG. 10, the difference between the first signal read from time T1 to time T2 and the second signal read from time T3 to time T4. Are output as true pixel signals.
　その後、時刻Ｔ４において、制御線８１に印加する電圧Ｖｃを第２電圧ＶBから第１電圧ＶAに戻す。これにより、容量素子Ｃ１を介した容量結合によって電荷蓄積ノードの電位がＶｒからＶ１ｅに上昇する。このときの変動量である｜Ｖｒ－Ｖ１ｅ｜は、制御線８１に印加する電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに低下させたときのΔＶＦＤに等しい。 Then, at time T4, it returns the voltage Vc to be applied to the control line 81 from the second voltage V B to the first voltage V A. Thereby, the potential of the charge storage node rises from Vr to V1e by capacitive coupling via the capacitive element C1. The fluctuation amount | Vr−V1e | at this time is equal to ΔV FD when the voltage Vc applied to the control line 81 is reduced from the first voltage V A to the second voltage V B.
　この例のように信号電荷として電子を用いる場合には、上述したように、支持基板６０Ｓとしてｎ型シリコン基板を用い、不純物領域６０ａ～６０ｅの導電型をｐ型とすると有益である。すなわち、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６をｐ型のトランジスタとすることが望ましい。 In the case where electrons are used as signal charges as in this example, as described above, it is useful to use an n-type silicon substrate as the support substrate 60S and to set the conductivity type of the impurity regions 60a to 60e to p-type. That is, it is desirable that the signal detection transistor 72, the address transistor 74, and the reset transistor 76 be p-type transistors.
　支持基板６０Ｓとしてｐ型シリコン基板を用い、リセットトランジスタ７６をｎチャンネルＭＯＳとした場合であれば、基板電位Ｖｓｕｂとしては例えば０Ｖが用いられる。ここで、リセットトランジスタ７６をｐチャンネルＭＯＳとし、基板電位Ｖｓｕｂとして０Ｖを採用したとする。このとき、図１０に模式的に示すように、信号電荷である電子の電荷蓄積ノードへの蓄積に伴い、電圧ＶＦＤが低下するので、不純物領域６０ａとその周囲との間のｐｎ接合に印加される電圧が順バイアスとなることを避けるために、信号電荷の蓄積に先立ち、電荷蓄積ノードの電位を基板電位Ｖｓｕｂよりも高い電位にリセットする必要がある。 If a p-type silicon substrate is used as the support substrate 60S and the reset transistor 76 is an n-channel MOS, for example, 0 V is used as the substrate potential Vsub. Here, it is assumed that the reset transistor 76 is a p-channel MOS, and 0 V is adopted as the substrate potential Vsub. At this time, as schematically shown in FIG. 10, voltage V FD is lowered along with accumulation of electrons which are signal charges in the charge storage node, so that the voltage is applied to the pn junction between impurity region 60a and the periphery thereof. It is necessary to reset the potential of the charge storage node to a potential higher than the substrate potential Vsub prior to the accumulation of the signal charge in order to avoid the forward bias of the output voltage.
　既に説明したように、信号電荷が電子である場合、リセット電圧Ｖｒとしては、例えば３．３Ｖの電圧を用い得る。この場合、信号電荷の蓄積に伴い、電荷蓄積ノードの電位が露光開始時の例えば３．３Ｖから低下し、基板電位Ｖｓｕｂとの間の電位差が縮小する。したがって、空乏層幅が縮小され、暗電流低減の効果が期待できる。 As described above, when the signal charge is an electron, for example, a voltage of 3.3 V can be used as the reset voltage Vr. In this case, with the accumulation of the signal charge, the potential of the charge storage node drops from, for example, 3.3 V at the start of the exposure, and the potential difference between it and the substrate potential Vsub decreases. Therefore, the depletion layer width is reduced, and the effect of dark current reduction can be expected.
　なお、暗電流低減の観点からは、信号電荷として正孔を用いる場合には、各トランジスタをｎチャンネルＭＯＳとする方が有利である。これは、以下の理由による。 From the viewpoint of reducing dark current, when holes are used as signal charges, it is more advantageous to use n-channel MOS transistors as transistors. This is due to the following reasons.
　例えばリセットトランジスタ７６にｐ型のトランジスタを適用した場合、基板電位Ｖｓｕｂとしては、例えば３．３Ｖ程度の電圧が用いられる。支持基板６０Ｓとしてｎ型シリコン基板を用い、不純物領域６０ａ～６０ｅの導電型がｐ型である場合、印加電圧が順バイアスとなることを避けるために、不純物領域６０ａの電位ＶFDを基板電位Ｖｓｕｂよりも上昇させることはできない。また、電荷蓄積ノードに正孔が蓄積されるに伴って不純物領域６０ａの電位ＶFDが上昇する。したがって、信号電荷の蓄積に先立ち、電荷蓄積ノードの電位は、基板電位Ｖｓｕｂよりも低い例えば０Ｖの電位にリセットされる。この場合、露光開始時の電荷蓄積ノードの電位と基板電位Ｖｓｕｂとの間の差が、リセットトランジスタ７６としてｎチャンネルＭＯＳを用いる場合と比較して拡大してしまうからである。 For example, when a p-type transistor is applied to the reset transistor 76, a voltage of, for example, about 3.3 V is used as the substrate potential Vsub. When an n-type silicon substrate is used as support substrate 60S and the conductivity type of impurity regions 60a to 60e is p-type, the potential V FD of impurity region 60a is set to the substrate potential Vsub to prevent the applied voltage from becoming forward bias. It can not be raised more than that. In addition, as holes are stored in the charge storage node, the potential V FD of the impurity region 60a rises. Therefore, prior to the accumulation of the signal charge, the potential of the charge storage node is reset to a potential of, for example, 0 V lower than the substrate potential Vsub. In this case, the difference between the potential of the charge storage node at the start of exposure and the substrate potential Vsub is enlarged as compared with the case where an n-channel MOS is used as the reset transistor 76.
　図１１Ａおよび図１１Ｂは、画素１０のさらに他の回路構成の例を模式的に示す。 11A and 11B schematically show an example of still another circuit configuration of the pixel 10.
　図３に示す画素１０Ａと比較して、図１１Ａに示す画素１０Ａｖは、容量素子Ｃと制御線８１との間に接続されたトランジスタ７１をさらに有する。図１１Ａに示す画素１０Ａｖと、図１１Ｂに示す画素１０Ａｗとの間の相違点は、画素１０Ａｗでは、トランジスタ７１がノードＦＤａと容量素子Ｃ１との間に接続されている点である。 Compared to the pixel 10A shown in FIG. 3, the pixel 10Av shown in FIG. 11A further includes a transistor 71 connected between the capacitive element C and the control line 81. The difference between the pixel 10Av shown in FIG. 11A and the pixel 10Aw shown in FIG. 11B is that in the pixel 10Aw, the transistor 71 is connected between the node FDa and the capacitive element C1.
　図１１Ａに示す画素１０Ａｖ中のトランジスタ７１は、容量素子Ｃ１と電圧供給回路１２８との間の接続および遮断を切り替えるスイッチング素子としての機能を有する。図１１Ｂに示す画素１０Ａｗ中のトランジスタ７１は、ノードＦＤａと容量素子Ｃ１との間の接続および遮断を切り替えるスイッチング素子としての機能を有する。図１１Ａに例示する回路構成によれば、トランジスタ７１のゲートに印加する制御信号Φｓの電位の制御によってトランジスタ７１をオフすることにより、電荷蓄積ノード全体の容量値を縮小することができる。図１１Ｂに例示する回路構成によれば、ノードＦＤａから容量素子Ｃ１を電気的に切り離すことができる。 The transistor 71 in the pixel 10Av illustrated in FIG. 11A has a function as a switching element that switches connection and disconnection between the capacitive element C1 and the voltage supply circuit 128. The transistor 71 in the pixel 10Aw illustrated in FIG. 11B has a function as a switching element that switches connection and disconnection between the node FDa and the capacitive element C1. According to the circuit configuration illustrated in FIG. 11A, by turning off the transistor 71 by controlling the potential of the control signal ss applied to the gate of the transistor 71, the capacitance value of the entire charge storage node can be reduced. According to the circuit configuration illustrated in FIG. 11B, capacitive element C1 can be electrically disconnected from node FDa.
　これまでの各例によって説明したように、ノードＦＤａまたはノードＦＤｂに容量素子Ｃ１を接続し、制御線８１に供給する電圧を切り替えることにより、容量素子Ｃ１を介して電荷蓄積ノードの電位を制御することが可能になる。ただし、容量素子Ｃ１を接続した結果、電荷蓄積ノード全体の容量値が増大するので、信号電荷を電圧に変換する際のコンバージョンゲインが低下し得る。 As described in each of the above examples, capacitive element C1 is connected to node FDa or node FDb, and the voltage supplied to control line 81 is switched to control the potential of the charge storage node via capacitive element C1. It becomes possible. However, since the capacitance value of the entire charge storage node is increased as a result of connecting the capacitive element C1, the conversion gain at the time of converting the signal charge into a voltage may be reduced.
　図１１Ａおよび図１１Ｂに例示するように、容量素子Ｃ１と電圧供給回路１２８との間、または、ノードＦＤａもしくはノードＦＤｂと容量素子Ｃ１との間にトランジスタ７１を介在させてもよい。これにより、トランジスタ７１のオンおよびオフの切り替えによって、電荷蓄積ノード全体の容量値を変化させ得る。換言すれば、トランジスタ７１のオンおよびオフの切り替えにより、容量素子Ｃ１を介して電荷蓄積ノードの電位を制御するＦＤ電位制御モード、および、信号電荷を効率的に電圧信号に変換する高ゲインモードを使い分けることが可能となる。ＦＤ電位制御モードは、トランジスタ７１をオンとして電圧供給回路１２８を、容量素子Ｃ１を介して電荷蓄積ノードに電気的に結合するモードであり、高ゲインモードは、トランジスタ７１をオフとして電荷蓄積ノード全体の容量値を低下させたモードである。 As illustrated in FIGS. 11A and 11B, a transistor 71 may be interposed between the capacitive element C1 and the voltage supply circuit 128, or between the node FDa or the node FDb and the capacitive element C1. As a result, the on / off switching of the transistor 71 can change the capacitance value of the entire charge storage node. In other words, the FD potential control mode in which the potential of the charge storage node is controlled via the capacitive element C1 by switching on and off of the transistor 71, and the high gain mode in which the signal charge is efficiently converted into a voltage signal. It becomes possible to use properly. The FD potential control mode is a mode in which the transistor 71 is turned on to electrically couple the voltage supply circuit 128 to the charge storage node via the capacitive element C1. In the high gain mode, the transistor 71 is turned off and the entire charge storage node is turned off. Is a mode in which the capacitance value of
　モードの切り替えは、暗電流への影響が大きくなるような露光時間または動作温度を判定基準として自動的に実行されてもよいし、ユーザの指示に基づいて実行されてもよい。例えば、１秒を超える長秒露光または８０度を超える高温環境下での撮影にＦＤ電位制御モードを選択し得る。ＦＤ電位制御モードにおける動作シーケンスは、図４Ａ、図４Ｂ、図４Ｃ、図８または図１０を参照して説明した動作シーケンスと同様であり得るので、動作に関する説明を省略する。 The mode switching may be automatically performed using an exposure time or an operating temperature as a criterion that has a large influence on dark current, or may be performed based on a user's instruction. For example, the FD potential control mode may be selected for imaging under a long second exposure for over 1 second or a high temperature environment for over 80 degrees. The operation sequence in the FD potential control mode may be the same as the operation sequence described with reference to FIG. 4A, FIG. 4B, FIG. 4C, FIG. 8 or FIG.
　図１１Ｃは、画素１０のさらに他の回路構成の例を模式的に示す。図１１Ｃに例示する構成において、撮像装置１００は、垂直信号線８９に接続された負荷トランジスタ７３を有する。負荷トランジスタ７３は、例えばｎチャンネルＭＯＳであり、電流源９４として機能する。 FIG. 11C schematically shows an example of still another circuit configuration of the pixel 10. In the configuration illustrated in FIG. 11C, the imaging device 100 includes a load transistor 73 connected to the vertical signal line 89. The load transistor 73 is, for example, an n-channel MOS, and functions as a current source 94.
　また、図１１Ｃに示す例において、撮像装置１００は、フィードバック回路９０ｘを有する。フィードバック回路９０ｘは、反転入力端子が垂直信号線８９に接続された反転増幅器９２を含む。反転増幅器９２は、垂直信号線８９に対応して画素１０Ａｘの列ごとに設けられ、ここでは、リセット電圧線８５がその出力端子に接続されている。図示する例において、信号検出トランジスタ７２、アドレストランジスタ７４、反転増幅器９２およびリセットトランジスタ７６は、光電変換部５０Ａで発生した電気信号を負帰還させるフィードバックループを形成する。 Further, in the example illustrated in FIG. 11C, the imaging device 100 includes a feedback circuit 90x. The feedback circuit 90x includes an inverting amplifier 92 whose inverting input terminal is connected to the vertical signal line 89. The inverting amplifier 92 is provided for each column of the pixels 10Ax corresponding to the vertical signal line 89, and here, the reset voltage line 85 is connected to the output terminal thereof. In the illustrated example, the signal detection transistor 72, the address transistor 74, the inverting amplifier 92, and the reset transistor 76 form a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion unit 50A.
　撮像装置１００の動作時、反転増幅器９２の非反転入力端子には、例えば１Ｖまたは１Ｖ近傍の電圧Ｖｒｅｆが供給される。電圧Ｖｒｅｆとしては、電源電圧Ｖｄｄおよび接地の範囲内の任意の大きさの電圧を用い得る。フィードバックループの形成時、垂直信号線８９の電圧は、反転増幅器９２の非反転入力端子に入力された電圧Ｖｒｅｆに収束する。換言すれば、フィードバックループの形成により、ノードＦＤａの電位を、垂直信号線８９の電圧がＶｒｅｆとなるような電位にリセットすることができる。 At the time of operation of the imaging device 100, a voltage Vref of, for example, 1 V or near 1 V is supplied to the non-inverting input terminal of the inverting amplifier 92. As the voltage Vref, any voltage within the range of the power supply voltage Vdd and the ground can be used. When the feedback loop is formed, the voltage of the vertical signal line 89 converges to the voltage Vref input to the non-inverting input terminal of the inverting amplifier 92. In other words, by forming the feedback loop, the potential of the node FDa can be reset to a potential at which the voltage of the vertical signal line 89 becomes Vref.
　第１の信号および第２の信号は、信号検出トランジスタ７２および電流源９４によって形成されるソースフォロアによって垂直信号線８９に読み出される。信号読み出し時におけるノードＦＤａの電位が低電位であると、信号検出トランジスタ７２を介して垂直信号線８９に現れる電圧も低くなり、飽和領域での動作に必要なソース－ドレイン電圧を確保できず、負荷トランジスタ７３が線形領域で動作する可能性がある。その結果、ソースフォロアが正常に動作せず信号の線形性が低下するおそれがある。 The first signal and the second signal are read out to the vertical signal line 89 by the source follower formed by the signal detection transistor 72 and the current source 94. When the potential of the node FDa at the time of signal reading is low, the voltage appearing on the vertical signal line 89 via the signal detection transistor 72 is also low, and the source-drain voltage necessary for operation in the saturation region can not be secured. The load transistor 73 may operate in the linear region. As a result, the source follower may not operate properly and the linearity of the signal may be degraded.
　電流源９４によって得られる電流値を小さく設定すれば負荷トランジスタ７３を飽和領域で動作させることが可能であるが、この場合、信号の読み出しに要する速度が低下するなどの課題が生じ得る。また、垂直信号線８９の電圧低下により、反転増幅器９２への入力信号が動作レンジから外れ、フィードバック回路９０ｘが正常に動作しなくなるおそれがある。つまり、ノードＦＤａの電位を垂直信号線８９の電圧がＶｒｅｆとなるような電位にリセットできなくなる可能性がある。 If the current value obtained by the current source 94 is set small, it is possible to operate the load transistor 73 in the saturation region, but in this case, a problem such as a reduction in the speed required for reading out a signal may occur. Further, the voltage drop of the vertical signal line 89 may cause the input signal to the inverting amplifier 92 to be out of the operating range, and the feedback circuit 90x may not operate properly. That is, there is a possibility that the potential of the node FDa can not be reset to such a potential that the voltage of the vertical signal line 89 becomes Vref.
　画素１０Ａｘを有する撮像装置には、例えば、図４Ｃ、図８または図１０を参照して説明した動作シーケンスを適用し得る。すなわち、制御線８１に供給する電圧を第１電圧ＶAおよび第２電圧ＶBの間で切り替えることにより、非露光期間の少なくとも一部の期間において電荷蓄積ノードの電位を、容量素子Ｃ１を介して一時的に上昇または低下させる。例えば信号電荷として正孔を用いる場合であれば、電圧供給回路１２８から制御線８１に印加する電圧の切り替えにより、露光期間以外の非露光期間において電荷蓄積ノードの電位を選択的に上昇させる。 For the imaging device having the pixel 10Ax, for example, the operation sequence described with reference to FIG. 4C, FIG. 8 or FIG. 10 can be applied. In other words, by switching the voltage supplied to the control line 81 between the first voltage V A and the second voltage V B, the potential of the charge storage node in at least a part of the period of non-exposure period, through the capacitor C1 Temporarily raise or lower. For example, in the case of using holes as signal charges, the potential of the charge storage node is selectively raised in a non-exposure period other than the exposure period by switching the voltage applied from the voltage supply circuit 128 to the control line 81.
　非露光期間において電荷蓄積ノードの電位を選択的に高電位に設定することにより、負荷トランジスタ７３が線形領域で動作することを抑制して、第１の信号および第２の信号を画素から正常に読み出すことが可能である。なお、信号の読み出し動作およびフィードバック動作は、非露光期間に実行されるので、露光期間では、電荷蓄積ノードの電位が、負荷トランジスタ７３が線形領域で動作するような低電位であっても問題はない。露光期間における電荷蓄積ノードの電位を低電位に設定することにより、回路特性を劣化させることなく、暗電流を抑制することができるという効果も得られる。 By setting the potential of the charge storage node to a high potential selectively in the non-exposure period, the load transistor 73 is prevented from operating in the linear region, and the first signal and the second signal are normally output from the pixel. It is possible to read out. Since the signal read operation and the feedback operation are performed during the non-exposure period, there is no problem even if the potential of the charge storage node is low such that the load transistor 73 operates in the linear region during the exposure period. Absent. By setting the potential of the charge storage node to a low potential in the exposure period, it is possible to obtain an effect that the dark current can be suppressed without deteriorating the circuit characteristics.
　（第２の実施形態）
　図１２は、本開示の第２の実施形態による撮像装置が有する画素１０Ｂの回路構成の一例を模式的に示す。図３に示す画素１０Ａと同様に、図１２に示す画素１０Ｂは、上述の画素１０の一例である。図１２に示す画素１０Ｂと、図３を参照して説明した画素１０Ａとの間の主な相違点は、画素１０Ｂが、リセットトランジスタ７６のソースおよびドレインのうちノードＦＤａに接続されていない側に接続されたトランジスタ７８をさらに有している点である。また、電圧供給回路１２８が、リセットトランジスタ７６およびトランジスタ７８の間のノードＲＤに電気的に接続されている点である。この例では、電圧供給回路１２８は、リセットトランジスタ７６を介して不純物領域６０ａに電気的に接続される。 Second Embodiment
FIG. 12 schematically illustrates an example of the circuit configuration of the pixel 10B included in the imaging device according to the second embodiment of the present disclosure. Similar to the pixel 10A shown in FIG. 3, the pixel 10B shown in FIG. 12 is an example of the pixel 10 described above. The main difference between the pixel 10B shown in FIG. 12 and the pixel 10A described with reference to FIG. 3 is that the pixel 10B is not connected to the node FDa among the source and drain of the reset transistor 76. It is the point which further has the transistor 78 connected. Also, the voltage supply circuit 128 is electrically connected to a node RD between the reset transistor 76 and the transistor 78. In this example, voltage supply circuit 128 is electrically connected to impurity region 60 a via reset transistor 76.
　図１２に例示されるように、撮像装置１００の各画素１０は、リセットトランジスタ７６に接続されたトランジスタ７８をさらに含む回路構成を有し得る。トランジスタ７８は、例えばｎチャンネルＭＯＳであり、リセットトランジスタ７６のソース領域またはドレイン領域としての不純物領域６０ｂをドレイン領域またはソース領域として含み得る。図１２に例示する構成において、トランジスタ７８のソースおよびドレインのうち、リセットトランジスタ７６に接続されていない側にはリセット電圧線８５が接続されており、撮像装置１００の動作時、例えば、所定のリセット電圧Ｖｒがトランジスタ７８に印加される。トランジスタ７８のゲートには、トランジスタ７８のオンおよびオフを制御するための信号Φｆｂをトランジスタ７８に供給するための信号線８８が接続されている。信号線８８は、例えば垂直走査回路１２２との接続を有し、垂直走査回路１２２は、信号線８８の電位を制御するように構成され得る。 As illustrated in FIG. 12, each pixel 10 of the imaging device 100 may have a circuit configuration further including a transistor 78 connected to the reset transistor 76. The transistor 78 is, for example, an n-channel MOS, and can include an impurity region 60 b as a source region or a drain region of the reset transistor 76 as a drain region or a source region. In the configuration illustrated in FIG. 12, among the source and drain of the transistor 78, the reset voltage line 85 is connected to the side not connected to the reset transistor 76. For example, when the imaging device 100 operates, a predetermined reset is performed. A voltage Vr is applied to the transistor 78. The gate of the transistor 78 is connected to a signal line 88 for supplying the transistor 78 with a signal fb fb for controlling the on and off of the transistor 78. The signal line 88 has, for example, a connection with the vertical scanning circuit 122, and the vertical scanning circuit 122 can be configured to control the potential of the signal line 88.
　この例では、電圧供給回路１２８は、容量素子Ｃ２を介して、リセットトランジスタ７６およびトランジスタ７８の間のノードＲＤに接続されている。すなわち、この例では、電圧供給回路１２８は、リセットトランジスタ７６の不純物領域６０ａ側ではなく、不純物領域６０ｂ側に容量素子Ｃ２を介して接続されている。なお、制御線８１と不純物領域６０ｂとの間に接続された容量素子Ｃ２は、上述の容量素子Ｃ１と同様の構成を有し得る。もちろん、容量素子Ｃ２および上述の容量素子Ｃ１の構成が同一であることは、必須ではない。 In this example, voltage supply circuit 128 is connected to a node RD between reset transistor 76 and transistor 78 via capacitive element C2. That is, in this example, the voltage supply circuit 128 is connected not to the impurity region 60a side of the reset transistor 76 but to the impurity region 60b side via the capacitive element C2. The capacitive element C2 connected between the control line 81 and the impurity region 60b can have the same configuration as the above-mentioned capacitive element C1. Of course, it is not essential that the configurations of the capacitive element C2 and the above-mentioned capacitive element C1 are the same.
　図１３は、図１２に示す回路構成が適用された、より具体的な例を示す。図１３に示す画素１０Ｂｆは、図１２に示す画素１０Ｂの一例であり、フィードバック回路９０を有する。図１３に例示する構成において、フィードバック回路９０は、図１１Ｃを参照して説明した例と同様に、反転入力端子が垂直信号線８９に接続された反転増幅器９２を含む。 FIG. 13 shows a more specific example to which the circuit configuration shown in FIG. 12 is applied. The pixel 10 </ b> Bf illustrated in FIG. 13 is an example of the pixel 10 </ b> B illustrated in FIG. 12 and includes a feedback circuit 90. In the configuration illustrated in FIG. 13, the feedback circuit 90 includes an inverting amplifier 92 whose inverting input terminal is connected to the vertical signal line 89, as in the example described with reference to FIG. 11C.
　図１３に例示する構成において、画素１０Ｂｆは、リセットトランジスタ７６に並列に接続された容量素子Ｃ３を有する。アドレストランジスタ７４と、少なくともトランジスタ７８とがオン状態のとき、フィードバック回路９０は、光電変換部５０Ａで発生した電気信号を負帰還させるフィードバックループを形成する。このフィードバックループは、その一部にトランジスタ７８を含む。 In the configuration illustrated in FIG. 13, the pixel 10 </ b> Bf includes a capacitive element C <b> 3 connected in parallel to the reset transistor 76. When the address transistor 74 and at least the transistor 78 are in the on state, the feedback circuit 90 forms a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion unit 50A. The feedback loop includes transistor 78 in part.
　よく知られているように、トランジスタのオンまたはオフに伴い、ｋＴＣノイズと呼ばれる熱ノイズが発生する。ノードＦＤａの電位のリセット後、リセットトランジスタ７６を単純にオフとするだけでは、リセットトランジスタ７６をオフとすることによって発生するｋＴＣノイズが、信号電荷の蓄積前の電荷蓄積ノードに残留してしまう。しかしながら、リセットトランジスタのオフに伴って発生するｋＴＣノイズは、国際公開第２０１２／１４７３０２号において説明されているように、負帰還を利用することによって低減可能である。参考のために、国際公開第２０１２／１４７３０２号の開示内容の全てを本明細書に援用する。 As well known, thermal noise called kTC noise occurs when the transistor is turned on or off. After resetting the potential of the node FDa, simply turning off the reset transistor 76 causes kTC noise generated by turning off the reset transistor 76 to remain at the charge storage node before the signal charge is stored. However, the kTC noise generated with the turning off of the reset transistor can be reduced by using negative feedback as described in WO 2012/147302. The entire disclosure of WO 2012/147302 is incorporated herein by reference.
　図１２および図１３に示すような回路構成において、リセットトランジスタ７６およびトランジスタ７８の間のノードＲＤに注目すると、このノードＲＤは、浮遊ノードである。上述したように、トランジスタ７８は、不純物領域６０ｂを例えばドレイン領域として含み得る。そのため、トランジスタ７８をオフすると、トランジスタ７８が有する寄生容量に起因した電気的なカップリングによって不純物領域６０ｂの電位が基板電位を下回ってしまうおそれがある。不純物領域６０ｂの電位が基板電位を下回ると、ｐウェルからの余計な正孔の流入によって意図しない電位の変動が不純物領域６０ｂに生じ、ＳＮ比が低下し得る。しかしながら、ここでは、不純物領域６０ｂに電圧供給回路１２８が電気的に接続されている。以下に説明するように、電圧供給回路１２８から制御線８１に印加する電圧Ｖｃを第１電圧ＶAおよび第２電圧ＶBの間で切り替えることにより、不純物領域６０ｂの電位が基板電位を下回ってしまうことを防止可能である。 In the circuit configurations as shown in FIGS. 12 and 13, focusing on the node RD between the reset transistor 76 and the transistor 78, this node RD is a floating node. As described above, the transistor 78 can include the impurity region 60b, for example, as a drain region. Therefore, when the transistor 78 is turned off, there is a possibility that the potential of the impurity region 60b may fall below the substrate potential due to electrical coupling caused by the parasitic capacitance of the transistor 78. When the potential of the impurity region 60b is lower than the substrate potential, the inflow of unnecessary holes from the p well causes an unintended fluctuation of the potential in the impurity region 60b, which may lower the SN ratio. However, here, the voltage supply circuit 128 is electrically connected to the impurity region 60 b. As described below, by switching the voltage Vc to be applied to the control line 81 from the voltage supply circuit 128 between the first voltage V A and the second voltage V B, the potential of the impurity region 60b is lower than the substrate potential Can be prevented.
　図１４Ａは、図１３に示す回路構成を有する画素１０Ｂｆの例示的な動作を説明するためのタイミングチャートである。図１４Ａ中、下から２番目のチャートは、ノードＲＤの電位すなわち不純物領域６０ｂの電位ＶRDの時間的変化を示す。なお、電圧Ｖｃの時間的変化を示すチャートからわかるように、ここでは、図４Ａおよび図４Ｂを参照して説明した第１の例と同様に、時刻Ｔ１の時点において制御線８１には第１電圧ＶAが印加されている。 FIG. 14A is a timing chart for describing an exemplary operation of the pixel 10Bf having the circuit configuration shown in FIG. The second chart from the bottom in FIG. 14A shows temporal changes in the potential of the node RD, ie, the potential V RD of the impurity region 60b. As can be seen from the chart showing temporal changes in voltage Vc, here, as in the first example described with reference to FIG. 4A and FIG. The voltage V A is applied.
　露光による信号電荷の蓄積後、まず、時刻Ｔ１においてアドレス信号Φｓｅｌをハイレベルとする。このとき、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号を読み出す。 After accumulation of signal charges by exposure, first, at time T1, the address signal selsel is set to the high level. At this time, the first signal of the voltage level corresponding to the signal charge stored in the charge storage node is read out.
　次に、時刻Ｔ２にリセット信号Φｒｓｔおよび信号Φｆｂをハイレベルとする。すなわち、リセットトランジスタ７６およびトランジスタ７８をオンとする。リセットトランジスタ７６およびトランジスタ７８のオンにより、フィードバックループが形成される。フィードバックループの形成により、ノードＦＤａの電位がリセットされる。ここでは、ノードＦＤａの電位が、垂直信号線８９の電圧がＶｒｅｆとなるような電圧Ｖ２ａに低下する。このとき、反転増幅器９２の非反転増幅端子に印加する電圧Ｖｒｅｆとして、Ｖ２ａ＞Ｖｓｕｂの関係が満たされるような電圧を用いる。なお、図１４Ａに示す例では、リセットトランジスタ７６およびトランジスタ７８のオンに伴ってノードＲＤの電位ＶRDがＶ３に上昇している。図１４Ａに示すように、電圧Ｖ３は、Ｖ３＞Ｖｓｕｂの関係を満たす。 Next, at time T2, the reset signal rstrst and the signal fbfb are set to the high level. That is, the reset transistor 76 and the transistor 78 are turned on. The turning on of the reset transistor 76 and the transistor 78 forms a feedback loop. The formation of the feedback loop resets the potential of the node FDa. Here, the potential of the node FDa is lowered to the voltage V2a such that the voltage of the vertical signal line 89 becomes Vref. At this time, a voltage that satisfies the relationship of V2a> Vsub is used as the voltage Vref applied to the non-inversion amplification terminal of the inversion amplifier 92. In the example shown in FIG. 14A, the potential V RD of the node RD with the ON of the reset transistor 76 and the transistor 78 is increased to V3. As shown in FIG. 14A, the voltage V3 satisfies the relationship of V3> Vsub.
　次に、時刻Ｔ３にリセット信号Φｒｓｔをローレベルとし、リセットトランジスタ７６をオフする。ここでは、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、リセットトランジスタ７６のオフに伴って不純物領域６０ａの電位ＶFDがＶ２ａからＶ４ａに低下している。上述したように、電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうと、不純物領域６０ａに余計な正孔が流入してしまう。ただし、反転増幅器９２の非反転増幅端子に印加する電圧Ｖｒｅｆを適切に選択することにより、電位ＶFDが基板電位Ｖｓｕｂを下回ることを防止し得る。この例では、電圧Ｖｒｅｆを適切に選択することによってＶ４ａ＞Ｖｓｕｂの関係が満たされている。なお、空乏層をなるべく縮小する観点から、Ｖ４ａ＞Ｖｓｕｂの関係が満たされる限りにおいてＶ４ａがＶｓｕｂになるべく近い電圧であると有益である。 Next, at time T3, the reset signal rstrst is set to low level, and the reset transistor 76 is turned off. Here, due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76, the potential V FD of the impurity region 60a is lowered from V2a to V4a as the reset transistor 76 is turned off. As described above, when the potential V FD falls below the substrate potential Vsub, extra holes flow into the impurity region 60a. However, by appropriately selecting the voltage Vref applied to the non-inversion amplification terminal of the inverting amplifier 92, the potential V FD can be prevented from falling below the substrate potential Vsub. In this example, the relationship of V4a> Vsub is satisfied by properly selecting the voltage Vref. From the viewpoint of reducing the depletion layer as much as possible, it is useful that V4a be as close as possible to Vsub as long as the relationship of V4a> Vsub is satisfied.
　上述したように、リセットトランジスタ７６をオフとすることにより、ｋＴＣノイズが発生する。ただし、図１３に例示する回路構成では、ノードＦＤａとノードＲＤとの間に容量素子Ｃ３が介在しており、トランジスタ７８がオフでない間は、容量素子Ｃ３をその経路に含むフィードバックループが形成された状態が継続する。そのため、トランジスタ７８が出力する信号は、容量素子Ｃ３とノードＦＤａ自体が有する寄生容量とによって形成される減衰回路で減衰される。 As described above, turning off the reset transistor 76 generates kTC noise. However, in the circuit configuration illustrated in FIG. 13, the capacitive element C3 is interposed between the node FDa and the node RD, and while the transistor 78 is not turned off, a feedback loop including the capacitive element C3 in its path is formed. Condition will continue. Therefore, the signal output from the transistor 78 is attenuated by the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa itself.
　リセットトランジスタ７６のオフ後、信号Φｆｂをローレベルとし、トランジスタ７８をオフとする。ここでは、時刻Ｔ４にリセットトランジスタ７６をオフとするだけでなく、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃを第２電圧ＶBに切り替えている。 After the reset transistor 76 is turned off, the signal fbfb is set to low level, and the transistor 78 is turned off. Here, not the time T4 just off the reset transistor 76, which switches the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to a second voltage V B.
　図１４Ａに模式的に示すように、トランジスタ７８をオフすると、トランジスタ７８が有する寄生容量に起因した電気的なカップリングによって不純物領域６０ｂの電位ＶRDが低下する。この例では、トランジスタ７８のオフに伴って、電位ＶRDがＶ３からＶ５ａに低下している。このとき、もし、Ｖ５ａ＜Ｖｓｕｂであると、不純物領域６０ｂに、ノイズの原因となる余計な正孔が流入してしまう。 As schematically shown in FIG. 14A, when the transistor 78 is turned off, the electrical coupling caused by the parasitic capacitance of the transistor 78 lowers the potential V RD of the impurity region 60b. In this example, the potential V RD decreases from V3 to V5a as the transistor 78 is turned off. At this time, if V5a <Vsub, extra holes causing noise will flow into the impurity region 60b.
　図１４Ａ中の電圧Ｖｃのチャートからわかるように、ここでは、電圧供給回路１２８が、トランジスタ７８をオンからオフに切り替えたタイミングで、電圧Ｖｃを第１電圧ＶAから第１電圧ＶAよりも高い第２電圧ＶBに切り替えるように構成されている。電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに切り替えることにより、容量素子Ｃ２を介してノードＲＤの電位ＶRDを上昇させることができ、電位ＶRDが基板電位を下回ってしまうことを防止し得る。第２電圧ＶBの具体的な値としては、トランジスタ７８のソース－ドレイン間の寄生容量の大きさなどを考慮して、トランジスタ７８のオフ時に電位ＶRDがＶ５ａ＞Ｖｓｕｂの関係を満たすこととなるような電圧を選択すればよい。 As can be seen from the chart of voltage Vc in FIG. 14A, here, the voltage supply circuit 128 at the timing of switching off the transistor 78 from ON, than the first voltage V A voltage Vc from the first voltage V A and it is configured to switch to a higher second voltage V B. By switching the voltage Vc from the first voltage V A to the second voltage V B, it is possible to increase the potential V RD of the node RD via the capacitor C2, the potential V RD falls below the substrate potential It can prevent. A specific value of the second voltage V B, the source of the transistor 78 - in consideration of the magnitude of the parasitic capacitance between the drain, the potential V RD at the OFF time of the transistor 78 satisfy the relation of V5a> Vsub and It is sufficient to select such a voltage as
　なお、トランジスタ７８のオフにおいては、トランジスタ７８の閾値電圧を跨ぐように、信号線８８の電位をハイレベルからローレベルに向けて徐々に低下させてもよい。信号線８８の電位をハイレベルからローレベルに向けて徐々に低下させると、トランジスタ７８の抵抗が徐々に増加する。トランジスタ７８の抵抗が増加すると、トランジスタ７８の動作帯域が狭くなり、帰還する信号の周波数領域が狭くなる。 Note that when the transistor 78 is off, the potential of the signal line 88 may be gradually lowered from the high level to the low level so as to cross the threshold voltage of the transistor 78. As the potential of the signal line 88 is gradually lowered from high level to low level, the resistance of the transistor 78 is gradually increased. As the resistance of the transistor 78 increases, the operating band of the transistor 78 narrows, and the frequency range of the signal to be fed back narrows.
　信号線８８の電圧がローレベルに達すると、トランジスタ７８がオフとなり、フィードバックループの形成が解消される。このとき、トランジスタ７８の動作帯域が信号検出トランジスタ７２の動作帯域よりも十分に低い帯域であると、トランジスタ７８で発生する熱ノイズが、フィードバック回路９０によって１／（１＋ＡＢ）1/2倍に抑制される。ここで、式中のＡは、フィードバック回路９０の利得であり、Ｂは、容量素子Ｃ３とノードＦＤａの寄生容量とによって形成される減衰回路の減衰率である。減衰率Ｂは、容量素子Ｃ３およびノードＦＤａの寄生容量の容量値をそれぞれＣｃおよびＣｆとすれば、Ｂ＝Ｃｃ／（Ｃｃ＋Ｃｆ）と表される。したがって、容量素子Ｃ２の容量値と比較して容量素子Ｃ３の容量値Ｃｃがなるべく小さい方が、熱ノイズの影響の低減に有利である。このように、トランジスタ７８の動作帯域が信号検出トランジスタ７２の動作帯域よりも低い状態でトランジスタ７８をオフとすることにより、ノードＦＤａに残存するｋＴＣノイズを低減することが可能である。なお、本明細書において「トランジスタ７８がオフである」とは、トランジスタ７８がｎ型のトランジスタであるとき、信号線８８の電圧が、トランジスタ７８の閾値電圧よりも低いローレベルとされていることを指し、トランジスタ７８がｐ型のトランジスタであるとき、信号線８８の電圧が、トランジスタ７８の閾値電圧よりも高いハイレベルとされていることを指す。 When the voltage of the signal line 88 reaches a low level, the transistor 78 is turned off and the formation of the feedback loop is eliminated. At this time, if the operating band of the transistor 78 is a band sufficiently lower than the operating band of the signal detection transistor 72, the thermal noise generated in the transistor 78 is suppressed by 1 / (1 + AB) 1/2 by the feedback circuit 90. Be done. Here, A in the equation is the gain of the feedback circuit 90, and B is the attenuation factor of the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa. The attenuation factor B is expressed as B = Cc / (Cc + Cf), where Cc and Cf denote capacitance values of parasitic capacitances of the capacitive element C3 and the node FDa, respectively. Therefore, it is advantageous to reduce the influence of the thermal noise if the capacitance value Cc of the capacitive element C3 is as small as possible as compared to the capacitance value of the capacitive element C2. As described above, by turning off the transistor 78 in a state where the operating band of the transistor 78 is lower than the operating band of the signal detection transistor 72, kTC noise remaining in the node FDa can be reduced. In the present specification, “the transistor 78 is off” means that when the transistor 78 is an n-type transistor, the voltage of the signal line 88 is set to a low level lower than the threshold voltage of the transistor 78. When the transistor 78 is a p-type transistor, it indicates that the voltage of the signal line 88 is at a high level higher than the threshold voltage of the transistor 78.
　トランジスタ７８のオフ後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ５までの期間に、電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。図４Ａおよび図４Ｂを参照して説明した第１の例と同様に、第１の信号および第２の信号の差分Δが、画像信号として水平走査回路１２４に出力される。 After the transistor 78 is turned off, a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises. Similar to the first example described with reference to FIGS. 4A and 4B, the difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
　以上に説明したように、この例では、電圧供給回路１２８は、リセットトランジスタ７６がオンである第１の期間に、不純物領域６０ｂに第１電圧ＶAを印加している。さらに、電圧供給回路１２８は、リセットトランジスタ７６がオフとされた後であってトランジスタ７８がオフに切り替えられた第２の期間に、第２電圧ＶBを不純物領域６０ｂに印加している。 As described above, in this example, the voltage supply circuit 128 applies the first voltage V A to the impurity region 60b during the first period in which the reset transistor 76 is on. Further, the voltage supply circuit 128, the reset transistor 76 is a transistor 78 even after having been turned off within a second time period which is switched off, and the second voltage V B is applied to the impurity regions 60b.
　第２の実施形態によれば、リセットトランジスタ７６およびトランジスタ７８をオンとしたときの不純物領域６０ａの電位Ｖ２ａと、トランジスタ７８をさらにオフとしたときの不純物領域６０ａの電位Ｖ４ａとを、基板電位Ｖｓｕｂを下回ることを抑制しながら、基板電位Ｖｓｕｂに近いなるべく低い電位とすることが可能である。また、不純物領域６０ｂに関しても、トランジスタ７８をオンとしたときの電位Ｖ３と、その後にトランジスタ７８をオフとしたときの電位Ｖ５ａとを、基板電位Ｖｓｕｂを下回ることを抑制しながら、基板電位Ｖｓｕｂに近いなるべく低い電位とすることが可能である。したがって、トランジスタ７８を介した、電気的なカップリングによる電位ＶRDの変動に起因する暗電流の発生を抑制して、暗電流に起因する画質の劣化が抑制された画像信号を得ることができる。 According to the second embodiment, the potential V2a of the impurity region 60a when the reset transistor 76 and the transistor 78 are turned on, and the potential V4a of the impurity region 60a when the transistor 78 is further turned off are the substrate potential Vsub. It is possible to make the potential as low as possible close to the substrate potential Vsub while suppressing that Further, with respect to impurity region 60b, the potential V3 when transistor 78 is turned on and the potential V5a when transistor 78 is turned off thereafter are suppressed to the substrate potential Vsub while being suppressed below the substrate potential Vsub. The potential can be as close as possible. Therefore, generation of dark current due to fluctuation of potential V RD due to electrical coupling via transistor 78 can be suppressed, and an image signal in which image quality deterioration due to dark current is suppressed can be obtained. .
　リセットトランジスタ７６およびトランジスタ７８に、ｎ型に代えてｐ型のトランジスタを適用することも可能である。図１４Ｂは、画素１０Ｂｆのリセットトランジスタ７６およびトランジスタ７８にｐ型のトランジスタを適用したときの例示的な動作を説明するためのタイミングチャートである。図４Ｂを参照して説明した例と同様に、ここでは、信号電荷として電子を用いた例を説明する。この場合、信号検出トランジスタ７２およびアドレストランジスタ７４も典型的にはｐ型のトランジスタである。 It is also possible to apply a p-type transistor to the reset transistor 76 and the transistor 78 instead of the n-type. FIG. 14B is a timing chart for describing an exemplary operation when a p-type transistor is applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf. Similar to the example described with reference to FIG. 4B, an example using electrons as signal charges will be described here. In this case, the signal detection transistor 72 and the address transistor 74 are also typically p-type transistors.
　露光による信号電荷の蓄積後、まず、時刻Ｔ１においてアドレス信号Φｓｅｌをローレベルとし、第１の信号を読み出す。次に、時刻Ｔ２にリセットトランジスタ７６およびトランジスタ７８をオンとし、フィードバックループを形成する。フィードバックループの形成により、ノードＦＤａの電位が、垂直信号線８９の電圧がＶｒｅｆとなるような電圧Ｖ２ｂにリセットされる。このとき、電圧Ｖｒｅｆとして、Ｖ２ｂ＜Ｖｓｕｂの関係が満たされるような電圧を用いる。また、この例では、リセットトランジスタ７６およびトランジスタ７８のオンに伴ってノードＲＤの電位ＶRDがＶ３に上昇している。電圧Ｖ３は、Ｖ３＜Ｖｓｕｂの関係を満たす。 After accumulation of signal charges by exposure, first, at time T1, the address signal selsel is set to low level, and the first signal is read out. Next, at time T2, the reset transistor 76 and the transistor 78 are turned on to form a feedback loop. By the formation of the feedback loop, the potential of the node FDa is reset to the voltage V2b such that the voltage of the vertical signal line 89 becomes Vref. At this time, a voltage that satisfies the relationship of V2b <Vsub is used as the voltage Vref. Further, in this example, the potential V RD of the node RD rises to V 3 as the reset transistor 76 and the transistor 78 are turned on. The voltage V3 satisfies the relationship of V3 <Vsub.
　次に、時刻Ｔ３にリセットトランジスタ７６をオフする。ここでは、リセットトランジスタ７６のオフに伴って不純物領域６０ａの電位ＶFDがＶ２ｂからＶ４ｂに上昇している。電位ＶFDが基板電位Ｖｓｕｂを上回ってしまうと暗電流が生じてしまうので、電位ＶFDが基板電位Ｖｓｕｂを超えないように、反転増幅器９２の非反転増幅端子に印加する電圧Ｖｒｅｆを適切に選択する。空乏層をなるべく縮小する観点からは、Ｖ４ｂ＜Ｖｓｕｂの関係が満たされる限りにおいてＶ４ｂがＶｓｕｂになるべく近い電圧であると有益である。 Next, at time T3, the reset transistor 76 is turned off. Here, as the reset transistor 76 is turned off, the potential V FD of the impurity region 60a is raised from V2b to V4b. Since the potential V FD is caused dark current when outweighs the substrate potential Vsub, so that the potential V FD does not exceed the substrate potential Vsub, proper selection of voltage Vref applied to the non-inverting amplifier terminal of the inverting amplifier 92 Do. From the viewpoint of reducing the depletion layer as much as possible, it is useful that V4b be as close as possible to Vsub as long as the relationship of V4b <Vsub is satisfied.
　リセットトランジスタ７６のオフ後、時刻Ｔ４に、トランジスタ７８をオフとする。このとき、トランジスタ７８の閾値電圧を跨ぐように信号線８８の電位をローレベルからハイレベルに向けて徐々に上昇させることにより、トランジスタ７８をオフとしてもよい。トランジスタ７８をオフすると、トランジスタ７８が有する寄生容量に起因した電気的なカップリングによって不純物領域６０ｂの電位ＶRDが上昇し得る。この例では、トランジスタ７８のオフに伴って、電位ＶRDがＶ３からＶ５ｂに上昇している。 After the reset transistor 76 is turned off, the transistor 78 is turned off at time T4. At this time, the transistor 78 may be turned off by gradually raising the potential of the signal line 88 from low level to high level so as to cross the threshold voltage of the transistor 78. When the transistor 78 is turned off, the electrical coupling due to the parasitic capacitance of the transistor 78 may increase the potential V RD of the impurity region 60b. In this example, the potential V RD rises from V3 to V5 b as the transistor 78 is turned off.
　このとき、もし、Ｖ５ｂ＞Ｖｓｕｂであると、不純物領域６０ｂに、ノイズの原因となる余計な電荷が混入してしまう。図１４Ｂに示すように、トランジスタ７８をオフとするだけでなく、電圧供給回路１２８から制御線８１に印加される電圧Ｖｃを、第１電圧ＶAよりも低い第２電圧ＶBに切り替えることにより、容量素子Ｃ２を介してノードＲＤの電位ＶRDを低下させることができ、電位ＶRDが基板電位を上回ってしまうことを防止し得る。 At this time, if V5b> Vsub, an extra charge causing noise will be mixed into the impurity region 60b. As shown in FIG. 14B, not only turns off the transistor 78, the voltage Vc applied from the voltage supply circuit 128 to the control line 81, by switching to lower than the first voltage V A second voltage V B , it is possible to lower the potential V RD of the node RD via the capacitor C2, the potential V RD may be prevented from being exceeded substrate potential.
　トランジスタ７８のオフ後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ５までの期間に、電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。第１の信号および第２の信号の差分Δが、画像信号として水平走査回路１２４に出力される。 After the transistor 78 is turned off, a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises. The difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
　このように、トランジスタ７８のオフのタイミングで電圧Ｖｃを第１電圧ＶAから第１電圧ＶAよりも低い第２電圧ＶBに切り替えることにより、リセットトランジスタ７６およびトランジスタ７８にｐ型のトランジスタを適用した場合であっても、トランジスタ７８を介した、電気的なカップリングによる電位ＶRDの変動に起因する暗電流の発生を抑制することが可能である。 Thus, by switching the voltage Vc from the first voltage V A to the second voltage V B lower than the first voltage V A at the timing when the transistor 78 is off, p-type transistors are used as the reset transistor 76 and the transistor 78. Even in the case of application, it is possible to suppress the generation of dark current due to the fluctuation of the potential V RD due to electrical coupling via the transistor 78.
　（第２の実施形態の変形例）
　図１５は、本開示の第２の実施形態による撮像装置の変形例を示す。図１５に示す画素１０Ｂｐは、図１２に示す画素１０Ｂの光電変換部５０Ａを光電変換部５０Ｂに置き換えた回路構成を有する。 (Modification of the second embodiment)
FIG. 15 shows a modification of the imaging device according to the second embodiment of the present disclosure. The pixel 10Bp illustrated in FIG. 15 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10B illustrated in FIG. 12 is replaced with a photoelectric conversion unit 50B.
　画素１０Ｂｐを有する撮像装置１００の動作は、例えば、図１４Ａまたは図１４Ｂを参照して説明した動作と同様であり得る。すなわち、リセットトランジスタ７６がオンである第１の期間に、不純物領域６０ｂに第１電圧ＶAを印加し、リセットトランジスタ７６がオフとされた後であってトランジスタ７８がオフに切り替えられた第２の期間に、不純物領域６０ｂに第２電圧ＶBを印加するような動作を適用し得る。 The operation of the imaging device 100 having the pixel 10Bp may be similar to, for example, the operation described with reference to FIG. 14A or 14B. That is, the first period the reset transistor 76 is on, the first voltage V A is applied to the impurity region 60b, the reset transistor 76 is a transistor 78 even after having been turned off is switched off 2 the period may apply operations such as applying a second voltage V B to the impurity regions 60b.
　図１５に示す回路構成によれば、図１２に示す画素１０Ｂと同様に、電圧Ｖｃを第１電圧ＶAから第２電圧ＶBに切り替えることにより、浮遊ノードであるノードＲＤの電位を、容量素子Ｃ２を介して例えば上昇させることができる。したがって、トランジスタ７８のオフに起因して不純物領域６０ｂの電位ＶRDが基板電位Ｖｓｕｂを下回ってしまうことを回避して、暗電流を抑制し得る。なお、図６に示す画素１０Ａｑと同様に、信号検出トランジスタ７２のゲートと光電変換部５０Ｂとの間に転送トランジスタ７９がさらに接続されてもよい。 According to the circuit configuration shown in FIG. 15, similarly to the pixel 10B shown in FIG. 12, by switching the voltage Vc from the first voltage V A to the second voltage V B, the potential of the node RD is floating node, capacitance It can be raised, for example, via element C2. Therefore, the dark current can be suppressed by preventing the potential V RD of the impurity region 60b from being lower than the substrate potential Vsub due to the turning off of the transistor 78. As in the pixel 10Aq shown in FIG. 6, a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
　図１６は、本開示の第２の実施形態による撮像装置の他の変形例を示す。図１６に示す画素１０Ｂｒも、上述の画素１０の一例である。図１６に示す画素１０Ｂｒと、図１２を参照して説明した画素１０Ｂとの間の主な相違点は、画素１０Ｂｒでは、トランジスタ７８およびリセットトランジスタ７６の間のノードＲＤではなく、トランジスタ７８のソースおよびドレインのうちリセットトランジスタ７６に接続されていない側に電圧供給回路１２８が電気的に接続されている点である。すなわち、図１６に示す例では、電圧供給回路１２８に接続された制御線８１が、トランジスタ７８のソースおよびドレインのうちリセットトランジスタ７６に接続されていない側に接続されている。 FIG. 16 shows another modified example of the imaging device according to the second embodiment of the present disclosure. The pixel 10Br illustrated in FIG. 16 is also an example of the above-described pixel 10. The main difference between the pixel 10Br shown in FIG. 16 and the pixel 10B described with reference to FIG. 12 is that in the pixel 10Br, the source of the transistor 78, not the node RD between the transistor 78 and the reset transistor 76. The voltage supply circuit 128 is electrically connected to the side of the drain and the drain not connected to the reset transistor 76. That is, in the example shown in FIG. 16, the control line 81 connected to the voltage supply circuit 128 is connected to the side of the source and the drain of the transistor 78 which is not connected to the reset transistor 76.
　（撮像装置１００の動作の第３の例）
　図１７Ａは、図１６に示す回路構成を有する画素１０Ｂｒの例示的な動作を説明するためのタイミングチャートである。図１４Ａを参照して説明した動作例と比較して、図１７Ａに示す動作例は、制御線８１に印加する電圧を第１電圧ＶAおよび第２電圧ＶBの間で切り替えるタイミングが異なっている。 (Third Example of Operation of Imaging Device 100)
FIG. 17A is a timing chart for illustrating an exemplary operation of the pixel 10Br having the circuit configuration shown in FIG. Compared to the operation example described with reference to FIG. 14A, the operation example shown in FIG. 17A, unlike the timing of switching the voltage applied to the control line 81 between the first voltage V A and the second voltage V B There is.
　露光による信号電荷の蓄積後、まず、時刻Ｔ１においてアドレス信号Φｓｅｌをハイレベルとし、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号を読み出す。 After accumulation of signal charges by exposure, first, at time T1, the address signal selsel is set to high level, and a first signal at a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read out.
　次に、時刻Ｔ２にリセット信号Φｒｓｔおよび信号Φｆｂをハイレベルとし、リセットトランジスタ７６およびトランジスタ７８をオンとする。電圧Ｖｃのチャートからわかるように、ここでは、電圧供給回路１２８は、時刻Ｔ２の時点で制御線８１に第１電圧ＶAを印加している。したがって、リセットトランジスタ７６およびトランジスタ７８のオンにより、不純物領域６０ａの電位ＶFDおよび不純物領域６０ｂの電位ＶRDは、ＶAに変化する。第１電圧ＶAとして、基板コンタクトに印加されて基板電位Ｖｓｕｂを与える電圧よりも大きな電圧を適用することにより、不純物領域６０ａの電位ＶFDおよび不純物領域６０ｂの電位ＶRDが半導体基板６０の基板電位Ｖｓｕｂを下回ってしまうことを回避できる。 Next, at time T2, the reset signal rstrst and the signal fbfb are set to high level, and the reset transistor 76 and the transistor 78 are turned on. As understood from the chart of the voltage Vc, the voltage supply circuit 128 applies the first voltage V A to the control line 81 at time T2. Therefore, when the reset transistor 76 and the transistor 78 are turned on, the potential V FD of the impurity region 60 a and the potential V RD of the impurity region 60 b change to V A. By applying a voltage higher than the voltage applied to the substrate contact to apply substrate potential Vsub as first voltage V A , potential V FD of impurity region 60 a and potential V RD of impurity region 60 b are substrates of semiconductor substrate 60. It is possible to avoid falling below the potential Vsub.
　次に、時刻Ｔ３にリセットトランジスタ７６をオフとする。リセットトランジスタ７６をオフすると、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、不純物領域６０ａの電位ＶFDがＶAから低下し得る。このとき、リセットトランジスタ７６のオフに起因して不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうと、不純物領域６０ａに余計な正孔が流入してしまう。 Next, at time T3, the reset transistor 76 is turned off. When the reset transistor 76 is turned off, the electric potential V FD of the impurity region 60a may drop from V A due to the electrical coupling caused by the parasitic capacitance of the reset transistor 76. At this time, if the potential V FD of the impurity region 60a falls below the substrate potential Vsub due to the turning off of the reset transistor 76, extra holes flow into the impurity region 60a.
　しかしながら、図１７Ａに示す例では、電圧供給回路１２８が、制御線８１に印加する電圧をリセットトランジスタ７６のオフのタイミングで第１電圧ＶAから第２電圧ＶBに切り替えている。このとき、トランジスタ７８は、オン状態であり、図１７Ａに示すように、不純物領域６０ｂの電位ＶRDは、ＶBに変化する。 However, in the example shown in FIG. 17A, the voltage supply circuit 128 are switched from the first voltage V A at the timing of the off the reset transistor 76 a voltage applied to the control line 81 to a second voltage V B. At this time, the transistor 78 is turned on, as shown in FIG. 17A, the potential V RD impurity region 60b is changed to V B.
　上述したように、電界効果トランジスタは、ソース－ドレイン間に寄生容量を有し、オフとされた状態では容量として機能する。したがって、制御線８１に印加する電圧を第１電圧ＶAから第２電圧ＶBに上昇させることにより、オフ状態のリセットトランジスタ７６を介して、不純物領域６０ａの電位ＶFDを上昇させることが可能である。第１電圧ＶAおよび第２電圧ＶBの具体的な値を適切に選択することにより、リセットトランジスタ７６のオフに伴う電位ＶFDの低下分を縮小または相殺でき、結果として、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回ってしまうことを回避し得る。この例では、不純物領域６０ａの電位ＶFDが、Ｖ６ａ＞Ｖｓｕｂの関係を満たすＶ６ａに変化している。 As described above, the field effect transistor has a parasitic capacitance between the source and drain, and functions as a capacitance in the off state. Therefore, by raising the voltage applied to control line 81 from first voltage V A to second voltage V B , potential V FD of impurity region 60 a can be raised via reset transistor 76 in the off state. It is. By appropriate selection of the specific value of the first voltage V A and the second voltage V B, can be reduced or offset the decreased amount of the potential V FD accompanying off the reset transistor 76, as a result, impurity regions 60a It can be avoided that the potential V FD falls below the substrate potential Vsub. In this example, the potential V FD of the impurity region 60a is changed to V6a satisfying the relationship of V6a> Vsub.
　次に、時刻Ｔ４にトランジスタ７８をオフとする。この例では、トランジスタ７８のオフのタイミングで、制御線８１に印加する電圧を第２電圧ＶBから第１電圧ＶAに戻している。このとき、トランジスタ７８を介した電気的なカップリングにより、トランジスタ７８のオフに起因して不純物領域６０ｂの電位ＶRDが低下し得る。この例では、不純物領域６０ｂの電位ＶRDがＶBからＶ７ａに低下している。 Next, the transistor 78 is turned off at time T4. In this example, at the timing of the off-transistor 78, the voltage applied to the control line 81 from the second voltage V B to return to the first voltage V A. At this time, the electrical coupling through the transistor 78 may lower the potential V RD of the impurity region 60 b due to the turning off of the transistor 78. In this example, the potential V RD of the impurity region 60 b is lowered from V B to V 7 a.
　ただし、ここでは、トランジスタ７８のオフ直前の不純物領域６０ｂの電位ＶRDがＶBである。基板電位Ｖｓｕｂに近い第１電圧ＶAよりも高い第２電圧ＶBが印加された状態でトランジスタ７８がオフとされているので、電位ＶRDが基板電位Ｖｓｕｂを下回ってしまうことを回避し得る。図１７Ａに示すように、ここでは、Ｖ７ａ＞Ｖｓｕｂの関係が成立している。第２電圧ＶBとしては、Ｖ７ａ＞Ｖｓｕｂの関係が満たされるような電圧を用いればよい。Ｖ７ａ＞Ｖｓｕｂの関係が満たされる限りにおいてなるべく低い電圧を第２電圧ＶBとして用いると、空乏層の縮小に有利である。制御線８１に印加する電圧をトランジスタ７８のオフのタイミングで切り替えず、時刻Ｔ４以降も制御線８１に第２電圧ＶBを印加し続けてもかまわない。なお、リセットトランジスタ７６のソース－ドレイン間に寄生容量は、比較的小さく、そのため、不純物領域６０ｂの電位ＶRDがＶBからＶ７ａに低下しても不純物領域６０ａの電位ＶFDにはほとんど影響が生じない。 However, here, the potential V RD of the impurity region 60 b immediately before the transistor 78 is turned off is V B. Since the transistor 78 in a state that is higher than the first voltage V A closer to the substrate potential Vsub second voltage V B is applied is turned off, the potential V RD may avoids falls below the substrate potential Vsub . As shown in FIG. 17A, the relationship of V7a> Vsub is established here. The second voltage V B, may be used voltage as satisfied relationship V7a> Vsub. With lowest possible voltage as the second voltage V B as long as the relationship V7a> Vsub is satisfied, it is advantageous to a reduction in the depletion layer. Without switching the voltage applied to the control line 81 at the timing of the off-transistor 78, the time T4 may be also be continuously applied to the second voltage V B to the control line 81 or later. The parasitic capacitance between the source and drain of reset transistor 76 is relatively small, so that even if the potential V RD of impurity region 60 b decreases from V B to V 7 a, it has almost no effect on the potential V FD of impurity region 60 a. It does not occur.
　トランジスタ７８のオフ後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ５までの期間に、電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。第１の信号および第２の信号の差分Δが、画像信号として水平走査回路１２４に出力される。 After the transistor 78 is turned off, a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises. The difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
　図１７Ａに示す第３の例において、電圧供給回路１２８が、リセットトランジスタ７６がオンである第１の期間に不純物領域６０ｂに第１電圧ＶAを印加する点は、図１４Ａを参照して説明した例と共通である。ただし、この例では、電圧供給回路１２８は、トランジスタ７８がオンとされた期間のうち、第１の期間を除く期間に、第２電圧ＶBを不純物領域６０ｂに印加している。このような制御によっても、不純物領域６０ｂの電位ＶRDが基板電位Ｖｓｕｂを下回ってしまうことを回避し得る。また、オフ状態のリセットトランジスタ７６を介した電気的なカップリングによる、不純物領域６０ａの電位ＶFDの変動に起因した暗電流の発生を抑制することが可能である。 In the third example shown in FIG. 17A, the point that the voltage supply circuit 128 applies the first voltage V A to the impurity region 60b during the first period in which the reset transistor 76 is on is described with reference to FIG. 14A. Common to the example. However, in this example, the voltage supply circuit 128, among the period in which the transistor 78 is turned on, a period excluding the first period, and a second voltage V B is applied to the impurity regions 60b. Such control can also prevent the potential V RD of the impurity region 60 b from falling below the substrate potential Vsub. Further, it is possible to suppress the generation of dark current due to the fluctuation of the potential V FD of the impurity region 60 a due to the electrical coupling through the reset transistor 76 in the off state.
　なお、図１６に例示する回路構成に、図１４Ａを参照して説明した例と同様の制御を適用することも可能である。再び図１４Ａを参照する。図１４Ａに示す例では、時刻Ｔ４においてトランジスタ７８がオフとされる。この点は、ここで説明した第３の例と共通である。トランジスタ７８がオフとされると、上述したように、トランジスタ７８を介した電気的なカップリングによって不純物領域６０ｂの電位ＶRDが低下し得る。ただし、図１４Ａに示すように、制御線８１に印加する電圧をトランジスタ７８のオフのタイミングで第２電圧ＶBに切り替えることにより、トランジスタ７８を介した電気的なカップリングに起因する電位の低下分を低減可能である。これは、時刻Ｔ４以降、トランジスタ７８はオフ状態であり、ソース－ドレイン間が非導通状態となるものの、ソース－ドレイン間に寄生容量を有するので、トランジスタ７８が容量として機能するからである。すなわち、トランジスタ７８の寄生容量による電気的なカップリングを利用して、不純物領域６０ｂの電位ＶRDを制御し得る。トランジスタ７８を介した電位ＶRDの制御により、トランジスタ７８のオフに伴って電位ＶRDが基板電位Ｖｓｕｂを下回ってしまうことを回避して、不純物領域６０ｂへの余計な正孔の流入を防止し得る。 In addition, it is also possible to apply control similar to the example described with reference to FIG. 14A to the circuit configuration illustrated in FIG. Refer again to FIG. 14A. In the example shown in FIG. 14A, the transistor 78 is turned off at time T4. This point is common to the third example described here. When the transistor 78 is turned off, the electrical coupling via the transistor 78 may lower the potential V RD of the impurity region 60b, as described above. However, as shown in FIG. 14A, by switching the voltage applied to the control line 81 to a second voltage V B at the timing of the off-transistor 78, a decrease in potential due to the electrical coupling through the transistor 78 It is possible to reduce the minutes. This is because the transistor 78 is off after time T4 and the source-drain is non-conductive, but since the parasitic capacitance is provided between the source and drain, the transistor 78 functions as a capacitance. That is, the electrical coupling due to the parasitic capacitance of the transistor 78 can be used to control the potential V RD of the impurity region 60 b. By controlling the potential V.sub.RD via the transistor 78, the potential V.sub.RD is prevented from falling below the substrate potential V.sub.sub with the turning off of the transistor 78, thereby preventing extra holes from flowing into the impurity region 60b. obtain.
　このように、オフ後のトランジスタ７８は、図１２に示す容量素子Ｃ２と同様の機能を発揮し得る。ただし、ソース－ドレイン間の寄生容量の容量値は一般に比較的小さい。そのため、図１２に例示する回路構成のように、より大きな容量値を有する容量素子Ｃ２を介して電圧供給回路１２８をノードＲＤに接続した方が、第１電圧ＶAおよび第２電圧ＶBとしてより小さな電圧差の電圧を適用しながらも、不純物領域６０ｂの電位ＶRDをより大きく変動させ得る。換言すれば、図１６に示す回路構成よりも、図１２に示す回路構成の方が、トランジスタ７８のオフに伴う電位ＶRDの低下をより効果的に低減できるので、より基板電位Ｖｓｕｂに近い電圧を第１電圧ＶAとして用いることが可能になる。 Thus, the transistor 78 after being turned off can exhibit the same function as the capacitive element C2 shown in FIG. However, the capacitance value of the source-drain parasitic capacitance is generally relatively small. Therefore, as the circuit configuration illustrated in FIG. 12, a voltage supply circuit 128 through the capacitor C2 having a greater capacitance who connected to the node RD is, as the first voltage V A and the second voltage V B The potential V RD of the impurity region 60b can be changed more largely while applying a smaller voltage difference voltage. In other words, the circuit configuration shown in FIG. 12 can more effectively reduce the drop in potential V RD accompanying turning off of the transistor 78 than the circuit configuration shown in FIG. it is possible to use as the first voltage V a.
　図１７Ｂは、画素１０Ｂｒのリセットトランジスタ７６、トランジスタ７８、信号検出トランジスタ７２およびアドレストランジスタ７４にｐ型のトランジスタを適用し、信号電荷として電子を用いたときの例示的な動作を示す。以下に説明するように、図１７Ｂに示す動作例において、制御線８１に印加する電圧を第１電圧ＶAおよび第２電圧ＶBの間で切り替えるタイミングは、図１７Ａを参照して説明した動作例と共通である。ただし、ここでは、第２電圧ＶBとして、第１電圧ＶAよりも低い電圧を用いる。 FIG. 17B illustrates an exemplary operation when a p-type transistor is applied to the reset transistor 76, the transistor 78, the signal detection transistor 72, and the address transistor 74 of the pixel 10Br, and electrons are used as signal charges. As described below, in the operation example shown in FIG. 17B, the timing of switching the voltage applied to the control line 81 between the first voltage V A and the second voltage V B has been described with reference to FIG. 17A operation Common to the example. However, here, as the second voltage V B, using a voltage lower than the first voltage V A.
　図１７Ｂに示す例では、露光による信号電荷の蓄積後、まず、時刻Ｔ１においてアドレストランジスタ７４をオンとし、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号を読み出す。次に、時刻Ｔ２にリセット信号Φｒｓｔおよび信号Φｆｂをローレベルとし、リセットトランジスタ７６およびトランジスタ７８をオンとする。ここでは、電圧供給回路１２８は、時刻Ｔ２の時点で制御線８１に第１電圧ＶAを印加しているので、不純物領域６０ａの電位ＶFDおよび不純物領域６０ｂの電位ＶRDは、ＶAに変化する。第１電圧ＶAとしては、電位ＶFDおよび電位ＶRDが基板電位Ｖｓｕｂを上回ってしまわないように、基板電位Ｖｓｕｂを与える電圧よりも低い電圧を用いる。 In the example shown in FIG. 17B, after accumulating signal charges by exposure, first, at time T1, the address transistor 74 is turned on, and a first signal of a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read. Next, at time T2, the reset signal rstrst and the signal fbfb are set to low level, and the reset transistor 76 and the transistor 78 are turned on. Here, voltage supply circuit 128 applies first voltage V A to control line 81 at time T 2, so potential V FD of impurity region 60 a and potential V RD of impurity region 60 b are set to V A. Change. The first voltage V A, the potential V FD and the potential V RD is so as not to exceed the substrate potential Vsub, using a voltage lower than the voltage giving the substrate potential Vsub.
　次に、時刻Ｔ３にリセットトランジスタ７６をオフとする。リセットトランジスタ７６をオフすると、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、不純物領域６０ａの電位ＶFDがＶAから上昇し得る。このとき、図１７Ｂに示すように、制御線８１に印加する電圧をリセットトランジスタ７６のオフのタイミングで第１電圧ＶAから第１電圧ＶAよりも低い第２電圧ＶBに切り替えることにより、不純物領域６０ｂの電位ＶRDがＶBに変化する。また、制御線８１に印加する電圧を第１電圧ＶAから第２電圧ＶBに切り替えることにより、オフ状態のリセットトランジスタ７６を介して、不純物領域６０ａの電位ＶFDを低下させることができる。これにより、リセットトランジスタ７６のオフに伴って不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを上回ってしまうことを回避し得る。この例では、不純物領域６０ａの電位ＶFDが、Ｖ６ｂ＜Ｖｓｕｂの関係を満たすＶ６ｂに変化している。 Next, at time T3, the reset transistor 76 is turned off. When the reset transistor 76 is turned off, the electrical coupling caused by the parasitic capacitance of the reset transistor 76 may cause the potential V FD of the impurity region 60 a to rise from V A. At this time, as shown in FIG. 17B, by switching from the first voltage V A and the voltage applied to the control line 81 at the timing of the off reset transistor 76 is lower than the first voltage V A second voltage V B, Potential V RD of impurity region 60 b changes to V B. Further, by switching the voltage applied to the control line 81 from the first voltage V A to the second voltage V B , the potential V FD of the impurity region 60 a can be reduced via the reset transistor 76 in the off state. This can prevent the potential V FD of the impurity region 60a from exceeding the substrate potential Vsub with the turning off of the reset transistor 76. In this example, the potential V FD of the impurity region 60a is changed to V6b which satisfies the relationship V6b <Vsub.
　次に、時刻Ｔ４にトランジスタ７８をオフとするとともに、トランジスタ７８のオフのタイミングで、制御線８１に印加する電圧を第２電圧ＶBから第１電圧ＶAに戻す。このとき、トランジスタ７８を介した電気的なカップリングにより、不純物領域６０ｂの電位ＶRDが上昇し得る。ただし、ここでは、基板電位Ｖｓｕｂに近い第１電圧ＶAよりも低い第２電圧ＶBが制御線８１に印加された状態でトランジスタ７８がオフとされており、トランジスタ７８のオフ直後の不純物領域６０ｂの電位ＶRDをＶ７ｂとすれば、Ｖ７ｂ＜Ｖｓｕｂの関係が成立している。すなわち、電位ＶRDが基板電位Ｖｓｕｂを上回ってしまうことが回避されている。 Then, the transistor 78 as well as off the time T4, at the timing of the off-transistor 78, and returns the voltage applied to the control line 81 from the second voltage V B to the first voltage V A. At this time, electrical coupling via the transistor 78 can increase the potential V RD of the impurity region 60 b. However, in this case, the transistor 78 in a state that is lower than the first voltage V A closer to the substrate potential Vsub second voltage V B is applied to the control line 81 are turned off, the impurity regions immediately off of the transistor 78 Assuming that the potential V RD of 60b is V7b, the relationship of V7b <Vsub is established. That is avoided potential V RD will exceed the substrate potential Vsub.
　トランジスタ７８のオフ後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ５までの期間に、電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。第１の信号および第２の信号の差分Δが、画像信号として水平走査回路１２４に出力される。 After the transistor 78 is turned off, a second signal corresponding to the voltage level of the charge storage node is read out in a period until time T5 when the next pulse of the horizontal synchronization signal HD rises. The difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.
　このような制御によれば、不純物領域６０ｂの電位ＶRDが基板電位Ｖｓｕｂを上回ってしまうことを回避し得る。また、オフ状態のリセットトランジスタ７６を介した電気的なカップリングによる、不純物領域６０ａの電位ＶFDの変動に起因した暗電流の発生を抑制することが可能である。なお、図１６に示す画素１０Ｂｒのリセットトランジスタ７６、トランジスタ７８、信号検出トランジスタ７２およびアドレストランジスタ７４にｐ型のトランジスタを適用し、信号電荷として電子を用いる場合には、図１４Ｂを参照して説明した例と同様の制御も適用し得る。 According to such control, the potential V RD of the impurity region 60 b can be avoided from exceeding the substrate potential Vsub. Further, it is possible to suppress the generation of dark current due to the fluctuation of the potential V FD of the impurity region 60 a due to the electrical coupling through the reset transistor 76 in the off state. When p-type transistors are applied to the reset transistor 76, the transistor 78, the signal detection transistor 72, and the address transistor 74 of the pixel 10Br shown in FIG. 16 and electrons are used as the signal charge, the description will be given with reference to FIG. The same control as in the example given can also be applied.
　図１８は、本開示の第２の実施形態による撮像装置のさらに他の変形例を示す。図１８に示す画素１０Ｂｑは、図１６に示す画素１０Ｂｒの光電変換部５０Ａを光電変換部５０Ｂに置き換えた回路構成を有する。画素１０Ｂｑを有する撮像装置１００の動作は、図１７Ａまたは図１７Ｂを参照して説明した動作と同様であり得る。すなわち、トランジスタ７８がオンとされた期間のうち、リセットトランジスタ７６がオンである第１の期間を除く期間に、第２電圧ＶBを不純物領域６０ｂに印加するような動作を適用し得る。このような制御によれば、例えば、不純物領域６０ｂの電位ＶRDが基板電位Ｖｓｕｂを下回ってしまうことを回避し得る。 FIG. 18 shows still another modified example of the imaging device according to the second embodiment of the present disclosure. The pixel 10Bq illustrated in FIG. 18 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10Br illustrated in FIG. 16 is replaced with a photoelectric conversion unit 50B. The operation of the imaging device 100 having the pixel 10Bq may be similar to the operation described with reference to FIG. 17A or 17B. That is, of the period during which the transistor 78 is turned on, a period excluding the first period the reset transistor 76 is on, may the second voltage V B is applied to operation as applied to the impurity regions 60b. According to such control, for example, the potential V RD of the impurity region 60 b can be avoided from falling below the substrate potential Vsub.
　なお、図１８に例示する回路構成に、図１４Ａおよび図１４Ｂを参照して説明した動作と同様の動作が適用されてもよい。図６に示す画素１０Ａｑと同様に、信号検出トランジスタ７２のゲートと光電変換部５０Ｂとの間に転送トランジスタ７９がさらに接続されてもよい。 An operation similar to the operation described with reference to FIGS. 14A and 14B may be applied to the circuit configuration illustrated in FIG. 18. Similarly to the pixel 10Aq illustrated in FIG. 6, a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
　（第３の実施形態）
　図１９Ａおよび図１９Ｂは、本開示の第３の実施形態による撮像装置が有する画素の回路構成の一例を模式的に示す。図１９Ａに示す撮像装置１４０は、画素１０Ｄを有する。図３を参照して説明した回路構成と同様に、画素１０Ｄは、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６の３つのトランジスタを画素１０Ｄ内に有する。図１９Ｂに示す画素１０Ｄｐは、図１９Ａに示す画素１０Ｄの光電変換部５０Ａを光電変換部５０Ｂに置き換えた回路構成を有する。 Third Embodiment
19A and 19B schematically illustrate an example of a circuit configuration of a pixel included in an imaging device according to a third embodiment of the present disclosure. The imaging device 140 shown in FIG. 19A has a pixel 10D. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10D has three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the pixel 10D. The pixel 10Dp illustrated in FIG. 19B has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10D illustrated in FIG. 19A is replaced with a photoelectric conversion unit 50B.
　図１９Ａに示す画素１０Ｄと、図３を参照して説明した画素１０Ａとの間の主な相違点は、画素１０Ｄでは、ノードＦＤａに電圧供給回路１２８は接続されておらず、ノードＦＤａとアドレス信号線８４とが容量素子Ｃ１を介して電気的に結合されている点である。画素１０Ｄは、層間絶縁層４０内に制御線８１が配置されないこと以外は、図２を参照して説明したデバイス構造と同様のデバイス構造を有し得る。図１９Ｂに示す画素１０Ｄｐにおいても図１９Ａに示す画素１０Ｄと同様に、容量素子Ｃ１の端子のうち、ノードＦＤｂに接続されていない側の端子は、アドレス信号線８４に接続されている。 The main difference between the pixel 10D shown in FIG. 19A and the pixel 10A described with reference to FIG. 3 is that in the pixel 10D, the voltage supply circuit 128 is not connected to the node FDa, and the node FDa and the address The point is that the signal line 84 is electrically coupled via the capacitive element C1. The pixel 10D may have the same device structure as the device structure described with reference to FIG. 2 except that the control line 81 is not disposed in the interlayer insulating layer 40. Also in the pixel 10Dp shown in FIG. 19B, the terminal of the capacitive element C1 not connected to the node FDb is connected to the address signal line 84 as in the pixel 10D shown in FIG. 19A.
　容量素子Ｃ１の端子のうち、アドレス信号線８４に接続された端子には、アドレス信号Φｓｅｌが入力される。したがって、これらの例示的な回路は、アドレス信号Φｓｅｌの制御により、ノードＦＤａまたはノードＦＤｂの電位を制御することが可能な構成を有する。ただし、容量素子Ｃ１の端子の一方にアドレス信号線８４が接続されることは必須ではない。例えば信号電荷として正孔を利用する場合であれば、容量素子Ｃ１のうち、ノードＦＤａまたはノードＦＤｂに接続された側とは反対側の端子には、リセット期間にハイレベルであり、行選択時でない期間にローレベルであるような制御信号が入力されていればよい。例えば、容量素子Ｃ１のうち、ノードＦＤａまたはノードＦＤｂに接続された側とは反対側の端子に、リセット信号Φｒｓｔまたは他の制御信号が入力されるような構成もあり得る。 An address signal selsel is input to a terminal connected to the address signal line 84 among the terminals of the capacitive element C1. Therefore, these exemplary circuits have a configuration capable of controlling the potential of node FDa or node FDb by control of address signal selsel. However, it is not essential that the address signal line 84 is connected to one of the terminals of the capacitive element C1. For example, in the case of using holes as signal charges, the terminal on the side opposite to the side connected to the node FDa or the node FDb in the capacitive element C1 has a high level during the reset period, and the row is selected It is only necessary to input a control signal which is low level in a period other than the above. For example, there may be a configuration in which the reset signal rstrst or another control signal is input to a terminal of the capacitive element C1 opposite to the side connected to the node FDa or the node FDb.
　図２０は、図１９Ａに示す回路構成を有する画素１０Ｄの例示的な動作を説明するためのタイミングチャートである。図４Ｃを参照して説明した動作シーケンスと比較して、図２０に例示する動作シーケンスでは、アドレス信号Φｓｅｌが、図４Ｃに示す電圧Ｖｃの役割も果たす図２０中、ΦHは、ハイレベルの信号ΦHを表し、ΦLは、ローレベルの信号ΦLを表す。ここでは、ローレベルの信号ΦLが第１電圧ＶAに対応し、ハイレベルの信号ΦHが第２電圧ＶBに対応する。 FIG. 20 is a timing chart for illustrating an exemplary operation of the pixel 10D having the circuit configuration shown in FIG. 19A. Reference compared with the operation sequence described with FIG. 4C, in the operation sequence illustrated in FIG. 20, the address signal Φsel is, in FIG. 20 also serve voltage Vc shown in FIG. 4C, [Phi H is the high level It represents the signal 信号H and Φ L represents the low level signal Φ L. Here, the low level signal Φ L corresponds to the first voltage V A , and the high level signal Φ H corresponds to the second voltage V B.
　画素１０Ｄにおいて、ノードＦＤａは、容量素子Ｃ１を介してアドレス信号線８４と容量結合している。そのため、時刻Ｔ１においてアドレス信号Φｓｅｌをハイレベルにすることにより、ノードＦＤａの電位を上昇させることができる。このときの電位の変動量ΔＶＦＤは、下記の式（２）で表される。 In the pixel 10D, the node FDa is capacitively coupled to the address signal line 84 via the capacitive element C1. Therefore, the potential of the node FDa can be raised by setting the address signal selsel to high level at time T1. The variation amount ΔV FD of the potential at this time is expressed by the following equation (2).
　　ΔＶＦＤ＝（ΦH－ΦL）（Ｃ１／（Ｃ１＋ＣＦＤ））　　　（２）
　時刻Ｔ４においてアドレス信号ΦｓｅｌをローレベルのΦLにすることにより、ノードＦＤａの電位は、上記の式（２）で表されるΔＶＦＤだけ低下する。このように、アドレス信号Φｓｅｌを用いて電荷蓄積ノードの電位を制御することも可能であり、図２０に示すように、例えば、アドレス信号ΦｓｅｌをローレベルのΦLに戻したときのノードＦＤａの電位をリセット電圧Ｖｒよりも低い電位Ｖ１ｆに設定することができる。なお、行選択時かつリセット実行後の不純物領域６０ａの電位ＶFDは、リセット電圧Ｖｒに持ち上げられた状態であるので、信号検出トランジスタ７２の後段回路において動作可能な電圧範囲で正常に第２の信号の読み出しを実行することが可能である。 ΔV FD = (Φ H −Φ L ) (C 1 / (C 1 + C FD )) (2)
By setting the address signal Φsel to a low level L L at time T4, the potential of the node FDa is lowered by ΔV FD represented by the above equation (2). Thus, it is also possible to control the potential of the charge storage node using the address signal .phi.SEL, as shown in FIG. 20, for example, node FDa when returning the address signal .phi.SEL to the low level [Phi L The potential can be set to a potential V1f lower than the reset voltage Vr. Since the potential V FD of the impurity region 60a at the row selection and after the reset is performed is raised to the reset voltage Vr, the second normal operation is normally performed within the voltage range operable in the circuit following the signal detection transistor 72. It is possible to carry out a readout of the signal.
　第３の実施形態によれば、例えばアドレス信号Φｓｅｌを用いて容量結合を通して電荷蓄積ノードの電位が制御されるので、信号線の数を減らすことができる。これにより画素の小型化を図ることができる。なお、容量素子Ｃ１としては、上述のＭＩＳ構造、ＭＩＭ構造などを有する素子に限定されない。例えば配線間の寄生容量などによって容量素子Ｃ１が実現されてもよい。例えば、信号検出トランジスタ７２のゲートと信号線などの配線との間の寄生容量によって容量素子Ｃ１を実現してもよい。 According to the third embodiment, since the potential of the charge storage node is controlled through capacitive coupling using, for example, the address signal selsel, the number of signal lines can be reduced. Thus, the pixel can be miniaturized. The capacitive element C1 is not limited to the element having the above-described MIS structure, MIM structure, or the like. For example, the capacitive element C1 may be realized by a parasitic capacitance between wires. For example, the capacitive element C1 may be realized by a parasitic capacitance between the gate of the signal detection transistor 72 and a wiring such as a signal line.
　（第４の実施形態）
　図２１は、本開示の第４の実施形態による撮像装置が有する画素の回路構成の一例を模式的に示す。図２１に示す撮像装置１５０は、画素１０Ｃを有する。図３を参照して説明した回路構成と同様に、画素１０Ｃは、信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６の３つのトランジスタを画素１０Ｃ内に有する。これら信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６の３つのトランジスタは、光電変換部５０Ａに電気的に接続されたノードＦＤａに蓄積される信号電荷を検出する検出回路９５を構成する。ただし、図３に示す画素１０Ａと比較して、図２１に示す画素１０ＣのノードＦＤａには、電圧供給回路１２８は接続されていない。画素１０Ｃは、層間絶縁層４０内に制御線８１が配置されないこと以外は、図２を参照して説明したデバイス構造と同様のデバイス構造を有し得る。 Fourth Embodiment
FIG. 21 schematically illustrates an example of a circuit configuration of a pixel included in an imaging device according to a fourth embodiment of the present disclosure. The imaging device 150 shown in FIG. 21 has a pixel 10C. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10C has three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the pixel 10C. The three transistors of the signal detection transistor 72, the address transistor 74, and the reset transistor 76 constitute a detection circuit 95 that detects the signal charge stored in the node FDa electrically connected to the photoelectric conversion unit 50A. However, in comparison with the pixel 10A shown in FIG. 3, the voltage supply circuit 128 is not connected to the node FDa of the pixel 10C shown in FIG. The pixel 10C may have the same device structure as the device structure described with reference to FIG. 2 except that the control line 81 is not disposed in the interlayer insulating layer 40.
　（撮像装置１５０の動作の例）
　図２２Ａは、図２１に示す回路構成を有する画素１０Ｃの例示的な動作を説明するためのタイミングチャートである。 (Example of Operation of Imaging Device 150)
FIG. 22A is a timing chart for describing an exemplary operation of the pixel 10C having the circuit configuration shown in FIG.
　露光による信号電荷の蓄積後、時刻Ｔ１にアドレストランジスタ７４をオンとし、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号を読み出す点は、上述の典型例と同様である。その後、第１の例と同様に、時刻Ｔ２にリセット信号Φｒｓｔをハイレベルとし、リセットトランジスタ７６をオンとして電荷蓄積ノードからリセットトランジスタ７６を介して信号電荷を排出する。このとき、不純物領域６０ａの電位ＶFDは、Ｖｒに変化する。なお、ここでは、Ｖｒ＞Ｖｓｕｂである。 Similar to the above-described typical example, the address transistor 74 is turned on at time T1 after signal charge storage by exposure, and the first signal at the voltage level corresponding to the signal charge stored in the charge storage node is read out. . Thereafter, similarly to the first example, at time T2, the reset signal ハ イ rst is set to the high level, the reset transistor 76 is turned on, and the signal charge is discharged from the charge storage node through the reset transistor 76. At this time, the potential V FD of the impurity region 60a changes to Vr. Here, Vr> Vsub.
　次に、時刻Ｔ３にリセット信号Φｒｓｔをローレベルとし、リセットトランジスタ７６をオフとする。リセットトランジスタ７６をオフすると、リセットトランジスタ７６が有する寄生容量に起因した電気的なカップリングにより、不純物領域６０ａの電位ＶFDがＶｒから低下する。ここで、例えばＶｒが基板電位Ｖｓｕｂに近い電圧であると、リセットトランジスタ７６のオフ後の電位ＶFDが基板電位Ｖｓｕｂを下回ることがある。この例では、リセットトランジスタ７６のオフによって、不純物領域６０ａの電位ＶFDが、Ｖｒから、Ｖ８ａ＜ＶｓｕｂとなるＶ８ａに低下している。 Next, at time T3, the reset signal rstrst is set to low level, and the reset transistor 76 is turned off. When the reset transistor 76 is turned off, the electrical coupling caused by the parasitic capacitance of the reset transistor 76 causes the potential V FD of the impurity region 60a to drop from Vr. Here, if Vr is a voltage close to the substrate potential Vsub, for example, the potential V FD after the reset transistor 76 is turned off may fall below the substrate potential Vsub. In this example, as the reset transistor 76 is turned off, the potential V FD of the impurity region 60a is lowered from Vr to V8a where V8a <Vsub.
　しかしながら、図２２Ａに示す例では、時刻Ｔ４に、リセットトランジスタ７６のゲートに印加されるリセット信号Φｒｓｔを、ハイレベルの信号ΦHよりも低くかつローレベルの信号ΦLよりも高い、中間的な電圧レベルの信号ΦMに切り替えている。ただし、中間的な電圧レベルとしては、リセットトランジスタ７６がオフ状態を維持するような電圧レベルを用いる。 However, in the example shown in FIG. 22A, at time T4, the reset signal rstrst applied to the gate of the reset transistor 76 is lower than the high level signal H H and higher than the low level signal L L. The voltage level signal M M is switched. However, as an intermediate voltage level, a voltage level that maintains the reset transistor 76 in the off state is used.
　リセットトランジスタ７６のオフ状態を維持させたまま、リセット信号Φｒｓｔをローレベルから中間的な電圧レベルの信号ΦMに上昇させることにより、リセットトランジスタ７６のゲート－ドレイン間の寄生容量による電気的なカップリングを利用して、不純物領域６０ａの電位ＶFDを基板電位Ｖｓｕｂよりも高い電位に引き上げることができる。この例では、リセット信号Φｒｓｔをローレベルの信号ΦLから中間的な電圧レベルの信号ΦMに上昇させることにより、不純物領域６０ａの電位ＶFDが、Ｖ９ａ＞Ｖｓｕｂを満たすＶ９ａに上昇している。 By raising the reset signal rstrst from the low level to the signal M M at an intermediate voltage level while maintaining the off state of the reset transistor 76, an electrical cup due to the parasitic capacitance between the gate and the drain of the reset transistor 76 utilizing a ring, it is possible to raise the potential V FD of the impurity regions 60a to a potential higher than the substrate potential Vsub. In this example, the potential V FD of the impurity region 60a is raised to V9a satisfying V9a> Vsub by raising the reset signal rstrst from the low level signal LL to an intermediate voltage level signal> M. .
　リセット信号Φｒｓｔをローレベルの信号ΦLから中間的な電圧レベルの信号ΦMに上昇させた後、水平同期信号ＨＤの次のパルスが立ち上がる時刻Ｔ５までの期間に、信号電荷の排出後、すなわち、リセット後の電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。すなわち、この例では、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂよりも高くされた状態で第２の信号の読み出しが実行されている。 After the reset signal rstrst is raised from the low level signal L L to an intermediate voltage level signal M M , after discharge of the signal charge, ie, until time T5 when the next pulse of the horizontal synchronization signal HD rises, ie, , And reads the second signal corresponding to the voltage level of the charge storage node after reset. That is, in this example, the reading of the second signal is performed in a state where the potential V FD of the impurity region 60a is higher than the substrate potential Vsub.
　このように、第１の信号の読み出しから第２の信号の読み出しまでの間において、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを一時的に下回ってもかまわない。ただし、リセット信号Φｒｓｔをローレベルの信号ΦLから中間的な電圧レベルの信号ΦMに上昇させたときに電位ＶFDが基板電位Ｖｓｕｂを上回るように、リセット信号線８６に印加する中間的な電圧レベルを決定する。不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを下回る期間がごく短時間であり、リセット後の不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂよりも高ければ、リセット後の電荷蓄積ノードの電圧レベルに対応する第２の信号への暗電流の影響を抑制し得る。 As described above, the potential V FD of the impurity region 60 a may be temporarily lower than the substrate potential Vsub between the reading of the first signal and the reading of the second signal. However, when the reset signal rstrst is raised from the low level signal L L to an intermediate voltage level signal 中間M , an intermediate voltage applied to the reset signal line 86 so that the potential V FD exceeds the substrate potential Vsub. Determine the voltage level. The potential V FD of the impurity regions 60a is a short time only a period below the substrate potential Vsub, is higher than the potential V FD is the substrate potential Vsub of the impurity regions 60a after reset, the voltage level of the charge storage node after the reset The influence of dark current on the corresponding second signal can be suppressed.
　図２２Ｂは、図２１に示す画素１０Ｃのリセットトランジスタ７６にｐ型のトランジスタを適用し、信号電荷として電子を用いたときの例示的な動作を説明するためのタイミングチャートである。ｎ型トランジスタに代えて信号検出トランジスタ７２、アドレストランジスタ７４およびリセットトランジスタ７６にｐ型のトランジスタを適用し、信号電荷として電子を用いる場合には、例えば以下の動作を適用し得る。 FIG. 22B is a timing chart for illustrating an exemplary operation when a p-type transistor is applied to the reset transistor 76 of the pixel 10C shown in FIG. 21 and electrons are used as signal charges. When a p-type transistor is applied to the signal detection transistor 72, the address transistor 74, and the reset transistor 76 instead of the n-type transistor and electrons are used as signal charges, for example, the following operation can be applied.
　露光による信号電荷の蓄積後、まず、時刻Ｔ１にアドレストランジスタ７４をオンとし、電荷蓄積ノードに蓄積された信号電荷に応じた電圧レベルの第１の信号を読み出す。次に、時刻Ｔ２にリセット信号Φｒｓｔをローレベルとしてリセットトランジスタ７６をオンとし、電荷蓄積ノードから信号電荷を排出する。このとき、不純物領域６０ａの電位ＶFDは、Ｖｒであり、この例では、Ｖｒ＜Ｖｓｕｂである。 After accumulation of signal charges by exposure, first, the address transistor 74 is turned on at time T1, and a first signal of a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read out. Next, at time T2, the reset signal rstrst is set to low level to turn on the reset transistor 76, and the signal charge is discharged from the charge storage node. At this time, the potential V FD of the impurity region 60 a is Vr, and in this example, Vr <Vsub.
　次に、時刻Ｔ３にリセット信号Φｒｓｔをハイレベルの信号ΦHとし、リセットトランジスタ７６をオフとする。この例では、リセットトランジスタ７６のオフによって、不純物領域６０ａの電位ＶFDが、Ｖｒから、Ｖ８ｂ＞ＶｓｕｂとなるＶ８ｂに上昇している。その後、時刻Ｔ４に、リセットトランジスタ７６のゲートに印加されるリセット信号Φｒｓｔを、ローレベルの信号ΦLとハイレベルの信号ΦHとの間の中間的な電圧レベルの信号ΦMに切り替える。この例では、中間的な電圧レベルの信号ΦMは、ローレベルの信号ΦLよりも高く、ハイレベルの信号ΦHよりも低い。ここでも、中間的な電圧レベルとしては、リセットトランジスタ７６がオフ状態を維持するような電圧レベルを用いる。 Next, at time T3, the reset signal rstrst is set to a high level signal Φ H , and the reset transistor 76 is turned off. In this example, as the reset transistor 76 is turned off, the potential V FD of the impurity region 60a is raised from Vr to V8b where V8b> Vsub. Thereafter, the time T4, the reset signal Φrst applied to the gate of the reset transistor 76 is switched to the signal [Phi M of intermediate voltage level between the signal of a low level [Phi L and a high-level signal [Phi H. In this example, the intermediate voltage level signal M M is higher than the low level signal L L and lower than the high level signal Φ H. Also here, as an intermediate voltage level, a voltage level which keeps the reset transistor 76 in the off state is used.
　リセットトランジスタ７６のオフ状態を維持させたまま、リセット信号Φｒｓｔをハイレベルから中間的な電圧レベルの信号ΦMに低下させることにより、リセットトランジスタ７６を介した電気的なカップリングを利用して、不純物領域６０ａの電位ＶFDを基板電位Ｖｓｕｂよりも低い電位に引き下げることができる。この例では、リセット信号Φｒｓｔをハイレベルの信号ΦHから中間的な電圧レベルの信号ΦMに低下させることにより、不純物領域６０ａの電位ＶFDが、Ｖ９ｂ＜Ｖｓｕｂを満たすＶ９ｂに低下している。その後、時刻Ｔ５までの期間に、信号電荷の排出後の電荷蓄積ノードの電圧レベルに対応する第２の信号を読み出す。 By lowering the reset signal rstrst from the high level to the signal M M at an intermediate voltage level while maintaining the off state of the reset transistor 76, electrical coupling via the reset transistor 76 is utilized, Potential V FD of impurity region 60 a can be lowered to a potential lower than substrate potential Vsub. In this example, by decreasing the reset signal Φrst from the high level of the signal [Phi H to signal [Phi M of intermediate voltage level, the potential V FD of the impurity regions 60a has decreased to V9b satisfying V9b <Vsub . Thereafter, in the period until time T5, the second signal corresponding to the voltage level of the charge storage node after the discharge of the signal charge is read out.
　この例では、第２の信号の読み出しの時点で、不純物領域６０ａの電位ＶFDは、基板電位Ｖｓｕｂよりも低くされている。第２の信号の読み出しの時点で、不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂよりも低ければ、第１の信号の読み出しから第２の信号の読み出しまでの間において不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを一時的に上回ってもかまわない。不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂを上回る期間がごく短時間であり、リセット後の不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂよりも低ければ、リセット後の電荷蓄積ノードの電圧レベルに対応する第２の信号への暗電流の影響を抑制し得る。 In this example, the potential V FD of the impurity region 60 a is lower than the substrate potential Vsub at the time of reading of the second signal. At the time of reading of the second signal, if the potential V FD of the impurity regions 60a is lower than the substrate potential Vsub, the potential V FD of the impurity regions 60a during the period from the reading of the first signal to the read of the second signal May temporarily exceed the substrate potential Vsub. The potential V FD of the impurity regions 60a is a short time only a period in excess of the substrate potential Vsub, is lower than the potential V FD is the substrate potential Vsub of the impurity regions 60a after reset, the voltage level of the charge storage node after the reset The influence of dark current on the corresponding second signal can be suppressed.
　第４の実施形態では、垂直走査回路１２２が、リセットトランジスタ７６がオンとなる第１レベルの信号、リセットトランジスタ７６がオフとなる第２レベルの信号、および、中間レベルの信号をリセットトランジスタ７６のゲートに順次に印加することにより、不純物領域６０ａの電位のリセットを実行している。ここで、中間レベルの信号ΦMに対応する電圧は、第１レベルの信号に対応する電圧および第２レベルの信号に対応する電圧の間であってリセットトランジスタ７６がオフ状態を維持できるような電圧である。図２１に例示する回路構成において、リセットトランジスタ７６のゲートへの中間レベルの信号ΦMの印加時に不純物領域６０ａの電位ＶFDが基板電位Ｖｓｕｂよりも高ければ、図２２Ａを参照して説明したように、リセット後の電荷蓄積ノードの電圧レベルに対応する第２の信号への暗電流の影響を抑制して、画質の劣化を回避し得る。このとき、リセットトランジスタ７６のゲートへの第２レベルの信号の印加時に不純物領域６０ａの電位ＶFDが一時的に基板電位Ｖｓｕｂを下回ってもよい。 In the fourth embodiment, the vertical scanning circuit 122 includes a first level signal for turning on the reset transistor 76, a second level signal for turning off the reset transistor 76, and an intermediate level signal for the reset transistor 76. The potential of the impurity region 60a is reset by sequentially applying to the gate. Here, the voltage corresponding to the intermediate level signal M M is between the voltage corresponding to the first level signal and the voltage corresponding to the second level signal so that the reset transistor 76 can maintain the off state. It is a voltage. In the circuit configuration illustrated in FIG. 21, if potential V FD of impurity region 60a is higher than substrate potential Vsub when intermediate level signal M M is applied to the gate of reset transistor 76, as described with reference to FIG. 22A. In addition, the influence of the dark current on the second signal corresponding to the voltage level of the charge storage node after reset can be suppressed to avoid the deterioration of the image quality. At this time, the potential V FD of the impurity region 60 a may be temporarily lower than the substrate potential Vsub when the signal of the second level is applied to the gate of the reset transistor 76.
　第４の実施形態によれば、回路が過度に複雑となることを避けながら、暗電流による画質の劣化を防止し得る。また、リセット後の電荷蓄積ノードの電圧レベルに対応する第２の信号の読み出し時の不純物領域６０ａの電位ＶFDを、例えば、基板電位Ｖｓｕｂに近い、なるべく低い電位とできるので、暗電流の発生を効果的に抑制することが可能である。 According to the fourth embodiment, it is possible to prevent the deterioration of the image quality due to the dark current while avoiding the circuit becoming excessively complicated. In addition, since the potential V FD of the impurity region 60a at the time of reading of the second signal corresponding to the voltage level of the charge storage node after reset can be set as low as possible, for example, close to the substrate potential Vsub, generation of dark current Can be effectively suppressed.
　（第４の実施形態の変形例）
　図２３は、本開示の第４の実施形態による撮像装置の変形例を示す。図２３に示す画素１０Ｃｐは、図２１に示す画素１０Ｃの光電変換部５０Ａを光電変換部５０Ｂに置き換えた回路構成を有する。 (Modification of the fourth embodiment)
FIG. 23 shows a modification of the imaging device according to the fourth embodiment of the present disclosure. The pixel 10Cp illustrated in FIG. 23 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10C illustrated in FIG. 21 is replaced with a photoelectric conversion unit 50B.
　画素１０Ｃｐを有する撮像装置１００の動作は、図２２Ａおよび図２２Ｂを参照して説明した動作と同様であり得る。図２３に示す回路構成によれば、図２１に示す画素１０Ｃと同様に、回路が過度に複雑となることを避けながら、暗電流による画質の劣化を防止し得る。図６に示す画素１０Ａｑと同様に、信号検出トランジスタ７２のゲートと光電変換部５０Ｂとの間に転送トランジスタ７９がさらに接続されてもよい。 The operation of the imaging device 100 having the pixel 10Cp may be similar to the operation described with reference to FIGS. 22A and 22B. According to the circuit configuration shown in FIG. 23, as with the pixel 10C shown in FIG. 21, it is possible to prevent the deterioration of the image quality due to the dark current while preventing the circuit from becoming excessively complicated. Similarly to the pixel 10Aq illustrated in FIG. 6, a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B.
　以上に説明したように、本開示の実施形態によれば、例えば、浮遊ノードに含まれる不純物領域の電位を、容量を介して制御することが可能であり、不純物領域とその周辺との間に形成される空乏層を縮小して空乏層内に位置する格子欠陥の数を低減できる。あるいは、浮遊ノードに含まれる不純物領域とその周辺との間のｐｎ接合に順方向電流が発生することによるノイズの混入を抑制可能である。したがって、暗電流に起因するＳＮ比の低下が抑制された撮像装置が提供される。 As described above, according to the embodiment of the present disclosure, for example, it is possible to control the potential of the impurity region included in the floating node via the capacitance, and between the impurity region and the periphery thereof The depletion layer formed can be reduced to reduce the number of lattice defects located in the depletion layer. Alternatively, it is possible to suppress noise mixing due to forward current generation in the pn junction between the impurity region included in the floating node and the periphery thereof. Therefore, the imaging device in which the fall of the SN ratio resulting from dark current is controlled is provided.
　本開示の実施形態による撮像装置は、上述した例に限定されず、種々の改変が可能である。電圧供給回路１２８などを含む周辺回路１２０の動作は、半導体基板６０、または、半導体基板６０とは異なる他の基板に実装された制御回路からの指示に基づいて実行されてもよい。撮像装置に含まれる各回路は、ＬＳＩなどの集積回路によって実現されてもよいし、それらの一部または全部が、単一の回路として１つのチップに集積されていてもよい。撮像装置に含まれる各回路は、ＦＰＧＡ（field-programmable gate array）として実現されてもよいし、リコンフィギュラブル・プロセッサなどであってもよい。撮像装置に含まれる各回路は、特定の処理に向けられた回路として実現されてもよいし、汎用の処理回路と、上述の実施形態に例示したような処理が記述されたプログラムとの組み合わせによって実現されてもよい。このプログラムは、半導体基板６０または他の基板に形成されたメモリなどに格納され得る。 The imaging device according to the embodiment of the present disclosure is not limited to the above-described example, and various modifications are possible. The operation of peripheral circuit 120 including voltage supply circuit 128 or the like may be performed based on an instruction from a control circuit mounted on semiconductor substrate 60 or another substrate different from semiconductor substrate 60. Each circuit included in the imaging device may be realized by an integrated circuit such as an LSI, or some or all of them may be integrated in one chip as a single circuit. Each circuit included in the imaging device may be realized as an FPGA (field-programmable gate array) or may be a reconfigurable processor or the like. Each circuit included in the imaging apparatus may be realized as a circuit directed to a specific process, or may be realized by a combination of a general-purpose processing circuit and a program in which the process as described in the above embodiment is described. It may be realized. This program may be stored in a memory or the like formed on the semiconductor substrate 60 or another substrate.
　（第５の実施形態）
　図２４は、本開示の第５の実施形態によるカメラシステムの機能ブロックを模式的に示す。図２４に示すカメラシステム２００は、光学系２０１と、撮像装置１００と、信号処理回路２０３と、システムコントローラ２０４と、表示装置２０５とを有する。カメラシステム２００は、例えばスマートフォン、デジタルカメラおよびビデオカメラなどであり得る。 Fifth Embodiment
FIG. 24 schematically shows functional blocks of a camera system according to a fifth embodiment of the present disclosure. A camera system 200 illustrated in FIG. 24 includes an optical system 201, an imaging device 100, a signal processing circuit 203, a system controller 204, and a display device 205. Camera system 200 may be, for example, a smartphone, a digital camera, a video camera, and the like.
　光学系２０１は、例えば、光学ズームおよびオートフォーカス用のレンズを含むレンズ群および絞りを有する。撮像装置１００としては、第１～第４の実施形態で説明した撮像装置のいずれも適用し得る。 The optical system 201 has, for example, a lens group including an optical zoom and a lens for autofocus and a stop. As the imaging device 100, any of the imaging devices described in the first to fourth embodiments can be applied.
　信号処理回路２０３は、例えばＤＳＰ（Digital Signal Processor）である。信号処理回路２０３は、撮像装置１００から出力データを受け取り、例えばガンマ補正、色補間処理、空間補間処理およびオートホワイトバランスなどの処理を行う。撮像装置１００および信号処理回路２０３が、単一の半導体装置として実現されてもよい。半導体装置は、例えばいわゆるＳｏＣ（System on a Chip）であり得る。このような構成によれば、撮像装置１００をその一部として含む電子機器をより小型化することができる。 The signal processing circuit 203 is, for example, a DSP (Digital Signal Processor). The signal processing circuit 203 receives output data from the imaging device 100, and performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The imaging device 100 and the signal processing circuit 203 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). According to such a configuration, the electronic device including the imaging device 100 as a part thereof can be further miniaturized.
　システムコントローラ２０４は、カメラシステム２００の全体を制御する。システムコントローラ２０４は、典型的には半導体集積回路であり、例えばＣＰＵ（Central Processing Unit）である。 A system controller 204 controls the entire camera system 200. The system controller 204 is typically a semiconductor integrated circuit, and is, for example, a CPU (Central Processing Unit).
　表示装置２０５は、例えば液晶ディスプレイまたは有機ＥＬディスプレイである。表示装置２０５は、タッチパネルのような入力インタフェースを備えていてもよい。これにより、ユーザは、タッチペンを用いて、信号処理回路２０３の処理内容の選択および制御ならびに撮像条件の設定を、入力インタフェースを介して実行できる。 The display device 205 is, for example, a liquid crystal display or an organic EL display. The display device 205 may include an input interface such as a touch panel. Thus, the user can execute selection and control of the processing content of the signal processing circuit 203 and setting of imaging conditions through the input interface using the touch pen.
　上述の信号検出トランジスタ７２、アドレストランジスタ７４、リセットトランジスタ７６、トランジスタ７１、トランジスタ７８、負荷トランジスタ７３および転送トランジスタ７９の各々は、ｐチャンネルＭＯＳであってもよい。上述したように、これらのトランジスタがｐチャンネルＭＯＳである場合には、第２電圧として、第１電圧よりも低い電圧を適用し得る。なお、信号検出トランジスタ７２、アドレストランジスタ７４、リセットトランジスタ７６、トランジスタ７１、トランジスタ７８、負荷トランジスタ７３および転送トランジスタ７９の全てがｎチャンネルＭＯＳまたはｐチャンネルＭＯＳのいずれかに統一されている必要はない。これらのトランジスタとして、電界効果トランジスタのほか、バイポーラトランジスタも用い得る。 Each of the signal detection transistor 72, the address transistor 74, the reset transistor 76, the transistor 71, the transistor 78, the load transistor 73, and the transfer transistor 79 described above may be a p-channel MOS. As described above, when these transistors are p-channel MOSs, a voltage lower than the first voltage can be applied as the second voltage. The signal detection transistor 72, the address transistor 74, the reset transistor 76, the transistor 71, the transistor 78, the load transistor 73, and the transfer transistor 79 need not all be unified into either n channel MOS or p channel MOS. As these transistors, besides field effect transistors, bipolar transistors can also be used.
　本開示の実施形態によれば、暗電流による影響を抑制して高画質で撮像が可能な撮像装置が提供される。本開示の撮像装置は、例えばイメージセンサ、デジタルカメラなどに有用である。本開示の撮像装置は、モバイル機器用カメラ、医療用カメラ、ロボット用カメラ、セキュリティカメラ、車両に搭載されて使用されるカメラなどに用いることができる。 According to an embodiment of the present disclosure, an imaging device capable of imaging with high image quality by suppressing the influence of dark current is provided. The imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, and the like. The imaging device of the present disclosure can be used as a camera for a mobile device, a medical camera, a camera for a robot, a security camera, a camera mounted on a vehicle, and the like.
　１０、１０Ａ～１０Ｃ、１０Ａｐ～１０Ａｘ　　画素
　１０Ｂｆ、１０Ｂｒ、１０Ｂｐ、１０Ｂｑ　　画素
　１０Ｃ、１０Ｃｐ、１０Ｄ、１０Ｄｐ　　画素
　４２　　接続部
　５０Ａ、５０Ｂ　　光電変換部
　５２　　画素電極
　５４　　光電変換層
　５６　　対向電極
　６０　　半導体基板
　６０Ｓ　　支持基板
　６０ａ～６０ｅ　　不純物領域
　６１ｐ　　第１ｐ型半導体層
　６２ｐ　　第２ｐ型半導体層
　７１　　トランジスタ
　７２、７２ｄ　　信号検出トランジスタ
　７２ｅ　　信号検出トランジスタのゲート電極
　７３　　負荷トランジスタ
　７４　　アドレストランジスタ
　７６　　リセットトランジスタ
　７８　　トランジスタ
　７９　　転送トランジスタ
　８１　　制御線
　８４　　アドレス信号線
　８６　　リセット信号線
　８８　　信号線
　８９　　垂直信号線
　９０、９０ｘ　　フィードバック回路
　９４　　電流源
　９５　　検出回路
　１００、１４０、１５０　　撮像装置
　１１０　　画素アレイ
　１２０　　周辺回路
　１２２　　垂直走査回路
　１２８　　電圧供給回路
　２００　　カメラシステム
　Ｃ１～Ｃ３　　容量素子 10, 10A to 10C, 10Ap to 10Ax pixel 10Bf, 10Br, 10Bp, 10Bq pixel 10C, 10Cp, 10D, 10Dp pixel 42 connection portion 50A, 50B photoelectric conversion unit 52 pixel electrode 54 photoelectric conversion layer 56 counter electrode 60 semiconductor substrate 60S supported Substrate 60a to 60e Impurity region 61p First p-type semiconductor layer 62p Second p-type semiconductor layer 71 Transistor 72, 72d Signal detection transistor 72e Gate electrode of signal detection transistor 73 Load transistor 74 Address transistor 76 Reset transistor 78 Transistor 79 Transfer transistor 81 Control line 84 address signal line 86 reset signal line 88 signal line 89 vertical signal line 90, 90x feedback circuit 94 current source 95 detection circuit 10 , 140, 150 imaging device 110 pixel array 120 around circuit 122 vertical scanning circuit 128 voltage supply circuit 200 camera system C1 ~ C3 capacitive element

Claims (13)

  1. 　ｎ型の導電型の第１不純物領域を有する半導体基板と、
    　前記第１不純物領域に電気的に接続され、光を電荷に変換する光電変換部と、
    　第１端子および第２端子を有し、前記第１端子が前記第１不純物領域に電気的に接続された容量素子と、
    　前記第２端子に電気的に接続された電圧供給回路と
    を備え、
    　前記電圧供給回路は、互いに異なる第１の電圧および第２の電圧を前記第２端子に供給し、
    　前記第１不純物領域は、前記光電変換部で生じた電荷のうち正電荷を蓄積する、撮像装置。     a semiconductor substrate having a first impurity region of n-type conductivity;
    A photoelectric conversion unit electrically connected to the first impurity region to convert light into charge;
    A capacitive element having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first impurity region;
    A voltage supply circuit electrically connected to the second terminal;
    The voltage supply circuit supplies first and second voltages different from each other to the second terminal,
    The imaging device according to claim 1, wherein the first impurity region stores positive charge among charges generated in the photoelectric conversion unit.
  2. 　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
    　前記電圧供給回路は、前記第１トランジスタがオンである第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオフである第２期間に前記第２電圧を前記第２端子に供給する、請求項１に記載の撮像装置。     The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
    The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off The imaging device according to claim 1, wherein the second voltage is supplied to the second terminal.
  3. 　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
    　前記電圧供給回路は、前記正電荷を前記第１不純物領域に蓄積する第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオンである第２期間に前記第２電圧を前記第２端子に供給する、請求項１に記載の撮像装置。     The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
    The voltage supply circuit supplies the first voltage to the second terminal during a first period in which the positive charge is accumulated in the first impurity region, and the first transistor is turned on after the first period. The imaging device according to claim 1, wherein the second voltage is supplied to the second terminal in a second period.
  4. 　前記半導体基板は、第２不純物領域を有し、
    　前記第１トランジスタは、前記第２不純物領域をソースおよびドレインの他方として含み、
    　前記第１端子は、前記第２不純物領域に接続されている、請求項２または３に記載の撮像装置。     The semiconductor substrate has a second impurity region,
    The first transistor includes the second impurity region as the other of a source and a drain,
    The imaging device according to claim 2, wherein the first terminal is connected to the second impurity region.
  5. 　前記第２電圧は、前記第１電圧よりも高い、請求項２から４のいずれか一項に記載の撮像装置。 The imaging device according to any one of claims 2 to 4, wherein the second voltage is higher than the first voltage.
  6. 　ｐ型の導電型の第１不純物領域を有する半導体基板と、
    　前記第１不純物領域に電気的に接続され、光を電荷に変換する光電変換部と、
    　第１端子および第２端子を有し、前記第１端子が前記第１不純物領域に電気的に接続された容量素子と、
    　前記第２端子に電気的に接続された電圧供給回路と
    を備え、
    　前記電圧供給回路は、互いに異なる第１の電圧および第２の電圧を前記第２端子に供給し、
    　前記第１不純物領域は、前記光電変換部で生じた電荷のうち負電荷を蓄積する、撮像装置。     a semiconductor substrate having a first impurity region of p-type conductivity;
    A photoelectric conversion unit electrically connected to the first impurity region to convert light into charge;
    A capacitive element having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first impurity region;
    A voltage supply circuit electrically connected to the second terminal;
    The voltage supply circuit supplies first and second voltages different from each other to the second terminal,
    The imaging device according to claim 1, wherein the first impurity region stores negative charge among charges generated in the photoelectric conversion unit.
  7. 　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
    　前記電圧供給回路は、前記第１トランジスタがオンである第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオフである第２期間に前記第２電圧を前記第２端子に供給する、請求項６に記載の撮像装置。     The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
    The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the first transistor is on, and in a second period after the first period and in which the first transistor is off The imaging device according to claim 6, wherein the second voltage is supplied to the second terminal.
  8. 　前記第１不純物領域をソースおよびドレインの一方として含む第１トランジスタをさらに備え、
    　前記電圧供給回路は、前記負電荷を前記第１不純物領域に蓄積する第１期間に前記第１電圧を前記第２端子に供給し、前記第１期間の後かつ前記第１トランジスタがオンである第２期間に前記第２電圧を前記第２端子に供給する、請求項６に記載の撮像装置。     The first transistor further includes a first transistor including the first impurity region as one of a source and a drain.
    The voltage supply circuit supplies the first voltage to the second terminal in a first period in which the negative charge is accumulated in the first impurity region, and the first transistor is turned on after the first period. The imaging device according to claim 6, wherein the second voltage is supplied to the second terminal in a second period.
  9. 　前記半導体基板は、第２不純物領域を有し、
    　前記第１トランジスタは、前記第２不純物領域をソースおよびドレインの他方として含み、
    　前記第１端子は、前記第２不純物領域に接続されている、請求項７または８に記載の撮像装置。     The semiconductor substrate has a second impurity region,
    The first transistor includes the second impurity region as the other of a source and a drain,
    The imaging device according to claim 7, wherein the first terminal is connected to the second impurity region.
  10. 　前記第２電圧は、前記第１電圧よりも低い、請求項７から９のいずれか一項に記載の撮像装置。 The imaging device according to any one of claims 7 to 9, wherein the second voltage is lower than the first voltage.
  11. 　前記容量素子および前記第１不純物領域は、前記光電変換部で生じた電荷のうち一方の極性の電荷を蓄積する電荷蓄積ノードの少なくとも一部であり、
    　前記容量素子の容量値は、前記電荷蓄積ノードのうち前記容量素子以外の部分の容量値よりも小さい、請求項１から１０のいずれか一項に記載の撮像装置。     The capacitive element and the first impurity region are at least a part of a charge storage node that stores charges of one polarity among charges generated in the photoelectric conversion unit,
    The imaging device according to any one of claims 1 to 10, wherein a capacitance value of the capacitive element is smaller than a capacitance value of a portion other than the capacitive element in the charge storage node.
  12. 　前記光電変換部は、
    　　第１電極と、
    　　前記第１電極に対向する第２電極と、
    　　前記第１電極および前記第２電極の間に位置する光電変換層と
    　を有し、
    　前記第１電極は、前記第１不純物領域に電気的に接続されている、請求項１から１１のいずれか一項に記載の撮像装置。     The photoelectric conversion unit is
    A first electrode,
    A second electrode facing the first electrode;
    A photoelectric conversion layer located between the first electrode and the second electrode;
    The imaging device according to any one of claims 1 to 11, wherein the first electrode is electrically connected to the first impurity region.
  13. 　前記光電変換部は、埋め込みフォトダイオードである、請求項１から４および６から９のいずれか一項に記載の撮像装置。 The imaging device according to any one of claims 1 to 4 and 6 to 9, wherein the photoelectric conversion unit is a buried photodiode.
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