JP2017175345A - Solid-state imaging device, method of driving the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a dynamic range of a solid-state imaging device while suppressing deterioration in image quality.SOLUTION: A solid-state imaging device performs control so as to read out a first data signal in a state where first electric charges generated by a first photoelectric conversion unit are stored in a first electric charge voltage converter, a second data signal in a state where the first electric charges are stored in a region where potentials of the first electric charge voltage converter and a second electric charge voltage converter are coupled, and a third data signal based on second electric charges generated by the second photoelectric conversion unit. This technology can be applied to a solid-state imaging device, for example.SELECTED DRAWING: Figure 6

Description

  The present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, and more particularly, to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device that can expand a dynamic range.

  Conventionally, there are various methods for expanding the dynamic range of solid-state imaging devices.

  For example, a time division method is known in which images are taken in time division with different sensitivities and a plurality of images taken in time division are combined.

  In addition, for example, a space division method is known in which a light receiving element having different sensitivity is provided and a dynamic range is expanded by combining a plurality of images captured by light receiving elements having different sensitivities (for example, see Patent Document 1). .

JP 2006-253876 A

  However, in the time division method and the space division method, the dynamic range can be expanded by increasing the number of divisions. On the other hand, when the number of divisions increases, the image quality is deteriorated due to the occurrence of artifacts or a decrease in resolution.

  Therefore, the present technology enables the dynamic range of a solid-state imaging device to be expanded while suppressing deterioration in image quality.

  The solid-state imaging device according to the first aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels. A conversion unit; a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit; a charge storage unit that stores charges generated by the second photoelectric conversion unit; and a first charge-voltage conversion unit; , A second charge voltage conversion unit, a first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge A second transfer gate unit that couples the potential of the storage unit; and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter. The first charge generated by the first photoelectric conversion unit is converted into the first charge. A second data in a state where the first charge is accumulated in a region where the potentials of the first data signal and the first charge voltage conversion unit and the second charge voltage conversion unit are combined. And a third data signal based on the second charge generated by the second photoelectric conversion unit.

  The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. It is possible to control to read out the second reset signal in a state where is reset.

  In the driving unit, the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. And a third reset signal in a state where the region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset. Can be controlled.

  A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and A signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal can be further provided.

  When the value of the first difference signal is equal to or less than a predetermined first threshold, the signal processing unit uses the first difference signal as a pixel signal of the unit pixel, and the value of the first difference signal Exceeds the first threshold and the value of the second difference signal is equal to or less than a predetermined second threshold, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal When the value of exceeds the second threshold, the third difference signal can be used as the pixel signal of the unit pixel.

  The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal. A pixel signal of the unit pixel can be generated by combining the second difference signal and the third difference signal.

  The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge The first reset signal is read out in a state in which the transfer gate portion is turned off, and then the first transfer gate portion is turned on to convert the first charge into the first charge-voltage conversion. The first data signal can be read out in a state where the data is transferred to a part, and then the second data signal can be read out in a state where the third transfer gate part is turned on.

  In the driving unit, the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The data signal can be controlled to be read out.

  The unit pixel is formed under a fourth transfer gate unit that transfers charges from the second photoelectric conversion unit to the charge storage unit, and under a gate electrode of the fourth transfer gate unit, An overflow path for transferring charges overflowing from the photoelectric conversion unit to the charge storage unit may be further provided.

  The second photoelectric conversion unit and the charge storage unit can be connected without a transfer gate unit.

  The counter electrode of the charge storage unit is connected to a variable voltage power source, and the drive unit has a period of reading a signal based on the charge stored in the charge storage unit in a period of storing charge in the charge storage unit, The voltage applied to the counter electrode of the charge storage portion can be lowered.

  A reset gate portion connected between a power supply of a predetermined voltage and the second charge voltage conversion portion can be further provided.

  The driving method of the solid-state imaging device according to the second aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels. 1 photoelectric conversion unit, a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge storage unit for storing charges generated by the second photoelectric conversion unit, and a first charge voltage A conversion unit; a second charge voltage conversion unit; a first transfer gate unit configured to transfer charges from the first photoelectric conversion unit to the first charge voltage conversion unit; and the second charge voltage conversion unit. And a second transfer gate unit that couples the potential of the charge storage unit, and a third transfer gate unit that couples the potential of the first charge voltage conversion unit and the second charge voltage conversion unit. The imaging apparatus uses the first charge generated by the first photoelectric conversion unit as a front The first charge is accumulated in a region where the first data signal in the state accumulated in the first charge voltage conversion unit and the potential of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. Control is performed to read out the second data signal in the state and the third data signal based on the second charge generated by the second photoelectric conversion unit.

  An electronic apparatus according to a third aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a drive unit that controls the operation of the unit pixel, and the unit pixel includes a first photoelectric conversion unit. A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge accumulation unit that accumulates charges generated by the second photoelectric conversion unit, a first charge voltage conversion unit, A second charge-voltage converter, a first transfer gate that transfers charges from the first photoelectric converter to the first charge-voltage converter, the second charge-voltage converter, and the charge storage A second transfer gate unit that couples the potentials of the first and second charge gates, and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter. The first charge generated by the photoelectric conversion unit is accumulated in the first charge voltage conversion unit. A first data signal in a state, a second data signal in a state where the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and A solid-state imaging device that controls to read out a third data signal based on the second charge generated by the second photoelectric conversion unit; and a signal processing device that processes a signal from the solid-state imaging device.

  In the first to third aspects of the present technology, the first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first data signal, A second data signal in a state where the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and a second data signal generated by the second photoelectric conversion unit. A third data signal based on the charge of 2 is read out.

  According to the first to third aspects of the present technology, it is possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.

1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the present technology is applied. It is a system configuration | structure figure (the 1) which shows the other system configuration | structure of the CMOS image sensor to which this technique is applied. It is a system configuration figure (the 2) showing other system composition of a CMOS image sensor to which this art is applied. It is a circuit diagram showing an example of composition of a unit pixel in a 1st embodiment of this art. 5 is a timing chart for explaining a first operation example at the start of exposure of the unit pixel of FIG. 4. FIG. 5 is a timing chart for explaining a first operation example during reading of the unit pixel of FIG. 4. FIG. 6 is a timing chart for explaining a second operation example at the start of exposure of the unit pixel of FIG. 4. FIG. 5 is a timing chart for explaining a second operation example at the time of reading the unit pixel of FIG. 4. FIG. It is a circuit diagram showing an example of composition of a unit pixel in a 2nd embodiment of this art. 10 is a timing chart for explaining an operation example at the start of exposure of the unit pixel of FIG. 9. 10 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 9. It is a circuit diagram showing an example of composition of a unit pixel in a 3rd embodiment of this art. 13 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 12. 13 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 12. It is a circuit diagram showing an example of composition of a unit pixel in a 4th embodiment of this art. 16 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 15. 16 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 15. It is an incident light quantity-output characteristic diagram for explanation of signal processing. It is a figure which shows the usage example of a solid-state imaging device. It is a block diagram which shows the structural example of an electronic device.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Solid-state imaging device to which the present technology is applied 1. First embodiment Second embodiment (example in which the fourth transfer gate unit is deleted from the first embodiment)
4). Third Embodiment (Example in which voltage applied to counter electrode of charge storage unit is variable)
5. Fourth embodiment (example in which the fourth transfer gate unit is deleted from the third embodiment)
6). 6. Explanation regarding noise removal processing and arithmetic processing Modification 8 Examples of using solid-state imaging devices

<1. Solid-state imaging device to which the present technology is applied>
{1-1. Basic system configuration}
FIG. 1 is a system configuration diagram showing an outline of a configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.

  A CMOS image sensor 10 according to this application example includes a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. It has a configuration. The peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.

  The CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19. The signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be disposed on a different substrate from the CMOS image sensor 10. Each processing of the signal processing unit 18 and the data storage unit 19 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 10, for example, a DSP (Digital Signal Processor) circuit or software. Absent.

  The pixel array unit 11 includes unit pixels (hereinafter also simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates charges according to the received light amount in the row direction and the column direction, that is, The configuration is two-dimensionally arranged in a matrix. Here, the row direction refers to the pixel arrangement direction (that is, the horizontal direction) of the pixel row, and the column direction refers to the pixel arrangement direction (that is, the vertical direction) of the pixel column. Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.

  In the pixel array unit 11, the pixel drive lines 16 are wired along the row direction for each pixel row, and the vertical signal lines 17 are wired along the column direction for each pixel column in the matrix pixel array. . The pixel drive line 16 transmits a drive signal for driving when reading a signal from the pixel. In FIG. 1, the pixel drive line 16 is shown as one wiring, but is not limited to one. One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.

  The vertical drive unit 12 includes a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 11 at the same time or in units of rows. That is, the vertical drive unit 12 constitutes a drive unit that controls the operation of each pixel of the pixel array unit 11 together with the system control unit 15 that controls the vertical drive unit 12. The vertical drive unit 12 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 11 sequentially in units of rows in order to read out signals from the unit pixels. The signal read from the unit pixel is an analog signal. The sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the exposure time.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion unit of the unit pixel in the readout row, thereby resetting the photoelectric conversion unit. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the electric charge in the photoelectric conversion unit is discarded and exposure is newly started (charge accumulation is started).

  The signal read by the read operation by the read scanning system corresponds to the amount of light received after the immediately preceding read operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the charge exposure period in the unit pixel.

  A signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 12 is input to the column processing unit 13 through each of the vertical signal lines 17 for each pixel column. The column processing unit 13 performs predetermined signal processing on signals output from the pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily outputs the pixel signals after the signal processing. Hold on.

  Specifically, the column processing unit 13 performs at least noise removal processing such as CDS (Correlated Double Sampling) processing and DDS (Double Data Sampling) processing as signal processing. For example, the CDS process removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel. In addition to noise removal processing, the column processing unit 13 may have, for example, an AD (analog-digital) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.

  The horizontal drive unit 14 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.

  The system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on various timings generated by the timing generator. Drive control is performed.

  The signal processing unit 18 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 13. The data storage unit 19 temporarily stores data necessary for the signal processing in the signal processing unit 18.

{1-2. Other system configuration}
The CMOS image sensor 10 to which the present technology is applied is not limited to the system configuration described above. Examples of other system configurations include the following system configurations.

  For example, as shown in FIG. 2, the data storage unit 19 is arranged at the subsequent stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 18 via the data storage unit 19. And a CMOS image sensor 10A having a system configuration.

  Further, as shown in FIG. 3, the column processing unit 13 is provided with an AD conversion function for performing AD conversion for each column or a plurality of columns of the pixel array unit 11, and a data storage unit is provided for the column processing unit 13. 19 and a CMOS image sensor 10B having a system configuration in which the signal processing unit 18 is provided in parallel.

<2. First Embodiment>
Next, a first embodiment of the present technology will be described with reference to FIGS. 4 to 7.

{Circuit configuration of unit pixel 100A}
FIG. 4 is a circuit diagram illustrating a configuration example of the unit pixel 100A arranged in the pixel array unit 11 of FIGS.

  The unit pixel 100A includes a first photoelectric conversion unit 101a, a second photoelectric conversion unit 101b, a first transfer gate unit 102a to a fourth transfer gate unit 102d, a reset gate unit 103, a charge storage unit 104, and a first FD (floating diffusion) unit. 105 a, a second FD (floating diffusion) portion 105 b, an amplification transistor 106, and a selection transistor 107.

  In addition, a plurality of drive lines are wired for each pixel row as the pixel drive lines 16 in FIGS. 1 to 3 for the unit pixel 100A, for example. Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical drive unit 12 of FIGS. 1 to 3 through a plurality of drive lines. These drive signals are pulses in which each of the transistors of the unit pixel 100A is an NMOS transistor, so that a high level (for example, power supply voltage VDD) is an active state and a low level (for example, a negative potential) is inactive. Signal.

  The first photoelectric conversion unit 101a is composed of, for example, a PN junction photodiode. The 1st photoelectric conversion part 101a produces | generates and accumulate | stores the electric charge according to the received light quantity.

  Similar to the first photoelectric conversion unit 101a, the second photoelectric conversion unit 101b includes, for example, a PN junction photodiode. The second photoelectric conversion unit 101b generates and accumulates charges corresponding to the received light amount.

  Comparing the first photoelectric conversion unit 101a and the second photoelectric conversion unit 101b, the first photoelectric conversion unit 101a has a larger light receiving surface area and higher sensitivity, and the second photoelectric conversion unit 101b has a light receiving surface area. Is narrow and has low sensitivity.

  The first transfer gate unit 102a is connected between the first photoelectric conversion unit 101a and the first FD unit 105a. A drive signal TGL is applied to the gate electrode of the first transfer gate portion 102a. When the drive signal TGL becomes active, the first transfer gate unit 102a becomes conductive, and the charge accumulated in the first photoelectric conversion unit 101a is transferred to the first FD unit 105a via the first transfer gate unit 102a. Is done.

  The second transfer gate unit 102b is connected between the charge storage unit 104 and the second FD unit 105b. A drive signal FCG is applied to the gate electrode of the second transfer gate portion 102b. When the drive signal FCG becomes active, the second transfer gate portion 102b becomes conductive, and the potentials of the charge storage portion 104 and the second FD portion 105b are coupled.

  The third transfer gate unit 102c is connected between the first FD unit 105a and the second FD unit 105b. A drive signal FDG is applied to the gate electrode of the third transfer gate portion 102c. When the drive signal FDG becomes active, the third transfer gate portion 102c becomes conductive, and the potentials of the first FD portion 105a and the second FD portion 105b are coupled.

  The fourth transfer gate unit 102d is connected between the second photoelectric conversion unit 101b and the charge storage unit 104. A drive signal TGS is applied to the gate electrode of the fourth transfer gate portion 102d. When the drive signal TGS is in the active state, the fourth transfer gate unit 102d becomes conductive, and the charge accumulated in the second photoelectric conversion unit 101b is transferred to the charge accumulation unit 104 via the fourth transfer gate unit 102d. Transferred.

  In addition, the lower part of the gate electrode of the fourth transfer gate portion 102d has a slightly deep potential, and the charge that exceeds the saturation charge amount of the second photoelectric conversion portion 101b and overflows from the second photoelectric conversion portion 101b is stored in the charge storage portion. An overflow path to be transferred to 104 is formed. Hereinafter, the overflow path formed below the gate electrode of the fourth transfer gate portion 102d is simply referred to as the overflow path of the fourth transfer gate portion 102d.

  The reset gate unit 103 is connected between the power supply VDD that supplies the power supply voltage VDD and the second FD unit 105b. A drive signal RST is applied to the gate electrode of the reset gate portion 103. When the drive signal RST becomes active, the reset gate unit 103 becomes conductive. Thereby, for example, the potential of the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined, or the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is Reset to the level of voltage VDD.

  The charge storage unit 104 includes, for example, a capacitor, and the counter electrode of the charge storage unit 104 is connected between the power supply VDD. The charge storage unit 104 stores the charge transferred from the second photoelectric conversion unit 101b.

  The first FD unit 105a and the second FD unit 105b convert the charge into a voltage signal and output it.

  The amplification transistor 106 has a gate electrode connected to the first FD unit 105a, a drain electrode connected to the power supply VDD, and a readout circuit that reads out the charge held in the first FD unit 105a, a so-called source follower circuit input unit and Become. That is, the amplification transistor 106 forms a source follower circuit with the constant current source 108 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 via the selection transistor 107.

  The selection transistor 107 is connected between the source electrode of the amplification transistor 106 and the vertical signal line 17. A drive signal SEL is applied to the gate electrode of the selection transistor 107. When the drive signal SEL becomes active, the selection transistor 107 becomes conductive and the unit pixel 100A becomes selected. As a result, the pixel signal output from the amplification transistor 106 is output to the vertical signal line 17 via the selection transistor 107.

  In the following description, each drive signal is in an active state, each drive signal is turned on, and each drive signal is in an inactive state, each drive signal is also turned off. In addition, hereinafter, each gate portion or each transistor is turned on, each gate portion or each transistor may be turned on, and each gate portion or each transistor is turned off. It is also said that the transistor is turned off.

{Operation of Unit Pixel 100A}
Next, the operation of the unit pixel 100A will be described with reference to the timing charts of FIGS.

(First operation example at the start of exposure of the unit pixel 100A)
First, a first operation example at the start of exposure of the unit pixel 100A will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 5 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.

  First, at time t1, the horizontal synchronization signal XHS is input, and the exposure processing of the unit pixel 100A starts.

  Next, at time t2, the drive signals RST and FDG are turned on, and the reset gate unit 103 and the third transfer gate unit 102c are turned on. As a result, the potentials of the first FD portion 105a and the second FD portion 105b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.

  Next, at time t3, the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. As a result, the electric charge accumulated in the first photoelectric conversion unit 101a is transferred to the region where the potentials of the first FD unit 105a and the second FD unit 105b are coupled via the first transfer gate unit 102a. The unit 101a is reset.

  Next, at time t4, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, accumulation of electric charges in the first photoelectric conversion unit 101a is started, and an exposure period is started.

  Next, at time t5, the drive signals TGS and FCG are turned on, and the fourth transfer gate unit 102d and the second transfer gate unit 102b are turned on. As a result, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled. In addition, the charge accumulated in the second photoelectric conversion unit 101b is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.

  Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, accumulation of electric charges in the second photoelectric conversion unit 101b is started.

  Next, at time t7, the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off. As a result, the charge accumulation unit 104 starts accumulating charges that overflow from the second photoelectric conversion unit 101b and are transferred through the overflow path of the fourth transfer gate unit 102d.

  Next, at time t8, the drive signals RST and FDG are turned off, and the reset gate unit 103 and the third transfer gate unit 102c are turned off.

  At time t9, the horizontal synchronization signal XHS is input.

(First operation example when reading out the unit pixel 100A)
Next, a first operation example at the time of reading a pixel signal of the unit pixel 100A will be described with reference to a timing chart of FIG. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 5 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows, for example. FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.

  First, at time t21, the horizontal synchronization signal XHS is input, and the readout period of the unit pixel 100A starts.

  Next, at time t22, the drive signals SEL, RST, and FDG are turned on, and the selection transistor 107, the reset gate unit 103, and the third transfer gate unit 102c are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the first FD portion 105a and the second FD portion 105b are combined, and the potential of the combined region is reset to the level of the power supply voltage VDD.

  Next, at time t23, the drive signal RST is turned off and the reset gate unit 103 is turned off.

  Next, at time ta between time t23 and time t24, a signal NH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17. The signal NH2 is a signal based on a potential in a reset state of a region where the potentials of the first FD unit 105a and the second FD unit 105b are combined.

  Hereinafter, the signal NH2 is also referred to as a high-sensitivity reset signal NH2.

  Next, at time t24, the drive signal FDG is turned off, and the third transfer gate unit 102c is turned off. Thereby, the potential coupling between the first FD part 105a and the second FD part 105b is canceled.

  Next, at time tb between time t24 and time t25, the signal NH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107. The signal NH1 is a signal based on the potential in the reset state of the first FD unit 105a.

  Hereinafter, the signal NH1 is also referred to as a high-sensitivity reset signal NH1.

  Next, at time t25, the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. Thereby, the charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is transferred to the first FD unit 105a via the first transfer gate unit 102a.

  At time t25, reading of the pixel signal is started, and the exposure period ends.

  Next, at time t26, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, the transfer of charge from the first photoelectric conversion unit 101a to the first FD unit 105a is stopped.

  Next, at time tc between time t26 and time t27, the signal SH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 through the amplification transistor 106 and the selection transistor 107. The signal SH1 is a signal based on the potential of the first FD unit 105a in a state where the electric charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is accumulated in the first FD unit 105a.

  Hereinafter, the signal SH1 is also referred to as a high sensitivity data signal SH1.

  Next, at time t27, the drive signals FDG and TGL are turned on, and the third transfer gate unit 102c and the first transfer gate unit 102a are turned on. As a result, the potentials of the first FD unit 105a and the second FD unit 105b are combined, and the charge remaining in the first photoelectric conversion unit 101a without being transferred between the time t25 and the time t26 passes through the first transfer gate unit 102a. To the combined area. Note that when reading the high-sensitivity data signal SH1, since the capacity for charge-voltage conversion is small with respect to the amount of charge handled, there is no problem even if charges remain in the first photoelectric conversion unit 101a. The charge remaining in the first photoelectric conversion unit 101a only needs to be transferred when the high-sensitivity data signal SH2 is read, and the charge is not damaged in the first photoelectric conversion unit 101a.

  Next, at time t28, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. As a result, transfer of charges from the first photoelectric conversion unit 101a to the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined is stopped.

  Next, at time td between time t28 and time t29, the signal SH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17. The signal SH2 is generated by the first photoelectric conversion unit 101a during the exposure period, and the accumulated electric charge is accumulated in the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined. It becomes a signal based on. Accordingly, the capacity for charge-voltage conversion at the time of reading the signal SH2 is the capacity of the first FD portion 105a and the second FD portion 105b, and is larger than that at the time of reading the high sensitivity data signal SH1 at time tc.

  Hereinafter, the signal SH2 is also referred to as a high-sensitivity data signal SH2.

  Next, at time t29, the drive signal RST is turned on, and the reset gate unit 103 is turned on. As a result, the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is reset to the level of the power supply voltage VDD.

  Next, at time t30, the drive signal SEL is turned off and the selection transistor 107 is turned off. As a result, the unit pixel 100A enters a non-selected state.

  Next, at time t31, the drive signal RST is turned off and the reset gate unit 103 is turned off.

  Next, at time t32, the drive signals SEL, TGS, and FCG are turned on, and the selection transistor 107, the fourth transfer gate unit 102d, and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges stored in the second photoelectric conversion unit 101b are transferred to the combined region. As a result, charges accumulated in the second photoelectric conversion unit 101b and the charge accumulation unit 104 during the exposure period are accumulated in the combined region.

  Next, at time t33, the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, the transfer of charge from the second photoelectric conversion unit 101b is stopped.

  Next, at time te between time t33 and time t34, the signal SL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected by the amplification transistor 106 and the selection transistor 106. The signal is output to the vertical signal line 17 through the transistor 107. The signal SL is generated by the second photoelectric conversion unit 101b during the exposure period, and the charges accumulated in the second photoelectric conversion unit 101b and the charge storage unit 104 are converted into the charge storage unit 104, the first FD unit 105a, and the second FD. The signal is based on the potential of the coupled region in the state where the potential of the portion 105b is accumulated in the coupled region. Therefore, the capacity for charge-voltage conversion at the time of reading the signal SL is a total capacity of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b. This capacity is larger than when reading the high sensitivity data signal SH1 at time tc and when reading the high sensitivity data signal SH2 at time td.

  Hereinafter, the signal SL is also referred to as a low sensitivity data signal SL.

  Next, at time t34, the drive signal RST is turned on, and the reset gate unit 103 is turned on. Thereby, the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is reset.

  Next, at time t35, the drive signals SEL and FCG are turned off, and the selection transistor 107 and the second transfer gate unit 102b are turned off. As a result, the unit pixel 100A enters a non-selected state. In addition, the potential of the charge storage unit 104 is separated from the potentials of the first FD unit 105a and the second FD unit 105b.

  Next, at time t36, the drive signal RST is turned off and the reset gate unit 103 is turned off.

  Next, at time t37, the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potential of the charge storage unit 104 is combined with the potentials of the first FD unit 105a and the second FD unit 105b.

  Next, at time tf between time t37 and time t38, the signal NL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected from the amplification transistor 106 and the selection transistor 106. The signal is output to the vertical signal line 17 through the transistor 107. This signal NL is a signal based on a potential in a reset state of a region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined.

  Hereinafter, the signal NL is also referred to as a low sensitivity reset signal NL.

  Next, at time t38, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor 107, the third transfer gate unit 102c, and the second transfer gate unit 102b are turned off. As a result, the unit pixel 100A enters a non-selected state. Further, the potential coupling of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b is eliminated.

  Next, at time t39, the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel 100A ends.

(Second operation example at the start of exposure of the unit pixel 100A)
Next, a second operation example at the start of exposure of the pixel signal of the unit pixel 100A will be described with reference to the timing chart of FIG.

  When the timing chart of FIG. 7 is compared with the timing chart of FIG. 5, only the operation timing of the drive signal RST is different. Specifically, in the timing chart of FIG. 7, the drive signal RST is kept on without being turned off.

(Second Example of Operation when Reading Unit Pixel 100A)
Next, a second operation example at the time of reading a pixel signal of the unit pixel 100A will be described with reference to a timing chart of FIG. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 7 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows.

  When the timing chart of FIG. 8 is compared with the timing chart of FIG. 6, only the operation timing of the drive signal RST is different. Specifically, as described above with reference to FIG. 7, the drive signal RST does not need to be turned on at time t22 as in the example of FIG. 6 because the drive signal RST is kept turned on at the start of exposure. Further, the drive signal RST is kept on after being turned on at time t34.

<3. Second Embodiment>
Next, a second embodiment of the present technology will be described with reference to FIGS. 9 to 11.

{Circuit configuration of unit pixel 100B}
FIG. 9 is a circuit diagram illustrating a configuration example of a unit pixel 100B that is a modification of the unit pixel 100A of FIG. In the figure, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  When the unit pixel 100B is compared with the unit pixel 100A of FIG. 4, the difference is that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d.

{Operation of Unit Pixel 100B}
Next, the operation of the unit pixel 100B will be described with reference to the timing charts of FIGS.

(Operation example when starting exposure of unit pixel 100B)
First, an operation example at the start of exposure of the unit pixel 100B will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 10 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.

  From time t1 to time t4, operations similar to those from time t1 to t4 in FIG. 5 are performed.

  Next, at time t5, the drive signal FCG is turned on, and the second transfer gate unit 102b is turned on. As a result, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled. In addition, the charge accumulated in the charge accumulation unit 104 is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.

  Next, at time t6, the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off. As a result, the charge accumulation unit 104 starts accumulating the charge transferred from the second photoelectric conversion unit 101b.

  Thereafter, at time t7 and time t8, operations similar to those at time t8 and time t9 in FIG. 5 are performed.

(Operation example when reading out the unit pixel 100B)
Next, with reference to the timing chart of FIG. 11, an operation example at the time of reading the pixel signal of the unit pixel 100B will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 10 is performed, for example, for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 11 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.

  From time t21 to time t31, operations similar to those from time t21 to time t31 in FIG. 6 are performed.

  At time t32, the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges generated in the second photoelectric conversion unit 101b and accumulated in the charge storage unit 104 during the exposure period are Accumulated in the combined area.

  Thereafter, at time te to time t38, operations similar to those at time te to time t39 in FIG. 6 are performed, and then the readout period of the pixel signal of the unit pixel 100B ends.

  In the unit pixel 100B, since the fourth transfer gate portion 102d is deleted, the area efficiency of the arrangement of each element constituting the unit pixel 100B is improved. For example, it is possible to increase the area of the light receiving surface of the first photoelectric conversion unit 101a and improve the sensitivity of the first photoelectric conversion unit 101a.

  Note that in the timing charts of FIGS. 10 and 11, the operation timing of the drive signal RST can be made the same as in the examples of FIGS. 7 and 8 described above.

<4. Third Embodiment>
Next, a third embodiment of the present technology will be described with reference to FIGS.

{Circuit configuration of unit pixel 100C}
FIG. 12 is a circuit diagram illustrating a configuration example of the unit pixel 100C arranged in the pixel array unit 11 of FIGS. In the figure, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  When the unit pixel 100C is compared with the unit pixel 100A of FIG. 4, the connection position of the counter electrode of the charge storage unit 104 is different. That is, the unit pixel 100C is different in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD. The power supply voltage FCVDD of the variable voltage power supply FCVDD is set to, for example, a high level voltage FCH or a low level voltage FCL. For example, the voltage FCH is set to substantially the same level as the power supply voltage VDD, and the voltage FCL is set to a predetermined intermediate potential.

{Operation example of unit pixel 100C}
Next, the operation of the unit pixel 100C will be described with reference to the timing charts of FIGS.

(Operation example at the start of exposure of the unit pixel 100C)
First, an operation example at the start of exposure of the unit pixel 100C will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 13 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and power supply voltage FCVDD.

  When the timing chart of FIG. 13 is compared with the timing chart of FIG. 5, only the operation timing of the power supply voltage FCVDD is different.

  Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2, the state set to the voltage FCH is maintained, and at the time t8, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to

(Operation example when reading out the unit pixel 100C)
Next, with reference to the timing chart of FIG. 14, an example of operation at the time of reading a pixel signal of the unit pixel 100C will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 13 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows, for example. FIG. 14 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, FCG, and the power supply voltage FCVDD.

  When the timing chart of FIG. 14 is compared with the timing chart of FIG. 6, only the operation timing of the power supply voltage FCVDD is different.

  Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t38, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to

  Thus, in the unit pixel 100C, the power supply voltage FCVDD is set to the voltage FCH only at the start of exposure and at the time of reading, and the period in which charges are accumulated in the charge accumulating unit 104 from the start of exposure to the start of reading. Among them, the power supply voltage FCVDD is set to the voltage FCL. As a result, the electric field applied to the charge storage unit 104 during the period in which charges are stored in the charge storage unit 104 is relaxed, and dark current generated in the charge storage unit 104 is suppressed.

  Note that in the timing charts of FIGS. 13 and 14, the operation timing of the drive signal RST can be made the same as in the examples of FIGS. 7 and 8 described above.

<5. Fourth Embodiment>
Next, a fourth embodiment of the present technology will be described with reference to FIGS. 15 to 17.

{Circuit configuration of unit pixel 100D}
FIG. 15 is a circuit diagram illustrating a configuration example of the unit pixel 100D arranged in the pixel array unit 11 of FIGS. 1 to 3. In the figure, portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  When the unit pixel 100D is compared with the unit pixel 100C of FIG. 12, the difference is that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d. Further, the unit pixel 100D is different from the unit pixel 100B in FIG. 9 in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.

{Operation example of unit pixel 100D}
Next, the operation of the unit pixel 100D will be described with reference to the timing charts of FIGS.

(Operation example at the start of exposure of the unit pixel 100D)
First, an operation example at the start of exposure of the unit pixel 100D will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 16 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.

  When the timing chart of FIG. 16 is compared with the timing chart of FIG. 10, only the operation timing of the power supply voltage FCVDD is different.

  Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2, the state set to the voltage FCH is maintained, and at the time t7, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to

(Operation example when reading out the unit pixel 100D)
Next, with reference to the timing chart of FIG. 17, an operation example at the time of reading the pixel signal of the unit pixel 100D will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 16 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 17 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.

  When the timing chart of FIG. 17 is compared with the timing chart of FIG. 11, only the operation timing of the power supply voltage FCVDD is different.

  Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t37, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to

  As described above, in the unit pixel 100D, similarly to the unit pixel 100C, the power supply voltage FCVDD is set to the voltage FCL during the period in which charges are accumulated in the charge accumulation unit 104 from the start of exposure to the start of reading. Set to As a result, the electric field applied to the charge storage unit 104 during the period in which charges are stored in the charge storage unit 104 is relaxed, and dark current generated in the charge storage unit 104 is suppressed.

  Note that in the timing charts of FIGS. 16 and 17, the operation timing of the drive signal RST can be made the same as in the examples of FIGS. 7 and 8 described above.

<6. Explanation regarding noise removal processing and arithmetic processing>
From the above-described unit pixels 100A to 100D, a vertical signal in the order of a high sensitivity reset signal NH2, a high sensitivity reset signal NH1, a high sensitivity data signal SH1, a high sensitivity data signal SH2, a low sensitivity data signal SL, and a low sensitivity reset signal NL. A signal is output to line 17. Then, in a subsequent signal processing unit, for example, the column processing unit 13 or the signal processing unit 18 shown in FIGS. 1 to 3, predetermined noise removal processing and signal processing are performed on these signals. Hereinafter, an example of noise removal processing in the column processing unit 13 in the subsequent stage and calculation processing in the signal processing unit 18 will be described.

{Noise removal processing}
First, noise removal processing by the column processing unit 13 will be described.

(Processing example 1 of noise removal processing)
First, processing example 1 of the noise removal processing will be described.

  For example, the column processing unit 13 generates the high sensitivity difference signal SNH1 by taking the difference between the high sensitivity data signal SH1 and the high sensitivity reset signal NH1. Therefore, the high sensitivity difference signal SNH1 = the high sensitivity data signal SH1−the high sensitivity reset signal NH1.

  Further, the column processing unit 13 generates the high sensitivity difference signal SNH2 by taking the difference between the high sensitivity data signal SH2 and the high sensitivity reset signal NH2. Therefore, the high sensitivity difference signal SNH2 = the high sensitivity data signal SH2-the high sensitivity reset signal NH2.

  Further, the column processing unit 13 generates the low sensitivity difference signal SNL by taking the difference between the low sensitivity data signal SL and the low sensitivity reset signal NL. Therefore, the low sensitivity difference signal SNL = the low sensitivity data signal SL−the low sensitivity reset signal NL.

  As described above, in the processing example 1, for low-sensitivity signals SL and NL, DDS processing that does not remove reset noise but removes fixed pattern noise peculiar to the pixel such as threshold variation of amplification transistors in the pixel. Done. For high-sensitivity signals SH1, SH2, NH1, and NH2, CDS processing is performed to remove pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.

  Further, since the processing example 1 is an arithmetic processing that does not require the use of a frame memory, there is an advantage that the circuit configuration can be simplified and the cost can be reduced.

(Noise removal processing example 2)
Next, processing example 2 of the noise removal process will be described.

  In the processing example 2, in order to use the information of the previous frame, a storage unit, for example, a frame memory is required. Accordingly, the arithmetic processing of the processing example 2 is performed, for example, by using the data storage unit 19 as a storage unit in the signal processing unit 18 or using a frame memory in an external DSP circuit.

  Specifically, the column processing unit 13 first generates a low sensitivity difference signal SNL by taking the difference between the low sensitivity data signal SL and the low sensitivity reset signal NLA in the previous frame. Therefore, the low sensitivity difference signal SNL = the low sensitivity data signal SL−the low sensitivity reset signal NLA.

  Next, the column processing unit 13 generates the high sensitivity difference signal SNH1 by taking the difference between the high sensitivity data signal SH1 and the high sensitivity reset signal NH1. Therefore, the high sensitivity difference signal SNH1 = the high sensitivity data signal SH1−the high sensitivity reset signal NH1.

  Further, the column processing unit 13 generates the high sensitivity difference signal SNH2 by taking the difference between the high sensitivity data signal SH2 and the high sensitivity reset signal NH2. Therefore, the high sensitivity difference signal SNH2 = the high sensitivity data signal SH2-the high sensitivity reset signal NH2.

  As described above, in the processing example 2, the CDS process for removing the fixed pattern noise unique to the pixel such as the reset noise and the threshold variation of the amplification transistor in the pixel is performed on the low-sensitivity signals SL and NL. Thereby, although a storage means such as a frame memory is required, there is an advantage that the reset noise can be significantly suppressed as compared with the processing example 1.

{Calculation of pixel signal}
Next, pixel signal calculation processing of the signal processing unit 18 in the first to third embodiments described above will be described.

(Processing Example 1 of Pixel Signal Calculation Processing)
First, processing example 1 of pixel signal calculation processing will be described.

  For example, when the high sensitivity difference signal SNH2 falls within a predetermined range, the signal processing unit 18 sets the ratio of the high sensitivity difference signal SNH2 to the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color, A gain table is generated by calculating as a gain for every specific pixel in the unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the high sensitivity difference signal SNH2 and the gain table as a correction value for the high sensitivity difference signal SNH2.

  Here, when the gain is G1 and the correction value of the high sensitivity difference signal SNH2 (hereinafter referred to as a correction high sensitivity difference signal) is SNH2 ′, the gain G and the correction high sensitivity difference signal SNH2 ′ are expressed by the following equation (1): It can be determined based on (2).

G1 = SNH1 / SNH2 = (Cfd1 + Cfd2) / Cfd1 (1)
SNH2 ′ = G1 × SNH2 (2)

  Here, Cfd1 is a capacitance value of the first FD unit 105a, and Cfd2 is a capacitance value of the second FD unit 105b. Therefore, the gain G1 is equivalent to the capacitance ratio of charge-voltage conversion when the high sensitivity data signal SH2 and the high sensitivity reset signal NH2 are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.

  Next, when the low sensitivity difference signal SNL falls within a predetermined range, the signal processing unit 18 shares the ratio of the low sensitivity difference signal SNL and the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color. A gain table is generated by calculating as a gain for each specific pixel in a pixel unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the low sensitivity difference signal SNL and the gain table as a correction value for the low sensitivity difference signal SNL.

  Here, when the gain is G2 and the correction value of the low sensitivity difference signal SNL (hereinafter referred to as a corrected low sensitivity difference signal) is SNL ′, the gain G and the corrected low sensitivity difference signal SNL ′ are expressed by the following equation (3): It can be determined based on (4).

G2 = SNH1 / SNL = (Cfd1 + Cfd2 + Cfc) / Cfd1
... (3)
SNL ′ = G2 × SNL (4)

  Here, Cfc is a capacitance value of the charge storage unit 104. Therefore, the gain G2 is equivalent to the capacitance ratio of charge-voltage conversion when the low sensitivity data signal SL and the low sensitivity reset signal NL are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.

  Next, the signal processing unit 18 uses predetermined threshold values Vt1 and Vt2 set in advance. The threshold value Vt1 is set in advance in a region where the high sensitivity difference signal SNH1 is saturated and the optical response characteristic is linear in the optical response characteristic. The threshold value Vt2 is set in advance in a region where the high sensitivity difference signal SNH2 is saturated and the light response characteristic is linear in the light response characteristic.

  Then, when the high sensitivity difference signal SNH1 does not exceed the predetermined threshold value Vt1, the signal processing unit 18 outputs the high sensitivity difference signal SNH1 as the pixel signal SN of the processing target pixel. That is, when SNH1 ≦ Vt1, the pixel signal SN = high sensitivity difference signal SNH1.

  On the other hand, when the high sensitivity difference signal SNH1 exceeds the predetermined threshold Vt1 and the high sensitivity difference signal SNH2 does not exceed the predetermined threshold Vt2, the signal processing unit 18 uses the corrected high sensitivity difference signal SNH2 ′ as the pixel signal of the processing target pixel. Output as SN. That is, when Vt1 <SNH1 and SNH2 ≦ Vt2, the pixel signal SN = the corrected high sensitivity difference signal SNH2 ′.

  Further, when the high sensitivity difference signal SNH2 exceeds the predetermined threshold value Vt2, the signal processing unit 18 outputs the corrected low sensitivity difference signal SNL ′ as the pixel signal SN of the processing target pixel. That is, when Vt2 <SNH2, the pixel signal SN = the corrected low sensitivity difference signal SNL ′.

  FIG. 18 is a graph showing how the pixel signal SN is switched when the high-sensitivity difference signal SNH2 is not used and when it is used. FIG. 18A is a graph when the high-sensitivity difference signal SNH2 is not used, and FIG. 18B is a graph when the high-sensitivity difference signal SNH2 is used.

  When the high sensitivity difference signal SNH2 is not used, when the high sensitivity difference signal SNH1 exceeds the threshold value Vt1, the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL '). However, since the value of the low-sensitivity differential signal SNL with respect to the light amount at the time of switching is small, the S / N ratio is greatly reduced and the image quality is deteriorated.

  On the other hand, when the high sensitivity difference signal SNH2 is used, when the high sensitivity difference signal SNH1 exceeds the threshold value Vt1, the pixel signal SN is switched to the high sensitivity difference signal SNH2 (more precisely, the corrected high sensitivity difference signal SNH2 ′). It is done. Here, the value of the high-sensitivity difference signal SNH2 with respect to the light amount at the time of switching is larger than the value of the low-sensitivity difference signal SNL with respect to the same light amount, so that the decrease in the SN ratio is suppressed and the image quality is kept good. Further, when the high sensitivity difference signal SNH2 exceeds the threshold value Vt2, the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL '). Here, the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching is larger than the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching when the high sensitivity difference signal SNH2 is not used, and the decrease in the SN ratio is suppressed. The image quality is kept good.

(Processing example 2 of pixel signal calculation processing)
Next, a processing example 2 of pixel signal calculation processing will be described.

  Specifically, the signal processing unit 18 combines the corrected high-sensitivity difference signal SNH2 ′ and the high-sensitivity difference signal SNH1 at a preset ratio within a predetermined range, and the pixel signal Output as SN. Further, the signal processing unit 18 synthesizes the corrected low-sensitivity difference signal SNL ′ and the corrected high-sensitivity difference signal SNH2 ′ at a preset ratio so that the pixel signal SN Output as.

  For example, the signal processing unit 18 performs the correction high-sensitivity difference step by step as in the following formulas (5) to (11) within the range before and after the high-sensitivity difference signal SNH1 with the threshold value Vt1 as a reference. The synthesis ratio of the signal SNH2 ′ and the high sensitivity difference signal SNH1 is changed. Further, for example, the signal processing unit 18 uses the threshold value Vt2 as a reference, and the corrected low-sensitivity difference step by step as in the following formulas (11) to (17) within the range before and after the high-sensitivity difference signal SNH2 The synthesis ratio of the signal SNL ′ and the corrected high sensitivity difference signal SNH2 ′ is changed.

When SNH1 <Vt1 × 0.90 SN = SNH1 (5)

When Vt1 × 0.90 ≦ SNH1 <Vt1 × 0.94 SN = 0.9 × SNH1 + 0.1 × SNH2 ′ (6)

When Vt1 × 0.94 ≦ SNH1 <Vt1 × 0.98 SN = 0.7 × SNH1 + 0.3 × SNH2 ′ (7)

When Vt1 × 0.98 ≦ SNH1 <Vt1 × 1.02 SN = 0.5 × SNH1 + 0.5 × SNH2 ′ (8)

When Vt1 × 1.02 ≦ SNH1 <Vt1 × 1.06 SN = 0.3 × SNH1 + 0.7 × SNH2 ′ (9)

When Vt × 1.06 ≦ SNH1 <Vt1 × 1.10. SN = 0.1 × SNH1 + 0.9 × SNH2 ′ (10)

When Vt1 × 1.10 ≦ SNH1 and SNH2 <Vt2 × 0.90 SN = SNH2 ′ (11)

When Vt2 × 0.90 ≦ SNH2 <Vt2 × 0.94 SN = 0.9 × SNH2 ′ + 0.1 × SNL ′ (12)

When Vt2 × 0.94 ≦ SNH2 <Vt2 × 0.98 SN = 0.7 × SNH2 ′ + 0.3 × SNL ′ (13)

When Vt2 × 0.98 ≦ SNH2 <Vt2 × 1.02 SN = 0.5 × SNH2 ′ + 0.5 × SNL ′ (14)

When Vt2 × 1.02 ≦ SNH2 <Vt2 × 1.06 SN = 0.3 × SNH2 ′ + 0.7 × SNL ′ (15)

When Vt2 × 1.06 ≦ SNH2 <Vt2 × 1.10. SN = 0.1 × SNH2 ′ + 0.9 × SNL ′ (16)

In the case of Vt2 × 1.10 ≦ SNH2, SN = SNL ′ (17)

  In Expressions (11) to (17), the weight for the high sensitivity difference signal SNH1 is set to 0, and in Expressions (5) and (17), the weight for the corrected high sensitivity difference signal SNH2 ′ is set to 0. In Equations (5) and (11), assuming that the weight for the corrected low sensitivity difference signal SNL ′ is set to 0, in each equation, the high sensitivity difference signal SNH1, the corrected high sensitivity difference signal SNH2 ′, In addition, it can be understood that the three signals of the corrected low sensitivity difference signal SNL ′ are synthesized at a set ratio and output as the pixel signal SN.

  By performing the arithmetic processing as described above, it is possible to smoothly switch from a signal at low illuminance to a signal at medium illuminance and from a signal at medium illuminance to a signal at high illuminance.

  In the CMOS image sensors 10, 10A, and 10B, the level at which the low-sensitivity data signal SL is saturated can be raised by providing the charge accumulation unit 104 for the low-sensitivity second photoelectric conversion unit 101b. As a result, the maximum value of the dynamic range can be increased while the minimum value of the dynamic range is maintained, and the dynamic range can be expanded.

  For example, in an in-vehicle image sensor, there may occur a phenomenon called LED flicker in which a blinking subject such as an LED light source cannot be imaged at the blinking timing. This LED flicker occurs, for example, because the dynamic range of a conventional image sensor is low and it is necessary to adjust the exposure time for each subject.

  That is, since the conventional image sensor is compatible with subjects with various illuminances, the exposure time is long for low-illuminance subjects and the exposure time is short for high-illuminance subjects. Thereby, it is possible to deal with subjects with various illuminances even in a low dynamic range. On the other hand, since the readout speed is constant regardless of the exposure time, when the exposure time is set in a unit shorter than the readout time, light incident on the photoelectric conversion unit other than the exposure time is photoelectrically converted into electric charges. , Discarded without being read.

  On the other hand, in the CMOS image sensors 10, 10A and 10B, the dynamic range can be expanded as described above, and the exposure time can be set long, so that the occurrence of LED flicker can be suppressed.

  Further, in the CMOS image sensors 10, 10A, and 10B, as described above, it is possible to prevent the occurrence of artifacts and the reduction in resolution that occur when the number of divisions is increased by the time division method or the space division method.

  Further, as described above, the signal is read twice from the high-sensitivity first photoelectric conversion unit 101a by switching the charge-voltage conversion capacitor, and by using two types of high-sensitivity signals, the SN at the time of signal switching is changed. A decrease in the ratio can be suppressed.

  In the above description, an example in which different threshold values are used for the high sensitivity difference signal SNH1 and the high sensitivity difference signal SNH2 is shown, but the same threshold value may be used. Further, for example, the signal may be switched by comparing the low sensitivity difference signal SNL with a threshold value.

<7. Modification>
In the above description, an example in which two photoelectric conversion units having different sensitivities are provided in one pixel is shown, but it is also possible to provide three or more photoelectric conversion units in one pixel. In this case, the charge storage unit may be provided in at least the photoelectric conversion unit having the lowest sensitivity without providing the charge storage unit in the photoelectric conversion unit having the highest sensitivity. Further, it is only necessary to read out a signal to at least the photoelectric conversion unit having the highest sensitivity by switching the charge-voltage conversion capacitor twice. Further, if this condition is satisfied, it is possible to provide two or more photoelectric conversion units having the same sensitivity.

  In addition, for example, signals may be read from the same photoelectric conversion unit using three or more different charge-voltage conversion capacitors.

  Further, in the timing charts of FIGS. 6, 8, 11, 14, and 17, the high-sensitivity reset signal NH2, the high-sensitivity reset signal NH1, the high-sensitivity data signal SH1, and the high-sensitivity data signal SH2 are read. The reading order of the low sensitivity data signal SL and the low sensitivity reset signal NL can be reversed.

  In the above embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels are arranged in a matrix has been described as an example. However, the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.

  Furthermore, the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid-state that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.

  Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

<8. Example of use of solid-state imaging device>
FIG. 19 is a diagram illustrating a usage example of the above-described solid-state imaging device.

  The solid-state imaging device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.

・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, etc. Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports, such as action cameras and wearable cameras for sports applications, etc. Equipment used for agriculture, such as cameras for monitoring the condition of fields and crops

{Imaging device}
FIG. 20 is a block diagram illustrating a configuration example of an imaging apparatus (camera apparatus) 400 that is an example of an electronic apparatus to which the present technology is applied.

  As illustrated in FIG. 20, the imaging apparatus 400 includes an optical system including a lens group 401, an imaging element 402, a DSP circuit 403 that is a camera signal processing unit, a frame memory 404, a display device 405, a recording device 406, and an operation system 407. And a power supply system 408 and the like. The DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, the operation system 407, and the power supply system 408 are connected to each other via a bus line 409.

  The lens group 401 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 402. The imaging element 402 converts the amount of incident light imaged on the imaging surface by the lens group 401 into an electrical signal in units of pixels and outputs it as a pixel signal.

  The display device 405 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 402. The recording device 406 records a moving image or a still image captured by the image sensor 402 on a recording medium such as a memory card, a video tape, or a DVD (Digital Versatile Disk).

  The operation system 407 issues operation commands for various functions of the imaging apparatus 400 under operation by the user. The power supply system 408 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, and the operation system 407 to these supply targets.

  Such an imaging apparatus 400 is applied to a camera module for a mobile device such as a video camera, a digital still camera, and a smartphone or a mobile phone. In the imaging apparatus 400, the solid-state imaging apparatus according to each of the above-described embodiments can be used as the imaging element 402. Thereby, the image quality of the imaging device 400 can be improved.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  For example, this technique can also take the following structures.

(1)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit. A second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device that controls to read data signals.
(2)
The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. The solid-state imaging device according to (1), wherein control is performed so as to read a second reset signal in a reset state.
(3)
The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. A data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out. The solid-state imaging device according to (2).
(4)
A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to (3), further including a signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal.
(5)
The signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal The solid-state imaging device according to (4), wherein when the value exceeds the second threshold, the third difference signal is used as a pixel signal of the unit pixel.
(6)
The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal, The solid-state imaging device according to (4), wherein a pixel signal of the unit pixel is generated by combining the second difference signal and the third difference signal.
(7)
The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, and then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion. The first data signal is read in the state transferred to, and then the second data signal is read in the state where the third transfer gate portion is turned on. (6) The solid-state imaging device according to any one of (6).
(8)
The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The solid-state imaging device according to (1) or (2), wherein control is performed so as to read out a data signal.
(9)
The unit pixel is
A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section;
An overflow path formed under the gate electrode of the fourth transfer gate portion and transferring the charge overflowing from the second photoelectric conversion portion to the charge storage portion; The solid-state imaging device according to any one of the above.
(10)
The solid-state imaging device according to any one of (1) to (8), wherein the second photoelectric conversion unit and the charge storage unit are connected without a transfer gate unit.
(11)
Connecting the counter electrode of the charge storage unit to a variable voltage power supply;
The drive unit lowers a voltage applied to the counter electrode of the charge storage unit in a period in which charges are stored in the charge storage unit, compared to a period in which a signal based on the charges stored in the charge storage unit is read. (1) The solid-state imaging device according to any one of (10).
(12)
The solid-state imaging device according to any one of (1) to (11), further including a reset gate unit connected between a power source having a predetermined voltage and the second charge-voltage conversion unit.
(13)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A solid-state imaging device comprising: a first transfer voltage unit that combines a potential of the first charge voltage conversion unit and a potential of the second charge voltage conversion unit.
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A method for driving the solid-state imaging device.
(14)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device to be controlled
An electronic device comprising: a signal processing device that processes a signal from the solid-state imaging device.

  10, 10A, 10B CMOS image sensor, 11 pixel array unit, 12 vertical drive unit, 13 column processing unit, 14 horizontal drive unit, 15 system control unit, 16 pixel drive line, 17 vertical signal line, 18 signal processing unit, 19 Data storage unit, 100A to 100D unit pixel, 101a first photoelectric conversion unit, 101b second photoelectric conversion unit, 102a to 102d first to fourth transfer gate unit, 103 reset gate unit, 104 charge storage unit, 105a first FD unit , 105b second FD section, 106 amplification transistor, 107 selection transistor, 400 imaging device, 402 imaging device, 403 DSP circuit

Claims (14)

A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit. A second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device that controls to read data signals. The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. The solid-state imaging device according to claim 1, wherein control is performed so that a second reset signal in a reset state is read out. The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. A data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out. The solid-state imaging device according to claim 2 to be controlled. A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to claim 3, further comprising a signal processing unit that generates a third difference signal that is a difference between the third data signal and the third reset signal. The signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal The solid-state imaging device according to claim 4, wherein when the value exceeds the second threshold, the third difference signal is used as a pixel signal of the unit pixel. The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal, The solid-state imaging device according to claim 4, wherein a pixel signal of the unit pixel is generated by combining the second difference signal and the third difference signal. The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, and then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion. 3. The control is performed so that the first data signal is read in a state where the second data signal is transferred, and then the second data signal is read in a state where the third transfer gate unit is in a conductive state. Solid-state imaging device. The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is controlled to read a data signal. The unit pixel is
A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section;
2. The solid-state imaging device according to claim 1, further comprising: an overflow path formed below the gate electrode of the fourth transfer gate unit and transferring the charge overflowing from the second photoelectric conversion unit to the charge storage unit. . The solid-state imaging device according to claim 1, wherein the second photoelectric conversion unit and the charge storage unit are connected without a transfer gate unit. Connecting the counter electrode of the charge storage unit to a variable voltage power supply;
The drive unit lowers a voltage applied to the counter electrode of the charge storage unit in a period in which charges are stored in the charge storage unit, compared to a period in which a signal based on the charges stored in the charge storage unit is read. Item 2. The solid-state imaging device according to Item 1. The solid-state imaging device according to claim 1, further comprising a reset gate unit connected between a power source having a predetermined voltage and the second charge voltage conversion unit. A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A solid-state imaging device comprising: a first transfer voltage unit that combines a potential of the first charge voltage conversion unit and a potential of the second charge voltage conversion unit.
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A method for driving the solid-state imaging device. A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device to be controlled
An electronic device comprising: a signal processing device that processes a signal from the solid-state imaging device.

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