WO2020080013A1 - Imaging device, method of controlling imaging device, and electronic apparatus - Google Patents

Abstract

An imaging device provided with: a conversion unit (130b) which performs conversion of an analog signal read from each of pixels (110) included in a pixel array (11) in a two-dimensional lattice arrangement into a digital signal; and a control unit (19) which controls the operation of the conversion unit. The control unit causes the state of the conversion unit to transition to a standby state in which no conversion is performed, in at least one of: a horizontal blanking period based on a horizontal synchronization signal indicating the timing of reading a line of the arrangement; and a vertical blanking period based on a trigger signal indicating the timing of starting pixel reading for one frame from the pixel array.

Description

IMAGING DEVICE, IMAGING DEVICE CONTROL METHOD, AND ELECTRONIC DEVICE

The present invention relates to an imaging device, a method for controlling the imaging device, and an electronic device.

Solid-state imaging devices using CMOS (Complementary Metal Oxide Semiconductor) etc. are known. In such a solid-state imaging device, pixels including light receiving elements are arranged in an array, and reading from the pixels arranged in the array is controlled for each row, and a signal from the pixel is output for each column. Then, an AD (Analog to Digital) converter provided for each column converts the signal read from the pixel into a pixel signal by a digital signal and outputs it.

JP, 2010-213011, A

▼ While the number of pixels in solid-state imaging devices tends to increase, there is a demand for reduced power consumption.

The present disclosure aims to provide an imaging device, a method of controlling the imaging device, and an electronic device capable of reducing power consumption.

In order to achieve the above object, an imaging apparatus according to the present disclosure includes a conversion unit that converts an analog signal read from each pixel included in a two-dimensional lattice array in a pixel array into a digital signal, and a conversion unit. And a control unit for controlling the operation of the., The control unit sets a horizontal blanking period based on a horizontal synchronization signal indicating a read timing of lines in the array, and a timing for starting reading of pixels for one frame from the pixel array. During at least one of the vertical blanking period based on the trigger signal shown, the state of the conversion unit is shifted to the standby state in which no conversion is performed.

It is a block diagram which shows the basic structural example of the solid-state image sensor applicable to embodiment. It is a figure which shows the structure of an example of the pixel applicable to each embodiment. 7 is a time chart showing an example of an operation in a pixel, which is applicable to the embodiment. It is a figure which shows the example of a structure of the AD converter by existing technology. It is a figure which shows roughly the structure of an example of the solid-state image sensor by existing technology. 7 is a time chart showing an example of a pixel signal read process from each pixel according to a vertical synchronization signal and a horizontal synchronization signal according to an existing technique. It is a figure which shows roughly the structure of an example of the solid-state image sensor by existing technology. 7 is a time chart showing an example of a process of reading a pixel signal from each pixel by external trigger control according to an existing technique. It is a block diagram which shows roughly the structural example of the solid-state image sensor as an imaging device which concerns on 1st Embodiment. 6 is a time chart showing an example of a process of reading a pixel signal from each pixel according to a vertical synchronization signal and a horizontal synchronization signal according to the first embodiment. It is a block diagram which shows roughly the structure of an example of the solid-state image sensor which inputs the external trigger signal based on 1st Embodiment. 6 is a time chart showing an example of a process of reading a pixel signal from each pixel according to an external trigger signal and a horizontal synchronization signal according to the first embodiment. It is a figure which shows the structure of an example of the AD converter which concerns on 1st Embodiment. FIG. 3 is a block diagram showing a configuration of an example of a control unit applicable to the first embodiment. 6 is a time chart of an example for explaining an ADC stop control signal according to the first embodiment. 6 is a time chart showing an example of control in a vertical blanking period in a process of reading a pixel signal from each pixel according to a vertical synchronization signal and a horizontal synchronization signal according to the first embodiment. 6 is a time chart showing an example of control in a vertical blanking period in a process of reading a pixel signal from each pixel by external trigger control according to the first embodiment. It is a block diagram which shows roughly the structural example of the solid-state image sensor which concerns on 2nd Embodiment. 9 is a time chart showing an example of a process of reading a pixel signal from each pixel according to a vertical synchronization signal and a horizontal synchronization signal according to the second embodiment. It is a block diagram which shows roughly the structural example of the solid-state image sensor which concerns on 3rd Embodiment. 9 is a time chart showing an example of a process of reading pixel signals from each pixel according to two external trigger signals and a horizontal synchronization signal according to the third embodiment. It is a block diagram which shows the structure of an example of the electronic device which concerns on 4th Embodiment. It is a figure which shows the usage example of the imaging device which concerns on this indication.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same parts will be denoted by the same reference numerals, and redundant description will be omitted.

[Embodiment]
(Example of configuration applicable to each embodiment)
FIG. 1 is a block diagram showing a basic configuration example of a solid-state image sensor applicable to the embodiment. In FIG. 1, the solid-state imaging device 10 includes a pixel array unit 11, a vertical scanning unit 12, an AD (Analog to Digital) conversion unit 13, a pixel signal line 16, a vertical signal line 17, and a control unit 19. The signal processing unit 20 is included.

The pixel array unit 11 includes a plurality of pixels 110 each having a photoelectric conversion unit such as a photodiode, which performs photoelectric conversion on received light. In the pixel array unit 11, the plurality of pixels 110 are arranged in a two-dimensional grid pattern in the horizontal direction (row direction) and the vertical direction (column direction). In the pixel array unit 11, the arrangement of the pixels 110 in the row direction is called a line. An image (image data) of one frame is formed by the pixel signals read from a predetermined number of lines in the pixel array unit 11. For example, when an image of one frame is formed with 3000 pixels × 2000 lines, the pixel array unit 11 includes at least 2000 lines including at least 3000 pixels 110.

Further, in the pixel array section 11, for each row and column of each pixel 110, the pixel signal line 16 is connected for each row, and the vertical signal line 17 is connected for each column.

The end of the pixel signal line 16 that is not connected to the pixel array section 11 is connected to the vertical scanning section 12. The vertical scanning unit 12 transmits a control signal such as a drive pulse for reading a pixel signal from a pixel to the pixel array unit 11 via the pixel signal line 16 under the control of the control unit 19 described later. An end portion of the vertical signal line 17 that is not connected to the pixel array unit 11 is connected to the AD conversion unit 13. The pixel signal read from the pixel is transmitted to the AD conversion unit 13 via the vertical signal line 17.

The AD conversion unit 13 includes an AD converter 130 provided for each vertical signal line 17, a reference signal generation unit 14, and a horizontal scanning unit 15. The AD converter 130 is a column AD converter that performs AD conversion processing on each column of the pixel array unit 11. The AD converter 130 performs AD conversion processing on the pixel signal supplied from the pixel 110 via the vertical signal line 17 and performs 2 for correlation double sampling (CDS: Correlated Double Sampling) processing for noise reduction. Generate two digital values. A specific example of the configuration and processing of the AD converter 130 will be described later.

The AD converter 130 supplies the two generated digital values to the signal processing unit 20. The signal processing unit 20 performs CDS processing based on the two digital values supplied from the AD converter 130, and generates a pixel signal (pixel data) by a digital signal. The pixel signal based on the digital signal generated by the signal processing unit 20 is output to the outside of the solid-state image sensor 10.

The pixel signal based on the digital signal output from the signal processing unit 20 is sequentially stored outside the solid-state image sensor 10, for example, in a frame buffer. When pixel signals for one frame are stored in the frame buffer, the stored pixel signals are read out from the frame buffer as image data for one frame.

The reference signal generation unit 14 generates a ramp signal RAMP used by each AD converter 130 to convert a pixel signal into two digital values, based on the ADC control signal input from the control unit 19. The ramp signal RAMP is a signal whose level (voltage value) decreases with a constant slope with respect to time, or a signal whose level decreases stepwise. The reference signal generation unit 14 supplies the generated ramp signal RAMP to each AD converter 130. The reference signal generation unit 14 is configured using, for example, a DA (Digital to Analog) conversion circuit or the like.

Under the control of the control unit 19, the horizontal scanning unit 15 performs a selective scan for selecting the AD converters 130 in a predetermined order, so that the digital values temporarily held by the AD converters 130 are detected. The signals are sequentially output to the signal processing unit 20. The horizontal scanning unit 15 is configured by using, for example, a shift register or an address decoder.

The control unit 19 controls the drive of the vertical scanning unit 12, the AD converting unit 13, the reference signal generating unit 14, the horizontal scanning unit 15, and the like. The control unit 19 generates various drive signals serving as a reference for the operations of the vertical scanning unit 12, the AD converting unit 13, the reference signal generating unit 14, and the horizontal scanning unit 15. The control unit 19 is, for example, a control signal for the vertical scanning unit 12 to supply each pixel 110 via the pixel signal line 16 based on a vertical synchronization signal or an external trigger signal supplied from the outside and a horizontal synchronization signal. To generate. The control unit 19 supplies the generated control signal to the vertical scanning unit 12.

The vertical scanning unit 12 supplies various signals including a drive pulse to the pixel signal line 16 of the selected pixel row of the pixel array unit 11 based on the control signal supplied from the control unit 19 to each pixel 110 line by line. Then, the pixel signal is output from each pixel 110 to the vertical signal line 17. The vertical scanning unit 12 is configured using, for example, a shift register or an address decoder.

The solid-state imaging device 10 thus configured is a column AD type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which the AD converters 130 are arranged in each column.

FIG. 2 is a diagram showing a configuration of an example of a pixel 110 applicable to each embodiment. In FIG. 2, the pixel 110 includes a photoelectric conversion element 111 formed of, for example, a PN junction photodiode, a trigger transistor 112, a reset transistor 114, an amplification transistor 115, and a selection transistor 116 which are N-type MOS (Metal Oxide Semiconductor) transistors, respectively. ,including. The pixel signal line 16 connected to the pixel 110 supplies a reset pulse RST, a transfer pulse TRG, and a selection signal SEL, respectively.

In the pixel 110, the photoelectric conversion element 111 has a cathode connected to the ground and an anode connected to the drain of the trigger transistor 112. The source of the trigger transistor 112 is connected to the floating diffusion layer 113. The transfer pulse TRG is supplied to the gate of the trigger transistor 112. The trigger transistor 112 is turned on (closed) when the transfer pulse TRG is in the high (High) state, and turned off (open) when the transfer pulse TRG is in the low (Low) state. With the trigger transistor 112 turned on, the electric charge output from the photoelectric conversion element 111 is supplied to the floating diffusion layer 113.

The floating diffusion layer 113 stores the electric charge supplied from the photoelectric conversion element 111. The floating diffusion layer 113 generates a voltage according to the amount of accumulated charge.

The source of the reset transistor 114 is connected to the floating diffusion layer 113. The power supply VDD for the pixel 110 is connected to the drain of the reset transistor 114. The reset pulse RST is supplied to the gate of the reset transistor 114. The reset transistor 114 is turned on when the reset pulse RST is high and turned off when the reset pulse RST is low.

The gate of the amplification transistor 115 is connected to the floating diffusion layer 113. The power supply VDD is connected to the drain of the amplification transistor 115, and the drain of the selection transistor 116 is connected to the source. The source of the selection transistor 116 is connected to the vertical signal line (VSL) 17. The selection signal SEL is supplied to the gate of the selection transistor 116. The selection transistor 116 is turned on when the selection signal SEL is high and turned off when the selection signal SEL is low.

FIG. 3 is a time chart showing an example of an operation in the pixel 110 shown in FIG. 2, which is applicable to the embodiment. In FIG. 3, “SEL”, “RST”, and “TRG” indicate the selection signal SEL, the reset pulse RST, and the transfer pulse TRG, respectively. Further, “FD” indicates the amount of charges accumulated in the floating diffusion layer 113, and “VSL” indicates the level (voltage) of the pixel signal output from the vertical signal line 17.

In the time chart of FIG. 3, in the initial state, the selection signal SEL, the reset pulse RST, and the transfer pulse TRG are in a low state. Further, since the photoelectric conversion element 111 is exposed and the trigger transistor 112 is turned off by the low-state transfer pulse TRG, the electric charge generated by the exposure is accumulated in the photoelectric conversion element 111.

At time t ₁₀₀ , the selection signal SEL is set to the high state and the selection transistor 116 is turned on. At time t ₁₀₁ , the reset pulse RST is set to the high state, and the charge of the floating diffusion layer 113 is discharged to the power supply VDD, so that the potential of the floating diffusion layer 113 is reset to the predetermined potential. A reset pulse RST is returned to a low state at time t ₁₀₂ after a predetermined time, the transfer pulse TRG is a high state, the charge accumulated in the photoelectric conversion element 111 by the exposure is supplied to the floating diffusion layer 113 is accumulated It A voltage corresponding to the charges accumulated in the floating diffusion layer 113 is generated, this voltage is amplified by the amplification transistor 115, and is output to the vertical signal line 17 as a pixel signal via the selection transistor 116.

Here, the reset level (black level) output to the vertical signal line 17 at a time t ₁₁₀ when the state of the floating diffusion layer 113 stabilizes after a predetermined time from the time t ₁₀₁ when the reset pulse RST is set to the high state. The signal A is converted into a digital value by the AD converter 130, and is temporarily stored in, for example, a register included in the AD converter 130. This signal A is offset noise. The reading of the signal A is called P-phase (Pre-Charge) reading, and the period in which the P-phase reading is performed is called the P-phase period.

Furthermore, the transfer pulse TRG from time t _102, which is a high state after treatment time, for example, for example, the state of the floating diffusion layer 113 is the signal level of the signal B output to the vertical signal line 17 at the time t ₁₁₁ to stabilize, It is converted into a digital value by the AD converter 130 and is temporarily stored in, for example, a register or the like included in the AD converter 130. The signal B is a signal including offset noise and a pixel signal. The reading of the signal B is called D-phase (Data Phase) reading, and the period in which the D-phase reading is performed is called the D-phase period.

The AD converter 130 supplies the stored signals A and B to the signal processing unit 20. The signal processing unit 20 obtains the difference between the signal A and the signal B. This makes it possible to obtain a pixel signal from which offset noise has been removed.

(AD conversion processing of pixel signals by existing technology)
Prior to description of the operation of the AD converter 130a according to the embodiment, in order to facilitate understanding, an AD conversion process by the existing technology by the column AD converter will be described. FIG. 4 is a diagram showing an example of the configuration of an AD converter 130a according to the existing technology as the column AD converter in FIG. In FIG. 4, the AD converter 130a includes a current source 131, a DA (Digital to Analog) converter 132, a comparator 133, and a counter 134. The DA converter 132, the comparator 133, and the counter 134 each operate by the power supplied from the power supply line Vp.

The pixel signal (signal A or signal B) read from the pixel 110 is drawn into the current source 131 from the vertical signal line 17, supplied to the AD converter 130 a, and input to one input terminal of the comparator 133. . More specifically, in the P-phase period, the reset level signal A read from the pixel 110 is input to one input terminal of the comparator 133. Further, in the D-phase period, the signal B including the offset noise and the pixel signal read from the pixel 110 is input to one input end of the comparator 133.

The ramp signal RAMP, which is a reference signal generated as a digital signal in the reference signal generation unit 14, is input to the DA converter 132. The DA converter 132 converts the ramp signal RAMP into an analog signal and inputs it to the other input end of the comparator 133 as a reference signal.

For example, the reference signal generation unit 14 generates, as the ramp signal RAMP, the above-described digital signal whose value decreases stepwise with time (clock). The DA converter 132 converts the ramp signal RAMP into an analog signal and inputs the analog signal into the other input terminal of the comparator 133. That is, to the other input terminal of the comparator 133, a signal whose voltage value changes stepwise (falls) in response to the clock is input as a reference signal.

The comparator 133 holds the pixel signal input to one input end, and compares the level of the held pixel signal with the level of the ramp signal RAMP input to the other input end. The comparator 133 outputs the difference signal in the high state when the level of the ramp signal RAMP is higher than the level of the held pixel signal. On the other hand, when the level of the ramp signal RAMP becomes equal to or lower than the level of the held pixel signal, the comparator 133 inverts the output and outputs the difference signal in the low state. The difference signal output from the comparator 133 is supplied to the counter 134. The level of the ramp signal RAMP is reset to a predetermined value after the output of the comparator 133 is inverted.

The counter 134 counts based on the difference signal output from the comparator 133, for example, according to a clock common to the reference signal generation unit 14. More specifically, in the P-phase period of the pixel 110, the counter 134 responds to the difference signal input from the comparator 133, and the level of the ramp signal RAMP starts to drop, and then the pixel signal (signal A). The time (clock) until reaching the following level is down-counted, and the count value (digital value) by this count is output to the signal processing unit 20. In addition, in the D-phase period of the pixel 110, the counter 134 changes the level of the ramp signal RAMP to a level equal to or lower than the pixel signal (signal B) after the voltage drop starts according to the difference signal input from the comparator 133. The time until is counted up, and the count value (digital value) by this count is output to the signal processing unit 20.

The signal processing unit 20 performs CDS processing using the count value for the signal A and the count value for the signal B.

A process of reading a pixel signal from each pixel 110 according to a vertical synchronization signal according to the existing technology will be described with reference to FIGS. 5 and 6. FIG. 5 is a diagram schematically showing an example of the configuration of an existing solid-state imaging device corresponding to FIG. 1, and shows how a vertical synchronizing signal is input to the control unit 19. The control unit 19 generates a reset pulse RST, a transfer pulse TRG, and a selection signal SEL that are supplied to each pixel 110 via the pixel signal line 16 based on the vertical synchronization signal and the horizontal synchronization signal.

Here, the horizontal synchronization signal is a signal indicating the read timing for each line. The vertical synchronization signal is a signal indicating the cycle of one frame. For example, by starting reading lines from the beginning of the pixel array unit 11 according to the vertical synchronizing signal and sequentially reading each line according to the horizontal synchronizing signal, the pixel signals of the pixels 110 included in the pixel array unit 11 are converted into pixel signals. Based on this, image data for one frame can be obtained. By repeatedly performing this operation according to the vertical synchronization signal, for example, moving image data of a predetermined frame period can be obtained.

Further, the control unit 19 generates an ADC control signal for controlling the generation of the ramp signal RAMP in the reference signal generation unit 14 in synchronization with the horizontal synchronization signal, for example. The reference signal generator 14 generates and outputs the ramp signal RAMP according to the ADC control signal. Each AD converter 130a AD-converts the pixel signal supplied from each pixel 110 based on the ramp signal RAMP output from the reference signal generation unit 14 according to the ADC control signal.

FIG. 6 is a time chart showing an example of a process of reading a pixel signal from each pixel 110 according to a vertical synchronizing signal and a horizontal synchronizing signal according to the existing technology. In FIG. 6, a chart showing timings of a vertical synchronizing signal, a horizontal synchronizing signal, a reading process, and an ADC (AD Converter) operation is shown from the top.

In the example of FIG. 6, the vertical synchronizing signal and the horizontal synchronizing signal are represented as downward pulses formed from pairs of falling edges and rising edges, respectively. This is not limited to this example, and the direction of the edge forming the pulse may be opposite (upward pulse), or the pulse direction may be different between the vertical synchronizing signal and the horizontal synchronizing signal.

The vertical synchronizing signal is one vertical period (1V period) from the falling edge of one pulse to the falling edge of the next pulse, and one frame is read within this 1V period. The horizontal synchronizing signal is one horizontal period (1H period) from the falling edge of one pulse to the falling edge of the next pulse, and one line is read during this 1H period.

In the example of FIG. 6, reading of one frame is started at the timing of the falling edge of the vertical sync signal. The period READ during which this one frame is read is referred to as a read period 30. A period VBLANK from the end timing of the read period 30 to the next falling edge of the vertical synchronizing signal is a vertical blanking period 31 in which no line is read. The leading timing of the vertical blanking period 31 can be known based on the timing of the falling edge of the vertical synchronizing signal.

At the timing of the falling edge of the horizontal synchronization signal, the reading of the pixel signal from each pixel 110 on one line is started, and the AD conversion operation by the AD converter 130a is executed on the pixel signal of each pixel 110 on the read line. . A reset pulse RST, a transfer pulse TRG, and a selection signal SEL are supplied in parallel by the pixel signal line 16 to each pixel 110 included in one line. Therefore, the AD conversion processing by each AD converter 130a connected to each vertical signal line 17 is executed so as to be completed during the period of one line, that is, from the pulse of the horizontal synchronizing signal to the next pulse.

More specifically, as shown as the ADC operation in FIG. 6, during the period 40 in the 1H period, the pixel signals (the signal A in the P-phase period and the signal B in the D-phase period) by each AD converter 130a are output. AD conversion processing is performed (shown as "AD" in FIG. 6). In the 1H period, a period 41 from the end of the AD conversion processing in the period 40 to the start of the next 1H period is called a horizontal blanking period (shown as “HBLK” in FIG. 6). The control unit 19 terminates the end of the period 40, for example, in all the AD converters 130a included in the AD conversion unit 13, the conversion process in the D phase period of the pixel 110 is completed, the output of the comparator 133 is inverted, and the ramp signal is output. This can be known as the timing at which the RAMP level is reset to a predetermined level.

Hereinafter, unless otherwise specified, the period 40 in which the AD converter 130a performs the AD conversion process is referred to as an AD conversion period 40, and the period 41 is referred to as a horizontal blanking period 41.

Note that, during the 1H period, when the AD conversion process of the Mth line is performed by each AD converter 130a, the AD conversion process of the M + 1th line is performed by each AD converter 130a during the next 1H period. In the 1V period, for example, a period in which the AD conversion process of the Mth line is not performed (a period other than the AD conversion period 40) is a period in which each pixel 110 of the Mth line can be exposed. Further, when the last line of one frame is the Nth line, the period from the 1H period shown as the (N + 1) th line in FIG. 6 to the pulse of the next vertical synchronizing signal is the vertical blanking period 31.

A process of reading a pixel signal from each pixel 110 according to an external trigger signal according to the existing technology will be described with reference to FIGS. 7 and 8. For example, when the electronic device on which the solid-state imaging device 10 is mounted is a camera, a signal based on shutter timing and shutter speed can be applied as the external trigger signal.

FIG. 7 is a diagram schematically showing an example of the configuration of a solid-state image sensor according to the existing technology, which corresponds to FIG. 1, and shows how an external trigger signal is input to the control unit 19. As described above, the external trigger signal is input to the control unit 19 instead of the vertical synchronization signal of FIG. The control unit 19 generates a reset pulse RST, a transfer pulse TRG, and a selection signal SEL that are supplied to each pixel 110 via the pixel signal line 16 based on the external trigger signal and the horizontal synchronization signal.

FIG. 8 is a time chart showing an example of reading processing of pixel signals from each pixel 110 by external trigger control according to the existing technology. In FIG. 8, a chart showing timings of the external trigger signal, the horizontal synchronizing signal, the reading process, and the ADC operation is shown from the top.

In the example of FIG. 8, the falling edge of the external trigger signal indicates the exposure start timing, and the rising edge indicates the exposure end timing. Further, the reading of one frame in the pixel array unit 11 is started in response to the rising edge of the external trigger signal. The control unit 19 controls the reading for each line in synchronization with the horizontal synchronizing signal based on the rising edge of the external trigger signal. The operation of each AD converter 130a in each 1H period is the same as the example in which the 1V period is started in response to the vertical synchronization signal described with reference to FIG. 6, and thus the description thereof is omitted here.

According to the existing technology, in the horizontal blanking period 41 after the AD conversion period 40 in the 1H period shown in FIGS. 6 and 8, each AD converter 130a performs the AD conversion process by the next falling edge of the horizontal synchronizing signal. It is a waiting period to wait for the start. Power is consumed in each AD converter 130a even during the standby period within this 1H period. Further, the vertical blanking period 31 in the 1V period is also a standby period in which the AD converters 130a do not perform AD conversion processing. Even during the standby time within this 1V period, power is similarly consumed in each AD converter 130a.

Further, by supplying power to each AD converter 130a during the standby period (horizontal blanking period 41 and vertical blanking period 31) of the 1H period and the 1V period, each AD converter 130a is in the operating state. As described above, by operating each AD converter 130a during the standby period, electric charge such as hot carriers may be generated from the circuit forming the AD converter 130a. This charge may become a noise source and may be a factor of deteriorating the image quality of the image by the pixel signal read from each pixel 110.

[First Embodiment]
Next, the operation of the AD converter 130 according to the first embodiment of the present disclosure will be described. In the first embodiment, during the above-described vertical blanking period 31 and horizontal blanking period 41, standby control is performed on the AD converter 130, and the AD converter 130 is controlled to the standby state. The standby state is a standby state for AD conversion processing, the AD conversion operation in the AD converter 130 is stopped, and power consumption can be suppressed. As a result, the power consumption of the AD conversion unit 13 can be reduced.

A process of reading a pixel signal from each pixel 110 according to the vertical synchronization signal according to the first embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram schematically showing a configuration example of a solid-state image pickup element as the image pickup apparatus according to the first embodiment. The solid-state image sensor 10a shown in FIG. 9 has the ADC stop control signal supplied from the controller 19 to the AD converter 13 added to the solid-state image sensor 10 described with reference to FIG. The ADC stop control signal is a signal for executing standby control for each AD converter 130 included in the AD conversion unit 13.

Note that, in FIG. 9, the configuration of the pixel array unit 11 is common to that of FIG.

FIG. 10 is a time chart showing an example of a process of reading a pixel signal from each pixel 110 according to a vertical synchronization signal and a horizontal synchronization signal according to the first embodiment. In FIG. 10, as in the case of FIG. 6 described above, a chart showing the vertical synchronizing signal, the horizontal synchronizing signal, the reading process, and the ADC operation is shown from the top. Further, in the lower part of FIG. 10, a chart showing details of the ADC operation in the 1H period is shown. In the example of FIG. 10, for the sake of explanation, in the chart showing the timing of the horizontal synchronizing signal, the horizontal synchronizing signal is represented as an upward pulse formed from a pair of a rising edge and a falling edge.

The timing of each pulse of the vertical synchronizing signal and the horizontal synchronizing signal, and the timing of the reading period 30 and the vertical blanking period 31 in the 1V period are the same as the timings described with reference to FIG. 6, and thus the description thereof is omitted here. To do.

In the first embodiment, as shown in the ADC operation chart of FIG. 10, in the 1H period, the horizontal blanking period 41 (see FIG. 6) after the AD conversion period 40 is restored after the circuit stop period 41a and the circuit blanking period 41a. It is divided into a period 41b. The circuit suspension period 41a is a period in which standby control is performed on each AD converter 130 included in the AD conversion unit 13a to set the operation state of the AD converter 130 to the standby state and stop the operation of each AD converter 130. . The return period 41b is a period from the release of the standby state of the AD converter 130 to the normal operation of the AD converter 130.

As shown in the lower part of FIG. 10, the AD conversion period 40 starts at the timing of the falling edge of the pulse 42 in the horizontal synchronization signal, and after the AD conversion period 40 ends, the control unit 19 controls the AD converters 130. An ADC stop control signal for instructing execution of standby control is generated and supplied to the AD conversion unit 13a. As a result, during the circuit stop period 41a, the operation state of the AD converter 130 becomes the standby state, and the operation of the AD converter 130 is stopped.

After that, the control unit 19 generates an ADC stop control signal for instructing the start of power supply to each AD converter 130 at the timing of the rising edge of the pulse 42, and supplies it to the AD conversion unit 13a. As a result, the standby state of the AD converter 130 is released, and the operation of the AD converter 130 shifts to the operation of the restoration period 41b. The AD converter 130 shifts from the restoration operation to the AD conversion operation, assuming that the restoration period 41b ends at the next falling edge of the pulse 42.

The transition timing from the circuit stop period 41a to the return period 41b and the length of the return period 41b are determined by the width H _{p_time} of the pulse 42. The width H _{p_time of the} pulse 42 is defined as the specification of the horizontal synchronizing signal according to the characteristics of the AD converter 130, and is set to the control unit 19 by the user, for example.

In the first embodiment, the control unit 19 further supplies an ADC stop control signal to the AD conversion unit 13a in the vertical blanking period 31 to set the operation state of the AD converter 130 to the standby state, and the AD conversion unit 130 is operated. The AD conversion operation is stopped. Also in this case, the control unit 19 supplies the ADC stop control signal to the AD conversion unit 13a at the timing of the falling edge of the horizontal synchronizing signal corresponding to the start timing of the vertical blanking period 31. The control unit 19 generates an ADC stop control signal for instructing each AD converter 130 to cancel the standby state at the timing of the rising edge of the vertical synchronization signal, and supplies the ADC stop control signal to the AD conversion unit 13a. The period VC _stop corresponding to the vertical blanking period 31 is a period during which the power supply to each AD converter 130 is stopped in units of 1V period.

A certain amount of time is required from the timing of the rising edge of the vertical synchronizing signal until the AD conversion operation is started in each AD converter 130. The return operation of each AD converter 130 after the vertical blanking period 31 can be completed between the timing of the rising edge of the vertical synchronizing signal and the start of the AD conversion operation.

Note that in the vertical blanking period 31, the operation of the AD converter 130 is stopped from the beginning of the period. Therefore, the return period 41b in the 1H period immediately before the vertical blanking period 31 can be omitted.

A process of reading a pixel signal from each pixel 110 according to an external trigger signal according to the first embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 is a block diagram schematically showing the configuration of an example of a solid-state image sensor to which an external trigger signal is input according to the first embodiment. 11 is a diagram corresponding to FIG. 7 described above. An external trigger signal is input to the control unit 19 and an ADC stop control signal is supplied from the control unit 19 to the AD conversion unit 13a. It

Note that, in FIG. 11, the configuration of the pixel array unit 11 is common to that in FIG. 1 described above, and therefore description thereof is omitted here.

FIG. 12 is a time chart showing an example of a process of reading a pixel signal from each pixel 110 according to an external trigger signal and a horizontal synchronization signal according to the first embodiment. 12, like FIG. 8 described above, a chart showing an external trigger signal, a horizontal synchronization signal, a read process, and an ADC operation is shown from the top, and the lower part shows the ADC in the 1H period as in FIG. A chart showing details of the operation is shown. Note that, similarly to FIG. 10 described above, in the example of FIG. 12 as well, for the sake of explanation, in the chart showing the timing of the horizontal synchronizing signal, the horizontal synchronizing signal is formed of a pair of a rising edge and a falling edge. It is represented as a pulse.

In the example of FIG. 12, similarly to the example of FIG. 8 described above, the exposure starts at the timing of the falling edge of the external trigger signal, and the exposure ends at the timing of the rising edge of the external trigger signal. The control unit 19 controls the reading for each line in synchronization with the horizontal synchronizing signal based on the rising edge of the external trigger signal. The timing of the rising edge of the external trigger signal is the start timing of the 1V period, and the reading of one frame is started. The operation of each AD converter 130 in the 1V period and the 1H period is the same as the example in which the 1V period is started in response to the vertical synchronization signal described with reference to FIG.

That is, the 1H period is divided into an AD conversion period 40, a circuit suspension period 41a, and a restoration period 41b. The control unit 19 supplies an ADC stop control signal for performing standby control to each AD converter 130 at the end of the AD conversion period 40 to the AD conversion unit 13a, and the operation state of each AD converter 130 during the circuit stop period 41a. Is set to a standby state, and the AD conversion operation of each AD converter 130 is stopped. The control unit 19 supplies an ADC stop control signal for canceling the standby state of each AD converter 130 to the AD conversion unit 13a at the next rising edge of the horizontal synchronization signal. As a result, each of the AD converters 130 included in the AD conversion unit 13a is released from the standby state and the operation shifts to the return operation.

The control unit 19 further performs the standby control in the vertical blanking period 31 and stops the operation of each AD converter 130, as in the example of FIG. 10. Then, the control unit 19 supplies the ADC stop control signal for canceling the standby state of each AD converter 130 to the AD conversion unit 13a at the timing of the next rising edge of the vertical synchronization signal, for example. The operation of 130 is transferred to the return operation.

Note that, also in the example of FIG. 12, in the vertical blanking period 31, the operation of the AD converter 130 is stopped from the beginning of the period. Therefore, the return period 41b in the 1H period immediately before the vertical blanking period 31 can be omitted.

(Specific example of the configuration according to the first embodiment)
Next, a more specific configuration example according to the first embodiment will be described. In the first embodiment, as an example of standby control, control for stopping the power supply to the AD converter 130 is performed. FIG. 13 is a diagram showing a configuration of an example of the AD converter 130b according to the first embodiment. The AD converter 130b shown in FIG. 13 can be applied as the AD converter 130 of FIG. Note that, in FIG. 13, portions common to those in FIG. 4 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

13, the AD converter 130b has switches 1300a, 1300b, and 1300c whose closed (on) and open (off) states are controlled by an ADC stop control signal in addition to the AD converter 130b shown in FIG. Has been done. The switch 1300a switches on and off the power supply from the power supply line Vp to the DA converter 132. The switch 1300b switches ON / OFF of power supply from the power supply line Vp to the comparator 133. Further, the switch 1300c switches ON / OFF of power supply from the power supply line Vp to the counter 134. Further, the current source 131 is controlled to turn on / off the current supply by the ADC stop control signal.

In such a configuration, the control unit 19 turns off the switches 1300a, 1300b, and 1300c, respectively, and supplies an ADC stop control signal for turning off the current supply by the current source 131 to each AD converter 130b. Thus, the power supply to each AD converter 130b can be stopped.

FIG. 14 is a block diagram showing an example of the configuration of the control unit 19 applicable to the first embodiment. In FIG. 14, the control unit 19 includes an ADC stop control signal generation unit 190 and an ADC control signal generation unit 191.

A horizontal sync signal is input to the ADC control signal generation unit 191. The ADC control signal generation unit 191 generates an ADC control signal for executing the AD conversion operation by each AD converter 130b, for example, according to the falling edge of the input horizontal synchronization signal. The ADC control signal is, for example, a signal for instructing the reference signal generation unit 14 to generate and output the ramp signal RAMP. The ADC control signal is supplied to the reference signal generation unit 14 and the ADC stop control signal generation unit 190.

The ADC stop control signal generation unit 190 is supplied with the ADC control signal from the ADC control signal generation unit 191, and is also supplied with the vertical synchronization signal or the external trigger signal from the control unit 19. Here, both the vertical synchronization signal and the external trigger signal are trigger signals that trigger the start of reading of each pixel 110 included in the pixel array unit 11. Therefore, the vertical synchronization signal and the external trigger signal will be distinguished below. When there is no need, these are collectively called a trigger signal.

The ADC stop control signal generation unit 190 generates an ADC stop control signal based on the ADC control signal and the trigger signal. FIG. 15 is an example time chart for explaining the ADC stop control signal according to the first embodiment. In FIG. 15, a chart showing the timing of the horizontal synchronizing signal, the ADC control, the ADC stop control signal, and the ADC operation is shown from the top.

The switches 1300a, 1300b, and 1300c in the AD converter 130b are turned off when the ADC stop control signal is in the high state and turned on when the ADC stop control signal is in the low state. Further, the current source 131 stops current supply when the ADC stop control signal is in a high state, and supplies power in a low state. That is, in each AD converter 130b, the power supply is stopped when the ADC stop control signal is high to stop the AD conversion operation, and the power is supplied when the ADC stop control signal is low to perform the AD conversion operation. It becomes feasible.

At the beginning of FIG. 15, the ADC stop control signal generation unit 190 sets the ADC stop control signal to the low state according to the rising edge of the horizontal synchronization signal. By setting the ADC stop control signal to the low state, the switches 1300a, 1300b and 1300c are turned on in each AD converter 130b, and power is supplied to the DA converter 132, the comparator 133 and the counter 134 from the power supply line Vp. . At the same time, the current is supplied from the current source 131 in each AD converter 130b. As a result, the operation of each AD converter 130b shifts to the operation in the return period 41b.

The ADC stop control signal generation unit 190 generates an ADC control signal for performing ADC control that causes an AD conversion operation in each AD converter 130b at a timing corresponding to the falling edge of the horizontal synchronization signal. In response to the ADC control signal, the operation of each AD converter 130 shifts to the operation of the AD conversion period 40, and the AD conversion operation is executed in each AD converter 130b. This AD conversion operation includes a conversion operation in the P-phase period and a conversion operation in the D-phase period in the pixel 110.

For example, the ADC control signal generation unit 191 generates an ADC control signal indicating the end of the AD conversion operation at the timing when the AD conversion operation by each AD converter 130b ends, and the generated ADC control signal is converted into each AD conversion signal. And the ADC stop control signal generation unit 190.

The ADC stop control signal generation unit 190 sets the ADC stop control signal to a high state according to the ADC control signal supplied from the ADC control signal generation unit 191 indicating the end of the AD conversion operation. As a result, in each AD converter 130b, the switches 1300a, 1300b, and 1300c are turned off, and the power supply from the power supply line Vp to the DA converter 132, the comparator 133, and the counter 134 is stopped. At the same time, the supply of current from the current source 131 is stopped in each AD converter 130b. Therefore, the operation of each AD converter 130b shifts to the operation of the circuit stop period 41a.

In response to the next rising edge of the horizontal sync signal, the ADC control signal generation unit 191 generates an ADC control signal instructing the supply of electric power to each AD converter 130b, and generates the generated ADC control signal as an ADC stop control signal. It is supplied to the section 190. The ADC stop control signal generation unit 190 shifts the ADC stop control signal from the high state to the low state according to the supplied ADC control signal. When the ADC stop control signal is shifted to the low state, the switches 1300a, 1300b and 1300c are turned on in each AD converter 130b, and the DA converter 132, the comparator 133 and the counter 134 are supplied with power from the power supply line Vp. It At the same time, the current is supplied from the current source 131 in each AD converter 130b. As a result, the operation of each AD converter 130b shifts to the operation in the return period 41b.

By performing the above operation, for example, every 1H period, it is possible to stop the power supply to each AD converter 130b during the horizontal blanking period 41 at the time of reading each line, and the power consumption in the AD conversion unit 13b. Can be reduced.

16 and 17 are time charts showing an example of control in the vertical blanking period 31 according to the first embodiment. FIG. 16 shows an example of control in the vertical blanking period 31 in the process of reading the pixel signal from each pixel 110 according to the vertical synchronization signal and the horizontal synchronization signal according to the first embodiment. Further, FIG. 17 shows an example of control in the vertical blanking period 31 in the process of reading the pixel signal from each pixel 110 by the external trigger control according to the first embodiment.

In FIG. 16, the control unit 19 generates an ADC stop control signal that is in a high state in the period VC _stop including the vertical blanking period 31. In this example, the control unit 19 omits the return period 41b (see FIG. 15) in the 1H period immediately before the vertical blanking period 31, and becomes the high state at the timing of the beginning of the circuit stop period 41a in the 1H period. An ADC stop control signal that goes low at the end of the blanking period 31 is generated. In response to the ADC stop control signal, during the period VC _stop, power supply is stopped for each AD converter 130b, the operation of the AD converter 130b is during the period VC _stop, is stopped.

In the example of FIG. 17 as well, as in the case of FIG. 16 described above, the control unit 19 generates the ADC stop control signal that is in the high state during the period VC _stop including the vertical blanking period 31. That is, the control unit 19 outputs an ADC stop control signal that becomes a high state at the beginning timing of the circuit stop period 41a in the 1H period immediately before the vertical blanking period 31 and becomes a low state at the end timing of the vertical blanking period 31. To generate. In response to the ADC stop control signal, during the period VC _stop, power supply is stopped for each AD converter 130b, the operation of the AD converter 130b is during the period VC _stop, is stopped.

In the above description, the power supply to each AD converter 130b is stopped during the circuit stop period 41a within the 1H period and the vertical blanking period 31, but this is not limited to this example. For example, the power supply to each AD converter 130b may be stopped in at least one of the circuit stop period 41a and the vertical blanking period 31 within the 1H period. Also in this case, it is possible to reduce the power consumption in the AD conversion unit 13a.

Further, in the above description, the standby state of the AD converter 130b is realized by stopping the supply of power to each unit of the AD converter 130b, but this is not limited to this example. For example, the standby state may be achieved by stopping the power supply to at least one of the DA converter 132, the comparator 133, and the counter 134 included in the AD converter 130b. It is also possible to realize the standby state of the AD converter 130b by reducing the power supplied to each part of the AD converter 130b.

[Second Embodiment]
Next, a second embodiment of the present disclosure will be described. The second embodiment is an example in which each pixel 110 included in the pixel array unit 11 is divided into a plurality of groups, and the AD conversion unit 13 is provided for each of the plurality of groups. Here, each pixel 110 included in the pixel array unit 11 is divided into two groups, and the AD conversion units 13 corresponding to the respective groups are arranged on both end sides of the pixel array unit 11.

FIG. 18 is a block diagram schematically showing a configuration example of the solid-state imaging device according to the second embodiment. In FIG. 18, the solid-state imaging device 10b has AD conversion units 13up and 13lw arranged at both ends of each column in the pixel array unit 11a. The control unit 19a supplies the ADC control signal up and the ADC stop control signal up (stop) to be supplied to the AD conversion unit 13up arranged on the upper side in FIG. 18 and the AD conversion unit 13lw arranged on the lower side. And an ADC stop control signal lw (stop) for generating the signal.

In the example of FIG. 18, each vertical signal line 17 derived from the pixel array unit 11a is alternately connected to the upper AD conversion unit 13up and the lower AD conversion unit 13lw. More specifically, for example, when the pixel array unit 11a includes 2n (n is an integer of 1 or more) columns (vertical signal lines 17), a vertical signal connected to the upper AD conversion unit 13up. The line 17 is an odd-numbered vertical signal line 17 which is VSL ₁ , VSL ₃ , ..., VSL _2n-1 , and the vertical signal line 17 connected to the lower AD converter 13lw is an even-numbered vertical signal line. The lines 17 are VSL ₂ , VSL ₄ , ..., VSL _2n . As described above, in the example of FIG. 18, each pixel 110 included in the pixel array unit 11a includes a group of pixels connected to the odd-numbered vertical signal lines 17 and a pixel connected to the even-numbered vertical signal lines 17. It is divided into two groups. The AD conversion unit 13up and the AD conversion unit 13lw each include n AD converters 130b, which is half the number of the 2n vertical signal lines 17 included in the pixel array unit 11a.

The same configuration as the configuration described with reference to FIG. 13 can be applied to the configuration of each AD converter 130b included in the AD conversion units 13up and 13lw.

The signal processing unit 20a performs CDS processing based on the two digital values output from the AD conversion unit 13up, and generates a pixel signal (pixel data) by a digital signal. Similarly, the signal processing unit 20a performs CDS processing based on the two digital values output from the AD conversion unit 13lw, and generates a pixel signal by a digital signal. The signal processing unit 20a alternately outputs, for example, a pixel signal based on the output of the AD conversion unit 13up and a pixel signal based on the output of the AD conversion unit 13lw in the order of the vertical signal lines 17.

The pixel signals output from the signal processing unit 20a are arranged and stored in a predetermined order in, for example, a frame buffer outside the solid-state imaging device 10b, and one image data is formed.

FIG. 19 is a time chart showing an example of a process of reading a pixel signal from each pixel 110 according to a vertical synchronization signal and a horizontal synchronization signal according to the second embodiment. In FIG. 19, each chart of the vertical synchronizing signal, the horizontal synchronizing signal, and the reading process is common to the corresponding chart of FIG. 10 described above.

In the second embodiment, the number of lines to be AD-converted by each AD converter 13up and 13lw is the same as the number of lines to be AD-converted by the AD converter 13a according to the first embodiment. Therefore, the ADC operation by each AD converter 130b included in each AD converter 13up and 13lw will be described with reference to FIG. 10 as shown in the charts of the ADC operations “up” and “lw” in FIG. The same operation is performed.

That is, the control unit 19a generates ADC stop control signals up (stop) and lw (stop) that fall according to the rising edge of the horizontal synchronization signal and rise with the end of the ADC operation of each AD converter 130b (FIG. 15), and supplies to the AD conversion units 13up and 13lw, respectively. Based on the ADC stop control signals up (stop) and lw (stop) and the ADC control signals up and lw for controlling the AD conversion operation in the AD converters 130b included in the AD converters 13up and 13lw, respectively. The 1H period is divided into an AD conversion period 40, a circuit stop period 41a, and a return period 41b.

Each AD converter 130b included in each AD conversion unit 13up and 13lw executes AD conversion processing in these AD conversion periods 40, and power supply is stopped in the circuit stop period 41a. Further, the supply of electric power is restarted in the return period 41b. The AD conversion period 40, the circuit stop period 41a, and the recovery period 41b are executed in each line in synchronization with the horizontal synchronization signal.

Similarly in the vertical blanking period 31, the control unit 19a generates the ADC stop control signals up (stop) and lw (stop) which are in the high state in the vertical blanking period 31, and the AD conversion units 13up and 13lw respectively. Supply. As a result, in the vertical blanking period 31, the power supply to the AD converters 130b included in the AD converters 13up and 13lw is stopped.

As described above, also in the second embodiment, similarly to the above-described first embodiment, the power supply is stopped during the period in which each AD converter 130b does not perform the AD conversion processing, and each AD converter 13up and The power consumption in 13 lw can be reduced. Also in the second embodiment, as in the above-described first embodiment, the operation of each AD converter 130b is stopped during a period in which AD conversion processing is not performed, so that the AD converter 130b is in the operating state. It is possible to reduce noise caused by electric charges such as hot carriers, which are caused by the above.

[Third Embodiment]
Next, a third embodiment of the present disclosure will be described. The third embodiment is an example in which one solid-state image sensor includes a plurality of pixel array units, and a plurality of external trigger signals that specify different exposure times are input corresponding to the plurality of pixel array units. is there.

FIG. 20 is a block diagram schematically showing a configuration example of the solid-state imaging device according to the third embodiment. In FIG. 20, the solid-state imaging device 10c includes a plurality (two in this example) of pixel array sections 11b ₁ and 11b ₂ . Note that in FIG. 20, the pixel array units 11b ₁ and 11b ₂ are also shown as the pixel array unit (1) and the pixel array unit (2). The pixel array units 11b ₁ and 11b ₂ are assumed to have the same configuration as the pixel array unit 11 described with reference to FIG.

A horizontal synchronizing signal and a plurality of external trigger signals are input to the control unit 19b. In FIG. 20, two external trigger signals of the external trigger signal (1) and the external trigger signal (2) are input to the control unit 19b. The control unit 19b generates an ADC control signal (1) corresponding to the pixel array unit 11b ₁ and an ADC stop control signal (1) based on the horizontal synchronization signal and the external trigger signal (1). Similarly, the control unit 19b generates an ADC control signal (2) corresponding to the pixel array unit 11b ₂ and an ADC stop control signal (2) based on the horizontal synchronization signal and the external trigger signal (2).

The solid-state imaging device 10c further includes vertical scanning units 12a ₁ and 12a ₂ and AD conversion units 13b ₁ and 13b ₂ . Each of the vertical scanning units 12a ₁ and 12a ₂ has the same function as the vertical scanning unit 12 described with reference to FIG. In FIG. 20, the vertical scanning units 12a ₁ and 12a ₂ are also shown as a vertical scanning unit (1) and a vertical scanning unit (2), respectively.

The vertical scanning unit 12a ₁ receives the reset pulse RST, the transfer pulse TRG, and the reset pulse RST supplied to each pixel 110 included in the pixel array unit 11b ₁ based on the external trigger signal (1) from the control unit 19b and the horizontal synchronizing signal. The selection signal SEL is generated. Similarly, the vertical scanning unit 12a ₂ transfers the reset pulse RST supplied to each pixel 110 included in the pixel array unit 11b ₂ based on the external trigger signal (2) by the control unit 19b and the horizontal synchronization signal, and transfers the reset pulse RST. The pulse TRG and the selection signal SEL are generated.

Each of the AD conversion units 13b ₁ and 13b ₂ has a function equivalent to that of the AD conversion unit 13a described with reference to FIG. 9, and includes a plurality of AD converters 130b. In this example, the AD conversion unit 13b ₁ includes the number of AD converters 130b corresponding to the number of columns (the number of columns) of the pixel array unit 11b ₁ . Similarly, the AD converter 13b ₂ includes the number of AD converters 130b corresponding to the number of columns of the pixel array unit 11b ₂ . In FIG. 20, the AD conversion units 13b ₁ and 13b ₂ are also shown as an AD conversion unit (1) and an AD conversion unit (2), respectively.

The ADC converter 13b ₁ is supplied with the ADC control signal (1) and the ADC stop control signal (1) generated by the controller 19b in response to the external trigger signal (1). The operation of each AD converter 130b included in the AD converter 13b ₁ is controlled according to the ADC control signal (1) and the ADC stop control signal (1), and is supplied from each vertical signal line 17 of the pixel array unit 11b _1. AD conversion processing is performed on the corresponding pixel signal. The digital value obtained by subjecting the pixel signal to AD conversion by the AD converter 13b ₁ is supplied to the signal processor 20b.

Similarly, the AD converter 13b ₂ is supplied with the ADC control signal (2) and the ADC stop control signal (2) generated by the controller 19b in response to the external trigger signal (2). The operation of each AD converter 130b included in the AD converter 13b ₂ is controlled according to the ADC control signal (2) and the ADC stop control signal (2), and is supplied from each vertical signal line 17 of the pixel array unit 11b _2. AD conversion processing is performed on the corresponding pixel signal. The digital value obtained by subjecting the pixel signal to AD conversion by the AD converter 13b ₂ is supplied to the signal processor 20b.

The signal processing unit 20b performs a CDS process based on each digital value supplied from the AD conversion unit 13b ₁ and outputs pixel data by a digital signal corresponding to the pixel array unit 11b ₁ as a pixel output (1). Similarly, the signal processing unit 20b performs CDS processing based on each digital value supplied from the AD conversion unit 13b ₂ and outputs pixel data corresponding to the pixel array unit 11b ₂ by a digital signal as a pixel output (2). To do.

FIG. 21 is a time chart showing an example of pixel signal read processing from each pixel 110 according to the external trigger signals (1) and (2) and the horizontal synchronization signal according to the third embodiment. In FIG. 21, from the top, the chart of the horizontal synchronizing signal, each chart of the external trigger signal (1) and the reading process (1) by the external trigger signal (1), the external trigger signal (2), and the external trigger signal. Each chart of the reading process (2) by (2) and the chart showing the ADC operation corresponding to each of the reading processes (1) and (2) are shown. A chart showing the details of the ADC operation in the 1H period is shown in the lower stage.

Note that, similarly to FIG. 10 described above, in the example of FIG. 12 as well, for the sake of explanation, in the chart showing the timing of the horizontal synchronizing signal, the horizontal synchronizing signal is formed of a pair of a rising edge and a falling edge. It is represented as a pulse.

In FIG. 21, the external trigger signal (1) is a signal that falls at time t ₂₀ and rises at time t ₂₁ , while the external trigger signal (2) is time t ₂₂ that is later than time t _20. It is a signal that falls at and rises at time t ₂₁ . As described above, in the example of FIG. 21, different exposure times are designated by the external trigger signals (1) and (2).

The vertical scanning unit 12a ₁ transmits a control signal based on the external trigger signal (1) to the pixel array unit 11b ₁ . In addition, the vertical scanning unit 12a ₂ transmits a control signal based on the external trigger signal (2) to the pixel array unit 11b ₂ . Each pixel 110 included in the pixel array unit 11b ₁ is exposed for the exposure time indicated by the time t ₂₀ and the time t ₂₁ in the external trigger signal (1). On the other hand, each pixel 110 included in the pixel array unit 11b ₂ is shorter than each pixel 110 included in the pixel array unit 11b ₁ by the exposure time shown at the time points t ₂₂ and t ₂₁ in the external trigger signal (1). To be done. In this way, by exposing the _two pixel array sections 11b ₁ and 11b ₂ included in one solid-state imaging device 10c with different exposure times, for example, the dynamic range of the obtained image data can be expanded.

The read process (1) and the ADC operation according to the external trigger signal (1) and the read process (2) and the ADC operation according to the external trigger signal (2) are the external trigger described with reference to FIG. 12, respectively. This is the same as the read processing and the ADC operation according to the signal. That is, in the pixel array section 11b ₁ , the timing of the rising edge of the external trigger signal (1) is set to the start timing of the 1V period, and reading of one frame is started. Similarly, in the pixel array unit 11b _2, the timing of the rising edge of the external trigger signal (2) is the head timing of the 1V period, 1 frame readout is started.

According to the AD converter 130b included in the AD conversion section 13b _1, operation within 1V period and in 1H period corresponding to the external trigger signal (1), and, each AD converter 130b included in the AD conversion unit 13b ₂ The operation in the 1V period and the 1H period according to the external trigger signal (2) is the same as the example in which the 1V period is started according to the vertical synchronization signal described with reference to FIG. .

That is, the 1H period is divided into the AD conversion period 40, the circuit stop period 41a, and the return period 41b. Control unit 19b is at the end of the AD conversion period 40, ADC stop control signal for stopping the supply of electric power to the AD converter 130b included in the AD conversion section 13b ₁ a (1) is supplied to the AD converter 13b ₁ The supply of power to each AD converter 130b is stopped in the circuit stop period 41a. Control unit 19b is supplied at the rising edge of the next horizontal synchronizing signal, ADC stop control signal to resume supply of power to each AD converter 130 included in the AD conversion section 13b ₁ (1) to the AD converter 13b ₁ To do. As a result, power is supplied to each AD converter 130b included in the AD conversion unit 13b _1, and the operation of each AD converter 130b shifts to the return operation.

The operation of the AD conversion unit 13b ₂ according to the external trigger signal (2) is also similar to the operation of the AD conversion unit 13b ₁ described above, and therefore the description thereof is omitted here. Further, the process of stopping the power supply to each AD converter 130b in the vertical blanking period 31 is also similar to the example described with reference to FIG. 10, and thus the description thereof is omitted here.

As described above, even when the external trigger signals (1) and (2) designating different exposure times are supplied to the two pixel array units 11b ₁ and 11b ₂ included in the solid-state imaging device 11c, the AD conversion units 13b are also provided. _The power supply is stopped during the period in which the AD converters 130b included in ₁ and 13b ₂ do not perform AD conversion processing, and the power consumption in the AD conversion units 13b ₁ and 13b ₂ can be reduced. Also in the third embodiment, as in the above-described first embodiment, the operation of each AD converter 130b is stopped during the period in which AD conversion processing is not performed, so that the AD converter 130b is in the operating state. It is possible to reduce noise caused by electric charges such as hot carriers, which are caused by the above.

[Fourth Embodiment]
Next, a fourth embodiment of the present disclosure will be described. The fourth embodiment will describe a configuration example of an electronic device to which the techniques according to the above-described first to third embodiments are applied. FIG. 22 is a block diagram showing the configuration of an example of the electronic device according to the fourth embodiment.

22, the electronic device 100 includes an optical system 1000, an image pickup apparatus 1001, a signal processing circuit 1002, a memory 1003, and a monitor 1004. FIG. 22 shows an embodiment in which any one of the above-described solid- state imaging devices 10a, 10b, and 10c of the present disclosure is provided in the electronic device 100 as the imaging device 1001. Here, as the electronic device 100, a digital still camera, a digital video camera, a mobile phone with an imaging function, a smartphone, or the like can be applied.

The optical system 1000 forms image light (incident light) from a subject on the image pickup surface of the image pickup apparatus 1001. As a result, the signal charges are accumulated in the imaging device 1001 for a certain period. The signal processing circuit 1002 performs various kinds of signal processing on the signal output from the imaging device 1001. The video signal subjected to the signal processing can be stored in a storage medium such as the memory 1003. Further, the video signal can be output to the monitor 1004.

[Fifth Embodiment]
Next, a usage example of the imaging device to which the technology according to the present disclosure is applied will be described. FIG. 23 is a diagram showing a usage example of the solid-state image pickup elements 10a, 10b, and 10c as the image pickup apparatus according to the present disclosure described above.

The solid- state imaging devices 10a, 10b, and 10c described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

-A device that captures images used for viewing, such as digital cameras and portable devices with a shooting function.
・ In-vehicle sensors that take images of the front, rear, surroundings, and inside of the vehicle for safe driving such as automatic stop and recognition of the driver's condition, surveillance cameras for monitoring traveling vehicles and roads, inter-vehicle etc. A device used for traffic, such as a distance measurement sensor for distance measurement.
A device used for home appliances such as a TV, a refrigerator, and an air conditioner in order to photograph a user's gesture and operate a device according to the gesture.
-A device used for medical care or healthcare, such as an endoscope or a device for taking an angiogram by receiving infrared light.
-A device used for security, such as a security surveillance camera or a person authentication camera.
-A device used for beauty, such as a skin measuring device that photographs the skin and a microscope that photographs the scalp.
-Devices used for sports such as action cameras and wearable cameras for sports purposes.
-A device used for agriculture, such as a camera for monitoring the condition of fields and crops.

It should be noted that the effects described in this specification are merely examples and are not limited, and there may be other effects.

Note that the present technology may also be configured as below.
(1)
A conversion unit that converts an analog signal read from each pixel included in the pixel array in a two-dimensional lattice array into a digital signal,
A control unit for controlling the operation of the conversion unit,
Equipped with
The control unit is
At least one of a horizontal blanking period based on a horizontal synchronizing signal indicating a read timing of lines in the array and a vertical blanking period based on a trigger signal indicating a timing to start reading pixels of one frame from the pixel array. An imaging device that shifts the state of the conversion unit to a standby state in which the conversion is not performed within one period.
(2)
The conversion unit is
The conversion is started in response to one of rising and falling of the horizontal synchronizing signal,
The control unit is
The state of the conversion unit is shifted to the standby state according to the end timing of the conversion, and the standby state of the conversion unit is released according to the other of rising and falling of the horizontal synchronization signal. The imaging device according to.
(3)
The trigger signal is
The image pickup apparatus according to (1) or (2), which is a vertical synchronization signal indicating a period for reading the pixels of the one frame from the pixel array.
(4)
The trigger signal is a signal that designates the start and end of exposure in the pixel array, and the vertical blanking period is based on the timing (1) or () based on the timing when the end of the exposure is designated by the trigger signal. The image pickup device according to 2).
(5)
The control unit is
The imaging device according to any one of (1) to (4), wherein the state of the conversion unit is shifted to the standby state by stopping the supply of power to the conversion unit.
(6)
The control unit is
A state control signal that shifts the state of the conversion unit to the standby state is generated based on a conversion control signal that controls the start and end of the conversion by the conversion unit, the trigger signal, and the horizontal synchronization signal. The imaging device according to any one of (1) to (5) above.
(7)
A plurality of conversion units corresponding to a plurality of groups each including the plurality of pixels,
The control unit is
The imaging device according to (6), wherein the state control signal is generated corresponding to each of the plurality of conversion units.
(8)
The imaging device includes a plurality of the pixel arrays,
The control unit is
The imaging device according to (6), wherein the state control signal is generated corresponding to each of the plurality of pixel arrays.
(9)
A horizontal synchronization signal input step in which a horizontal synchronization signal indicating a read timing of a line in the array of pixels in which the pixels are included in a two-dimensional lattice array is input;
A trigger signal input step of inputting a trigger signal indicating a timing of starting reading of pixels for one frame from the pixel array;
A conversion step in which the conversion section performs conversion of the analog signal read from the pixel into a digital signal;
A control step of shifting the state of the conversion unit to a standby state in which the conversion is not performed in at least one of a horizontal section ranking period based on the horizontal synchronization signal and a vertical blanking period based on the trigger signal. When,
And a method for controlling an image pickup apparatus.
(10)
A conversion unit that converts an analog signal read from each pixel included in the pixel array in a two-dimensional lattice array into a digital signal,
A control unit for controlling the operation of the conversion unit,
A storage unit for storing the digital signal,
Equipped with
The control unit is
At least one of a horizontal blanking period based on a horizontal synchronization signal indicating a read timing of a line in the array and a vertical blanking period based on a trigger signal indicating a timing to start reading pixels of one frame from the pixel array. An electronic device that shifts the state of the conversion unit to a standby state in which the conversion is not performed in one period.

10, 10a, 10b, 10c Solid- state imaging device 11, 11a, 11b ₁ , 11b ₂ Pixel array section 12, 12a ₁ , 12a ₂ Vertical scanning section 13, 13a, 13b ₁ , 13b ₂ 13up, 13lw AD conversion section 14 Reference signal Generation unit 16 Pixel signal line 17 Vertical signal lines 19, 19a, 19b Control unit 20, 20a, 20b Signal processing unit 30 Reading period 31 Vertical blanking period 40 AD conversion period 41a Circuit stop period 41b Recovery period 100 Electronic device 110 Pixel 130 , 130a, 130b AD converter 131 current source 132 DA converter 133 comparator 134 counter 190 ADC stop control signal generation unit 191 ADC control signal generation unit 1300a, 1300b, 1300c switch

Claims (10)

1. A conversion unit that converts an analog signal read from each pixel included in the pixel array in a two-dimensional lattice array into a digital signal,
   A control unit for controlling the operation of the conversion unit,
   Equipped with
   The control unit is
   At least one of a horizontal blanking period based on a horizontal synchronizing signal indicating a read timing of lines in the array and a vertical blanking period based on a trigger signal indicating a timing to start reading pixels of one frame from the pixel array. An imaging device that shifts the state of the conversion unit to a standby state in which the conversion is not performed within one period.
2. The conversion unit is
   The conversion is started in response to one of rising and falling of the horizontal synchronizing signal,
   The control unit is
   2. The state of the conversion unit is shifted to the standby state according to the end timing of the conversion, and the standby state of the conversion unit is released according to the other of rising and falling of the horizontal synchronization signal. The imaging device described.
3. The trigger signal is
   The image pickup apparatus according to claim 1, wherein the image pickup apparatus is a vertical synchronization signal indicating a cycle of reading the pixels of the one frame from the pixel array.
4. The said trigger signal is a signal which designates the start and end of exposure in the said pixel array, The said vertical blanking period is based on the timing with which the end of this exposure was designated by the said trigger signal. Imaging device.
5. The control unit is
   The imaging device according to claim 1, wherein the state of the conversion unit is shifted to the standby state by stopping the supply of electric power to the conversion unit.
6. The control unit is
   A state control signal that shifts the state of the conversion unit to the standby state is generated based on a conversion control signal that controls the start and end of the conversion by the conversion unit, the trigger signal, and the horizontal synchronization signal. The image pickup apparatus according to claim 1.
7. A plurality of conversion units corresponding to a plurality of groups each including the plurality of pixels,
   The control unit is
   The imaging device according to claim 6, wherein the state control signal is generated corresponding to each of the plurality of conversion units.
8. The imaging device includes a plurality of the pixel arrays,
   The control unit is
   The imaging device according to claim 6, wherein the state control signal is generated corresponding to each of the plurality of pixel arrays.
9. A horizontal synchronization signal input step in which a horizontal synchronization signal indicating a read timing of a line in the array of pixels in which the pixels are included in a two-dimensional lattice array is input;
   A trigger signal input step of inputting a trigger signal indicating a timing of starting reading of pixels for one frame from the pixel array;
   A conversion step in which the conversion unit performs conversion of the analog signal read from the pixel into a digital signal,
   A control step of shifting the state of the conversion unit to a standby state in which the conversion is not performed in at least one of a horizontal section ranking period based on the horizontal synchronization signal and a vertical blanking period based on the trigger signal. When,
   And a method for controlling an image pickup apparatus.
10. A conversion unit that converts an analog signal read from each pixel included in the pixel array in a two-dimensional lattice array into a digital signal,
    A control unit for controlling the operation of the conversion unit,
    A storage unit for storing the digital signal,
    Equipped with
    The control unit is
    At least one of a horizontal blanking period based on a horizontal synchronizing signal indicating a read timing of lines in the array and a vertical blanking period based on a trigger signal indicating a timing to start reading pixels of one frame from the pixel array. An electronic device that shifts the state of the conversion unit to a standby state in which the conversion is not performed in one period.

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