JP6307771B2 - Imaging device - Google Patents

Description

  The present application relates to an imaging apparatus. The present application particularly relates to an imaging apparatus having a photoelectric conversion unit including a photoelectric conversion film stacked on a semiconductor substrate.

  As a MOS (Metal Oxide Semiconductor) type imaging device, a stacked type imaging device has been proposed. In a stacked imaging device, a photoelectric conversion film is stacked on the outermost surface of a semiconductor substrate, and charges generated by photoelectric conversion in the photoelectric conversion film are stored in a charge storage region (referred to as “floating diffusion”). The imaging device reads out the accumulated electric charge using a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit in a semiconductor substrate. For example, Patent Document 1 discloses such an imaging apparatus.

JP 2009-164604 A JP 2011-228621 A

  There is a demand for noise reduction in the field of imaging devices. In particular, there is a demand for reducing kTC noise (also referred to as “reset noise”) generated at reset.

  According to certain non-limiting exemplary embodiments of the present application, the following is provided.

  A photoelectric conversion unit that photoelectrically converts incident light, a signal detection circuit that detects a signal of the photoelectric conversion unit, and a capacitor circuit in which a first capacitor and a second capacitor having a capacitance value larger than the first capacitor are connected in series A photoelectric conversion unit, a photoelectric conversion film, a first electrode formed on a light receiving surface side of the photoelectric conversion film, and a surface opposite to the first electrode of the photoelectric conversion film. The signal detection circuit amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and one of a source and a drain is connected to the second electrode. The feedback circuit negatively feeds back the signal of the photoelectric conversion unit to the other of the source and the drain of the second transistor, and the capacitor circuit is provided between the second electrode and the reference potential. An imaging device.

  Note that comprehensive or specific aspects may be realized by an element, a device, a system, an integrated circuit, or a method. In addition, comprehensive or specific aspects may be realized by any combination of elements, devices, systems, integrated circuits, and methods.

  Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. The effects and / or advantages are individually provided by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of these.

  According to one aspect of the present disclosure, an imaging apparatus that can further reduce noise such as kTC noise is provided.

FIG. 1 is a schematic diagram illustrating an exemplary circuit configuration of the imaging apparatus according to the first embodiment. FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of the unit pixel cell 11 illustrated in FIG. 1. FIG. 3 is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging apparatus according to the first embodiment. FIG. 4 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging apparatus according to the first embodiment. FIG. 5 is a plan view schematically showing an example of the layout of each element in the unit pixel cell 11. 6 is a cross-sectional view schematically showing a cross section taken along line A-A ′ shown in FIG. 5. FIG. 7 is a plan view schematically showing another example of the layout of each element in the unit pixel cell 11. FIG. 8 is a cross-sectional view schematically showing a cross section taken along line B-B ′ shown in FIG. 7. FIG. 9 is a schematic cross-sectional view for explaining an exemplary manufacturing method of the imaging device 101. FIG. 10 is a schematic cross-sectional view for explaining an exemplary manufacturing method of the imaging device 101. FIG. 11 is a schematic cross-sectional view for explaining an exemplary manufacturing method of the imaging apparatus 101. FIG. 12 is a schematic cross-sectional view for explaining an exemplary manufacturing method of the imaging apparatus 101. FIG. 13 is a schematic diagram illustrating another exemplary circuit configuration of the unit pixel cell in the imaging apparatus according to the first embodiment. FIG. 14 is a schematic diagram illustrating an exemplary circuit configuration of a unit pixel cell in the imaging apparatus according to the second embodiment. FIG. 15 is a schematic diagram illustrating an exemplary circuit configuration of a unit pixel cell in the imaging apparatus according to the third embodiment. FIG. 16 is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging apparatus according to the third embodiment. FIG. 17 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging apparatus according to the third embodiment. FIG. 18 is a schematic diagram illustrating an exemplary circuit configuration of a unit pixel cell 14a in an imaging apparatus according to a modification of the third embodiment. FIG. 19 is a schematic diagram illustrating an exemplary circuit configuration of a unit pixel cell 14b in another modification of the imaging apparatus according to the third embodiment. FIG. 20 is a schematic cross-sectional view illustrating an example of a device structure of a unit pixel cell in the imaging apparatus according to the fourth embodiment. FIG. 21 is a schematic plan view showing an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b in the unit pixel cell 60A shown in FIG. FIG. 22 is a schematic cross-sectional view showing another example of the device structure of the unit pixel cell in the imaging apparatus according to the fourth embodiment. FIG. 23 is a schematic plan view showing an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b in the unit pixel cell 60B shown in FIG. FIG. 24 is a schematic cross-sectional view showing still another example of the device structure of the unit pixel cell in the imaging apparatus according to the fourth embodiment. FIG. 25 is a schematic plan view showing an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b in the unit pixel cell 60C shown in FIG. FIG. 26 is a schematic diagram illustrating a configuration example of a camera system according to the fifth embodiment.

  The knowledge of the present inventor will be described before the embodiments of the present disclosure are described in detail.

  As a circuit for reading out the charge accumulated in the charge accumulation region, a configuration in which three transistors are arranged in a pixel is known. For example, FIG. 4 of Patent Document 2 describes a signal readout circuit having an output transistor, a row selection transistor, and a reset transistor for resetting a floating diffusion. There is also known a readout circuit in which a charge transistor generated by photoelectric conversion is transferred to a floating diffusion and a transfer transistor is further provided in the pixel. For example, the signal readout circuit in FIG. 7 of Patent Document 2 has four transistors: a reset transistor, an output transistor, a row selection transistor, and a transistor for charge transfer. Of these four transistors, the fourth transistor is connected between the pixel electrode and the floating diffusion. The fourth transistor is a transfer transistor that transfers charges generated by photoelectric conversion and collected in the pixel electrode to the floating diffusion. Hereinafter, a readout circuit having a transfer transistor in a pixel may be referred to as a “4Tr readout circuit”. A readout circuit that does not have a transfer transistor in a pixel may be referred to as a “3Tr readout circuit”. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2011-228621 is incorporated herein by reference.

  In a so-called CCD image sensor or CMOS image sensor in which a photodiode is formed on a semiconductor substrate, the influence of reset kTC noise is eliminated by applying correlated double sampling (CDS) to the 4Tr readout circuit. It is known that it can. However, according to the study of the present inventor, it is difficult to remove the influence of the reset kTC noise by the above-described method in the multilayer imaging device.

  In the stacked imaging device, typically, a metal wiring or a metal layer is interposed between the photoelectric conversion unit and the semiconductor substrate for electrical connection between the photoelectric conversion unit and the semiconductor substrate. For this reason, it is difficult to completely transfer the charges collected by the pixel electrode to the floating diffusion. Therefore, it is not effective to simply apply a technique of applying correlated double sampling by providing a transfer transistor in a pixel in a stacked imaging device. It is desired to reduce kTC noise in a multilayer imaging device.

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, components, arrangement and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. The various aspects described herein can be combined with each other as long as no contradiction arises. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements. In the following description, components having substantially the same function are denoted by common reference numerals, and description thereof may be omitted.

(First embodiment)
FIG. 1 schematically illustrates an exemplary circuit configuration of the imaging apparatus according to the first embodiment. An imaging apparatus 101 illustrated in FIG. 1 includes a plurality of unit pixel cells 11 and peripheral circuits. The plurality of unit pixel cells 11 are two-dimensionally arranged on the semiconductor substrate to form a photosensitive region (pixel region). The semiconductor substrate is not limited to a substrate that is entirely a semiconductor. The semiconductor substrate may be an insulating substrate in which a semiconductor layer is provided on the surface on the side where the photosensitive region is formed.

  In the illustrated example, the plurality of unit pixel cells 11 are arranged in the row direction and the column direction. In this specification, the row direction and the column direction refer to directions in which rows and columns extend, respectively. That is, in the drawing, the vertical direction on the paper is the column direction, and the horizontal direction is the row direction. The plurality of unit pixel cells 11 may be arranged in one dimension. In other words, the imaging device 101 can be a line sensor.

  Each unit pixel cell 11 is connected to a power supply wiring 22. A predetermined power supply voltage is supplied to each unit pixel cell 11 via the power supply wiring 22. As will be described in detail later, each of the unit pixel cells 11 includes a photoelectric conversion unit having a photoelectric conversion film stacked on a semiconductor substrate. As illustrated, the imaging apparatus 101 includes an accumulation control line 17 for applying the same constant voltage to all the photoelectric conversion units.

  Peripheral circuits of the imaging device 101 are a vertical scanning circuit (also referred to as a “row scanning circuit”) 16, a load circuit 19, a column signal processing circuit (also referred to as a “row signal storage circuit”) 20, and a horizontal signal readout circuit ( 21) (also referred to as “column scanning circuit”) and an inverting amplifier 24. In the configuration shown in the drawing, the column signal processing circuit 20, the load circuit 19, and the inverting amplifier 24 are arranged for each column of the unit pixel cells 11 arranged in two dimensions. That is, in this example, the peripheral circuit includes a plurality of column signal processing circuits 20, a plurality of load circuits 19, and a plurality of inverting amplifiers 24.

  The vertical scanning circuit 16 is connected to the address signal line 30 and the reset signal line 26. The vertical scanning circuit 16 applies a predetermined voltage to the address signal line 30 to select a plurality of unit pixel cells 11 arranged in each row in units of rows. Thereby, the reading of the signal voltage of the selected unit pixel cell 11 and the resetting of the pixel electrode described later are executed.

  In the illustrated example, the vertical scanning circuit 16 is also connected to the feedback control line 28 and the sensitivity adjustment line 32. As will be described later, when the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, a feedback circuit that negatively feeds back the output of the unit pixel cell 11 can be formed. Further, the vertical scanning circuit 16 can supply a predetermined voltage to the plurality of unit pixel cells 11 via the sensitivity adjustment line 32. As will be described in detail later, in the present disclosure, each of the unit pixel cells 11 includes one or more capacitive elements in the pixel. In this specification, a “capacitor” means a structure in which a dielectric such as an insulating film is sandwiched between electrodes. The “electrode” in the present specification is not limited to an electrode formed from a metal, and is interpreted to include a polysilicon layer and the like. The “electrode” in this specification may be a part of a semiconductor substrate.

  The unit pixel cells 11 arranged in each column are electrically connected to the column signal processing circuit 20 via the vertical signal line 18 corresponding to each column. A load circuit 19 is electrically connected to the vertical signal line 18. The column signal processing circuit 20 performs noise suppression signal processing represented by correlated double sampling, analog-digital conversion (AD conversion), and the like. A horizontal signal readout circuit 21 is electrically connected to the plurality of column signal processing circuits 20 provided corresponding to the columns of the unit pixel cells 11. The horizontal signal reading circuit 21 sequentially reads signals from the plurality of column signal processing circuits 20 to the horizontal common signal line 23.

  In the configuration illustrated in FIG. 1, a plurality of inverting amplifiers 24 are provided corresponding to each column. The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18. A predetermined voltage (for example, 1 V or a positive voltage near 1 V) Vref is supplied to the positive input terminal of the inverting amplifier 24. The output terminal of the inverting amplifier 24 is connected to a plurality of unit pixel cells 11 having a connection with the negative input terminal of the inverting amplifier 24 via a feedback line 25 provided corresponding to each column. ing. The inverting amplifier 24 constitutes a part of a feedback circuit that negatively feeds back the output from the unit pixel cell 11. The inverting amplifier 24 may be called a feedback amplifier. The inverting amplifier 24 includes a gain adjustment terminal 24a for changing the inverting amplification gain. The operation of the inverting amplifier 24 will be described later.

  FIG. 2 shows an exemplary circuit configuration of the unit pixel cell 11 shown in FIG. The unit pixel cell 11 includes a photoelectric conversion unit 15 and a signal detection circuit SC.

  The photoelectric conversion unit 15 typically has a structure in which a photoelectric conversion film 15b is sandwiched between a first electrode 15a and a second electrode (pixel electrode) 15c. As will be described later with reference to the drawings, the photoelectric conversion film 15b is stacked on a semiconductor substrate on which the unit pixel cells 11 are formed. The photoelectric conversion film 15b is formed from an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion film 15b may include a layer composed of an organic material and a layer composed of an inorganic material.

  The first electrode 15a is provided on the light receiving surface side of the photoelectric conversion film 15b. The first electrode 15a is formed from a transparent conductive material such as ITO. A second electrode 15c is provided on the side facing the first electrode 15a via the photoelectric conversion film 15b. The second electrode 15c collects charges generated by photoelectric conversion in the photoelectric conversion film 15b. The second electrode 15c is formed of a metal such as aluminum or copper, a metal nitride, or polysilicon that is given conductivity by being doped with impurities.

  As illustrated, the first electrode 15 a is connected to the storage control line 17, and the second electrode 15 c is connected to a charge storage node (also referred to as “floating diffusion node”) 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, it is possible to collect either the hole or the electron among the hole-electron pairs generated by the photoelectric conversion by the second electrode 15c. it can. When holes are used as signal charges, the potential of the first electrode 15a may be higher than that of the second electrode 15c. Below, the case where a hole is utilized as a signal charge is illustrated. For example, a voltage of about 10 V is applied to the first electrode 15 a via the accumulation control line 17. As a result, the signal charge is stored in the charge storage node 44. Of course, electrons may be used as signal charges.

  The signal detection circuit SC included in the unit pixel cell 11 includes an amplification transistor (first transistor) 34 and a first reset transistor (second transistor) 36. The unit pixel cell 11 includes a capacitor circuit 45 in which a first capacitor element (first capacitor) 41 and a second capacitor element (second capacitor) 42 are connected in series. In the illustrated configuration, the second capacitive element 42 has a larger capacitance value than the first capacitive element 41. In the configuration illustrated in FIG. 2, one of the source and drain of the first reset transistor 36 and one electrode of the first capacitor element 41 are connected to the charge storage node 44. That is, they have an electrical connection with the second electrode 15c.

  The other of the source and drain of the first reset transistor 36 and the other electrode of the first capacitor element 41 are connected to one electrode of the second capacitor element 42. That is, in this example, the first capacitor element 41 is connected in parallel to the first reset transistor 36. By connecting the first capacitive element 41 and the first reset transistor 36 in parallel, transistor junction leakage to the charge storage node 44 can be reduced. Therefore, dark current can be reduced. Hereinafter, a node including a connection point between the first capacitor element 41 and the second capacitor element 42 may be referred to as a reset drain node 46.

  Of the electrodes of the second capacitive element 42, the electrode not connected to the reset drain node 46 is connected to the sensitivity adjustment line 32. The potential of the sensitivity adjustment line 32 is set to 0 V (reference potential), for example. The potential of the sensitivity adjustment line 32 does not need to be fixed when the imaging apparatus 101 is in operation. For example, a pulse voltage may be supplied from the vertical scanning circuit 16. As will be described later, the sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. Of course, the potential of the sensitivity adjustment line 32 may be fixed during the operation of the imaging apparatus 101.

  As illustrated, the gate of the amplification transistor 34 is connected to the charge storage node 44. In other words, the gate of the amplification transistor 34 has an electrical connection with the second electrode 15c. One of the source and drain (drain if N-channel MOS) of the amplification transistor 34 is connected to the power supply wiring (source follower power supply) 22, and the other is connected to the vertical signal line 18. A source follower circuit is formed by the amplification transistor 34 and the load circuit 19 (not shown in FIG. 2, refer to FIG. 1). The amplification transistor 34 amplifies the signal generated by the photoelectric conversion unit 15.

  As illustrated, the unit pixel cell 11 includes an address transistor (third transistor) 40. The source or drain of the address transistor 40 is connected to the side of the source and drain of the amplification transistor 34 that is not connected to the power supply wiring 22. The gate of the address transistor 40 is connected to the address signal line 30. In the configuration illustrated in FIG. 2, the address transistor 40 constitutes a part of the signal detection circuit SC.

  A voltage corresponding to the amount of signal charge stored in the charge storage node 44 is applied to the gate of the amplification transistor 34. The amplification transistor 34 amplifies this voltage. The voltage amplified by the amplification transistor 34 is selectively read out by the address transistor 40 as a signal voltage.

  In the configuration illustrated in FIG. 2, the unit pixel cell 11 includes a second reset transistor (fourth transistor) 38 in which one of the source and the drain is connected to the reset drain node 46 and the other is connected to the feedback line 25. In addition. In other words, in the illustrated configuration, the side connected to the reset drain node 46 of the source and drain of the first reset transistor 36 and the feedback line 25 are connected via the second reset transistor 38. Yes. The gate of the second reset transistor 38 is connected to the feedback control line 28. As will be described in detail later, by controlling the voltage of the feedback control line 28, it is possible to form a feedback circuit FC that feeds back (in this case, negative feedback) the output of the signal detection circuit SC.

  Each of the amplification transistor 34, the first reset transistor 36, the address transistor 40, and the second reset transistor 38 may be an N-channel MOS or a P-channel MOS. It is not necessary that all of these be unified with either the N-channel MOS or the P-channel MOS. Hereinafter, a case where the amplification transistor 34, the first reset transistor 36, the address transistor 40, and the second reset transistor 38 are N-channel MOSs will be exemplified. As a transistor, a bipolar transistor can be used in addition to a field effect transistor (FET).

(Outline of operation of imaging apparatus 101)
Next, an example of the operation of the imaging apparatus 101 will be described with reference to the drawings. As will be described below, according to the configuration illustrated in FIG. 2, two operation modes having different sensitivities are switched by appropriately controlling the gate voltages of the first reset transistor 36 and the second reset transistor 38. It is possible. The two operation modes described here are a first mode in which imaging can be performed with a relatively high sensitivity and a second mode in which imaging can be performed with a relatively low sensitivity.

  First, an outline of the operation of the imaging apparatus 101 in the first mode will be described. The first mode is a mode suitable for imaging under low illuminance. Under low illumination, high sensitivity is beneficial. However, if the sensitivity is relatively high, noise may be amplified. According to the embodiments of the present disclosure, it is possible to reduce and / or eliminate the influence of kTC noise while achieving relatively high sensitivity.

  FIG. 3 is a timing chart for explaining an example of the operation of the transistor in the first mode. In FIG. 3, ADD, RST1, RST2, and GCNT are the gate voltage of the address transistor 40, the gate voltage of the first reset transistor 36, the gate voltage of the second reset transistor 38, and the gain adjustment terminal of the inverting amplifier 24, respectively. An example of the change of the voltage applied to 24a is shown typically. In the example shown in FIG. 3, at time t0, the address transistor 40, the first reset transistor 36, and the second reset transistor 38 are all OFF. The voltage at the gain adjustment terminal 24a of the inverting amplifier 24 is a certain predetermined value. For simplicity, description of the operation of the electronic shutter is omitted below.

  First, the address transistor 40 is turned on by controlling the potential of the address signal line 30 (time t1). At this time, the signal charge stored in the charge storage node 44 is read.

  Next, the first reset transistor 36 and the second reset transistor 38 are turned on by controlling the potentials of the reset signal line 26 and the feedback control line 28 (time t2). As a result, the charge storage node 44 and the feedback line 25 are connected via the first reset transistor 36 and the second reset transistor 38, and a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC is formed. By interposing the second reset transistor 38 between the reset drain node 46 and the feedback line 25, the reset transistor 38 can selectively form a feedback circuit FC to feed back the signal of the photoelectric conversion unit 15. .

  In this example, the formation of the feedback circuit FC is performed for one of the plurality of unit pixel cells 11 sharing the feedback line 25. By controlling the gate voltage of the address transistor 40, a unit pixel cell 11 that is a target for forming the feedback circuit FC can be selected, and reset and / or noise cancellation described later can be performed on the desired unit pixel cell 11.

  Here, the feedback circuit FC is a negative feedback amplification circuit including the amplification transistor 34, the inverting amplifier 24, and the second reset transistor 38. The address transistor 40 turned ON at time t1 supplies the output of the amplification transistor 34 as an input to the feedback circuit FC.

  When the charge storage node 44 and the feedback line 25 are electrically connected, the charge storage node 44 is reset. At this time, the output of the signal detection circuit SC is negatively fed back, so that the voltage of the vertical signal line 18 converges to the voltage Vref applied to the positive input terminal of the inverting amplifier 24. That is, in this example, the reference voltage for reset is the voltage Vref. In the configuration illustrated in FIG. 2, the voltage Vref can be arbitrarily set within the range of the power supply voltage (for example, 3.3 V) and the ground (0 V). In other words, any voltage (for example, a voltage other than the power supply voltage) can be used as a reference voltage for resetting within a certain range.

  At time t2, the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to reduce the gain of the inverting amplifier 24. In the inverting amplifier 24, since the product G × B of the gain G and the band B is constant, the band B becomes wider (the cut-off frequency is higher) when the gain G is decreased. For this reason, it is possible to speed up the above-described convergence in the negative feedback amplifier circuit.

  Next, the first reset transistor 36 is turned off (time t3). Hereinafter, a period from time t2 when the first reset transistor 36 and second reset transistor 38 are turned on to time when the first reset transistor 36 is turned off (time t2 to time t3 in FIG. It may be called a “reset period”. In FIG. 3, the reset period is schematically indicated by an arrow Rst. By turning off the first reset transistor 36 at time t3, kTC noise is generated. Therefore, kTC noise is added to the voltage of the charge storage node 44 after reset.

  As can be seen from FIG. 2, while the second reset transistor 38 is ON, the state in which the feedback circuit FC is formed continues. Therefore, the kTC noise generated by turning off the first reset transistor 36 at time t3 is canceled to a magnitude of 1 / (1 + A), where A is the gain of the feedback circuit FC.

  In this example, the voltage of the vertical signal line 18 immediately before turning off the first reset transistor 36 (immediately before the start of noise cancellation) is substantially equal to the voltage Vref applied to the negative input terminal of the inverting amplifier 24. In this way, the kTC noise can be canceled in a relatively short time by bringing the voltage of the vertical signal line 18 at the start of noise cancellation close to the target voltage Vref after the noise cancellation. Hereinafter, a period from time t1 to time t4 in FIG. 3 after turning off the first reset transistor 36 to turning off the second reset transistor 38 may be referred to as a “noise cancel period”. In FIG. 3, the noise cancellation period is schematically indicated by an arrow Ncl.

  At time t3, the gain of the inverting amplifier 24 is in a lowered state. For this reason, noise can be canceled at high speed in the early stage of the noise cancellation period.

  Subsequently, at time t3 ', the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to increase the gain of the inverting amplifier 24. This further reduces the noise level. At this time, since the product G × B of the gain G and the band B is constant, the band B becomes narrow (the cut-off frequency is low) by increasing the gain G. That is, it takes time to converge in the negative feedback amplifier circuit. However, since the voltage of the vertical signal line 18 is already controlled in the vicinity of the convergence level between t3 and t3 ', the width of the voltage to be converged is small, and the convergence time is increased by narrowing the band. Can be suppressed.

  As described above, according to the embodiment of the present disclosure, it is possible to reduce the kTC noise generated by turning off the reset transistor and cancel the generated kTC noise in a relatively short time.

Next, the second reset transistor 38 is turned off (time t4), and exposure is executed for a predetermined period. By turning off the second reset transistor 38 at time t4, kTC noise is generated. At this time, the magnitude of the kTC noise added to the voltage of the charge storage node 44 is such that the first capacitor element 41 and the second capacitor element 42 are not provided in the unit pixel cell 11, and the second reset transistor 38 is used as the charge storage node 44. (Cfd / C2) ^1/2 × (C1 / (C1 + Cfd)) times when directly connected. In the above formula, Cfd, C1, and C2 represent the capacitance value of the charge storage node 44, the capacitance value of the first capacitance element 41, and the capacitance value of the second capacitance element 42, respectively. Note that “x” in the expression represents multiplication. Thus, the larger the capacitance value C2 of the second capacitive element 42, the smaller the generated noise itself, and the smaller the capacitance value C1 of the first capacitive element 41, the greater the attenuation factor. Therefore, according to the embodiment of the present disclosure, the second reset transistor 38 is turned off by appropriately setting the capacitance value C1 of the first capacitance element 41 and the capacitance value C2 of the second capacitance element 42. It is possible to sufficiently reduce the kTC noise.

  In FIG. 3, the exposure period is schematically indicated by an arrow Exp. The reset voltage from which the kTC noise has been canceled is read out at a predetermined timing during the exposure period (time t5). Since the time required for reading the reset voltage is a short time, the reset voltage may be read while the ON state of the address transistor 40 continues.

  By taking the difference between the signal read between time t1 and time t2 and the signal read at time t5, a signal from which fixed noise has been removed is obtained. In this way, a signal from which kTC noise and fixed noise are removed is obtained.

  Note that the second capacitor element 42 is connected to the charge storage node 44 via the first capacitor element 41 in a state where the first reset transistor 36 and the second reset transistor 38 are turned off. Here, it is assumed that the charge storage node 44 and the second capacitor element 42 are directly connected without using the first capacitor element 41. In this case, the capacitance value of the entire signal charge accumulation region when the second capacitor element 42 is directly connected is (Cfd + C2). That is, if the second capacitance element 42 has a relatively large capacitance value C2, the capacitance value of the entire signal charge accumulation region also becomes a large value, so that a high conversion gain (may be referred to as a high SN ratio) is obtained. Absent. Therefore, in the embodiment of the present disclosure, the second capacitive element 42 is connected to the charge storage node 44 via the first capacitive element 41. In such a configuration, the capacitance value of the entire signal charge accumulation region is expressed as (Cfd + (C1C2) / (C1 + C2)). Here, when the first capacitor element 41 has a relatively small capacitance value C1 and the second capacitor element 42 has a relatively large capacitance value C2, the capacitance value of the entire signal charge accumulation region is approximately ( Cfd + C1). That is, the increase in the capacitance value of the entire signal charge accumulation region is small. In this way, by connecting the second capacitor element 42 to the charge storage node 44 via the first capacitor element 41 having a relatively small capacitance value, it is possible to suppress a decrease in conversion gain.

  Next, an outline of the operation of the imaging apparatus 101 in the second mode capable of imaging with relatively low sensitivity will be described with reference to FIG. The second mode is a mode suitable for imaging under high illuminance. Under high illuminance, lower sensitivity is advantageous. Under a relatively low sensitivity, the influence of noise is small, but the capacity of the entire signal charge accumulation region is required to be large.

  FIG. 4 is a timing chart for explaining an example of the operation of the transistor in the second mode. In the first mode described with reference to FIG. 3, the charge storage node 44 is reset using the first reset transistor 36. In contrast, in the second mode, as described below, the charge storage node 44 is reset using the second reset transistor 38 while the first reset transistor 36 is kept ON.

  As shown in FIG. 4, in the second mode, the first reset transistor 36 is always ON. At time t1, the address transistor 40 is turned on as in the first mode. At this time, the signal charge stored in the charge storage node 44 is read. The voltage applied to the gain adjustment terminal 24a of the inverting amplifier 24 has a certain predetermined value.

  Next, the second reset transistor 38 is turned on (time t2). As a result, a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC is formed, and the charge storage node 44 is reset. At this time, the reference voltage at the reset is the voltage Vref applied to the positive input terminal of the inverting amplifier 24.

  At time t2, the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to reduce the gain of the inverting amplifier 24. In the inverting amplifier 24, since the product G × B of the gain G and the band B is constant, the band B becomes wider (the cut-off frequency is higher) when the gain G is decreased. For this reason, it is possible to speed up the above-described convergence in the negative feedback amplifier circuit.

  Next, the second reset transistor 38 is turned off (time t4). By turning off the second reset transistor 38, kTC noise is generated. In this example, the gain of the inverting amplifier 24 is lowered at time t4. For this reason, convergence in the negative feedback amplifier circuit can be performed at high speed. At time t2, the gain of the inverting amplifier 24 may be increased by controlling the potential of the gain adjustment terminal 24a of the inverting amplifier 24. In this case, time is required for convergence in the negative feedback amplifier circuit, but the band B can be narrowed (cut-off frequency is lowered). The potential of the gain adjustment terminal 24a (which may be referred to as the gain of the inverting amplifier 24) may be set appropriately in consideration of the time allowable for noise reduction.

  Thereafter, exposure is performed for a predetermined period. The reset voltage is read at a predetermined timing during the exposure period (time t5).

  In the second mode, there is no noise cancellation period. However, in the second mode used for imaging under high illuminance, shot noise is dominant and the influence of kTC noise is small. By taking the difference between the signal read between time t1 and time t2 and the signal read at time t5, a signal from which fixed noise has been removed is obtained.

  As can be seen from the above description, in the configuration illustrated in FIG. 2, the first reset transistor 36 functions as a reset transistor that resets the charge storage node 44 and switches between the first mode and the second mode. It also functions as a switch. According to such a configuration, the unit pixel cell can be miniaturized relatively easily.

  In this example, the second capacitor 42 is connected to the charge storage node 44 via the first reset transistor 36 by switching ON and OFF in the first reset transistor 36, or via the first capacitor 41. Whether the second capacitive element 42 is connected to the charge storage node 44 can be switched. That is, the amount of change in the potential of the second electrode 15c can be switched by turning on and off the first reset transistor 36, and by turning on and off the first reset transistor 36, It is possible to switch the sensitivity. As described above, in the configuration illustrated in FIG. 2, the first reset transistor 36 can be used as a gain switching transistor.

  The second capacitive element 42 has both the function of reducing the kTC noise in the first mode and the function of increasing the capacity of the entire signal charge accumulation region. According to the embodiment of the present disclosure, it is possible to expand the dynamic range with a simple configuration while suppressing an increase in the number of elements in a pixel. This is particularly beneficial in pixel miniaturization.

(Device structure of unit pixel cell 11 and manufacturing method of imaging apparatus 101)
Next, an example of the device structure of the unit pixel cell 11 will be described with reference to FIGS.

  FIG. 5 schematically shows an example of the layout of each element in the unit pixel cell 11. FIG. 6 schematically shows a cross section taken along line A-A ′ shown in FIG. 5. As already described, the unit pixel cells 11 are arranged on the semiconductor substrate. Here, an example in which a P-type silicon (Si) substrate is used as the semiconductor substrate 2 (see FIG. 6) will be described.

  In the configuration illustrated in FIG. 5, four transistors, that is, an amplification transistor 34, a first reset transistor 36, a second reset transistor 38, and an address transistor 40 are arranged in the unit pixel cell 11. Each unit pixel cell 11 is isolated by an element isolation region 2 s formed in the semiconductor substrate 2.

  Here, both the amplification transistor 34 and the first reset transistor 36 are formed on the semiconductor substrate 2. In the example described here, the second reset transistor 38 and the address transistor 40 are also formed on the semiconductor substrate 2. For example, paying attention to the second reset transistor 38, the second reset transistor 38 includes an impurity region (here, N-type region) 2 d formed in the semiconductor substrate 2. Each of these impurity regions 2 d functions as the source or drain of the second reset transistor 38. The impurity region 2 d is typically a diffusion layer formed in the semiconductor substrate 2. Hereinafter, the impurity region 2d in the semiconductor substrate 2 may be referred to as a “source / drain diffusion layer 2d”. In the configuration illustrated in FIG. 5, one of the two source / drain diffusion layers 2d constituting the source and drain of the second reset transistor 38 is connected via the polysilicon plug sp1, the polysilicon layer s1, and the contact plug cp1. It is connected to a feedback line 25 (not shown in FIG. 5, see FIG. 2).

  A first capacitor element 41 and a second capacitor element 42 are also formed on the semiconductor substrate 2. In the configuration illustrated in FIG. 5, the second capacitor element 42 occupies a relatively large area in the unit pixel cell 11. Thereby, a relatively large capacitance value is realized. In the embodiment described here, as shown in FIG. 5, the first capacitive element 41 is formed at a position overlapping the second capacitive element 42 when viewed from the normal direction of the semiconductor substrate. As will be described in detail later, the upper electrode 41w of the first capacitor element 41 electrically connects the source or drain of the first reset transistor 36 (source / drain diffusion layer 2d) and the gate electrode 34e of the amplification transistor 34. It is a part of wiring (conductive layer) to be connected.

  Please refer to FIG. As shown in FIG. 6, the unit pixel cell 11 has a photoelectric conversion unit 15 on the semiconductor substrate 2. In the illustrated example, interlayer insulating layers 4s, 4a, 4b, and 4c are stacked on the semiconductor substrate 2, and the photoelectric conversion film 15b of the photoelectric conversion unit 15 is stacked thereon. The first electrode 15a is provided on the light receiving surface 15h on the photoelectric conversion film 15b on the side where light from the subject is incident. The second electrode 15c is disposed on the surface opposite to the light receiving surface 15h. The second electrode 15 c is electrically separated between the plurality of unit pixel cells 11.

  In the configuration illustrated in FIG. 6, the semiconductor substrate 2 includes a well 2w (here, a P-type impurity region) having a relatively high acceptor concentration and a source / drain diffusion layer 2d (here, an N-type impurity region). ing. As shown in the figure, the second reset transistor 38 includes two source / drain diffusion layers 2d, a gate insulating film 38g formed on the semiconductor substrate 2, and a gate electrode 38e formed on the gate insulating film 38g. including. A channel region 38c is formed between the two source / drain diffusion layers 2d as the source or drain. Similarly, the first reset transistor 36 includes two source / drain diffusion layers 2d, a gate insulating film 36g formed on the semiconductor substrate 2, and a gate electrode 36e formed on the gate insulating film 36g. . A channel region 36c is formed between the two source / drain diffusion layers 2d as the source or drain. In the illustrated example, the first reset transistor 36 and the second reset transistor 38 share one of the source / drain diffusion layers 2d. Similarly, the amplification transistor 34 includes two source / drain diffusion layers 2d, a gate insulating film 34g formed on the semiconductor substrate 2, and a gate electrode 34e formed on the gate insulating film 34g. In FIG. 6, the two source / drain diffusion layers 2d in the amplification transistor 34 are not shown, and are formed between the gate insulating film 34g, the gate electrode 34e, and the two source / drain diffusion layers 2d. A channel region 34c is shown. The address transistor 40 (see FIG. 5) may have substantially the same configuration as the amplification transistor 34.

  The semiconductor substrate 2 has an element isolation region 2s for electrical isolation between elements. In this example, the set of the first reset transistor 36 and the second reset transistor 38 and the set of the amplification transistor 34 and the address transistor 40 are separated by the element isolation region 2s (see FIG. 5).

  The semiconductor substrate 2 is electrically isolated from the four transistors (amplification transistor 34, first reset transistor 36, second reset transistor 38, and address transistor 40) of the unit pixel cell 11 by being surrounded by the element isolation region 2s. The electrode region 42c is formed.

  In the configuration illustrated in FIG. 6, the second capacitor element 42 is formed on a part of the semiconductor substrate 2 via the dielectric layer (first dielectric layer) 42 g provided on the electrode region 42 c and the dielectric layer 42 g. The upper electrode 42e which opposes is included. The upper electrode 42e is electrically connected to the side of the source and drain of the first reset transistor 36 that is not connected to the charge storage node 44.

  In the embodiment described here, the second capacitor element 42 is a so-called MIS capacitor. However, as will be described later, here, the upper electrode 42e of the second capacitive element 42 is not an electrode formed of metal but an electrode formed of polysilicon. A portion of the semiconductor substrate 2 facing the upper electrode 42e functions as one of the electrodes in the second capacitor element 42.

  The electrode region 42c is electrically connected to the sensitivity adjustment line 32 (see FIG. 2). A predetermined voltage is applied to the electrode region 42 c from the voltage source (here, the vertical scanning circuit 16) via the sensitivity adjustment line 32. By controlling the potential of the electrode region 42c, the potential of the charge storage node 44 can be controlled. In other words, the sensitivity of the imaging device 101 can be adjusted by adjusting the voltage supplied to the electrode region 42 c via the sensitivity adjustment line 32.

  When viewed from the normal direction of the semiconductor substrate 2, the shape and area of the dielectric layer 42g do not have to coincide with the shape and area of the electrode region 42c. It is not necessary for the dielectric layer 42g to cover the entire electrode region 42c. The dielectric layer 42g may also be formed on the element isolation region 2s surrounding the electrode region 42c. For example, the electrode region 42c may be formed as a region having a higher impurity concentration than the well 2w by ion implantation. Alternatively, the electrode region 42c may be formed as a region having a conductivity type different from that of the well 2w.

  As shown in FIG. 6, the upper electrode 41 w electrically connects the source or drain (source / drain diffusion layer 2 d) of the first reset transistor 36 and the gate electrode 34 e of the amplification transistor 34. In the configuration illustrated in FIG. 6, the upper electrode 41w is electrically connected to the second electrode 15c via the contact plug cpa, the wiring layer 6s, the via va, the wiring layer 6a, the via vb, the wiring layer 6b, and the via vc. Has been. Typically, the contact plug cpa, the wiring layers 6s, 6a and 6b, and the vias va to vc are formed from a metal such as copper. The polysilicon plug sp2, the upper electrode 41w, the contact plug cpa, the wiring layers 6s, 6a and 6b, the vias va to vc, and one of the source and drain (here, drain) of the first reset transistor 36 are the charge storage region Function as.

  As shown in the drawing, the upper electrode 41 w extends to above the upper electrode 42 e of the second capacitor element 42. The first capacitive element 41 is formed from the upper electrode 41w, the upper electrode 42e, and an insulating film (second dielectric layer) 41g sandwiched therebetween. In other words, the first capacitive element 41 is connected to the upper electrode 42e of the second capacitive element 42, the dielectric layer 41g formed on the upper electrode 42e, and the second electrode 15c of the photoelectric conversion unit 15. The upper electrode 41w is included. When viewed from the normal direction of the semiconductor substrate 2, the upper electrode 41w of the first capacitive element 41 at least partially overlaps the upper electrode 42e via the dielectric layer 41g.

  In this example, the first capacitive element 41 and the second capacitive element 42 share one of the two electrodes for forming the capacitive element. The dielectric layer 41g can be a part of the interlayer insulating layer 4s. As described above, the dielectric layer 41g may be a part of the interlayer insulating layer formed on the semiconductor substrate 2, or may be a separate insulating film (or insulating layer) different from the interlayer insulating layer. Good.

  Here, the upper electrode 41w of the first capacitive element 41 is made of polysilicon, like the upper electrode 42e of the second capacitive element 42. The CV curve of a capacitive element having a structure in which a dielectric is sandwiched between two electrodes formed of polysilicon has a flat portion in a relatively wide voltage range. As the voltage of the charge storage node 44 changes according to the amount of light, the voltage between the electrodes of the first capacitive element 41 shows a relatively large fluctuation. Forming the two electrodes constituting the first capacitive element 41 from polysilicon is advantageous because it can realize a highly accurate capacitive element having flat CV characteristics while suppressing an increase in the element size. In addition, as will be described later, an advantage of suppressing an increase in the number of processes in the manufacturing process of the imaging device is also obtained.

  Here, another example of the device structure in the first embodiment will be described with reference to FIGS.

  FIG. 7 schematically shows another example of the layout of each element in the unit pixel cell 11. FIG. 8 schematically shows a cross section taken along line B-B ′ shown in FIG. 7. The difference between the configuration illustrated in FIGS. 7 and 8 and the configuration described with reference to FIGS. 5 and 6 is that the unit pixel cell 11 illustrated in FIGS. 7 and 8 further includes a third capacitance element 43. Is a point.

  As shown in FIGS. 7 and 8, the third capacitive element 43 includes an upper electrode 43 e disposed on the upper electrode 42 e of the second capacitive element 42. In the configuration illustrated in FIGS. 7 and 8, the upper electrode 43e is electrically connected to the electrode region 42c of the semiconductor substrate 2 constituting a part of the second capacitor element 42 via the contact plug cp3. . As will be described later, the upper electrode 43e of the third capacitive element 43 faces the upper electrode 42e of the second capacitive element 42 through the dielectric layer 43g. That is, the third capacitive element 43 and the second capacitive element 42 share one of the two electrodes for forming the capacitive element and are electrically connected in parallel. Therefore, the capacitance value of the capacitive element connected between the reset drain node 46 and the sensitivity adjustment line 32 can be increased (see FIG. 2). Thereby, kTC noise can be reduced more effectively.

(Method for Manufacturing Imaging Device 101)
Next, an example of a method for manufacturing the imaging device 101 will be described with reference to FIGS. 9 to 11 are views corresponding to the cross-sectional view taken along the line AA ′ shown in FIG. 5. FIG. 12 is a view corresponding to the cross-sectional view taken along the line BB ′ shown in FIG.

  First, the semiconductor substrate 2 is prepared. Here, a P-type silicon substrate is used. Next, a patterned resist mask is formed on the semiconductor substrate 2 using lithography. Thereafter, a well 2w is formed by ion-implanting an acceptor (for example, boron (B)) under predetermined implantation conditions.

  Next, a resist mask (resist pattern) for forming a channel region of a transistor to be arranged in the unit pixel cell 11 is formed using lithography. Here, four transistors of the amplification transistor 34, the first reset transistor 36, the second reset transistor 38, and the address transistor 40 are formed in the unit pixel cell 11. The resist mask is formed so as to cover a portion other than a portion to be a channel region of each transistor. Thereafter, an acceptor or a donor is ion-implanted under predetermined implantation conditions, thereby forming a channel region of each transistor. In FIG. 9, the channel region 34 c of the amplification transistor 34, the channel region 36 c of the first reset transistor 36, and the channel region 38 c of the second reset transistor 38 are illustrated. By using ion implantation, a desired threshold voltage can be realized in each transistor.

  Here, a donor (for example, arsenic (As)) is ion-implanted into a predetermined region of the semiconductor substrate 2 using a resist mask having an opening in the predetermined region of the semiconductor substrate 2. That is, in this example, the electrode region 42 c is formed by performing ion implantation in a predetermined region of the semiconductor substrate 2.

Next, gate oxidation is performed by, for example, ISSG (In Situ Steam Generation) to form a gate oxide film on the main surface of the semiconductor substrate 2. Typically, the gate oxide is silicon dioxide (SiO ₂ ). Next, a material for forming a gate electrode is deposited on the gate oxide by chemical vapor deposition (CVD). Here, a polysilicon film is formed on the gate oxide.

  Next, a resist mask is formed on the polysilicon film by lithography, and dry etching is performed to form gate insulating films (gate insulating films 34g, 36g, 36g, respectively) from the gate oxide film and the polysilicon film, respectively. 38g) and gate electrodes (gate electrodes 34e, 36e, 36e). At this time, a stacked body of the gate oxide film and the polysilicon film is also formed on the semiconductor substrate 2 on a region different from the region where the gate insulating films and gate electrodes of the four transistors are formed. Patterning is performed as follows. Thereby, a structure in which the first dielectric layer 42g and the upper electrode 42e are sequentially laminated on a part of the semiconductor substrate 2 can be formed. That is, the second capacitor element 42 as the MIS capacitor can be formed in parallel with the formation of the gate insulating films and the gate electrodes of the four transistors (see FIG. 9). As described above, according to the embodiment of the present disclosure, the second capacitor element 42 can be formed in the unit pixel cell 11 without increasing the number of steps.

  Next, a resist mask is formed by lithography to cover portions to be the source and drain regions of each transistor. Thereafter, the element isolation region 2s is formed by implanting acceptor ions under predetermined implantation conditions. At this time, the acceptor for forming the element isolation region 2s is not directly driven directly under the gate electrodes (gate electrodes 34e, 36e, 36e) of the respective transistors and the upper electrode 42e of the second capacitor element 42. Here, the element isolation region 2s is formed so as to surround the set of the first reset transistor 36 and the second reset transistor 38, the set of the amplification transistor 34 and the address transistor 40, and the second capacitor element 42 (FIG. 5). After the element isolation region 2s is formed, the resist mask is removed.

  Next, a resist mask having openings in portions to be the source region and the drain region of each transistor is formed by lithography. Thereafter, donor ions are implanted under predetermined implantation conditions to form the source / drain diffusion layer 2d (see FIG. 9). At this time, the donor may be ion-implanted by applying so-called gate implantation to the gate electrode of the transistor in the unit pixel cell 11 and / or the upper electrode 42 e of the second capacitor element 42.

  Next, an insulating film that covers the polysilicon layer constituting the gate electrode of each transistor and the upper electrode 42e of the second capacitor element 42 and the semiconductor substrate 2 is formed by CVD. Typically, the insulating film formed at this time is a silicon dioxide film.

  Next, a resist mask for forming contact holes is formed on the insulating film covering the polysilicon layer and the semiconductor substrate 2 by lithography. Thereafter, the contact hole chg and the contact hole chs are respectively formed on the gate electrode and the source / drain diffusion layer 2d of each transistor by dry etching, thereby forming the insulating layer 48 (see FIG. 10). The contact hole is also formed on the upper electrode 42e of the second capacitor element 42. The contact hole on the upper electrode 42e is provided to electrically connect the upper electrode 42e to the reset drain node 46 (see FIG. 5).

  Next, donor ions are implanted through the contact holes chs and contact holes chg formed in the insulating layer 48, so that the gate electrode and the source / drain diffusion layer 2d of each transistor have a relatively high impurity concentration. Regions are formed (not shown in FIG. 10). Thereafter, the impurity implanted by annealing is activated to lower the resistance of the region having a relatively high impurity concentration.

  Next, a polysilicon film containing a high concentration N-type impurity is deposited on the insulating layer 48 by CVD or the like. At this time, polysilicon is also deposited inside the contact holes (contact holes chs and chg) provided in the insulating layer 48.

  Next, a resist mask is formed by lithography. After the formation of the resist mask, a polysilicon layer is formed on the insulating layer 48 by dry etching, and a polysilicon plug (polysilicon plug sp1) that connects the polysilicon layer on the insulating layer 48 and the source / drain diffusion layer 2d. , Sp2), and a polysilicon plug (polysilicon plug sp3) for connecting the polysilicon layer on the insulating layer 48 and the gate electrode (gate electrode 34e, 36e, 38e) of each transistor. Note that a plug formed of polysilicon is used as a contact with the source / drain diffusion layer 2d constituting a part of the charge storage node 44 (for example, see FIG. 5), as in the case of using a metal plug. Since the influence of crystal defects due to the metal / semiconductor interface can be avoided, the advantage of suppressing dark current can be obtained. Thereafter, the resistance of the surface of the polysilicon layer on the insulating layer 48 is reduced by silicidation to form a polysilicon layer s1 as a conductive layer (see FIG. 11).

  At this time, a conductive portion (polysilicon wiring) that connects the source or drain of the first reset transistor 36 and the gate electrode 34e of the amplification transistor 34 is formed by patterning polysilicon. The patterning is performed so that at least a part of the conductive portion overlaps the upper electrode 42e of the second capacitor element 42 with the insulating layer 48 interposed therebetween. Thus, the first capacitor element 41 having a structure in which the insulating film is sandwiched between the two polysilicon layers can be formed. As is apparent from the above, the upper electrode 41w of the first capacitor element 41 can be a part of the polysilicon layer s1. Further, the second dielectric layer 41 g included in the first capacitor element 41 may be a part of the insulating layer 48. According to the first embodiment of the present disclosure, the first capacitor element 41 can be formed in the unit pixel cell 11 without increasing the number of steps.

  Further, as shown in FIG. 12, polysilicon patterning may be performed so that a conductive portion different from the upper electrode 41 w is formed at a position overlapping the upper electrode 42 e of the second capacitor element 42. By electrically connecting this conductive portion and the electrode region 42 c of the semiconductor substrate 2, this conductive portion can function as the upper electrode 43 e of the third capacitor element 43. The dielectric layer 43g included in the third capacitor element 43 may be a part of the insulating layer 48, similarly to the second dielectric layer 41g included in the first capacitor element 41. As described above, according to the embodiment of the present disclosure, the third capacitor element 43 that exhibits flat CV characteristics in a relatively wide voltage range is formed in the unit pixel cell 11 without adding a dedicated process. Is possible. In addition, the combined capacitance of the second capacitor element 42 and the third capacitor element 43 can be increased while suppressing an increase in pixel size.

  After the formation of the polysilicon layer s1, the interlayer insulating layer 4s, the contact plug cpa for connection between the wiring layer 6s and the upper electrode 41w, the wiring layer 6s, the interlayer insulating layer 4a, the via va, the wiring layer 6a, the interlayer insulation The layer 4b, the via vb, the wiring layer 6b, the interlayer insulating layer 4c, and the via vc are sequentially formed. Note that the number of interlayer insulating layers and the like can be arbitrarily set, and need not be four layers. By forming the photoelectric conversion portion 15 on the interlayer insulating layer 4c, the unit pixel cell 11 shown in FIG. 6 or FIG. 8 is obtained.

  As described above, the imaging device 101 can be manufactured using a known semiconductor manufacturing technique. A camera system can be configured by the imaging device 101 obtained in this way and the optical system that forms an image of a subject on the light receiving surface 15h of the photoelectric conversion film 15b. A protective film, a color filter, a lens (microlens), and the like may be further formed on the first electrode 15a of the photoelectric conversion unit 15.

(Modification of the first embodiment)
A modification of the imaging device according to the first embodiment of the present disclosure will be described with reference to FIG.

  FIG. 13 schematically illustrates an exemplary circuit configuration of the unit pixel cell 12 in the imaging device according to the first embodiment. The difference between the configuration illustrated in FIG. 13 and the configuration illustrated in FIG. 2 is that the side of the source and drain of the first reset transistor 36 that is not connected to the second electrode 15c (charge storage node 44) The point is that it is connected to the feedback line 25 instead of the reset drain node 46.

  In the configuration illustrated in FIG. 13, switching between the first mode and the second mode described with reference to FIGS. 3 and 4 cannot be performed. However, since the source and drain of the first reset transistor 36 that are not connected to the charge storage node 44 are directly connected to the feedback line 25, the driving force of the first reset transistor 36 is ensured. There is an advantage that the degree of freedom in designing the impurity profile is improved. Note that the operation timing of each transistor in the configuration illustrated in FIG. 13 is the same as that in the first mode.

  In the configuration described with reference to FIG. 2, one of the electrodes of the first capacitive element 41 is directly connected to one of the source and the drain of the first reset transistor 36, and the first The other of the electrodes of the capacitive element 41 is directly connected to the other of the source and drain of the first reset transistor 36. However, as shown in FIG. 13, the first reset transistor 36 is not necessarily connected in parallel with the first capacitor element 41.

  The layout and device structure of each element in the unit pixel cell 12 shown in FIG. 13 are substantially the same as the layout described with reference to FIGS. 5 and 7 and the device structure described with reference to FIGS. Since there is, description is abbreviate | omitted. The manufacturing method of the unit pixel cell 12 shown in FIG. 13 may be the same as the manufacturing method described with reference to FIGS.

(Second Embodiment)
FIG. 14 schematically illustrates an exemplary circuit configuration of the unit pixel cell 13 in the imaging apparatus according to the second embodiment. As illustrated in FIG. 14, the imaging apparatus according to the second embodiment is provided with a switching circuit 50 instead of the inverting amplifier 24 (see FIGS. 2 and 13) in each column of the unit pixel cells 13. This is different from the imaging device 101 of the first embodiment. For this reason, in the plurality of unit pixel cells 13 constituting each column of the imaging device according to the second embodiment, the feedback line 25 does not connect the unit pixel cells 13.

  In each unit pixel cell 13, the feedback line 25 is connected to the source or drain of the second reset transistor 38 that is not connected to the reset drain node 46. The address transistor 40 is provided between one of the source and drain of the amplification transistor 34 and the feedback line 25. The source or drain connected to the feedback line 25 of the address transistor 40 is connected to the vertical signal line 18. Hereinafter, differences from the imaging apparatus 101 of the first embodiment will be mainly described.

  The switching circuit 50 includes switch elements 51 and 51 ′ connected in parallel to the power supply wiring 22 and switch elements 52 ′ and 52 connected in parallel to the vertical signal line 18. The switch elements 51 and 51 'are connected to a power supply voltage (AVDD) and a reference potential (AVSS), respectively. The switch elements 52 'and 52 are connected to the power supply voltage (AVDD) and the reference potential (AVSS) via the constant current sources 27' and 27, respectively.

  In the unit pixel cell 13, when reading a signal, one of the unit pixel cells 13 in each column is selected by applying a voltage to the gate of the address transistor 40 via the address signal line 30. Further, by turning on the switch element 51 and the switch element 52 of the switching circuit 50, for example, a current flows from the constant current source 27 in the direction from the amplification transistor 34 to the address transistor 40, and the charge amplified by the amplification transistor 34 The potential of storage node 44 is detected.

  On the other hand, in the reset operation, by turning on the switch element 51 ′ and the switch element 52 ′ of the switching circuit 50, a current in the direction opposite to that at the time of signal reading flows through the address transistor 40 and the amplification transistor 34. Thus, a feedback circuit FC including the amplification transistor 34, the address transistor 40, the feedback line 25, the second reset transistor 38, and the first reset transistor 36 is configured. At this time, since the address transistor 40 and the amplification transistor 34 are cascode-connected, a large gain can be obtained. Therefore, the feedback circuit FC can perform noise cancellation with a large gain.

  The image pickup apparatus according to the present embodiment controls the first reset transistor 36 and the second reset transistor 38, so that the first image which can be picked up with a relatively high sensitivity, like the image pickup apparatus according to the first embodiment. It is possible to operate in the mode and the second mode in which imaging can be performed with relatively low sensitivity. In addition, the imaging apparatus of the present embodiment can reduce kTC noise as in the first embodiment.

  Further, according to the imaging apparatus of the present embodiment, the inverting amplifier 24 is not provided, and the address transistor 40 and the amplification transistor 34 serve as the signal detection circuit SC and the amplifier of the feedback circuit FC. For this reason, the area which comprises the circuit of an imaging device can be made small. In addition, power consumption of the imaging device can be reduced. Furthermore, since a large gain can be obtained by cascode connection, kTC noise can be reduced even when the capacitances of the first capacitive element 41 and the second capacitive element 42 are small.

  The layout of each element in the unit pixel cell 13 shown in FIG. 14 can be substantially the same as the layout in the unit pixel cell 11 described with reference to FIGS. Further, the device structure of each element in the unit pixel cell 13 may be substantially the same as the device structure in the unit pixel cell 11 described with reference to FIGS. 6 and 8. Therefore, the description of the layout and device structure of each element in the unit pixel cell 13 is omitted. The manufacturing method of the unit pixel cell 13 may be the same as the manufacturing method of the unit pixel cell 11 described with reference to FIGS. Therefore, description of the manufacturing method of the unit pixel cell 13 is omitted.

(Third embodiment)
FIG. 15 illustrates an exemplary circuit configuration of the unit pixel cell 14 in the imaging apparatus according to the third embodiment. Similar to the second embodiment, the imaging device of the third embodiment is provided with a switching circuit 50 ′ in each column of the unit pixel cells 14 instead of the inverting amplifier 24 (see FIGS. 2 and 13). This is different from the imaging device 101 of the first embodiment. In the plurality of unit pixel cells 14 constituting each column, the feedback line 25 does not connect the unit pixel cells 14.

  In each unit pixel cell 14, the feedback line 25 is connected to the source or drain of the second reset transistor 38 that is not connected to the reset drain node 46. One of the source and the drain of the address transistor 40 is connected to the constant current source 27 through the vertical signal line 18. The other of the source or drain of the address transistor 40 is connected to one of the feedback line 25 and the source or drain of the amplification transistor 34. The other of the source and drain of the amplification transistor 34 is connected to the switching circuit 50 ′ via the power supply wiring 22.

  The switching circuit 50 ′ includes switch elements 51 and 51 ′ connected in parallel, and the switch elements 51 and 51 ′ are connected to a power supply voltage (AVDD) and a reference potential (AVSS), respectively.

  Similar to the imaging apparatus 101 of the first embodiment, the imaging apparatus of the present embodiment also operates in the first mode in which imaging can be performed with a relatively high sensitivity and the second mode in which imaging can be performed with a relatively low sensitivity. Can be made.

  FIG. 16 is a timing chart for explaining an example of the operation of the transistor in the first mode. In FIG. 16, ADD, RST1, and RST2 schematically show examples of changes in the gate voltage of the address transistor 40, the gate voltage of the first reset transistor 36, and the gate voltage of the second reset transistor 38, respectively. In the example shown in FIG. 16, the address transistor 40, the first reset transistor 36, and the second reset transistor 38 are all OFF at time t0. For simplicity, description of the operation of the electronic shutter is omitted below.

  First, the address transistor 40 is turned on by controlling the potential of the address signal line 30 (time t1). At this time, the signal charge stored in the charge storage node 44 is read.

  Next, the address transistor 40 is turned off (time t1 '). Thereafter, by controlling the potentials of the reset signal line 26 and the feedback control line 28, the first reset transistor 36 and the second reset transistor 38 are turned on (time t2). Further, the switching circuit 50 ′ is controlled to apply the reference potential (AVSS) to one of the source and the drain of the amplification transistor 34. At this time, the address transistor 40 remains OFF. Thereby, in the unit pixel cell 14, the charge storage node 44 and the feedback line 25 are connected via the first reset transistor 36 and the second reset transistor 38, and the output of the signal detection circuit SC including the amplification transistor 34. Is formed as a feedback circuit FC.

  At time t3, the first reset transistor 36 is turned off (time t3). By turning off the first reset transistor 36 at time t3, kTC noise is generated. Therefore, kTC noise is added to the voltage of the charge storage node 44 after reset. The kTC noise generated by turning off the first reset transistor 36 is canceled to 1 / (1 + A), where A is the gain of the feedback circuit FC. By setting the potential of the feedback control line 28 so that the operation band of the second reset transistor 38 becomes the first band which is a wide band, noise can be suppressed at high speed.

  Subsequently, at time t3 ', the potential of the feedback control line 28 is set to an intermediate potential between the high level and the low level. As a result, the operating band of the second reset transistor 38 becomes a second band narrower than the first band.

Here, at the time t4, the kTC noise is generated by turning off the second reset transistor 38. Therefore, kTC noise is further added to the voltage of the charge storage node 44 after reset. The generated kTC noise is suppressed by the feedback circuit FC in a state where the second band is lower than the operating band of the amplification transistor 34, and is canceled to a magnitude of 1 / (1 + A) ^1/2 .

  Subsequently, at time t5, the address transistor 40 is turned on. Further, the switching circuit 50 ′ is controlled to connect one of the source and the drain of the amplification transistor 34 to the power supply voltage (AVDD). Thereby, for example, a current flows from the constant current source 27 in the direction from the amplification transistor 34 to the address transistor 40, and the potential of the charge storage node 44 amplified by the amplification transistor 34 is detected. The detected potential is output to the constant current source 27 (column signal processing circuit 20, see FIG. 1) via the vertical signal line 18. In FIG. 16, the exposure period is schematically indicated by an arrow Exp. The reset voltage from which the kTC noise has been canceled is read at a predetermined timing during the exposure period (time t5 '). Since the time required for reading the reset voltage is a short time, the reset voltage may be read while the ON state of the address transistor 40 continues.

  By taking the difference between the signal read between time t1 and time t1 'and the signal read at time t5', a signal from which fixed noise has been removed is obtained. In this way, a signal from which kTC noise and fixed noise are removed is obtained.

  FIG. 17 is a timing chart for explaining an example of the operation of the transistor in the second mode in which imaging can be performed with relatively low sensitivity. As described in the first embodiment, except that the first reset transistor 36 is always ON, it is driven in the same manner as in the first mode, and kTC noise is generated by the feedback circuit in each unit pixel cell 14. Is suppressed.

  Similarly to the first embodiment, the imaging device of the present embodiment also includes a function of a reset transistor that resets the charge storage node 44 and a switch for switching between the first mode and the second mode. It also serves as a function. The second capacitive element 42 has both a function of reducing the kTC noise in the first mode and a function of increasing the capacity of the entire signal charge accumulation region. According to the present embodiment, it is possible to expand the dynamic range with a simple configuration while suppressing an increase in the number of elements in the pixel. This is particularly beneficial in pixel miniaturization.

(Modification of the third embodiment)
FIG. 18 schematically illustrates an exemplary circuit configuration of a unit pixel cell 14a in an imaging apparatus according to a modification of the third embodiment. As shown in FIG. 18, also in this example, the inverting amplifier 24 (see FIGS. 2 and 13) is omitted, and the feedback line 25 is a reset drain node of the source or drain of the second reset transistor 38. The side not connected to 46 and the source or drain of the amplification transistor 34 are connected. In the configuration illustrated in FIG. 18, the output of the amplification transistor 34 is used as a reference voltage at reset.

  In the illustrated configuration, a voltage switching circuit 54 is connected to the power supply wiring 22. The voltage switching circuit 54 has a set of a first switch 53a and a second switch 53b. The voltage switching circuit 54 switches whether to supply the first voltage Va1 or the second voltage Va2 to the power supply wiring 22. The first voltage Va1 is, for example, 0V (ground), and the second voltage Va2 is, for example, a power supply voltage. The voltage switching circuit 54 may be provided for each pixel or may be shared among a plurality of pixels.

  Even with such a circuit configuration, the kTC noise can be reduced as in the first embodiment.

  FIG. 19 schematically illustrates an exemplary circuit configuration of a unit pixel cell 14b in an imaging apparatus according to another modification of the third embodiment. In the configuration illustrated in FIG. 19, as in the circuit configuration described with reference to FIG. 13, the side that is not connected to the charge storage node 44 among the source and drain of the first reset transistor 36 is the reset drain node 46. Instead, it is connected to the feedback line 25. Even with such a circuit configuration, the kTC noise can be reduced as in the first embodiment.

  The layout of each element in the unit pixel cell 14 shown in FIG. 15, the unit pixel cell 14a shown in FIG. 18, and the unit pixel cell 14b shown in FIG. 19 is the same as that in the unit pixel cell 11 described with reference to FIGS. It can be almost similar to the layout. Further, the device structure of each element in the unit pixel cells 14, 14a and 14b may be substantially the same as the device structure in the unit pixel cell 11 described with reference to FIGS. Therefore, description of the layout and device structure of each element in the unit pixel cells 14, 14a and 14b is omitted. The unit pixel cell 14 shown in FIG. 15, the unit pixel cell 14a shown in FIG. 18, and the unit pixel cell 14b shown in FIG. 19 are manufactured by the method of manufacturing the unit pixel cell 11 described with reference to FIGS. Can be similar. Therefore, description of the manufacturing method of the unit pixel cells 14, 14a and 14b is omitted.

(Fourth embodiment)
In the above-described embodiment, the electrode region 42c is provided on the semiconductor substrate 2, and the second capacitor element 42 is formed as a so-called MIS capacitor. However, the configuration of the high-capacitance capacitive element in the signal detection circuit SC is not limited to the above-described example. As will be described below, a capacitive element having a structure in which a dielectric is sandwiched between two electrodes formed of a metal or a metal compound is provided between the semiconductor substrate 2 and the photoelectric conversion unit 15. You may arrange | position in an insulating layer. Hereinafter, a structure in which a dielectric is sandwiched between two electrodes formed of a metal or a metal compound may be referred to as a “MIM (Metal-Insulator-Metal) structure”. By forming the capacitive element disposed in the interlayer insulating layer between the semiconductor substrate 2 and the photoelectric conversion unit 15 as a capacitive element having a so-called MIM structure, a larger capacitance value can be easily obtained. The device structure described below is applicable to any of the first to third embodiments described above.

  FIG. 20 schematically shows another example of the device structure of the unit pixel cell. Note that the layout of each element on the semiconductor substrate 2 in the unit pixel cell 60A shown in FIG. 20 may be the same as the layout in the unit pixel cell 11 illustrated in FIG. 20 is a diagram corresponding to the cross-sectional view taken along the line C-C ′ illustrated in FIG. 5.

  A unit pixel cell 60A illustrated in FIG. 20 includes a capacitive element 62 disposed between the semiconductor substrate 2 and the second electrode 15c. The capacitive element 62 includes an upper electrode 62u, a lower electrode 62b, and a dielectric layer 62d disposed between the upper electrode 62u and the lower electrode 62b. As illustrated, the lower electrode 62b is arranged farther from the second electrode 15c than the upper electrode 62u (that is, closer to the semiconductor substrate 2 than the upper electrode 62u). Note that the terms “upper” and “lower” in the present specification are used to indicate the relative arrangement between members, and are not intended to limit the posture of the imaging device of the present disclosure.

  Here, the lower electrode 62b is formed on the interlayer insulating layer 4c, and the capacitive element 62 is covered with the interlayer insulating layer 4d provided between the interlayer insulating layer 4c and the photoelectric conversion film 15b. Thus, by arranging the lower electrode 62b and the upper electrode 62u between the photoelectric conversion unit 15 and the gate electrode 34e of the amplification transistor 34, the wiring layer including the gate electrode 34e of the amplification transistor 34, the lower electrode 62b, Interference with the upper electrode 62u can be suppressed. Therefore, it is possible to form the capacitive element 62 having a relatively large electrode area.

  The lower electrode 62b is typically a metal electrode or a metal nitride electrode. Examples of the material for forming the lower electrode 62b are Ti, TiN, Ta, TaN, Mo, Ru, and Pt. The lower electrode 62b may be a part of a wiring layer provided in the interlayer insulating layer 4d.

  A dielectric layer 62d is stacked on the lower electrode 62b. In this example, the dielectric layer 62d covers the surface and the side surface of the lower electrode 62b facing the second electrode 15c.

The dielectric layer 62d may be made of a material (for example, metal oxide or metal nitride) different from the material (typically silicon dioxide) constituting the interlayer insulating layer 4d. When the capacitive element 62 is disposed in an interlayer insulating layer provided between the semiconductor substrate 2 and the photoelectric conversion unit 15, a material having a relatively high dielectric constant is employed as a material for forming the dielectric layer 62d. It is relatively easy. Therefore, it is easy to realize a relatively large capacitance value. An example of a material for forming the dielectric layer 62d is an oxide containing one or more selected from the group consisting of Zr, Al, La, Ba, Ta, Ti, Bi, Sr, Si, Y, and Hf Or it is nitride. The material for forming the dielectric layer 62d may be a binary compound, a ternary compound, or a quaternary compound. As a material for forming the dielectric layer 62d, for example, a material having a relatively high dielectric constant such as HfO ₂ , Al ₂ O ₃ , ZrO ₂ , TiO ₂ , or SrTiO ₃ can be used. The dielectric layer 62d may include two or more layers formed from different materials.

  An upper electrode 62u is stacked on the dielectric layer 62d. In this example, the upper electrode 62u covers the surface on the side facing the second electrode 15c and the side surface of the dielectric layer 62d. The upper electrode 62u is typically a metal electrode or a metal nitride electrode. That is, here, the capacitive element 62 has a so-called MIM structure. As a material for forming the upper electrode 62u, the same material as that for forming the lower electrode 62b can be used. The upper electrode 62u may be a part of a wiring layer provided in the interlayer insulating layer 4d.

  A protective layer formed of a metal such as Cu or Al or polysilicon may be disposed between the upper electrode 62u and the dielectric layer 62d. By disposing a protective layer between the upper electrode 62u and the dielectric layer 62d, it is possible to suppress damage to the dielectric layer 62d in the manufacturing process. Therefore, generation of leakage current between the upper electrode 62u and the lower electrode 62b Can be suppressed.

  The upper electrode 62u has an opening AP. A via vd, a connection part 66u, and a connection part 66b are disposed in the opening AP. The connection portion 66u and the connection portion 66b are in the same layer as the upper electrode 62u and the lower electrode 62b, respectively. As illustrated, the second electrode 15c of the photoelectric conversion unit 15 and the via vc having a connection with the gate electrode 34e of the amplification transistor 34 are connected via the via vd, the connection unit 66u, and the connection unit 66b. The via vd can be formed from a metal such as copper. The via vd, the connection part 66u, and the connection part 66b constitute a part of the charge storage region in the unit pixel cell 60A.

  In the configuration illustrated in FIG. 20, the portion of the lower electrode 62b shown on the right side of the via vd is the via vc1, the wiring layer 6b, the via vb1, the wiring layer 6a, the via va1, the wiring layer 6s, and the interlayer insulating layer 4s. It is connected to the upper electrode 42e of the second capacitive element 42 through a contact plug cpb provided inside. That is, the lower electrode 62b is connected to the reset drain node 46 (not shown in FIG. 20). Here, the lower electrode 62b is a single electrode provided for each unit pixel cell 60A (see FIG. 21 described later), and two lower electrodes 62b, which are shown separately on the left and right of the opening AP in FIG. The part is equipotential.

  In this example, the upper electrode 62u covers the connection portion 64b formed in the same layer as the lower electrode 62b. The connecting portion 64b is connected to the wiring 6z that is a part of the wiring layer 6s through the via vc3, the wiring layer 6b, the via vb3, the wiring layer 6a, and the via va3. The wiring 6z has a connection with a sensitivity adjustment line 32 (not shown in FIG. 20). That is, the capacitive element 62 is electrically connected in parallel with the above-described second capacitive element 42 and functions in the same manner as the second capacitive element 42. That is, in this example, the unit pixel cell 60A has a capacitor circuit in which the first capacitor element 41, the capacitor element 62, and the second capacitor element 42 are connected in series.

By forming the capacitive element 62 in the unit pixel cell, the second capacitive element 42 can be omitted. When the second capacitive element 42 is omitted, it is not necessary to secure a region for the electrode region 42c in the semiconductor substrate 2. Therefore, the degree of freedom in designing the element layout in the semiconductor substrate 2 is improved. For example, the pixel size can be reduced by omitting the electrode region 42c. Alternatively, the size of the transistor (for example, the amplification transistor 34) on the semiconductor substrate 2 can be increased. Since the variation in transistor characteristics can be reduced by increasing the transistor size, the sensitivity variation between unit pixel cells can be reduced. Further, since the driving capability is improved by increasing the size of the transistor (it may be said that the mutual conductance g _m is improved), noise can be further reduced.

  In this example, the upper electrode 62u is electrically connected to the via vc3 on the surface opposite to the surface facing the second electrode 15c of the photoelectric conversion unit 15. Thus, by providing a contact for electrical connection between the upper electrode 62u and the sensitivity adjustment line 32 on the surface near the semiconductor substrate 2, the complexity of the wiring can be avoided. In addition, since the distance between the upper electrode 62u and the second electrode 15c of the photoelectric conversion unit 15 can be reduced, the parasitic capacitance between the charge storage regions between adjacent pixels can be reduced.

  During the operation of the imaging apparatus 101, a predetermined voltage is applied to the upper electrode 62 u via the sensitivity adjustment line 32. Here, like the lower electrode 62b, the upper electrode 62u is a single electrode provided for each unit pixel cell 60A (see FIG. 21 described later), and is separated to the left and right of the opening AP in FIG. The two parts of the upper electrode 62u shown in FIG.

  FIG. 21 shows an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b when the unit pixel cell 60A is viewed from the normal direction of the semiconductor substrate 2. FIG. 21 also shows a C-C ′ cut line as in FIG. 5. As shown in FIG. 21, the shape of the upper electrode 62u and the shape of the lower electrode 62b do not have to match when viewed from the normal direction of the semiconductor substrate 2. When viewed from the normal direction of the semiconductor substrate 2, it is sufficient that the upper electrode 62u includes a portion facing at least a part of the lower electrode 62b.

  In this example, the lower electrode 62b and the upper electrode 62u occupy a large area in the unit pixel cell 60A. Therefore, by forming at least one of the lower electrode 62b and / or the upper electrode 62u as a light shielding electrode, the lower electrode 62b or the upper electrode 62u can function as a light shielding layer. For example, by allowing the upper electrode 62u to function as a light shielding layer, it is possible to block light that has passed through the gap formed between the second electrodes 15c by the upper electrode 62u. Thereby, it is possible to suppress the light that has passed through the gap formed between the second electrodes 15c from entering the channel region of the transistor (for example, the amplification transistor 34) on the semiconductor substrate 2. For example, a sufficient light shielding property can be realized by forming a TaN electrode having a thickness of 100 nm as the upper electrode 62u.

  According to the fourth embodiment, it is possible to suppress the stray light from entering the channel region of the transistor on the semiconductor substrate 2 to suppress the shift of the transistor characteristics (for example, the fluctuation of the threshold voltage). By suppressing the stray light from entering the channel region of the transistor on the semiconductor substrate 2, the characteristics of the transistor of each pixel can be stabilized, and variations in the operation of the transistor among a plurality of pixels can be reduced. As described above, suppressing the incidence of stray light on the channel region of the transistor on the semiconductor substrate 2 contributes to the improvement of the reliability of the imaging device.

  In the configuration illustrated in FIG. 21, the upper electrode 62u is electrically separated between the unit pixel cells 60A by spatially separating the upper electrode 62u. That is, in this example, there is a slight gap between the upper electrodes 62u adjacent to each other. However, here, each of the upper electrodes 62u is configured to be supplied with a predetermined voltage via the sensitivity adjustment line 32. Therefore, the distance between the upper electrodes 62u adjacent to each other can be made sufficiently smaller than the distance between the second electrodes 15c adjacent to each other. Therefore, most of the light that has passed through the gap formed between the second electrodes 15c can be blocked by the upper electrode 62u. In the circuit configuration illustrated in FIG. 1, a common voltage is applied to the upper electrode 62u in the unit pixel cells belonging to the same row. Therefore, a plurality of strip-like electrodes extending in the row direction over a plurality of columns may be used as the upper electrode 62u. Of course, as shown in FIG. 21, the upper electrode 62u may be spatially separated for each unit pixel cell 60A, and an independent voltage may be supplied for each upper electrode 62u.

  In this example, the opening AP of the upper electrode 62u is formed below the unit pixel cell 60A in the drawing. However, the arrangement of the aperture AP is not limited to this example. For example, the opening AP may be arranged in the center of the unit pixel cell 60A, and the upper electrode 62u may be formed so as to surround the connection part 66u and the connection part 66b. If the opening AP is arranged in the center of the unit pixel cell 60A and the shape of the upper electrode 62u is highly symmetric with respect to the connection portion 66u, it is advantageous because the capacitance deviation in the unit pixel cell 60A can be reduced. The shape of the upper electrode 62u when viewed from the normal direction of the semiconductor substrate 2 is not limited to the shape shown in FIG. For example, the upper electrode 62u may include a plurality of portions. The same applies to the dielectric layer 62d and the lower electrode 62b.

  As described above, in this example, since the upper electrode 62u has a connection with the sensitivity adjustment line 32, by supplying a constant voltage to the upper electrode 62u via the sensitivity adjustment line 32, the operation of the imaging device 101 is performed. At this time, the potential of the upper electrode 62u can be made constant. Therefore, the upper electrode 62u is formed so as to surround the connection portion 66u and the connection portion 66b, and a certain voltage is applied to the upper electrode 62u, whereby the upper electrode 62u can function as a shield electrode. By the upper electrode 62u functioning as a shield electrode, noise mixing into the charge storage node 44 can be suppressed.

  As described above, in the fourth embodiment, as the capacitive element connected between the reset drain node 46 and the sensitivity adjustment line 32, the capacitive element 62 is used as the second electrode of the upper electrode 41 w and the photoelectric conversion unit 15. It arrange | positions between the electrodes 15c. As illustrated in FIG. 20, the capacitive element 62 is disposed in an interlayer insulating layer (for example, the interlayer insulating layer 4d) of the unit pixel cell. Therefore, the capacitor 62 can be formed as a capacitor having a so-called MIM structure. That is, it is easy to obtain a relatively large capacitance value in the capacitive element 62. Even with such a configuration, similarly to the first to third embodiments described above, it is possible to reduce kTC noise caused by resetting while suppressing an increase in the capacitance value of the entire signal charge accumulation region. It is. Further, if the capacitance element 62 has a high capacity, the capacity of the entire signal charge accumulation region can be increased, which is advantageous for photographing under high illuminance.

(Method for Forming Capacitive Element 62)
Hereinafter, an outline of a method for manufacturing an imaging device having the unit pixel cell 60A will be described. The manufacturing process until the via vc is formed can be substantially the same as that in the first embodiment, and thus the description thereof is omitted. As described with reference to FIG. 12, the upper electrode 43 e electrically connected to the electrode region 42 c may be formed at a position overlapping the upper electrode 42 e of the second capacitor element 42. Here, the vias vc1 and vc3 are also formed in parallel with the formation of the via vc.

  After the formation of the vias vc, vc1, and vc3, the lower electrode 62b, the connection portion 66b, and the connection portion 64b are formed on the interlayer insulating layer 4c. Here, TaN is used as a material for forming the lower electrode 62b, the connection portion 66b, and the connection portion 64b. Photolithography introduced in a general semiconductor process can be applied to the formation of the lower electrode 62b, the connection portion 66b, and the connection portion 64b on the interlayer insulating layer 4c. Thereafter, a dielectric film is formed by depositing a material for the dielectric layer 62d, and patterning of the dielectric film is performed.

For example, atomic layer deposition (ALD) can be applied to the formation of the dielectric film. According to ALD, several atoms different from each other can be stacked. Here, an Hf oxide film is formed as the dielectric film. In the formation of the Hf oxide film, tetrakisethylmethylamido hafnium is used as a precursor, and plasma discharge is performed after introduction of the precursor. By performing plasma discharge in an oxygen atmosphere, oxidation of Hf is promoted. By repeating the above-described steps, HfO ₂ is laminated one by one. For example, a film having a thickness of 22 nm is formed by repeating introduction of a gaseous precursor and plasma discharge 250 times.

  Photolithography introduced in a general semiconductor process can be applied to the patterning of the dielectric film. A dielectric layer 62d is formed by patterning the dielectric film. The dielectric layer 62d may be a continuous single film, or may include a plurality of portions arranged at different locations on the lower electrode 62b.

  After the formation of the dielectric layer 62d, the upper electrode 62u and the connection portion 66u are formed in the same manner as the lower electrode 62b. Thereafter, the interlayer insulating layer 4d and the via vd are formed, and the photoelectric conversion portion 15 is formed on the interlayer insulating layer 4d, whereby the device structure shown in FIG. 20 is obtained.

  The second electrode 15c of the photoelectric conversion unit 15 may be formed using a metal nitride such as TiN, TaN, or WN. Metal nitride is excellent in denseness and has a property that impurity elements are less likely to move and / or mix even at high temperatures. Therefore, the upper electrode 62u located above the dielectric layer 62d is formed using metal nitride (here, TaN), and the second electrode 15c is formed using metal nitride, resulting in impurities. Can be prevented from entering the dielectric layer 62d. By suppressing the entry of impurities into the dielectric layer 62d, the leakage current between the upper electrode 62u and the lower electrode 62b in the capacitive element 62 can be reduced.

  In addition, since metal nitride hardly causes migration during sputtering, it is easy to form a flat surface. When the second electrode 15c of the photoelectric conversion unit 15 is formed using metal nitride, bonding via a flat interface can be realized. By suppressing the unevenness of the surface of the second electrode 15c, smooth charge transport between the second electrode 15c and the photoelectric conversion film 15b can be realized. In addition, generation of levels due to interface defects can be suppressed, and dark current can be suppressed. Thus, forming both the upper electrode 62u of the capacitive element 62 and the second electrode 15c of the photoelectric conversion unit 15 from metal nitride is advantageous from the viewpoint of reducing leakage current and dark current. Furthermore, if the lower electrode 62b of the capacitive element 62 is formed using metal nitride, it is beneficial because the flatness of the upper electrode 62u can be further improved. Further, it is useful because oxidation of the dielectric layer 62d can be suppressed.

(First Modification of Fourth Embodiment)
FIG. 22 schematically shows still another example of the device structure of the unit pixel cell. FIG. 23 shows an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b when the unit pixel cell 60B shown in FIG. 22 is viewed from the normal direction of the semiconductor substrate 2. FIG. 22 is a view corresponding to the cross-sectional view taken along the line CC ′ shown in FIG. The main difference between the unit pixel cell 60B shown in FIGS. 22 and 23 and the unit pixel cell 60A described with reference to FIGS. 20 and 21 is that the upper electrode 62u and the lower electrode 62b are reset, respectively. This is connected to the drain node 46 and the sensitivity adjustment line 32.

  As shown in FIG. 22, in this example, the upper electrode 62u is a part of the wiring layer 6s via the connecting portion 64b, the via vc2, the wiring layer 6b, the via vb2, the wiring layer 6a, and the via va2. It is connected to the. The wiring 6 w has a connection with the reset drain node 46. That is, the upper electrode 62 u has a connection with the reset drain node 46. On the other hand, the lower electrode 62b is connected to the wiring 6z through the via vc3, the wiring layer 6b, the via vb3, the wiring layer 6a, and the via va3. As described above, the wiring 6z has a connection with the sensitivity adjustment line 32 (not shown in FIG. 22). That is, the lower electrode 62 b has a connection with the sensitivity adjustment line 32. That is, the capacitive element 62 is connected between the reset drain node 46 and the sensitivity adjustment line 32 also in this example. Accordingly, the capacitive element 62 functions in the same manner as the second capacitive element 42 described above. In this example, since the lower electrode 62 b has a connection with the sensitivity adjustment line 32, the potential of the lower electrode 62 b can be controlled via the sensitivity adjustment line 32. By controlling the potential of the lower electrode 62b, the potential of the charge storage node 44 can be controlled to adjust the sensitivity of the imaging device. Further, when a constant voltage is supplied to the lower electrode 62b via the sensitivity adjustment line 32 during the operation of the imaging apparatus, the lower electrode 62b can function as a shield electrode.

  As shown in FIG. 22, in this example, the upper electrode 41x that connects the source or drain of the first reset transistor 36 (source / drain diffusion layer 2d) and the gate electrode 34e of the amplification transistor 34 has a second capacitance. It does not extend above the upper electrode 42e of the element 42. In other words, the upper electrode 41 x does not overlap the upper electrode 42 e when viewed from the normal direction of the semiconductor substrate 2. Therefore, the unit pixel cell 60B does not have the first capacitor element 41 configured by two polysilicon layers facing each other and the insulating film sandwiched between them in the interlayer insulating layer 4s.

  Here, paying attention to the photoelectric conversion unit 15 and the capacitive element 62, the second electrode 15c of the photoelectric conversion unit 15 and the upper electrode 62u of the capacitive element 62 face each other through the interlayer insulating layer 4d. As described above, in this example, the upper electrode 62 u has a connection with the reset drain node 46. That is, the capacitive element 41B formed by the second electrode 15c, the upper electrode 62u, and the interlayer insulating layer 4d can be regarded as a capacitive element connected between the charge storage node 44 and the reset drain node 46. For example, as can be seen from the circuit configuration shown in FIG. 2, the capacitive element 41 </ b> B functions in the same manner as the first capacitive element 41 described above. That is, in this example, the capacitive element is formed by connecting the capacitive element 41B, the capacitive element 62, and the second capacitive element 42 in series.

  In this manner, instead of the first capacitor element 41, the capacitor formed between the second electrode 15c of the photoelectric conversion unit 15 and the upper electrode 62u of the capacitor element 62 may be used as a low-capacitance capacitor element. Good. Even in such a configuration, as long as a sufficiently large capacitance value can be obtained by the capacitor 62, the second capacitor 42 formed as a so-called MIS capacitor can be omitted.

  For example, like the upper electrode 41w shown in FIG. 20, the upper electrode 41x may extend over the upper electrode 42e of the second capacitor element 42. However, it is advantageous that the upper electrode 41x does not overlap with the upper electrode 42e of the second capacitor element 42 from the viewpoint of reducing noise and suppressing conversion gain.

  The manufacturing method of the unit pixel cell 60B is the same as the manufacturing method of the unit pixel cell 60A, except that the resist mask pattern for forming the upper electrode 41x and the resist mask pattern for forming the wiring layer 6s are different. It can be almost the same. Therefore, description of the manufacturing method of the unit pixel cell 60B is omitted.

(Second modification of the fourth embodiment)
FIG. 24 schematically shows still another example of the device structure of the unit pixel cell. FIG. 25 illustrates an example of the arrangement of the upper electrode 62u, the dielectric layer 62d, and the lower electrode 62b when the unit pixel cell 60C illustrated in FIG. 24 is viewed from the normal direction of the semiconductor substrate 2. 24 is a view corresponding to the cross-sectional view taken along the line CC ′ shown in FIG. The main difference between the unit pixel cell 60C shown in FIGS. 24 and 25 and the unit pixel cell 60A described with reference to FIGS. 20 and 21 is that, instead of the first capacitor element 41, the lower electrode 62b. The low-capacitance capacitive element 41C is formed in the interlayer insulating layer as one electrode.

  In the unit pixel cell 60C illustrated in FIG. 24, similarly to the unit pixel cell 60A described with reference to FIG. 20, the lower electrode 62b and the upper electrode 62u are connected to the reset drain node 46 and the sensitivity adjustment line 32, respectively. ing. Similarly to the unit pixel cell 60B described with reference to FIG. 22, the unit pixel cell 60C does not include the first capacitor element 41 in the interlayer insulating layer 4s.

  In the configuration illustrated in FIG. 24, the wiring layer 6b formed in the interlayer insulating layer 4b includes an electrode 6bx disposed between the via vc and the via vb. As schematically shown in FIGS. 24 and 25, the electrode 6bx has a portion overlapping the lower electrode 62b when viewed from the normal direction of the semiconductor substrate 2. That is, at least a part of the electrode 6bx faces at least a part of the lower electrode 62b via at least a part of the interlayer insulating layer 4c. Thereby, the capacitive element 41C is formed between the capacitive element 62 and the wiring layer (here, the electrode 6bx) disposed in the interlayer insulating layer (here, the interlayer insulating layer 4c). Of the interlayer insulating layer 4c, a portion sandwiched between the lower electrode 62b and the electrode 6bx functions as a dielectric layer in the capacitive element 41C. Since the lower electrode 62b has a connection with the reset drain node 46 and the electrode 6bx has a connection with the second electrode 15c, the capacitive element 41C functions in the same manner as the first capacitive element 41 described above. In other words, in this example, the capacitive element is formed by connecting the capacitive element 41C, the capacitive element 62, and the second capacitive element 42 in series.

  In this manner, a capacitive element may be formed between the capacitive element 62 and the wiring layer disposed in the interlayer insulating layer. According to such a configuration, a low-capacitance (for example, about 0.5 fF) capacitive element can be disposed in the unit pixel cell relatively easily. In this example, a part of the wiring layer 6b (here, the electrode 6bx) is used as one electrode in the low-capacitance capacitive element, but the one electrode in the low-capacitance capacitive element is the wiring layer 6a or 6s, etc. It may be a part of another wiring layer. Also in the configuration described with reference to FIGS. 24 and 25, the second capacitive element 42 formed as a so-called MIS capacitor can be omitted if a sufficiently large capacitance value is obtained by the capacitive element 62.

  The manufacturing method of the unit pixel cell 60C is almost the same as the manufacturing method of the unit pixel cell 60A, except that the resist mask pattern for forming the upper electrode 41x and the resist mask pattern for forming the electrode 6bx are different. It can be the same. Therefore, description of the manufacturing method of the unit pixel cell 60C is omitted.

(Fifth embodiment)
The camera system 105 according to the present embodiment will be described with reference to FIG.

  FIG. 26 schematically illustrates a configuration example of the camera system 105 according to the present embodiment. The camera system 105 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604.

  The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and a diaphragm. The lens optical system 601 collects light on the imaging surface of the imaging device 602. As the imaging device 602, the imaging devices according to the first to fourth embodiments described above can be widely used.

  A system controller 603 controls the entire camera system 105. The system controller 603 can be realized by a microcomputer, for example.

  The camera signal processing unit 604 functions as a signal processing circuit that processes an output signal from the imaging device 602. The camera signal processing unit 604 performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance, for example. The camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor).

  According to the camera system according to the present embodiment, reset noise (kTC noise) at the time of reading can be appropriately suppressed by using the imaging device according to the first to fourth embodiments. As a result, charges can be read out accurately and a good image can be acquired.

  In addition, as described in detail in the first embodiment, it is possible to switch between a mode in which the subject can be imaged with bright and low sensitivity and a mode in which the subject is dark and capable of imaging with relatively high sensitivity. It is possible to realize a simple camera system.

  According to the embodiments of the present disclosure, kTC noise may be reduced. Further, since the dynamic range can be expanded with a simple configuration, it is useful for digital cameras and the like.

2 Semiconductor substrate 2d Drain diffusion layer 2s Element isolation region 2w Wells 4a-4d, 4s Interlayer insulating layers 6a, 6b, 6s Wiring layer 6bx Electrode 6w, 6z Wirings 11-14, 14a, 14b Unit pixel cell 15 Photoelectric conversion unit 15a First 1 electrode 15b photoelectric conversion film 15c second electrode 15h light receiving surface 16 vertical scanning circuit 17 accumulation control line 18 vertical signal line 19 load circuit 20 column signal processing circuit 21 horizontal signal readout circuit 22 power supply wiring 23 horizontal common signal line 24 inverting amplifier 24a Gain adjustment terminal 25 Feedback line 26 Reset signal line 27, 27 'Constant current source 28 Feedback control line 30 Address signal line 32 Sensitivity adjustment line 34 Amplifying transistor 34c Channel region 34e Gate electrode 34g Gate insulating film 36 First reset transistor 36c Channel Region 36e Gate electrode 36g gate insulating film 38 second reset transistor 38c channel region 38e gate electrode 38g gate insulating film 40 address transistors 41, 41B, 41C first capacitor element 41g dielectric layer 41w, 41x upper electrode 42 second capacitor element 42c Electrode region 42e Upper electrode 42g Dielectric layer 43 Third capacitor 43e Upper electrode 43g Dielectric layer 44 Charge storage node 45 Capacitor circuit 46 Reset drain node 50, 50 'Switching circuit 51 Switch element 51' Switch element 52 Switch element 52 ' Switch element 53a First switch 53b Second switch 54 Voltage switching circuit 60A-60C Unit pixel cell 62 Capacitance element 62b Lower electrode 62d Dielectric layer 62u Upper electrode 101, 602 Imaging device 105 Camera system 601 Lens optical system 602 Image device 603 System controller 604 Camera signal processing unit

Claims (7)

A photoelectric conversion unit that photoelectrically converts incident light to generate an electrical signal, a signal detection circuit that detects the electrical signal, and a first capacitor and a second capacitor having a capacitance value larger than the first capacitor are connected in series. A unit pixel cell including a capacitance circuit;
A feedback circuit that forms a feedback path for negatively feeding back the electrical signal,
The photoelectric conversion unit includes a photoelectric conversion film, a first electrode formed on a light receiving surface side of the photoelectric conversion film, and a second electrode formed on a surface opposite to the first electrode of the photoelectric conversion film; Have
The signal detection circuit includes a first transistor that has a gate connected to the second electrode, amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and one of a source and a drain connected to the second electrode. A connected second transistor;
The first capacitor is electrically connected between the source and the drain of the second transistor;
The second capacitor is electrically connected to the other of the source and the drain of the second transistor;
The feedback circuit includes the first transistor and an inverting amplifier in a part of the feedback path, and the electrical signal is passed through the first transistor and the inverting amplifier to the source of the second transistor and Electrically negative feedback to the other of the drains,
The capacitance circuit is provided between the second electrode and a reference potential.
Imaging device. A photoelectric conversion unit that photoelectrically converts incident light to generate an electrical signal, a signal detection circuit that detects the electrical signal, and a first capacitor and a second capacitor having a capacitance value larger than the first capacitor are connected in series. A unit pixel cell including a capacitance circuit;
A feedback circuit that forms a feedback path for negatively feeding back the electrical signal,
The photoelectric conversion unit includes a photoelectric conversion film, a first electrode formed on a light receiving surface side of the photoelectric conversion film, and a second electrode formed on a surface opposite to the first electrode of the photoelectric conversion film; Have
The signal detection circuit includes a first transistor that amplifies and outputs a signal voltage corresponding to the potential of the second electrode, and a second transistor having one of a source and a drain connected to the second electrode. ,
The first capacitor is electrically connected between the source and the drain of the second transistor;
The second capacitor is electrically connected to the other of the source and the drain of the second transistor;
The feedback circuit electrically negatively feeds back the electrical signal to the other of the source and the drain of the second transistor,
The capacitance circuit is provided between the second electrode and a reference potential.
Imaging device. The feedback circuit includes the first transistor and an inverting amplifier in a part of the feedback path, and the electrical signal is passed through the first transistor and the inverting amplifier to the source of the second transistor and Electrically negative feedback to the other of the drains,
The imaging device according to claim 2 . Switching the amount of change in potential of the second electrode by turning on and off the second transistor;
The imaging device according to any one of claims 1 to 3 . The signal detection circuit further includes a third transistor that selectively outputs the output of the first transistor to the feedback circuit.
The imaging device according to any one of claims 1 to 4 . The signal detection circuit further includes a fourth transistor that selectively transmits the electrical signal fed back by the feedback circuit to the other of the source and the drain of the second transistor.
The imaging device according to any one of claims 1 to 5 . The signal detection circuit includes a fourth transistor that is electrically connected between the source and the drain of the second transistor and selectively transmits the electric signal fed back by the feedback circuit to the first capacitor. In addition,
The imaging device according to any one of claims 1 to 5 .

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