JP2013030820A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lamination type solid-state image pickup device having small noise.SOLUTION: A solid state image pickup device has plural pixels 11 arranged in a matrix form, vertical signal lines 141 formed every column, and a load portion 23 connected to the vertical signal lines. The pixel 11 has an amplifying transistor 113, an address transistor 115, a reset transistor 117 and a photoelectric conversion portion 111. The photoelectric conversion portion 111 contains a photoelectric conversion film formed on a semiconductor substrate, a pixel electrode formed on a surface at the substrate side of the photoelectric conversion film, and a transparent electrode formed on the surface at the opposite side to the pixel electrode of the photoelectric conversion film. The reset transistor 117 has a source connected to the pixel electrode and a drain connected to a power supply line together with the drain of the amplifying transistor 113, and the load 23 contains negative resistance 23B.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a stacked solid-state imaging device.

  In recent years, a photodiode is provided inside a semiconductor substrate made of crystalline silicon, and a pixel of a CCD type or MOS type solid-state imaging device using a CCD (Charge Coupled Device) or a MOS (Metal Oxide Semiconductor) as a scanning circuit has rapidly become finer. It has become. The pixel size, which was 3 μm around 2000, became 2 μm or less in 2007. A solid-state imaging device with a pixel size of 1.4 μm is scheduled to be put into practical use in 2010, and it is expected that a pixel size of 1 μm or less can be realized within a few years as the pixel size becomes finer at this pace. The

  However, in order to realize a pixel size of 1 μm or less, the inventor of the present application needs to solve the first problem caused by the small light absorption coefficient of crystalline silicon and the second problem related to the amount of handled signals. Found. The first problem will be described in detail. The light absorption coefficient of crystalline silicon depends on the wavelength of light. In order to absorb the green light near the wavelength of 550 nm, which determines the sensitivity of the solid-state imaging device, almost completely and to perform photoelectric conversion, crystalline silicon having a thickness of about 3.5 μ is required. Therefore, the depth of the photodiode formed inside the semiconductor substrate needs to be about 3.5 μm. When the planar pixel size is 1 μm, it is very difficult to form a photodiode with a depth of about 3.5 μm. Assuming that a photodiode with a depth of about 3.5 μm could be formed However, there is a high possibility that a problem that light incident obliquely enters a photodiode of an adjacent pixel will occur. When light incident obliquely enters a photodiode of an adjacent pixel, color mixing (crosstalk) occurs, which is a big problem in a color solid-state imaging device. If the photodiode is formed to be shallower than this in order to prevent color mixing, the green light absorption efficiency deteriorates and the sensitivity of the image sensor deteriorates. In pixel miniaturization, since the pixel size is reduced, the sensitivity of one pixel is lowered. In addition to this, it is fatal that the light absorption efficiency is lowered.

  To describe the second problem in detail, the amount of signal to be handled is determined by the saturation charge amount of an embedded photodiode that is a photodiode structure used in a general solid-state imaging device. The embedded photodiode has an advantage that the signal charge accumulated inside can be transferred almost completely to the adjacent charge detection section (complete transfer). For this reason, noise related to charge transfer hardly occurs, and the embedded photodiode is widely used in solid-state imaging devices. However, the capacity per unit area of the photodiode cannot be increased in order to realize complete transfer. For this reason, when the pixel is miniaturized, a decrease in saturation charge becomes a problem. In a compact digital camera, a saturation electron number of 10,000 electrons per pixel is required, but when the pixel size is about 1.4 μm, the saturation electron number is limited to about 5000 electrons. At present, it is possible to reduce the number of saturated electrons by creating an image by noise suppression processing using a digital signal processing technique, but it is difficult to obtain a natural reproduced image. Furthermore, in the case of a high-grade single-lens reflex camera, it is said that a saturation electron number of about 30000 electrons per pixel is necessary.

  Note that, in a MOS type image sensor using a crystalline silicon substrate, a structure in which light is incident from the back surface side rather than the front surface side where the pixel circuit is formed by thinly cutting the substrate has been studied. However, it is only possible to avoid that the incident light is hindered by the wiring or the like constituting the pixel circuit, and the first problem and the second problem cannot be solved.

  A promising technique for solving these two problems is a stacked solid-state imaging device (see, for example, Patent Document 1). A stacked solid-state imaging device has a configuration in which a photoelectric conversion film is formed on a semiconductor substrate on which a pixel circuit is formed via an insulating film. For this reason, it is possible to use a material having a large light absorption coefficient such as amorphous silicon for the photoelectric conversion film. For example, in the case of amorphous silicon, green light having a wavelength of 550 nm can be almost absorbed with a thickness of about 0.4 nm.

  In addition, since the embedded photodiode is not used, the capacity of the photoelectric conversion unit can be increased and the saturation charge can be increased. Further, since the charge is not completely transferred, it is possible to add an additional capacitor positively, and a sufficiently large capacity can be realized even in a miniaturized pixel, and the second problem can be solved. A structure like a stack cell in a dynamic random access memory may be used.

JP 58-050030 A

  However, the conventional stacked solid-state imaging device has a problem of large random noise. In the conventional stacked solid-state imaging device, noise is generated when the signal charge is reset. Since the next signal charge is added in a state where noise is generated, the signal charge superimposed with the reset noise is read out. For this reason, random noise increases.

  An object of the present invention is to solve the above-described problems and to realize a stacked solid-state imaging device with low noise.

  In order to achieve the above-mentioned object, the present invention connects a solid-state imaging device with a drain of an amplification transistor and a drain of a reset transistor directly or via an address transistor, and uses a negative resistance load as a load of a vertical signal line. The reset noise reduction means is provided.

  Specifically, the first solid-state imaging device includes a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, a vertical signal line formed for each column, and a load unit connected to the vertical signal line. The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit. The photoelectric conversion unit is formed on a surface of the photoelectric conversion film on the substrate side of the photoelectric conversion film formed on the semiconductor substrate. And a transparent electrode formed on a surface opposite to the pixel electrode of the photoelectric conversion film. The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line, and a drain The reset transistor is connected to the power supply line, the source is connected to the pixel electrode, the drain is connected to the power supply line, and the address transistor is connected between the source of the amplification transistor and the vertical signal line. Is connected between the drain and the power line, the load unit includes a negative resistance.

  In the first solid-state imaging device, the load unit includes a negative resistance. For this reason, the gain of the source follower circuit constituted by the amplification transistor and the load unit can be made larger than one. Therefore, the noise at the time of reset can be significantly reduced. Further, since the drain of the reset transistor is connected to the power supply line together with the drain of the amplification transistor, an element isolation region for separating the reset transistor and the amplification transistor is not necessary, and the solid-state imaging device can be reduced.

  In the first solid-state imaging device, the resistance unit includes a negative resistance and a positive resistance. When the pixel signal is reset, the negative resistance is connected to the vertical signal line and the signal is read from the pixel. The positive resistor may be connected to the vertical signal line.

  In the first solid-state imaging device, the negative resistance is a gain of the source follower circuit formed by the amplification transistor and the negative resistance from 1 to (Cs + Cox) / Cox (where Cs is a capacitance value of the storage capacitor) Yes, Cox may be set to be between the capacitance value of the gate insulating film of the amplification transistor.

  In the first solid-state imaging device, when a signal is read from the pixel, the gain of the source follower circuit formed by the amplification transistor and the negative resistance may be smaller than that when the signal of the pixel is reset.

  In the first solid-state imaging device, the pixel may have a zero bias capacitance connected to the pixel electrode.

  The second solid-state imaging device includes a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, a vertical signal line formed for each column, and a differential in which one terminal is connected to the vertical signal line. The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit. The photoelectric conversion unit includes a photoelectric conversion film formed on a semiconductor substrate, and a substrate side surface of the photoelectric conversion film. And a transparent electrode formed on a surface opposite to the pixel electrode of the photoelectric conversion film. The amplification transistor has a gate connected to the pixel electrode and a source connected to the vertical signal line via the address transistor. The reset transistor has a source connected to the pixel electrode, and an output terminal of the differential amplifier is connected to the amplifying transistor and reset transistor provided in the corresponding column. And it is connected to the Inn.

  In the second solid-state imaging device, the output terminal of the differential amplifier whose one terminal is connected to the vertical signal line is connected to the drains of the amplification transistor and the reset transistor provided in the corresponding column. For this reason, noise generated in the reset transistor can be negatively fed back. Therefore, it is possible to greatly reduce noise at the time of reset. In addition, an element isolation region for separating the reset transistor and the amplification transistor is not necessary, and the solid-state imaging device can be reduced. In addition, since the feedback wiring provided for noise suppression is shared with the power supply wiring, it is effective for pixel miniaturization.

  A third solid-state imaging device includes a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, an address drain line formed for each column, a vertical signal line formed for each column, A pixel having a differential amplifier connected to a vertical signal line, a pixel having an amplifying transistor, an address transistor, a first feedback transistor, and a photoelectric conversion unit, the photoelectric conversion unit being formed on a semiconductor substrate; A photoelectric conversion film, a pixel electrode formed on the surface of the photoelectric conversion film on the substrate side, and a transparent electrode formed on the surface opposite to the pixel electrode of the photoelectric conversion film. The first feedback transistor has a source connected to the pixel electrode and a drain connected to the address transistor along with the drain of the amplifying transistor. The drain of the address transistor is connected to the corresponding address drain line for each column, and the address drain line is connected to the power supply line and the output terminal of the differential amplifier in the corresponding column via a switch. ing.

  In the third solid-state imaging device, the drain of the first feedback transistor is connected to the source of the address transistor together with the drain of the amplification transistor, the drain of the address transistor is connected to the corresponding address drain line for each column, The power supply line and the output terminal of the differential amplifier in the corresponding column are connected through the switch. For this reason, not only the noise at the time of reset can be negatively fed back, but also a rolling reset operation for suppressing noise for each column is possible. In addition, since the feedback wiring provided for noise suppression is shared with the power supply wiring, it is effective for pixel miniaturization.

  In the third solid-state imaging device, the pixel may have a second feedback transistor and a feedback capacitor connected between the source of the first feedback and the pixel electrode. In addition, the configuration may include a feedback capacitor connected between the source of the first feedback and the pixel electrode, and a second feedback transistor connected between the pixel electrode and the source of the address transistor. Good. With such a configuration, it is possible to reduce noise with a feedback capacitor having a small capacitance value.

Furthermore, in the third solid-state imaging device, the pixel includes a feedback capacitor connected between the source of the first feedback transistor and the pixel electrode, and a reset transistor whose source is connected to the pixel electrode. It is good.
With such a configuration, noise can be reduced by a feedback capacitor having a small capacitance value, and dark current can also be reduced.

  A fourth solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, a power supply line formed for each column, and a vertical signal line formed for each column. A differential amplifier having one terminal connected to the vertical signal line, and a load unit connected to the vertical signal line. The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit. The photoelectric conversion unit includes a photoelectric conversion film formed on the semiconductor substrate, a pixel electrode formed on the substrate side surface of the photoelectric conversion film, and a transparent surface formed on the surface opposite to the pixel electrode of the photoelectric conversion film. The amplification transistor includes a gate, the gate is connected to the pixel electrode, the source is connected to the vertical signal line, the drain is connected to the power supply line, and the reset transistor is connected to the pixel electrode and the drain is electrically connected. The address transistor is connected between the source of the amplification transistor and the vertical signal line or between the drain of the amplification transistor and the power supply line, and the output of the differential amplifier is coupled to the vertical signal line. It is characterized by that.

  In the fourth solid-state imaging device, the output of the differential amplifier is coupled to the vertical signal line. For this reason, the voltage of the vertical signal line can be inverted and negative feedback can be applied to the vertical signal line. Accordingly, it is possible to reduce noise during reset.

  In the fourth solid-state imaging device, the pixel may have a zero bias capacitance connected to the pixel electrode.

  The solid-state imaging device according to the present invention can realize a stacked solid-state imaging device with low noise.

1 is a circuit diagram illustrating a solid-state imaging device according to a first embodiment. It is sectional drawing which shows the pixel cell of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows the negative resistance of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows the negative resistance of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows a source follower circuit. It is a current-voltage characteristic figure which shows operation | movement of a source follower circuit. (A)-(c) is an enlarged view of the current-voltage characteristic of a source follower circuit, (a) is a case where the resistance value of a load is infinite, (b) is a case where a load is a positive resistance load. Yes, (c) is the case where the load is a negative resistance load. (A) And (b) is a potential of the driver transistor of the source follower circuit, (a) is a diagram showing a case where the load is a positive resistance load, and (b) is a case where the load is a statically high load. FIG. It is a circuit diagram which shows a part of pixel cell of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows the solid-state imaging device which concerns on the modification of 1st Embodiment. It is a circuit diagram which shows the solid-state imaging device which concerns on 2nd Embodiment. It is a circuit diagram which shows the solid-state imaging device which concerns on 3rd Embodiment. It is a circuit diagram which shows the solid-state imaging device which concerns on 4th Embodiment. (A) And (b) shows the state of the transistor in weak inversion operation | movement, (a) is a circuit diagram, (b) is a figure which shows the state of an electric potential. (A) And (b) shows the state of the transistor in weak inversion feedback operation | movement, (a) is a circuit diagram, (b) is a figure which shows the state of an electric potential. (A) And (b) shows the state of the transistor at the time of capacitive insertion weak inversion feedback operation, (a) is a circuit diagram, (b) is a figure which shows the state of an electric potential. It is a circuit diagram which shows the modification of the solid-state imaging device which concerns on 4th Embodiment. It is a circuit diagram which shows the solid-state imaging device which concerns on 5th Embodiment.

(First embodiment)
FIG. 1 shows a circuit configuration of a solid-state imaging device according to this embodiment. As shown in FIG. 1, a plurality of pixels 11 arranged in a matrix, a vertical scanning unit 13 for supplying various timing signals to the pixels 11, and a horizontal signal reading unit for sequentially reading the signals of the pixels 11 to a horizontal output 142 15. In FIG. 1, the pixel 11 describes only two rows and two columns, but the number of rows and the number of columns may be arbitrarily set.

  The pixel 11 includes a photoelectric conversion unit 111, an amplification transistor 113 whose gate is connected to the photoelectric conversion unit 111, a reset transistor 117 whose source is connected to the photoelectric conversion unit 111, and a drain that is connected to the source of the amplification transistor 113. Address transistor 115. The photoelectric conversion unit 111 is connected between the gate of the amplification transistor 113 and the source of the reset transistor 117 and the photoelectric conversion unit control line 131. The source of the address transistor 115 is connected to the corresponding vertical signal line 141. The gate of the address transistor 115 is connected to the vertical scanning unit 13 via the address control line 121. The gate of the reset transistor 117 is connected to the vertical scanning unit 13 through the reset control line 123. The drain of the amplification transistor 113 and the drain of the reset transistor 117 are connected to a power source (not shown) via the drain control line 133.

  The vertical signal line 141 is provided for each column and is connected to the horizontal signal reading unit 15 through the column signal processing unit 21. The column signal processing unit 21 performs noise suppression signal processing represented by correlated double sampling, analog-digital conversion, and the like. Further, the load unit 23 is connected to the vertical signal line 141. The load unit 23 includes a load resistor 23A and a negative resistor 23B, which are normal positive resistors. The load resistor 23A and the negative resistor 23B are connected to the vertical signal line 141 via the first switch 143 and the second switch 144, respectively. The address control line 121 and the reset control line 123 are provided for each row. The photoelectric conversion unit control line 131 and the drain control line 133 are common to all pixels. Although the amplification transistor 113 and the address transistor 115 are arranged in series, there is no problem in operation even if this positional relationship is switched. Therefore, the source of the amplification transistor 113 may be directly connected to the vertical signal line 141, and the drain may be connected to the drain control line 133 via the address transistor 115. Further, a constant current load may be provided instead of the load resistance 23A which is a positive resistance.

  The solid-state imaging device of this embodiment is a stacked solid-state imaging device, and each pixel 11 has the following configuration. FIG. 2 shows a cross-sectional configuration of the pixel 11 in the solid-state imaging device of the present embodiment. As shown in FIG. 2, an amplification transistor, an address transistor, and a reset transistor are formed on a semiconductor substrate 31 made of silicon. The amplification transistor includes a gate electrode 41, a diffusion layer 51 that is a source, and a diffusion layer 52 that is a drain. The address transistor includes a gate electrode 42, a diffusion layer 52 that is a source, and a diffusion layer 53 that is a drain. The reset transistor includes a gate electrode 43, a diffusion layer 55 that is a source, and a diffusion layer 51 that is a drain. The source of the amplification transistor and the drain of the address transistor are a common diffusion layer, and the drain of the amplification transistor 113 and the drain of the reset transistor are a common diffusion layer.

  An insulating film 35 is formed on the semiconductor substrate 31 so as to cover each transistor. A photoelectric conversion unit 111 is formed on the insulating film 35. The photoelectric conversion unit 111 includes a photoelectric conversion film 45 made of amorphous silicon or the like, a pixel electrode 46 formed on the lower surface of the photoelectric conversion film 45, and a transparent electrode 47 formed on the upper surface of the photoelectric conversion film 45. . The pixel electrode 46 is connected to the gate electrode 41 of the amplification transistor and the diffusion layer 54 that is the source of the reset transistor via the contact 36. The diffusion layer 54 connected to the pixel electrode 46 functions as a storage diode.

  FIG. 3 shows a circuit configuration of the negative resistance 23B in the present embodiment. A load transistor 151 and an inverter circuit 152 are included. Since the inverted output of the inverter circuit 152 is connected to the gate of the load transistor 151, the current flowing through the circuit decreases when the voltage at the input terminal 150 increases. Conversely, when the voltage at the input terminal 150 decreases, the current flowing through the circuit increases. Note that the load transistor 151 and the inverter circuit 152 may be grounded via the transistor 153 as shown in FIG. In this way, the circuit can be operated differentially, so that the operation can be stabilized.

  The principle of reducing the reset noise by providing the negative resistance 23B will be described below. First, consider the operation of a source follower circuit comprising a driver transistor 161 as shown in FIG. 5 and a load transistor 162 having a constant voltage input to the gate. When the input voltage input to the gate of the driver transistor 161 is Vg, the drain current is Id, and the output voltage from the source is Vs, these relationships are as shown in FIG.

  The load transistor 162 exhibits a constant current characteristic with an infinite resistance in a saturation region in an ideal state. For this reason, in the ideal state, the current-voltage characteristic of the load transistor 162 becomes a load curve denoted by reference numeral A1 in FIG. On the other hand, the current of the driver transistor 161 increases as Vs decreases. For this reason, the current-voltage characteristic of the driver transistor is a parabolic driver curve labeled B1 in FIG. The intersection of the load curve A1 and the driver curve B1 becomes the operating point of the source follower circuit, and the output voltage of the source follower circuit is determined. When a signal is input to the gate of the driver transistor 161 and Vg rises, the driver curve B1 shifts to the right and becomes a driver curve B2. For this reason, the output of the source follower circuit increases. However, the actual load transistor 162 does not exhibit a constant current characteristic, but exhibits a positive resistance load characteristic that rises slightly to the right, due to a phenomenon called the Early effect. For this reason, it becomes a load curve like A2. On the other hand, when the load transistor is a negative resistance as in the present embodiment, the load curve is slightly lower right as shown by A3.

  FIGS. 7A to 7C are enlarged views of the operating point portion of the source follower circuit of FIG. As shown in FIG. 7A, when the load resistance is infinite and exhibits constant current characteristics, the change amount ΔVg of the input voltage Vg and the change amount ΔVs of the output voltage Vs are equal. Therefore, the gain G of the source follower circuit is 1. When the load is a positive resistance load, ΔVs is smaller than ΔVg as shown in FIG. For this reason, the gain G is less than 1. When the load is a negative resistance load, ΔVs is larger than ΔVg and the gain G is larger than 1 as shown in FIG.

  FIGS. 8A and 8B show the potential of each part of the driver transistor. In FIG. 8, the hatched portion shows a state where charges are accumulated. Electrons flow from the source S of the driver transistor under the gate G to the drain D. When an input signal is received, the channel potential of the gate G changes from Vc1 to Vc2. As shown in FIG. 8A, when the load is a positive resistance load, the output voltage change ΔVs at the source S is smaller than the channel potential change ΔVc, and the gain G is less than 1. Therefore, when the voltage of the gate G rises as shown in FIG. 8A, the amount of charge accumulated in the channel portion increases. The increased charge becomes a capacitance having a capacitance value of Cox (1-G) with respect to the gate. Cox in this case is the capacitance of the gate insulating film. This indicates that the capacitance of the input gate of the driver transistor increases as the gain G decreases.

  On the other hand, when the load is a negative resistance load, as shown in FIG. 8B, the change ΔVs in the output voltage becomes larger than the change ΔVc in the channel potential of the gate G, and the gain G becomes larger than 1. . For this reason, when the voltage of the gate G rises, the amount of electric charge accumulated in the channel portion decreases and becomes an electrically negative capacitance.

  FIG. 9 shows a part of the pixel cell in this embodiment. The storage capacitance Cs is the sum of the capacitance of the photoelectric conversion film, the capacitance of the source to which the pixel electrode is coupled, and other stray capacitance. The capacitance Cg of the gate of the amplification transistor 113 serving as the source follower circuit is Cox (1-G) as described above. The noise of the reset transistor 117 at the time of reset becomes √kT (Cs + Cg) in the charge region. That is, √kT (Cs + Cox (1−G)). If the gain G of the source follower circuit is set to be (Cs + Cox) / Cox, that is, 1 + Cs / Cox, noise can be reduced to zero.

  That is, by making the gain of the source follower circuit constituted by the amplification transistor 113 and the negative resistance 23B shown in FIG. 1 larger than 1, the noise at the time of reset can be significantly reduced. The closer the gain is to 1 + Cs / Cox, the greater the effect of reducing noise. In particular, the reset noise can be made almost zero by setting the gain of the source follower circuit to 1 + Cs / Cox. At this time, it is preferable to use a taper reset operation that moderates the fall time of the reset pulse. This is to make the noise band of the reset transistor narrower than the band of the source follower circuit.

  Further, the signal may be read out in a state where the negative resistor 23B is connected instead of the load resistor 23A. If the gain of the source follower circuit is set between 1 and 1 + Cs / Cox, the amplified signal can be read out.

  In the solid-state imaging device of this embodiment, the drain of the reset transistor 117 and the drain of the amplification transistor 113 are connected. Therefore, an element isolation region that separates the reset transistor 117 and the amplification transistor 113 is not necessary. Further, the drain of the reset transistor 117 and the drain of the amplification transistor 113 can be a common diffusion layer. Thereby, the area of the pixel cell can be reduced. For example, the area of the pixel cell is suppressed to about 75% as compared with the case where the reset transistor 117 and the amplification transistor are separated and separate wirings are connected to the source of the reset transistor 117 and the drain of the amplification transistor. It becomes possible.

  If a negative resistance is used for the load part of the source follower circuit of the first stage of the two-stage or three-stage source follower circuit used in the output circuit of the CCD image sensor, the gain of the source follower circuit is improved and noise is reduced. It is valid.

(One modification of the first embodiment)
FIG. 10 shows a solid-state imaging device according to a modification of the first embodiment. A zero bias capacitor 118 is connected between the gate of the amplification transistor 113 and the zero bias capacitor control line 125. The source voltage of the reset transistor 117 to be reset is held at the power supply voltage, but the power supply voltage is a positive high voltage. This may increase the dark current of the source. After resetting, dark current can be reduced by applying a negative pulse to the zero bias capacitor 118 to lower the source voltage during signal accumulation to near 0V.

(Second Embodiment)
FIG. 11 shows a circuit configuration of the solid-state imaging device according to the second embodiment. In FIG. 11, the same components as those in FIG.

  The solid-state imaging device according to the second embodiment includes a differential amplifier 221 in which a negative-side input (inverting input) terminal is connected to a vertical signal line 141. The output of the differential amplifier 221 is connected to the drain of the amplification transistor 113 and the drain of the reset transistor 117 via the driver 222.

  When the drain of the reset transistor 117 is fixed at the power supply potential, a large thermal noise is generated by the reset transistor 117 when the signal is reset. In the solid-state imaging device of this embodiment, a signal obtained by inverting and amplifying the output of the vertical signal line 141 is input to the drain of the reset transistor 117. As a result, the noise generated in the reset transistor 117 can be suppressed by negative feedback. Since the source follower circuit constituted by the amplification transistor 113 does not affect the characteristics even when the power supply fluctuates, such a circuit configuration is not problematic.

  Depending on the driving capability of the differential amplifier 221, the output of the differential amplifier 221 may be directly connected to the drain of the amplification transistor 113 and the drain of the reset transistor 117 without passing through the driver 222. Further, such driving may be performed only at the time of resetting, and the drain of the amplification transistor 113 and the drain of the reset transistor 117 may be connected to a fixed power supply voltage at the time of signal reading. Furthermore, a zero bias capacitance may be added to the gate of the amplification transistor.

  The solid-state imaging device of this embodiment also connects the drain of the reset transistor 117 and the drain of the amplification transistor 113. Therefore, an element isolation region that separates the reset transistor 117 and the amplification transistor 113 is not necessary. Further, the drain of the reset transistor 117 and the drain of the amplification transistor 113 can be a common diffusion layer, and the area of the pixel cell can be reduced.

  As in the first embodiment, there is no problem even if the arrangement of the amplification transistor 113 and the address transistor 115 is switched.

(Third embodiment)
FIG. 12 shows a circuit configuration of a solid-state imaging device according to the third embodiment. In FIG. 12, the same components as those in FIG.

  In the first embodiment and the second embodiment, a solid-state imaging device of a rolling reset operation that performs noise suppression for each column is shown. The solid-state imaging device of this embodiment can perform noise suppression in a global reset that resets all pixels simultaneously. As shown in FIG. 12, a feedback transistor 311 is connected between the amplification transistor 113 and the address transistor 115. Further, a differential amplifier 321 having a negative input connected to the vertical signal line 141 is provided. The output of the differential amplifier 321 is connected to the drain of the address transistor 115 via the switch 323. The drain of the address transistor 115 is connected to the drain control line 133 via the switch 324. The switch 323 is turned off, the switch 324 is turned on, and then the address transistors 115 of all the pixels are turned off. As a result, the drain voltage of the amplification transistor 113 decreases, and the voltage is fed back to the gate of the amplification transistor 113 via the feedback transistor 311. Therefore, the feedback operation can be performed simultaneously on all the pixels. In the solid-state imaging device of this embodiment, the feedback transistor 311 functions as a reset transistor. When the switch 324 is turned off, the switch 323 is turned on, and the output of the differential amplifier 321 is fed back to the gate of the amplification transistor 113 as a noise suppression voltage via the address transistor 115 and the feedback transistor 311 for each line. A rolling reset operation can be performed.

  Also in this embodiment, a zero bias capacitor can be connected to the gate of the amplification transistor 113. It is preferable to set the gate voltage of the amplifying transistor 113 to a positive voltage in the vicinity of 0 V by the zero bias capacitance after the reset operation is completed in both the case of all pixel reset and the case of rolling reset. Thereby, the voltage of the source / drain diffusion layer of the address transistor 311 connected to the gate voltage of the amplification transistor 113 can be lowered, and the dark current generated in the source / drain diffusion layer of the address transistor 311 can be suppressed.

(Fourth embodiment)
FIG. 13 shows a circuit configuration of a solid-state imaging device according to the fourth embodiment. In FIG. 13, the same components as those of FIG. As shown in FIG. 13, a first feedback transistor 411 and a second feedback transistor 412 are connected between the amplification transistor 113 and the address transistor 115. The source of the second feedback transistor is connected to the gate of the amplification transistor 113, the source of the first feedback transistor 411 is connected to the drain of the second feedback transistor 412, and the amplification transistor 113 is connected via the feedback capacitor 413. Connected to the gate. The gate of the first feedback transistor 411 and the gate of the second feedback transistor 412 are connected to the vertical scanning unit 13 via the first feedback transistor control line 431 and the second feedback transistor control line 432, respectively. Further, a differential amplifier 421 having a negative input connected to the vertical signal line 141 is provided. When all pixels are reset, first, the address transistors 115, the first feedback transistors 411, and the second feedback transistors 412 of all the pixels are turned on, and the first feedback operation is performed as in the third embodiment. . Thereafter, in order to further suppress noise, the second feedback transistor 412 is turned off, and a second feedback operation is performed via the feedback capacitor 413 in series. As will be described later, such an operation can further improve the noise suppression effect. The second feedback operation has a larger noise suppression effect, but the DC component of the signal charge accumulated at the gate of the amplification transistor 113 cannot be reset only by the second feedback operation. For this reason, the first feedback operation is necessary. Regarding the rolling reset, the first feedback transistor 411 and the second feedback transistor 412 may be turned on and performed in the same manner as in the third embodiment. It is also possible to further improve the noise suppression effect by turning off the second feedback transistor 412.

  The solid-state imaging device of the present embodiment has a feedback capacitor 413, and noise can be reduced by reducing the capacitance value of the feedback capacitor 413. Noise can also be reduced when performing a rolling reset.

The principle that noise can be reduced by providing the feedback capacitor 413 is as follows. 14A shows a transistor in which a capacitor C is connected to the source S, a bias voltage Vd is applied to the drain D, and the voltage of the gate G is fixed, and FIG. 14B shows the potential of each part. Since the source S is in a floating state, the potential gradually increases when electrons flow to the drain D. When the potential of the channel formed under the gate G and the potential of the source are approximately the same, a current flows due to thermal diffusion of electrons called weak inversion current. The noise in this case is √ (kTC / 2) in the charge region. This is due to the fact that when one electron jumps from the source, the potential of the source rises by q / C, so that the probability of the next jumping electron becomes exp (q ² / kTC) times smaller.

FIG. 15A shows a transistor in which the bias voltage Vs is applied to the source S, and the drain D and the gate G are connected to the capacitor C, and FIG. 15B shows the potential of each part. In this case, electrons flow from the source S to the drain D, and when the potential of the drain D decreases, the voltage of the gate G also decreases, so that the inflow of electrons from the source S gradually decreases. The noise in this case becomes √ (kTC / 2) because when one electron jumps out, the probability of the next electron jumping becomes exp (q ² / kTC) times smaller.

In FIG. 16A, a bias voltage Vs is applied to the source S, a capacitor Cp is connected to the gate G, a gate G and a drain D are connected to the capacitor C, and a minute capacitor C0 is connected between the drain D and the gate G. (B) shows the potential of each part. The capacitor Cp connected to the gate G imagines the capacitance of the photoelectric conversion film. When C0 is sufficiently smaller than C and Cp, when one electron jumps out of the source S, the probability that the next electron jumps out is smaller by exp (q ² / kTC · (C0 / Cp)). As a result, the noise at the drain D increases to √ (kTC · Cp / 2C0). However, the noise at the gate G is reduced to √ (kTC · C0 / 2Cp). When C and Cp are substantially equal, the noise becomes √ (kTC0 / 2), and is converted into a small noise by the minute capacitance C0. Thus, by using the feedback capacitor 413 having a small capacitance value, it is possible to suppress noise by converting the capacitance.

  Here, the feedback is briefly described. When electrons jump from the source to the drain, the drain voltage decreases. The degree to which the drain voltage decreases increases as the gate voltage increases. Therefore, the drain voltage is inverted with respect to the gate voltage. Negative feedback can be applied by returning the drain voltage inverted to the gate voltage to the gate.

  As shown in FIG. 17, the pixel cell of this embodiment may have a configuration in which the drain of the second feedback transistor 412 is connected to the address transistor 115 instead of the source of the first feedback transistor 411. In this case, the same effect can be obtained.

  In this embodiment as well, a zero bias capacitor can be connected to the gate of the amplification transistor 113.

(Fifth embodiment)
FIG. 18 shows a circuit configuration of a solid-state imaging device according to the fifth embodiment. In FIG. 18, the same components as those in FIG. As shown in FIG. 18, a reset transistor 117 connected between the gate of the amplification transistor 113 and the reset bias line 145 is provided instead of the second feedback transistor. The solid-state imaging device of the present embodiment can suppress dark current by setting the voltage of the reset bias line 145 in the vicinity of 0V. Further, since the feedback capacitor 413 having a small capacitance value is used, a large noise suppression effect can be obtained. The solid-state imaging device of the present embodiment can reduce the dark current without adding a zero bias capacitance if the voltage of the reset bias line 145 is set near 0V. However, a zero bias capacity may be provided.

  In the third to fifth embodiments, the feedback transistor has a function as a reset transistor for resetting a signal.

  In each embodiment, an example of a so-called 1-pixel 1-cell structure in which a photoelectric conversion element, a transfer transistor, a floating diffusion, a reset transistor, and an amplification transistor are provided in each pixel is shown. However, a so-called multi-pixel 1-cell structure in which a plurality of photoelectric conversion elements are included in a pixel and any or all of the floating diffusion, the reset transistor, and the amplification transistor are shared in the pixel may be employed.

  The solid-state imaging device according to the present invention can realize a stacked solid-state imaging device with low noise, and is particularly useful as a small-sized image pickup device or the like.

11 Pixel 13 Vertical scanning unit 15 Horizontal signal reading unit 21 Column signal processing unit 23 Load unit 23A Load resistor 23B Negative resistance 31 Semiconductor substrate 35 Insulating film 36 Contact 41 Gate electrode 42 Gate electrode 43 Gate electrode 45 Photoelectric conversion film 46 Pixel electrode 47 Transparent electrode 51 Diffusion layer 52 Diffusion layer 53 Diffusion layer 54 Diffusion layer 55 Diffusion layer 111 Photoelectric converter 113 Amplifier transistor 115 Address transistor 117 Reset transistor 118 Zero bias capacitor 121 Address control line 123 Reset control line 125 Zero bias capacitor control line 131 Photoelectric conversion unit control line 133 Drain control line 141 Vertical signal line 142 Horizontal output 143 First switch 144 Second switch 145 Reset bias line 150 Input terminal 151 Load transistor 152 Inverter circuit 153 transistor 161 driver transistor 162 load transistor 221 differential amplifier 222 driver 311 feedback transistor 321 differential amplifier 323 switch 324 switch 411 first feedback transistor 412 second feedback transistor 413 feedback capacitor 421 differential amplifier 423 switch 424 switch 431 first 1 feedback transistor control line 432 2nd feedback transistor control line

Claims (12)

A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
Vertical signal lines formed for each column;
A load unit connected to the vertical signal line,
The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed on the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the substrate side, and a surface opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line, a drain connected to a power supply line,
The reset transistor has a source connected to the pixel electrode, a drain connected to a power supply line,
The address transistor is connected between a source of the amplification transistor and the vertical signal line or between a drain of the amplification transistor and the power line.
The load unit includes a negative resistance. The resistance unit includes the negative resistance and a positive resistance or a constant current load,
When resetting the signal of the pixel, the negative resistance is connected to the vertical signal line,
The solid-state imaging device according to claim 1, wherein when reading a signal from the pixel, the positive resistance or a constant current load is connected to the vertical signal line.   The negative resistance is such that the gain of a source follower circuit formed by the amplification transistor and the negative resistance is 1 to (Cs + Cox) / Cox (where Cs is a capacitance value of a storage capacitor, and Cox is the amplification transistor) 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is set to be between the first and second gate insulating films.   The gain of the source follower circuit formed by the amplification transistor and the negative resistance is smaller when resetting the signal of the pixel when reading the signal from the pixel. Solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the pixel has a zero bias capacitance connected to the pixel electrode. A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
Vertical signal lines formed for each column;
A differential amplifier having one terminal connected to the vertical signal line;
The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed on the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the substrate side, and a surface opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line through the address transistor,
The reset transistor has a source connected to the pixel electrode,
An output terminal of the differential amplifier is connected to a drain of the amplification transistor and reset transistor provided in a corresponding column. A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
An address drain line formed for each column;
Vertical signal lines formed for each column;
A differential amplifier having one terminal connected to the vertical signal line;
The pixel includes an amplification transistor, an address transistor, a first feedback transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed on the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the substrate side, and a surface opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line,
The first feedback transistor has a source connected to the pixel electrode, a drain connected to a source of the address transistor together with a drain of the amplification transistor,
The drain of the address transistor is connected to the address drain line corresponding to each column,
The solid-state imaging device, wherein the address drain line is connected to a power supply line and an output terminal of the differential amplifier in a corresponding column via a switch.   The solid-state imaging device according to claim 7, wherein the pixel includes a second feedback transistor and a feedback capacitor connected between the source of the first feedback and the pixel electrode. The pixel is
A feedback capacitor connected between the source of the first feedback and the pixel electrode;
The solid-state imaging device according to claim 7, further comprising a second feedback transistor connected between the pixel electrode and a source of the address transistor. The pixel is
A feedback capacitor connected between a source of the first feedback transistor and the pixel electrode;
The solid-state imaging device according to claim 7, wherein a source includes a reset transistor connected to the pixel electrode. A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
A power line formed for each column;
Vertical signal lines formed for each column;
A differential amplifier having one terminal connected to the vertical signal line;
A load unit connected to the vertical signal line,
The pixel includes an amplification transistor, an address transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed on the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the substrate side, and a surface opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line, a drain connected to a power supply line,
The reset transistor has a source connected to the pixel electrode, a drain connected to a power supply line,
The address transistor is connected between a source of the amplification transistor and the vertical signal line or between a drain of the amplification transistor and the power line.
The solid-state imaging device, wherein an output of the differential amplifier is coupled to the vertical signal line.   The solid-state imaging device according to claim 11, wherein the pixel has a zero bias capacitance connected to the pixel electrode.

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