JP2012019169A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked-type solid-state imaging device of small size.SOLUTION: A solid-state imaging device comprises unit pixel cells 13 and vertical signal lines 17. Each unit pixel cell 13 comprises: a photoelectric conversion film 6 formed on a semiconductor substrate; a pixel electrode 5 that is formed on the semiconductor substrate and contacts the photoelectric conversion film 6; an amplifier transistor 10 in the semiconductor substrate, which has a gate electrode connected to the pixel electrode 5 and outputs a signal voltage corresponding to a potential of the pixel electrode 5; a reset transistor 11 in the semiconductor substrate, which resets the potential of the gate electrode of the amplifier transistor 10; and an address transistor 12 in the semiconductor substrate, which is formed between the amplifier transistor 10 and each vertical signal line 17 and outputs a signal voltage from the unit pixel cell 13 to each vertical signal line 17. A gate electrode of the reset transistor 11 is electrically connected to a gate electrode of the address transistor 12.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a stacked solid-state imaging device.

  In a general solid-state imaging device, an embedded photodiode structure is used as a light receiving portion.

  In Patent Document 1, a photoelectric conversion layer is formed on a control electrode constituting a solid-state amplification device, a transparent electrode layer is provided thereon, and the action of the voltage applied thereto is controlled via the photoelectric conversion layer. A device that changes optical information into an electrical signal with a good S / N ratio, that is, a so-called stacked solid-state imaging device is disclosed.

Japanese Patent Laid-Open No. 55-120182

  A stacked solid-state imaging device has a configuration in which a photoelectric conversion film is formed on a semiconductor substrate on which a pixel circuit is formed via an insulating film. For this reason, it is possible to use a material having a large light absorption coefficient such as amorphous silicon for the photoelectric conversion film. For example, in the case of amorphous silicon, green light having a wavelength of 550 nm is almost absorbed at a thickness of about 0.4 nm.

  In addition, since the embedded photodiode structure is not used, the capacity of the photoelectric conversion unit can be increased, and the saturation charge amount can be increased. Furthermore, it is possible to actively add additional capacity because it does not transfer charges completely, and a sufficiently large capacity can be realized even in a miniaturized unit pixel cell. Furthermore, a stack cell in a dynamic random access memory It is also possible to make the structure as follows.

  However, since the stacked solid-state imaging device disclosed in Patent Document 1 has three transistors per unit pixel cell, it is difficult to reduce the unit pixel cell.

  In view of the above problems, an object of the present invention is to provide a small stacked solid-state imaging device.

  In order to achieve the above object, a solid-state imaging device according to an aspect of the present invention is provided corresponding to a plurality of unit pixel cells arranged in a two-dimensional manner and a column of the unit pixel cells. A vertical signal line that transmits a signal voltage of the unit pixel cell, the unit pixel cell is formed on a semiconductor substrate, and is formed on the semiconductor substrate, a photoelectric conversion film that photoelectrically converts incident light, Amplifying a pixel electrode in contact with the photoelectric conversion film and a transistor formed in the semiconductor substrate, the gate electrode being connected to the pixel electrode, and outputting a signal voltage corresponding to the potential of the pixel electrode A transistor formed in the semiconductor substrate, a reset transistor for resetting a potential of the gate electrode of the amplification transistor, and a transistor formed in the semiconductor substrate. An address transistor that is provided between the amplification transistor and the vertical signal line and outputs a signal voltage from the unit pixel cell to the vertical signal line, and a gate electrode of the reset transistor and the The gate electrode of the address transistor is electrically coupled.

  Here, the threshold voltage of the reset transistor may be higher than the threshold voltage of the address transistor.

  The solid-state imaging device may further include a vertical scanning unit that supplies ternary drive pulses to the gate electrode of the reset transistor and the gate electrode of the address transistor.

  According to this aspect, since the wiring of the gate electrode of the reset transistor and the wiring of the gate electrode of the address transistor can be made common, the wiring is reduced by one for each unit pixel cell, and a small stacked solid-state imaging device is obtained. Can be realized.

  The gate electrode of the reset transistor and the gate electrode of the address transistor may be formed of a common gate electrode.

  According to this aspect, since one gate electrode can be reduced with respect to one unit pixel cell, the unit pixel cell can be miniaturized.

  The common gate electrode may form a wiring for electrically connecting the plurality of unit pixel cells.

  According to this aspect, since the gate electrodes of the reset transistor and the address transistor can be used for the wiring, the wiring can be reduced.

  The plurality of unit pixel cells adjacent in the column direction may share either the source region or the drain region of the amplification transistor.

  According to this aspect, since one of the source region and the drain region of the amplification transistor can be reduced by one with respect to the two unit pixel cells, the unit pixel cell can be miniaturized.

  The plurality of unit pixel cells adjacent in the column direction may share either the source region or the drain region of the address transistor.

  According to this aspect, since one of the source region and the drain region of the address transistor can be reduced by one with respect to the two unit pixel cells, the unit pixel cell can be miniaturized.

  The unit pixel cell shares one of the source pixel and drain regions of the address transistor with one of the unit pixel cells adjacent in the column direction, and the other of the unit pixel cell adjacent in the column direction and the amplification. Either the source region or the drain region of the transistor may be shared.

  According to this aspect, one of the source region and drain region of the address transistor is reduced by one with respect to the two unit pixel cells, and one of the source region and drain region of the amplification transistor is reduced with respect to the two unit pixel cells. Therefore, the unit pixel cell can be miniaturized.

  The plurality of unit pixel cells adjacent in the column direction may share either the source region or the drain region of the reset transistor.

  According to this aspect, since one of the source region and the drain region of the reset transistor can be reduced by one with respect to the two unit pixel cells, the unit pixel cell can be miniaturized.

  In the unit pixel cell, the source and drain regions of the address transistor and the amplification transistor are formed in a first active region in the semiconductor substrate, and the source and drain regions of the reset transistor are the first and second regions. The active region may be formed in a second active region in the semiconductor substrate arranged side by side in the row direction.

  According to this aspect, since the active region is shared by the address transistor and the amplification transistor, the unit pixel cell can be miniaturized.

  The plurality of unit pixel cells adjacent in the column direction may share the first active region.

  According to this aspect, since the active region is shared by different unit pixel cells, the unit pixel cell can be miniaturized.

  The solid-state imaging device according to one aspect of the present invention is provided corresponding to a plurality of unit pixel cells arranged in a two-dimensional manner and the column of the unit pixel cells, and the unit pixel cells of the corresponding column The unit pixel cell is formed on a semiconductor substrate and photoelectrically converts incident light photoelectrically, and is formed on the semiconductor substrate and is in contact with the photoelectric conversion film. A pixel electrode, a transistor formed in the semiconductor substrate, having a gate electrode connected to the pixel electrode, and outputting a signal voltage corresponding to the potential of the pixel electrode; and the semiconductor substrate A plurality of transistors electrically connected to the amplifying transistor, and two transistors having different threshold voltages among the plurality of transistors. The gate electrodes of the capacitor is characterized in that it is electrically coupled.

  According to this aspect, since the gate electrodes of the two transistors of the unit pixel cell can be made common, it is possible to realize a small stacked solid-state imaging device by reducing one wiring for each unit pixel cell.

  According to one embodiment of the present invention, it is possible to reduce the size of a stacked image sensor.

It is a figure which shows the circuit structure of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the drive pulse of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the detailed structure of the unit pixel cell of the solid-state imaging device concerning the 1st Embodiment of this invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the 4th Embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the 4th Embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device concerning the 5th Embodiment of this invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on the 6th Embodiment of this invention. It is a figure which shows the circuit structure of the unit pixel cell of the solid-state imaging device which concerns on the 7th Embodiment of this invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on the comparative example of embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the comparative example of embodiment of this invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on the comparative example of embodiment of this invention. It is a top view which shows the detailed structure of the unit pixel cell of the solid-state imaging device which concerns on the comparative example of embodiment of this invention.

(First embodiment)
Hereinafter, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a circuit configuration of a solid-state imaging device according to the first embodiment of the present invention.

  This solid-state imaging device is characterized in that the component parts related to the transistors in the unit pixel cell 13 are shared, that is, the wiring of the gate electrode of the reset transistor 11 and the wiring of the gate electrode of the address transistor 12 are made common.

  This solid-state imaging device is a stacked solid-state imaging device, and as shown in FIG. 1, a plurality of unit pixel cells 13 arranged in a two-dimensional manner, a vertical scanning unit (row selection unit) 15, A photoelectric conversion film control line 16, a vertical signal line (vertical signal line wiring) 17, a load unit 18, a column signal processing unit 19, a horizontal signal reading unit 20, and a power supply wiring 21 are provided.

  The unit pixel cell 13 includes a photoelectric conversion film unit 9, an amplification transistor 10, a reset transistor 11, and an address transistor (row selection transistor) 12. In the unit pixel cell 13, the gate electrode of the reset transistor 11 and the gate electrode of the address transistor 12 are electrically coupled.

  The photoelectric conversion film unit 9 photoelectrically converts incident light, and generates and accumulates signal charges corresponding to the amount of incident light. The amplification transistor 10 outputs a signal voltage corresponding to the signal charge amount generated by the photoelectric conversion film unit 9. The reset transistor 11 resets (initializes) the gate voltage of the photoelectric conversion film unit 9, in other words, the amplification transistor 10. The address transistor 12 selectively outputs the signal voltage of the unit pixel cells 13 in a predetermined row to the vertical signal line 17. The threshold voltage of the reset transistor 11 is higher than the threshold voltage of the address transistor 12.

  The vertical scanning unit 15 scans the row of the unit pixel cells 13 in the vertical direction (column direction), and selects the row of the unit pixel cells 13 that outputs the signal voltage to the vertical signal line 17. The vertical scanning unit 15 supplies ternary drive pulses to the gate electrode of the reset transistor 11 and the gate electrode of the address transistor 12.

  The photoelectric conversion film control line 16 is commonly connected to the plurality of unit pixel cells 13 and applies the same voltage to the plurality of photoelectric conversion film units 9.

  A plurality of vertical signal lines 17 are arranged in the row direction and connected to the unit pixel cell 13, that is, the source of the address transistor 12. The vertical signal line 17 is provided corresponding to each column of the unit pixel cells 13 and transmits the signal voltage output from the unit pixel cell 13 of the corresponding column in the vertical direction (column direction).

  The load unit 18 is provided corresponding to each vertical signal line 17 and connected to the corresponding vertical signal line 17.

  The column signal processing unit 19 performs noise suppression signal processing typified by correlated double sampling, AD conversion (analog-digital conversion), and the like. The column signal processing unit 19 is provided corresponding to each vertical signal line 17 and connected to the corresponding vertical signal line 17.

  The horizontal signal reading unit 20 sequentially reads signals from a plurality of column signal processing units 19 arranged in the horizontal direction (row direction) to the horizontal common signal line.

  The power supply wiring 21 is connected to the drains of the amplification transistor 10 and the reset transistor 11 and wired in the vertical direction (up and down direction in the drawing of FIG. 1) in the arrangement region (imaging region) of the unit pixel cells 13. This is because the unit pixel cell 13 is addressed for each column, and therefore, if the drain wiring is wired in the column direction (vertical direction), all the pixel driving currents in one column flow through one wiring, and the voltage drop increases. is there.

In the case of the configuration shown in FIG. 1, if the reset transistor 11 and the address transistor 12 have the same threshold voltage, the signal voltage cannot be read out. Therefore, it is necessary to make a difference between the two threshold voltages. That is, in order to read the signal voltage of the unit pixel cell 13 to the vertical signal line 17 with the reset transistor 11 in the OFF state and the address transistor 12 in the ON state, the threshold voltage of the reset transistor 11 is set from the threshold voltage of the address transistor 12. Need to be high. The driving voltage applied to the gate electrodes of these transistors needs to be a three-level driving pulse. An example of the drive pulse is shown in FIG. A narrow reset pulse 26 for turning on the reset transistor 11 is superimposed on a wide address pulse 33 for turning on the address transistor 12. The signal voltage is read out to the vertical signal line 17 at time t ₁ immediately before the reset pulse 26 is applied, and noise is read out at time t ₂ immediately after the reset pulse 26 is applied. This signal voltage and noise are taken into the column signal processing unit 19 and processed. Such an operation is possible because the address transistor 12 is always in the ON state while the reset transistor 11 is in the ON state. When the address transistor 12 is in an OFF state and an operation for turning the reset transistor 11 in an ON state is required, the signal voltage cannot be read out with the configuration shown in FIG.

  FIG. 3 is a cross-sectional view showing a detailed structure of one unit pixel cell 13.

  In the unit pixel cell 13, as shown in FIG. 3, n-type diffusion layer regions 8A and 8B formed in a p-type silicon substrate 1 as a p-type semiconductor substrate, and a gate electrode formed on the silicon substrate 1 4, a reset transistor 11 is formed. Similarly, an amplification transistor 10 is formed from n-type diffusion layer regions 8B and 8C formed in the p-type silicon substrate 1 and a gate electrode 3 formed on the p-type silicon substrate 1. Further, an address transistor 12 is formed from n-type diffusion layer regions 8C and 8D formed in the p-type silicon substrate 1 and a gate electrode 2 formed on the p-type silicon substrate 1.

  An element isolation region that electrically isolates the unit pixel cells is formed between the unit pixel cells 13.

  The n-type diffusion layer region 8A functions as the source of the reset transistor 11, and the n-type diffusion layer region 8B functions as the drains of the reset transistor 11 and the amplification transistor 10. The n-type diffusion layer region 8C functions as the source of the amplification transistor 10 and the drain of the address transistor 12, and the n-type diffusion layer region 8D functions as the source of the address transistor 12.

  An interlayer insulating film, a pixel electrode 5, a photoelectric conversion film 6, and a transparent electrode 7 are sequentially stacked above a circuit composed of three transistors, that is, a pixel circuit including an address transistor 12, an amplification transistor 10, and a reset transistor 11. ing.

  The photoelectric conversion film 6 made of amorphous silicon or the like, the pixel electrode 5, the transparent electrode 7 formed on the upper surface of the photoelectric conversion film 6, and the n-type diffusion layer region 8A constitute a photoelectric conversion film unit 9. . The pixel electrode 5 is connected to the gate electrode 3 of the amplification transistor 10 and the n-type diffusion layer region 8A functioning as the source of the reset transistor 11 through contacts. The n-type diffusion layer region 8A connected to the pixel electrode 5 also functions as a storage diode.

  The photoelectric conversion film 6 is formed on the p-type silicon substrate 1 and photoelectrically converts incident light. The pixel electrode 5 is formed on the p-type silicon substrate 1 (on the surface of the photoelectric conversion film 6 on the silicon substrate 1 side), contacts the photoelectric conversion film 6, and collects signal charges generated in the photoelectric conversion film 6. The transparent electrode 7 is formed on the p-type silicon substrate 1 (on the surface opposite to the surface of the photoelectric conversion film 6 on the silicon substrate 1 side), and in order to read the signal charge of the photoelectric conversion film 6 to the pixel electrode 5, A constant voltage is applied to the photoelectric conversion film 6. The amplification transistor 10 is a transistor formed below the pixel electrode 5 in the p-type silicon substrate 1, has a gate electrode 3 connected to the pixel electrode 5, and a signal voltage corresponding to the potential of the pixel electrode 5. Is output. The reset transistor 11 is a transistor formed below the pixel electrode 5 in the p-type silicon substrate 1 and resets the potential of the gate electrode 3 of the amplification transistor 10. The address transistor 12 is a transistor formed below the pixel electrode 5 in the p-type silicon substrate 1. The address transistor 12 is provided between the amplification transistor 10 and the vertical signal line 17, and extends from the unit pixel cell 13 to the vertical signal line 17. To output a signal voltage.

  As described above, according to the solid-state imaging device according to the first embodiment of the present invention, the wiring of the gate electrodes of the reset transistor 11 and the address transistor 12 constituting the unit pixel cell 13 (to supply the driving pulse). Common wiring) can be reduced by one wiring for one unit pixel cell 13, and the area of the solid-state imaging device can be reduced.

(Second Embodiment)
Hereinafter, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 is a diagram illustrating a circuit configuration of a solid-state imaging apparatus according to the second embodiment of the present invention.

  As shown in FIG. 4, the solid-state imaging device according to the present embodiment has a configuration in which the gate electrode of the reset transistor 11 and the gate electrode of the address transistor 12 are commonly wired with respect to the solid-state imaging device of the first embodiment. However, it is different in a configuration in which a path for negative feedback of the thermal noise generated in the reset transistor 11 to the source of the reset transistor 11 is formed.

  As shown in FIG. 4, the solid-state imaging device includes a unit pixel cell 13, a vertical scanning unit 15, a photoelectric conversion film control line 16, a vertical signal line 17, a load unit 18, and a column signal processing unit 19. A horizontal signal reading unit 20, a power supply wiring 21, a feedback amplifier 23, and a feedback line 24.

  The feedback amplifier 23 is provided corresponding to each vertical signal line 17 and connected to the corresponding vertical signal line 17. The feedback line 24 is provided corresponding to each feedback amplifier 23, one end is connected to the output of the corresponding feedback amplifier 23, and the other end is commonly connected to the source of the reset transistor 11 of the unit pixel cell 13 in the same column. ing.

  In the solid-state imaging device of FIG. 4, the threshold voltages of the reset transistor 11 and the address transistor 12 and the driving method are the same as those of the solid-state imaging device of the first embodiment.

  In the configuration of FIG. 4, the thermal noise generated in the reset transistor 11 when the reset transistor 11 is in the ON state passes through the amplification transistor 10, the address transistor 12, the vertical signal line 17, the feedback amplifier 23, and the feedback line 24. Negative feedback to the source of the feedback. As a result, the thermal noise of the reset transistor 11 is canceled and random noise is suppressed. In this case as well, since the address transistor 12 is always in the ON state when the reset transistor 11 is in the ON state as in the configuration of FIG. 1, the gate electrode of the reset transistor 11 and the gate electrode of the address transistor 12 are wired in common. It is possible to read out the signal voltage with three levels of driving pulses.

  As described above, according to the solid-state imaging device according to the second embodiment of the present invention, wiring is provided for one unit pixel cell 13 for the same reason as in the solid-state imaging device of the first embodiment. The number can be reduced by one to reduce the size of the solid-state imaging device.

  Also, in a general stacked sensor, noise is generated when resetting the signal charge, and the next signal charge is added to it, so that the signal charge superimposed with the reset noise is read out, and random noise is read out. There is a problem that is large. However, according to the solid-state imaging device according to the second embodiment of the present invention, since the thermal noise generated in the reset transistor 11 can be negatively fed back to the source, the switching operation of the reset transistor 11 which is a problem of the stacked sensor It is possible to suppress random noise related to.

(Third embodiment)
Hereinafter, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a plan view showing a detailed configuration of the unit pixel cell 13 of the solid-state imaging device according to the present embodiment.

  The solid-state imaging device according to the present embodiment is the second embodiment in that the gate electrode of the address transistor 12 and the gate electrode of the reset transistor 11 are formed by a common (same) gate electrode 42 in the unit pixel cell 13. This is different from the solid-state imaging device. Moreover, it is different from the solid-state imaging device of the second embodiment in that the common gate electrode 42 forms a wiring for electrically connecting the plurality of unit pixel cells 13. Further, in the unit pixel cell 13, the active regions of the address transistor 12 and the amplification transistor 10 are formed in the same first active region 22 in the semiconductor substrate, and the active region of the reset transistor 11 is the first active region 22. The solid-state imaging device of the second embodiment is also different in that it is formed in the second active region 25 in the semiconductor substrate arranged side by side in the row direction.

  In the unit pixel cell 13, active regions of the amplification transistor 10 and the address transistor 12 are formed in the first active region 22 formed in the semiconductor substrate, and a reset transistor is formed in the second active region 25 formed in the semiconductor substrate. Eleven active regions are formed. The active region refers to a source diffusion layer region, a drain diffusion layer region, and a gate region (channel region). On the first active region 22, the gate electrode 42 of the address transistor 12 and the gate electrode 3 of the amplification transistor 10 are provided. On the second active region 25, the gate electrode 42 of the reset transistor 11 is provided. Each of the gate electrodes 3 and 42 is made of polysilicon or the like, and a wiring (a thick line in FIG. 5) made of Al (aluminum), Cu (copper) or the like through a contact hole (black square in FIG. 5). ).

  The vertical signal line 17 is connected to the source of the address transistor 12, and the drain of the amplification transistor 10 is connected to the power supply wiring 21. The drain of the reset transistor 11 is connected to the feedback line 24.

  In order to make the upper surface shape of the unit pixel cell 13 substantially square, the first active region 22 and the second active region 25 are arranged side by side in the row direction, and the gate electrode of the reset transistor 11 and the gate electrode of the address transistor 12 Are common electrodes. Here, polysilicon, which is the material of the gate electrode 42, is used for wiring that runs in the horizontal direction (the horizontal direction in FIG. 5), and a common driving pulse is applied to the gate electrodes 42 of the plurality of unit pixel cells 13 in the same row by this wiring. When supplied, wiring such as Al and Cu becomes unnecessary, so that one more wiring is unnecessary compared with the solid-state imaging device of the second embodiment, and the solid-state imaging device can be further downsized. FIG. 6 is used to explain this easily. The common gate electrode 42 of the reset transistor 11 and the address transistor 12 in the predetermined unit pixel cell 13 is used as the reset transistor 11 of the unit pixel cell 13 and the gate electrode 42 of the address transistor 12 adjacent to the predetermined unit pixel cell 13 as they are. It can be used as wiring for connection. Even if the gate electrodes of the address transistor 12 and the reset transistor 11 are shared, one wiring is necessary if Al and Cu are used as the wiring. However, by using the polysilicon of the gate electrode 42 as the wiring as it is, Miniaturization of the solid-state imaging device can be realized.

  As described above, according to the solid-state imaging device according to the third embodiment of the present invention, wiring is provided for one unit pixel cell 13 for the same reason as in the solid-state imaging device of the first embodiment. The number can be reduced by one to reduce the size of the solid-state imaging device.

  Further, according to the solid-state imaging device according to the third embodiment of the present invention, it is possible to suppress random noise related to the switching operation of the reset transistor 11 for the same reason as that of the solid-state imaging device of the second embodiment. It is.

  In addition, according to the solid-state imaging device according to the third embodiment of the present invention, since the gate electrode is shared by the reset transistor 11 and the address transistor 12, the gate electrode can be reduced and the unit pixel cell can be miniaturized.

  Further, according to the solid-state imaging device according to the third embodiment of the present invention, the wiring for supplying the driving pulse to the reset transistor 11 and the address transistor 12 is configured by the gate electrode 42 in the unit pixel cell 13. Therefore, wiring for supplying drive pulses can be reduced, and the solid-state imaging device can be downsized.

(Fourth embodiment)
Hereinafter, a solid-state imaging device according to a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 is a plan view showing a detailed configuration of the unit pixel cell 13 of the solid-state imaging device according to the present embodiment.

  In the solid-state imaging device according to the present embodiment, a plurality of unit pixel cells 13 (two unit pixel cells 13 arranged in the vertical direction on the paper surface of FIG. 7) adjacent to each other in the vertical direction are arranged with the transistors inverted in the vertical direction. The plurality of unit pixel cells 13 adjacent in the vertical direction is different from the solid-state imaging device of the third embodiment in that the drain diffusion layer region of the reset transistor 11 and the source diffusion layer region of the address transistor 12 are shared. . Further, the first active region 22 and the second active region 25 are shared by a plurality of unit pixel cells 13 (two unit pixel cells 13 arranged in the vertical direction on the paper surface of FIG. 7) adjacent in the vertical direction. The solid-state imaging device of the third embodiment is different in that the contact hole and the element isolation region are shared. The first active region 22 is continuous in the vertical direction with respect to the plurality of unit pixel cells 13.

  As described above, according to the solid-state imaging device according to the fourth embodiment of the present invention, wiring is provided for one unit pixel cell 13 for the same reason as in the solid-state imaging device of the first embodiment. The number can be reduced by one to reduce the size of the solid-state imaging device.

  Further, according to the solid-state imaging device according to the fourth embodiment of the present invention, it is possible to suppress random noise related to the switching operation of the reset transistor 11 for the same reason as that of the solid-state imaging device according to the second embodiment. It is.

  Moreover, according to the solid-state imaging device according to the fourth embodiment of the present invention, the gate electrode can be reduced and the unit pixel cell can be miniaturized for the same reason as the solid-state imaging device of the third embodiment.

  Further, according to the solid-state imaging device according to the fourth embodiment of the present invention, as shown in FIG. 8, wiring for supplying drive pulses to the reset transistor 11 and the address transistor 12 is provided in the unit pixel cell 13. The gate electrode 42 is used. Therefore, wiring for supplying drive pulses can be reduced, and the solid-state imaging device can be downsized.

  Further, according to the solid-state imaging device according to the fourth embodiment of the present invention, the contact hole, source diffusion layer region, drain diffusion layer region in the unit pixel cell 13 adjacent in the vertical direction as compared with the configuration of FIG. 1 and the element isolation region can be reduced one by one, so that the unit pixel cell 13 can be miniaturized in the vertical direction.

  In the solid-state imaging device according to the fourth embodiment of the present invention, the gate electrode of the address transistor 12 and the gate electrode of the reset transistor 11 are formed by a common gate electrode 42 in the unit pixel cell 13. However, when only the vertical miniaturization of the unit pixel cell 13 is performed, the gate electrode of the address transistor 12 and the gate electrode of the reset transistor 11 in the unit pixel cell 13 may be formed by separate independent gate electrodes. Good. Similarly, wiring for supplying drive pulses to the address transistor 12 and the reset transistor 11 may be formed separately from the gate electrode.

(Fifth embodiment)
Hereinafter, a solid-state imaging device according to a fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 9 is a plan view showing a detailed configuration of the unit pixel cell 13 of the solid-state imaging device according to the present embodiment.

  In the solid-state imaging device according to the present embodiment, a plurality of unit pixel cells 13 (two unit pixel cells 13 arranged in the vertical direction on the paper surface of FIG. 9) adjacent to each other in the vertical direction serve as the drain diffusion layer region of the amplification transistor 10. It differs from the solid-state imaging device of the fourth embodiment in that it is shared. In other words, the unit pixel cell 13 shares the source diffusion layer region of the address transistor 12 with one of the unit pixel cells 13 adjacent in the vertical direction, and the drain of the amplification transistor 10 with the other of the unit pixel cells 13 adjacent in the vertical direction. It differs from the solid-state imaging device of the fourth embodiment in that it shares the diffusion layer region.

  Two unit pixel cells 13 adjacent in the vertical direction share the second active region 25. In contrast, the four unit pixel cells 13 adjacent in the vertical direction share the first active region 22. The first active region 22 has a layout that is continuous in the vertical direction.

  As described above, according to the solid-state imaging device according to the fifth embodiment of the present invention, wiring is provided for one unit pixel cell 13 for the same reason as in the solid-state imaging device of the first embodiment. The number can be reduced by one to reduce the size of the solid-state imaging device.

  Further, according to the solid-state imaging device according to the fifth embodiment of the present invention, it is possible to suppress random noise related to the switching operation of the reset transistor 11 for the same reason as in the solid-state imaging device of the second embodiment. It is.

  Further, according to the solid-state imaging device according to the fourth embodiment of the present invention, for the same reason as the solid-state imaging device of the third embodiment, wiring for supplying drive pulses is reduced, and the solid-state imaging device is reduced in size. Can be In addition, the number of gate electrodes can be reduced, and the unit pixel cell can be miniaturized.

  Further, according to the solid-state imaging device according to the fifth embodiment of the present invention, compared to the configuration of FIG. 5, the four unit pixel cells 13 adjacent in the vertical direction have contact holes, source diffusion layer regions, and drain diffusions. Since two or more layer regions and element isolation regions can be reduced, the unit pixel cell 13 can be miniaturized in the vertical direction.

  In the solid-state imaging device according to the fifth embodiment of the present invention, the drain diffusion layer region of the amplification transistor 10 is shared by the two unit pixel cells 13 adjacent in the vertical direction. May be shared by two unit pixel cells 13 adjacent to each other in the left-right direction of the sheet). In this case, the two unit pixel cells 13 adjacent in the horizontal direction are arranged with the transistors inverted in the horizontal direction, that is, the horizontal positional relationship between the first active region 22 and the second active region 25 is reversed. To be arranged.

  In the solid-state imaging device according to the fifth embodiment of the present invention, the gate electrode of the address transistor 12 and the gate electrode of the reset transistor 11 are formed by the common gate electrode 42 in the unit pixel cell 13. However, when only the vertical miniaturization of the unit pixel cell 13 is performed, the gate electrode of the address transistor 12 and the gate electrode of the reset transistor 11 in the unit pixel cell 13 may be formed by separate independent gate electrodes. Good. Similarly, wiring for supplying drive pulses to the address transistor 12 and the reset transistor 11 may be formed separately from the gate electrode.

(Sixth embodiment)
Hereinafter, a solid-state imaging device according to a sixth embodiment of the present invention will be described with reference to the drawings.

  FIG. 10 is a diagram illustrating a circuit configuration of a solid-state imaging apparatus according to the sixth embodiment of the present invention.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the first embodiment in that the unit pixel cell 13 includes a first feedback transistor 29 and a second feedback transistor 30 with gate electrodes wired in common. Different. In other words, the unit pixel cell 13 is a transistor formed in a semiconductor substrate, and includes a first feedback transistor 29 and a second feedback transistor 30 that are electrically connected to the amplification transistor 10 and have different threshold voltages. The first feedback transistor 29 and the second feedback transistor 30 are different from the solid-state imaging device of the first embodiment in that the gate electrodes of the first feedback transistor 29 and the second feedback transistor 30 are electrically coupled.

  Similar to the reset transistor 11, the first feedback transistor 29 and the second feedback transistor 30 have a function of resetting the gate voltage (signal reset) of the amplification transistor 10. The feedback transistor operates as follows. That is, first, the first feedback transistor 29 and the second feedback transistor 30 are simultaneously turned on, and the signal is reset. Next, only the second feedback transistor 30 is turned off and a feedback operation is performed. In order to realize such an operation, the threshold voltage of the second feedback transistor 30 is larger than the threshold voltage of the first feedback transistor 29, and the first feedback transistor 29 and the second feedback transistor 30 are connected as shown in FIG. It is necessary to drive with such three-level drive pulses.

  As described above, for the two transistors in one unit pixel cell 13, an operation in which the ON state period of one first transistor is included in the ON state period of the other second transistor is that of the first transistor. By making the threshold voltage higher than the threshold voltage of the second transistor, it is possible to wire with a common gate electrode and drive with three levels of driving pulses. Since the first feedback transistor 29 and the second feedback transistor 30 are in this relationship, the wiring of the gate electrode can be made common.

  In general, if two transistors have the ON state period of one transistor including the ON state period of the other transistor, the gate electrodes can be shared, and the three transistors have this relationship. Sometimes, the three transistors can be driven with four levels of driving pulses by setting the threshold voltages to be different. However, this is just a general theory, and it is practical to drive the two transistors with three-level driving pulses with the gate electrodes of the two transistors in common.

  As described above, according to the solid-state imaging device according to the sixth embodiment of the present invention, the wirings of the gate electrodes of the first feedback transistor 29 and the second feedback transistor 30 constituting the unit pixel cell 13 ( By making the wiring for supplying the driving pulse common, one wiring is reduced with respect to one unit pixel cell 13, and the area of the unit pixel cell 13 can be reduced.

(Seventh embodiment)
Hereinafter, a solid-state imaging device according to a seventh embodiment of the present invention will be described with reference to the drawings.

  FIG. 11 is a diagram illustrating a circuit configuration of the unit pixel cell 13 of the solid-state imaging device according to the seventh embodiment of the present invention.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device of the first embodiment in that it includes a third feedback transistor 31 and a fourth feedback transistor 32 in which gate electrodes are wired in common.

  The third feedback transistor 31 and the fourth feedback transistor 32 have a function of resetting a signal in the same manner as the reset transistor 11. The feedback transistor operates as follows. First, the third feedback transistor 31 and the fourth feedback transistor 32 are simultaneously turned on, and the signal is reset. Next, only the fourth feedback transistor 32 is turned off and a feedback operation is performed. In order to realize such an operation, the threshold voltage of the fourth feedback transistor 32 is larger than the threshold voltage of the third feedback transistor 31, and the third feedback transistor 31 and the fourth feedback transistor 32 are configured as shown in FIG. It is necessary to drive with three levels of driving pulses.

  As described above, according to the solid-state imaging device according to the seventh embodiment of the present invention, the wirings of the gate electrodes of the third feedback transistor 31 and the fourth feedback transistor 32 constituting the unit pixel cell 13 ( By making the wiring for supplying the driving pulse common, one wiring is reduced with respect to one unit pixel cell 13, and the area of the unit pixel cell 13 can be reduced.

(Comparative example)
Hereinafter, a solid-state imaging device according to a comparative example of the embodiment of the present invention will be described with reference to the drawings.

  FIG. 12 is a diagram illustrating a circuit configuration of a solid-state imaging device according to a comparative example of the present embodiment.

  The solid-state imaging device includes a plurality of unit pixel cells 113 arranged in a two-dimensional manner, a vertical scanning unit 115, a photoelectric conversion film control line 116, a vertical signal line 117, a load unit 118, and a column signal processing unit. 119, a horizontal signal reading unit 120, and a power supply wiring 121.

  The unit pixel cell 113 includes a photoelectric conversion film unit 109, an amplification transistor 110, a reset transistor 111, and an address transistor 112.

  The photoelectric conversion film control line 116 is commonly connected to the plurality of unit pixel cells 113, and applies the same voltage to the plurality of photoelectric conversion film units 109.

  A plurality of vertical signal lines 117 are arranged in the row direction and connected to the unit pixel cell 113, that is, the source of the address transistor 112.

  The load unit 118 is provided corresponding to each vertical signal line 117 and connected to the corresponding vertical signal line 117.

  The column signal processing unit 119 performs noise suppression signal processing represented by correlated double sampling, AD conversion, and the like. The column signal processing unit 119 is provided corresponding to each vertical signal line 117 and connected to the corresponding vertical signal line 117.

  The horizontal signal reading unit 120 sequentially reads the signals of the plurality of column signal processing units 119 arranged in the horizontal direction to the horizontal common signal line.

  The power supply wiring 121 is connected to the drains of the amplification transistor 110 and the reset transistor 111, and is wired in the vertical direction (up and down direction in the drawing of FIG. 12) in the arrangement region of the unit pixel cells 113. This is because the unit pixel cell 113 is addressed for each column, and therefore, if the drain wiring is wired in the column direction (vertical direction), all the pixel driving currents in one column flow through one wiring and the voltage drop increases. is there.

  FIG. 13 is a plan view showing a detailed configuration of one unit pixel cell 113.

  In the unit pixel cell 113, active regions of the amplification transistor 110, the reset transistor 111, and the address transistor 112 are formed in the first active region 122 formed on the semiconductor substrate. The active region refers to a source diffusion layer region, a drain diffusion layer region, and a gate region. On the first active region 122, the gate electrode 102 of the address transistor 12, the gate electrode 103 of the amplification transistor 110, and the gate electrode 104 of the reset transistor 111 are provided. Each of the gate electrodes 102, 103, and 104 is made of polysilicon or the like, and wiring made of Al (aluminum), Cu (copper), or the like through a contact hole (black square in FIG. 13) (FIG. 13). Thick line).

  A vertical signal line 117 is connected to the source of the address transistor 112, and the drains of the amplification transistor 110 and the reset transistor 111 are in a common region and are connected to the power supply wiring 121.

  The source of the reset transistor 111 and the gate of the amplification transistor 110 are drawn in common above the semiconductor substrate and connected to the pixel electrode. At this time, in an embedded image sensor (embedded solid-state imaging device) having a photodiode inside a semiconductor substrate that is not a stacked sensor (stacked solid-state imaging device), a photodiode is connected instead of a pixel electrode. In order to efficiently use incident light, the area of the photodiode is designed to be as large as possible. Therefore, the layout method of the unit pixel cell is completely different between the stacked sensor and the embedded sensor. In the multilayer sensor, the area of the photodiode is unnecessary, and the design is unique to the multilayer sensor. In the multilayer sensor, the area of the photodiode is unnecessary, so that the effect of miniaturization when the area of the circuit portion is reduced is significantly increased as compared with the case where the photodiode is provided. This is because the embedded sensor is required to secure the area of the photodiode more than half the area of the unit pixel cell. In the case of a stacked sensor, the area of the photoelectric conversion unit is almost equal to the area of the unit pixel cell, so that the effect of miniaturization is enormous.

  In the configuration of FIG. 12, a large thermal noise is generated from the reset transistor 111 when the signal is reset. In order to suppress this noise, a solid-state imaging device having the configuration shown in FIG. 14 can be considered. In the configuration of FIG. 14, the drain of the reset transistor 111 is disconnected from the drain of the amplification transistor 110, and the output signal of the vertical signal line 117 inverted and amplified by the differential amplifier 123 provided for each column passes through the reset transistor source line 124. To the source of the reset transistor 111. With such a configuration, suppression of noise generated in the reset transistor 111 due to negative feedback can be expected.

  FIG. 15 is a plan view showing a detailed configuration of the unit pixel cell 113 of the solid-state imaging device having the configuration of FIG.

  In order to separate the drain of the reset transistor 111 from the drain of the amplification transistor 110, a second active region 125 and a reset transistor source line 124 are newly required. The configuration of FIG. 15 seems to have only one additional wiring, but the area of the unit pixel cell 113 is about 1.5 times that of FIG.

  In the solid-state imaging device shown in FIGS. 12 and 14, the address transistor 112 and the reset transistor 111 need to be driven independently in the unit pixel cell 113, and the wirings of the gate electrodes 102 and 104 need to be arranged separately. is there. Therefore, the solid-state imaging device according to this comparative example has a problem that it cannot be reduced in size.

  The unit pixel cell 113 in FIG. 15 is a long rectangular cell. In contrast, in the unit pixel cell 13 of the solid-state imaging device of the third to fifth embodiments, the first active region 22 and the second active region 25 are juxtaposed, and the gate electrode and the address transistor of the reset transistor 11 Since the 12 gate electrodes are shared, the unit pixel cell 13 is substantially square.

  The solid-state imaging device of the present invention has been described based on the embodiments. However, the present invention is not limited to these embodiments. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  For example, in the above embodiment, the conductivity type of the silicon substrate 1 is p-type and each transistor is n-channel type. However, the conductivity type of the silicon substrate 1 is n-type and each transistor is p-channel type. It does not matter if it is a type.

  In this case, the sign of the voltage potential is reversed. In the solid-state imaging device of the fourth embodiment, a plurality of unit pixel cells 13 adjacent in the vertical direction share the source diffusion layer region of the reset transistor 11 and the drain diffusion layer region of the address transistor 12. In the solid-state imaging device according to the fifth embodiment, the plurality of unit pixel cells 13 adjacent in the vertical direction share the source diffusion layer region of the amplification transistor 10.

  The present invention can be used for a solid-state imaging device, and in particular, for a small-sized image pickup device.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 3, 4, 42, 102, 103, 104 Gate electrode 5 Pixel electrode 6 Photoelectric conversion film 7 Transparent electrode 8A, 8B, 8C, 8D n-type diffused layer area | region 9, 109 Photoelectric conversion film part 10, 110 Amplifying transistor 11, 111 Reset transistor 12, 112 Address transistor 13, 113 Unit pixel cell 15, 115 Vertical scanning unit 16, 116 Photoelectric conversion film control line 17, 117 Vertical signal line 18, 118 Load unit 19, 119 Column signal processing unit 20, 120 Horizontal signal readout unit 21, 121 Power supply wiring 22, 122 First active region 23 Feedback amplifier 24 Feedback line 25, 125 Second active region 26 Reset pulse 29 First feedback transistor 30 Second feedback transistor 31 Third Feedback transistor 32 and the fourth feedback transistor 33 address pulse 123 differential amplifier 124 reset transistor source line

Claims (12)

A plurality of unit pixel cells arranged two-dimensionally;
A vertical signal line provided corresponding to the column of the unit pixel cells and transmitting a signal voltage of the unit pixel cell of the corresponding column;
The unit pixel cell is
A photoelectric conversion film formed on a semiconductor substrate and photoelectrically converting incident light;
A pixel electrode formed on the semiconductor substrate and in contact with the photoelectric conversion film;
An amplifying transistor which is formed in the semiconductor substrate and has a gate electrode connected to the pixel electrode and outputs a signal voltage corresponding to the potential of the pixel electrode;
A transistor formed in the semiconductor substrate, the reset transistor resetting the potential of the gate electrode of the amplification transistor;
A transistor formed in the semiconductor substrate, provided between the amplification transistor and the vertical signal line, and having an address transistor for outputting a signal voltage from the unit pixel cell to the vertical signal line;
A solid-state imaging device, wherein a gate electrode of the reset transistor and a gate electrode of the address transistor are electrically coupled. The solid-state imaging device according to claim 1, wherein a threshold voltage of the reset transistor is higher than a threshold voltage of the address transistor. The solid-state imaging device according to claim 2, further comprising a vertical scanning unit that supplies ternary drive pulses to the gate electrode of the reset transistor and the gate electrode of the address transistor. The solid-state imaging device according to claim 1, wherein a gate electrode of the reset transistor and a gate electrode of the address transistor are formed by a common gate electrode. The solid-state imaging device according to claim 4, wherein the common gate electrode forms a wiring that electrically connects the plurality of unit pixel cells. The solid-state imaging device according to claim 1, wherein the plurality of unit pixel cells adjacent in the column direction share either a source region or a drain region of the amplification transistor. The solid-state imaging device according to claim 1, wherein the plurality of unit pixel cells adjacent in the column direction share either a source region or a drain region of the address transistor. The unit pixel cell shares one of the source pixel region and the drain region of the address transistor with one of the unit pixel cells adjacent in the column direction, and the other of the unit pixel cell adjacent to the column direction and the amplification transistor. The solid-state imaging device according to claim 7, wherein either the source region or the drain region is shared. The solid-state imaging device according to claim 1, wherein the plurality of unit pixel cells adjacent in the column direction share either a source region or a drain region of the reset transistor. In the unit pixel cell, a source region and a drain region of the address transistor and the amplifying transistor are formed in a first active region in the semiconductor substrate, and a source region and a drain region of the reset transistor are the first active region. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed in a second active region in the semiconductor substrate arranged side by side in a row direction with the region. The solid-state imaging device according to claim 10, wherein the plurality of unit pixel cells adjacent in the column direction share the first active region. A plurality of unit pixel cells arranged two-dimensionally;
A vertical signal line provided corresponding to the column of the unit pixel cells and transmitting a signal voltage of the unit pixel cell of the corresponding column;
The unit pixel cell is
A photoelectric conversion film formed on a semiconductor substrate and photoelectrically converting incident light;
A pixel electrode formed on the semiconductor substrate and in contact with the photoelectric conversion film;
An amplifying transistor which is formed in the semiconductor substrate and has a gate electrode connected to the pixel electrode and outputs a signal voltage corresponding to the potential of the pixel electrode;
A transistor formed in the semiconductor substrate, and having a plurality of transistors electrically connected to the amplification transistor;
A solid-state imaging device in which gate electrodes of two transistors having different threshold voltages among the plurality of transistors are electrically coupled.

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