WO2021124974A1 - Imaging device - Google Patents

Abstract

This imaging device is provided with a semiconductor substrate having a plurality of sensor pixels for performing photoelectric conversion arrayed in a matrix, and a circuit layer including a plurality of pixel circuits that output pixel signals on the basis of charges output from each of the sensor pixels, the circuit layer being disposed on the semiconductor substrate with an interlayer dielectric layer therebetween. A gate electrode of at least one transistor included in the pixel circuits extends across the plurality of pixel circuits in the plane of the circuit layer, and electrically connects to the gate electrode of the same type of the transistor provided in each of the plurality of the pixel circuits.

Description

Imaging device

This disclosure relates to an imaging device.

Conventionally, miniaturization of the area per pixel of an image pickup device having a two-dimensional structure has been realized by introducing a fine process and improving the mounting density. In recent years, an image pickup device having a three-dimensional structure has been developed in order to further reduce the size of the image pickup device and increase the density of pixels. An image pickup device having a three-dimensional structure is obtained by, for example, three-dimensionally stacking a semiconductor substrate having a plurality of sensor pixels and a semiconductor layer having a pixel circuit that converts the charge obtained by each sensor pixel into a pixel signal. It is configured (see Patent Document 1).

JP-A-2010-245506

In such an imaging device, as the area per pixel is miniaturized, the intervals between the wirings and the like extending over a plurality of pixels become narrower, which increases the process difficulty in forming the wirings. ing. Therefore, it is desired to relax the wiring design rule by reducing the density of the wiring provided over the plurality of pixels.

Therefore, it is desirable to provide an imaging device in which the wiring design rules are relaxed.

The image pickup apparatus according to the embodiment of the present disclosure transmits a pixel signal based on a semiconductor substrate provided with a plurality of sensor pixels performing photoelectric conversion arranged in a matrix and charges output from each of the sensor pixels. The gate electrode of at least one or more transistors included in the pixel circuit includes a plurality of pixel circuits for output, a circuit layer provided on the semiconductor substrate via an interlayer insulating layer, and the circuit. It extends to the plurality of pixel circuits in the plane of the layer and is electrically connected to the gate electrode of the same type of transistor provided for each of the plurality of pixel circuits.

Further, the image pickup apparatus according to another embodiment of the present disclosure is based on a semiconductor substrate provided with a plurality of sensor pixels for photoelectric conversion arranged in a matrix and charges output from the plurality of sensor pixels. It has a plurality of pixel circuits for outputting pixel signals, a circuit layer provided on the semiconductor substrate via an interlayer insulating layer, and a gate electrode of at least one or more transistors included in the pixel circuit. Is embedded and provided from above the semiconductor layer included in the circuit layer to the inside of the semiconductor layer.

According to the image pickup apparatus according to the embodiment of the present disclosure, a semiconductor substrate in which a plurality of sensor pixels are arranged in a matrix and a pixel that outputs a pixel signal based on the charge output from each of the sensor pixels. A circuit layer having a plurality of circuits is laminated, and the gate electrodes of at least one or more transistors included in the pixel circuit are extended to the plurality of pixel circuits and are provided for each of the plurality of pixel circuits. It is electrically connected to the gate electrode of the same type of transistor. Thereby, for example, the image pickup apparatus can reduce the number of wirings extending to the plurality of pixel circuits in the multilayer wiring layer provided above the circuit layer.

It is a vertical cross-sectional view explaining the laminated structure of the image pickup apparatus to which the technique which concerns on this disclosure is applied. It is an equivalent circuit diagram explaining the circuit structure of an image pickup apparatus. It is a schematic explanatory drawing which shows the planar arrangement of each transistor in the circuit layer of the image pickup apparatus which concerns on one Embodiment of this disclosure. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a vertical cross-sectional view in the AAA cut line of FIG. 4A. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a vertical cross-sectional view in the AAA cut line of FIG. 5A. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a vertical cross-sectional view in the B-BB cutting line of FIG. 6A. It is a vertical cross-sectional view which shows the variation of the cross-sectional structure of a gate electrode. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. 9 is a vertical cross-sectional view taken along the B-BB cutting line of FIG. 9A. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a top view which shows the plane arrangement of each structure in one cross section of a pixel circuit. It is a top view which shows the variation of the plane arrangement of the gate electrode of a pixel circuit. It is a vertical cross-sectional view in the B-BB cutting line of FIG. 13A. It is a vertical cross-sectional view which shows a part variation of the cross-sectional structure in the B-BB cutting line of FIG. 13A. It is a vertical cross-sectional view which shows a part variation of the cross-sectional structure in the B-BB cutting line of FIG. 13A. It is a vertical cross-sectional view which shows a part variation of the cross-sectional structure in the B-BB cutting line of FIG. 13A. It is a top view which shows the variation of the plane arrangement of the gate electrode of a pixel circuit. It is a vertical cross-sectional view in the B-BB cutting line of FIG. 17A. It is a vertical sectional view in the C-CC cutting line of FIG. 17A. It is a block diagram which shows an example of the schematic structure of the image pickup system provided with the image pickup apparatus which concerns on this embodiment. It is a flowchart which shows the flow of the imaging operation in an imaging system. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit. It is a figure which shows an example of the schematic structure of the endoscopic surgery system. It is a block diagram which shows an example of the functional structure of a camera head and a CCU.

Hereinafter, the embodiments in the present disclosure will be described in detail with reference to the drawings. The embodiments described below are specific examples of the present disclosure, and the technique according to the present disclosure is not limited to the following aspects. Further, the arrangement, dimensions, dimensional ratio, etc. of each component of the present disclosure are not limited to the modes shown in the respective figures.

The explanation will be given in the following order.
1. 1. Technical background 2. Overview 3. Example 4. Modification example 5. Application example

<1. Technical background ＞
First, the technical background of the present disclosure will be described with reference to FIGS. 1 and 2.

FIG. 1 is a vertical cross-sectional view illustrating a laminated structure of an image pickup apparatus 1 to which the technique according to the present disclosure is applied. As shown in FIG. 1, the image pickup apparatus 1 has a first laminate 10 including sensor pixels that perform photoelectric conversion, and a second laminate 20 including a pixel circuit that converts charges output from the sensor pixels into pixel signals. It is composed of stacking. The image pickup device 1 is a so-called back-illuminated image pickup device, and for example, a color filter 40 and a light receiving lens 50 are provided on the light incident surface (also referred to as the back surface) of the first laminated body 10.

The first laminated body 10 is configured by laminating a first insulating layer 46 on a semiconductor substrate 11. The semiconductor substrate 11 is, for example, a silicon substrate, and a photodiode PD, which is an n-type semiconductor region, is provided for each sensor pixel 12. The light that has passed through the light receiving lens 50 and the color filter 40 and is incident on the first laminated body 10 is photoelectrically converted by the photodiode PD.

Each of the sensor pixels 12 is separated by the element separation unit 43. The element separation unit 43 is provided with an insulating material so as to extend in the normal direction of one main surface of the semiconductor substrate 11, and electrically separates the adjacent sensor pixels 12. The element separation unit 43 may be provided, for example, so as to penetrate the semiconductor substrate 11 with _{SiO 2.}

Further, for example, the semiconductor substrate 11 is provided with a p-well layer 42, which is a p-type semiconductor region, in a part of the surface side on which the first insulating layer 46 is laminated, and p-wells are provided on the side surface of the element separation portion 43. Layer 44 is provided. The p-well layer 44 is a conductive type (specifically, p-type) semiconductor region different from the photodiode PD, and suppresses the generation of dark current due to a defect generated at the interface between the semiconductor substrate 11 and the element separation portion 43. To do.

Further, a fixed charge film 45 is provided on the light receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is provided with an insulating film having a negative fixed charge, and suppresses the generation of dark current due to the interface state on the light receiving surface side of the semiconductor substrate 11. The fixed charge film 45 may be provided with, for example, hafnium oxide, zircon oxide, aluminum oxide, titanium oxide, tantalum oxide, or the like.

The first laminated body 10 is provided with a transfer transistor TR and a floating diffusion FD for each sensor pixel 12. Specifically, the transfer transistor TR and the floating diffusion FD are provided on the side of the semiconductor substrate 11 opposite to the light incident surface side. The transfer transistor TR is a so-called vertical transistor, and takes out the electric charge photoelectrically converted by the photodiode PD provided inside the semiconductor substrate 11. The floating diffusion FD is provided inside the p-well layer 42 as a conductive type (specifically, n-type) semiconductor region different from the p-well layer 42, and charges read by the transfer transistor TR. accumulate.

The color filter 40 is provided on the surface (so-called back surface) opposite to the surface (so-called front surface) on which the first insulating layer 46 is provided on the semiconductor substrate 11. Specifically, the color filter 40 is provided in contact with the fixed charge film 45 for each sensor pixel 12, for example. The light receiving lens 50 is provided in contact with the color filter 40 for each one or a plurality of sensor pixels 12, for example.

The second laminated body 20 is configured by laminating a second insulating layer 57 on the circuit layer 21. The circuit layer 21 includes a semiconductor layer 48 made of a semiconductor material such as silicon and a circuit insulating layer 47 made of an insulating material.

A through wiring 54 is provided in the circuit insulating layer 47. The through wiring 54 is electrically insulated from the semiconductor layer 48 by covering the side surface with the circuit insulating layer 47. The through wiring 54 extends in the normal direction of one main surface of the circuit layer 21, and comprises a floating diffusion FD provided on the semiconductor substrate 11 and a multilayer wiring layer 23 provided on the second insulating layer 57. Connect electrically. For example, one through wiring 54 may be provided for each sensor pixel 12.

The second laminated body 20 may be provided by sequentially laminating the semiconductor layer 48, the circuit insulating layer 47, and the second insulating layer 57 on the first insulating layer 46. Alternatively, in the second laminated body 20, the circuit layer 21 and the silicon substrate on which the second insulating layer 57 is formed in advance are arranged so that the circuit layer 21 and the first insulating layer 46 face each other (that is, face-to-back). ) It may be provided by laminating with the first laminated body 10.

A pixel circuit is provided in the circuit layer 21 and the second insulating layer 57 of the second laminated body 20. The pixel circuit is provided in, for example, a through wiring 54 electrically connected to the floating diffusion FD, a multilayer wiring layer 23 and a contact plug 59 provided in the second insulating layer 57, and a field effect transistor 22 provided in the circuit layer 21. It is composed of. One pixel circuit is provided for each one or a plurality of sensor pixels 12, for example. The pixel circuit converts the charges output from each of the sensor pixels 12 and stored in the floating diffusion FD into pixel signals. For example, one pixel circuit may be provided for every four sensor pixels 12.

FIG. 2 is an equivalent circuit diagram illustrating the circuit structure of the image pickup apparatus 1. As shown in FIG. 2, the image pickup apparatus 1 includes, for example, a photodiode PD, a transfer transistor TR, a floating diffusion FD, an FD conversion gain switching transistor FDG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. And.

As described above, the photodiode PD, the transfer transistor TR, and the floating diffusion FD are provided in the first laminated body 10. The FD conversion gain switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided in the second laminated body 20.

The photodiode PD performs photoelectric conversion to generate an electric charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to the reference potential line (eg, ground).

The transfer transistor TR is, for example, a vertical MOS (Metal Oxide Semiconductor) transistor, and transfers the charge photoelectrically converted by the photodiode PD to the floating diffusion FD. The source of the transfer transistor TR is electrically connected to the cathode of the photodiode PD. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line.

The floating diffusion FD temporarily holds the electric charge output from the photodiode PD via the transfer transistor TR. The floating diffusion FD is electrically connected to the drain of the transfer transistor TR, the gate of the amplification transistor AMP, and the source of the reset transistor RST.

The FD conversion gain switching transistor FDG is, for example, a MOS transistor, and is provided to switch the charge-voltage conversion efficiency in the pixel circuit. When the FD conversion gain switching transistor FDG is turned on, the capacitance C of the floating diffusion FD can be increased by the gate capacitance of the FD conversion gain switching transistor FDG as compared with the off state.

Since the charge Q stored in the floating diffusion FD is represented by the product of the capacitance C and the voltage V, when the capacitance C of the floating diffusion FD is large, the voltage V after conversion by the amplification transistor AMP becomes low. It ends up. On the other hand, when the charge Q output from the photodiode PD is large, the charge Q from the photodiode PD cannot be held by the floating diffusion FD unless the capacitance C of the floating diffusion FD is sufficiently large. It is also important that the capacitance C of the floating diffusion FD is appropriately large so that the voltage V converted by the amplification transistor AMP does not become excessively high.

Therefore, the FD conversion gain switching transistor FDG can switch the charge-voltage conversion efficiency in the pixel circuit by switching the on or off state to change the capacitance C of the floating diffusion FD.

The reset transistor RST is, for example, a MOS transistor, and resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The source of the reset transistor RST is electrically connected to the floating diffusion FD. The drain of the reset transistor RST is electrically connected to the power supply line VDD, and the gate of the reset transistor RST is electrically connected to the pixel drive line.

The amplification transistor AMP is, for example, a MOS transistor, and generates a voltage signal as a pixel signal according to the level of electric charge held in the floating diffusion FD. The amplification transistor AMP constitutes a so-called source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of electric charge generated by the photodiode PD. The drain of the amplification transistor AMP is electrically connected to the power supply line VDD. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

The selection transistor SEL is, for example, a MOS transistor, and controls the output timing of the pixel signal from the pixel circuit. When the selection transistor SEL is turned on, the amplification transistor AMP can amplify the potential of the floating diffusion FD and output a voltage corresponding to the amplified potential via the vertical signal line. The drain of the selection transistor SEL is electrically connected to the source of the amplification transistor AMP. The source of the selection transistor SEL is electrically connected to the vertical signal line, and the gate of the selection transistor SEL is electrically connected to the pixel drive line.

With the above configuration, the image pickup apparatus 1 can output a pixel signal corresponding to the amount of light incident on the sensor pixel 12 of the first laminated body 10 from the pixel circuit.

<2. Overview>
Subsequently, the outline of the technique according to the present disclosure will be described with reference to FIG. FIG. 3 is a schematic explanatory view showing a planar arrangement of each transistor in the circuit layer 21 of the image pickup apparatus 1 according to the embodiment of the present disclosure.

As described with reference to FIGS. 1 and 2, in the image pickup apparatus 1, for example, the FD conversion gain switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor are applied to the circuit layer 21 of the second laminated body 20. SEL is provided. In the image pickup apparatus 1 according to the present embodiment, the gate electrodes of at least one or more transistors other than the amplification transistor AMP are extended over a plurality of pixel circuits, so that the gates of the same type of transistors in the plurality of pixel circuits are gated. It is used as a wiring that electrically connects electrodes.

Specifically, as shown in the equivalent circuit diagram of FIG. 2, the gate electrodes of the FD conversion gain switching transistor FDG, the reset transistor RST, and the selection transistor SEL, excluding the amplification transistor AMP, are of the same type as the other pixel circuits. Together with the gate electrode of the transistor, it is electrically connected to a pixel drive line or a vertical signal line. The wiring for electrically connecting each of these gate electrodes can be provided, for example, in the multilayer wiring layer 23 inside the second insulating layer 57. However, as the sensor pixel 12 has been miniaturized, the area where the pixel circuit is provided has been miniaturized, and as a result, the wiring provided in the multilayer wiring layer 23 has become narrower and narrower in pitch. Therefore, the process difficulty in forming the wiring in the multilayer wiring layer 23 is increasing.

In the image pickup apparatus 1 according to the present embodiment, at least one or more gate electrodes of the FD conversion gain switching transistor FDG, the reset transistor RST, or the selection transistor SEL and the gate electrodes of the same type of transistors of a plurality of pixel circuits are electrically connected. The wiring connected to is provided on the circuit layer 21 integrally with the gate electrode. According to this, the image pickup apparatus 1 can widen the width and pitch of the wiring formed in the multi-layer wiring layer 23 by reducing the number of wirings formed in the multi-layer wiring layer 23. Therefore, the multi-layer wiring layer 1 can be widened. The process difficulty in forming 23 can be reduced. Further, the image pickup apparatus 1 can reduce the resistance and capacitance of the wiring formed on the multilayer wiring layer 23 by widening the width and pitch of the wiring formed on the multilayer wiring layer 23.

In an imaging device having a two-dimensional structure, sensor pixels 12 and pixel circuits are provided in the same plane, so it is difficult to form wiring extending over a plurality of pixel circuits due to the demand for arrangement of each element. Is. On the other hand, since the image pickup apparatus 1 according to the present embodiment has a three-dimensional structure, the sensor pixels 12 and the pixel circuits can be stacked in the vertical direction. As a result, the image pickup apparatus 1 can reduce the number of elements provided in the circuit layer 21, so that it is possible to form wiring extending over a plurality of pixel circuits. Further, in the image pickup apparatus 1, by sharing one pixel circuit among the four sensor pixels 12, the area where one pixel circuit is formed is compared with the case where the pixel circuit is formed for each sensor pixel 12. The size can be expanded four times. This makes it possible for the image pickup apparatus 1 to more easily secure a region in which wiring extending over a plurality of pixel circuits is formed.

For example, as shown in FIG. 3, in the image pickup apparatus 1 to which the technique according to the present disclosure is applied, the first direction (for example, FIG. The semiconductor layer 48 is provided so as to extend in the vertical direction facing the third layer. Further, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL are placed in a second direction (for example, in the left-right direction facing FIG. 3) perpendicular to the first direction. ), And crossing with the semiconductor layer 48, each transistor is formed.

According to this, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL extend in the second direction over a plurality of repeating regions RU. Therefore, it functions as a wiring for electrically connecting the gate electrodes 25 of the reset transistor RST, the gate electrodes 26 of the FD conversion gain switching transistor FDG, and the gate electrodes 28 of the selection transistor SEL. Therefore, since the image pickup apparatus 1 can form a part of the wiring provided in the multilayer wiring layer 23 inside the second insulating layer 57 on the circuit layer 21, the number of wirings provided in the multilayer wiring layer 23 Can be reduced. Therefore, the image pickup apparatus 1 can relax the design rule in the multilayer wiring layer 23.

In FIG. 3, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL are provided so as to extend in the second direction. Such techniques are not limited to such examples. At least one of the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL may be provided so as to extend in the second direction.

The gate electrode 27 of the amplification transistor AMP is not electrically connected to the gate electrode of the amplification transistor AMP of another pixel circuit, but is electrically connected to the floating diffusion FD. Therefore, the gate electrode 27 of the amplification transistor AMP is provided in a rectangular shape, for example, so as to overlap the inflection point of the semiconductor layer 48. According to this, since the gate electrode 27 of the amplification transistor AMP can have a larger gate length, it is possible to suppress random telegraph noise (Random Telegraph Noise: RTN).

<3. Example>
Subsequently, a specific structure of the image pickup apparatus 1 according to the present embodiment will be described with reference to FIGS. 4A to 12. 4A, 5A, 6A, 8, 9A, and 10 to 12 are plan views showing the planar arrangement of each configuration in one cross section of the pixel circuit. 4A, 5A, 6A, 8, 9A, and 10 to 12 show only the configuration of the layer of interest, and the configuration of the layer not of interest is omitted. The sensor pixel 12 and the pixel circuit of the image pickup apparatus 1 are configured by repeatedly arranging the repeating units RU shown in FIGS. 4A, 5A, 6A, 8, 9A, and 10 to 12 on a plane. ..

4B is a vertical sectional view taken along the AAA cutting line of FIG. 4A, FIG. 5B is a vertical sectional view taken along the AAA cutting line of FIG. 5A, and FIG. 6B is a B-BB of FIG. 6A. It is a vertical cross-sectional view in the cutting line, and FIG. 9B is a vertical cross-sectional view in the B-BB cutting line of FIG. 9A.

As shown in FIGS. 4A and 4B, the semiconductor substrate 11 is provided with element separation portions 43 in a grid pattern so as to separate the sensor pixels 12 arranged in a matrix. A polysilicon layer 602 that electrically connects to the semiconductor substrate 11 of each of the four sensor pixels 12 is provided on the intersection of the element separation portions 43 at the center of the repeating unit RU. The polysilicon layer 602 functions as a floating diffusion FD shared by the four sensor pixels 12. A contact plug 620 penetrating the circuit insulating layer 47 is provided on the polysilicon layer 602 at a later stage.

Further, at the intersection of the polysilicon layer 602 and the element separation portion 43 on the diagonal line, a polysilicon layer 601 that electrically connects to the semiconductor substrate 11 is provided. The polysilicon layer 601 is provided to electrically connect the anode of the photodiode PD and the reference potential line VSS. Contact plugs 625, 626, 627, and 628 penetrating the circuit insulating layer 47 are provided on the polysilicon layer 601 at a later stage.

Further, at the center of each of the four sensor pixels 12, vertical gate electrodes TG1, TG2, TG3, and TG4 of the transfer transistor TR are provided, respectively. On the vertical gate electrodes TG1, TG2, TG3, and TG4, wiring layers 611, 612, 613, and 614 are provided so as to be routed over the element separating portion 43 via the insulating layer 46A. The wiring layers 611, 612, 613, and 614 above the element separation unit 43 are provided with contact plugs 621, 622, 623, and 624 that penetrate the circuit insulation layer 47 at a later stage.

As shown in FIGS. 5A and 5B, each configuration shown in FIGS. 4A and 4B is embedded in the first insulating layer 46. A semiconductor layer 48 is provided on the first insulating layer 46. The semiconductor layer 48 is bent twice in the first direction (for example, FIG. 5A) so as to avoid the region where the contact plugs 620, 621, 622, 623, 624, 625, 626, 627, and 628 are provided in the subsequent stage. It is provided so as to extend in the vertical direction (in the vertical direction) facing the. The semiconductor layer 48 is provided, for example, by depositing silicon or the like in the above-mentioned predetermined region in an island shape.

As shown in FIGS. 6A and 6B, the semiconductor layer 48 shown in FIGS. 5A and 5B is embedded in the circuit insulating layer 47, and the circuit layer 21 is composed of the semiconductor layer 48 and the circuit insulating layer 47. The circuit layer 21 includes the gate electrode 25 of the reset transistor RST and the FD conversion gain switching transistor FDG in the second direction (for example, the left-right direction facing FIG. 6A) orthogonal to the first direction in which the semiconductor layer 48 extends. A gate electrode 26 and a gate electrode 28 of the selection transistor SEL are provided. The gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL extend beyond the repetition unit RU, and are the same type of transistors of the other repetition unit RU. It is electrically connected to the gate electrode of. That is, these gate electrodes 25, 26, and 28 also function as wiring for electrically connecting the gate electrodes of the same type of transistors of the plurality of repeating units RU.

Further, the gate electrode 27 of the amplification transistor AMP is provided, for example, in a rectangular shape in a region overlapping the inflection point of the semiconductor layer 48.

Here, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplification transistor AMP, and the gate electrode 28 of the selection transistor SEL are provided in the cross-sectional structure shown in FIG. 6B. You may.

Specifically, these gate electrodes 25, 26, 27, and 28 are provided on the polysilicon layer 711 embedded in the semiconductor layer 48 via the gate insulating film (not shown) and the polysilicon layer 711. The electrode layer 713 may be composed of a barrier layer 712 provided so as to cover the side surface and the bottom surface of the electrode layer 713.

For example, after an interlayer insulating film is formed on the semiconductor layer 48, a groove is formed in the semiconductor layer 48 by etching or the like. Next, a gate insulating film (not shown) is formed inside the groove, and the groove is embedded in the polysilicon layer 711. Subsequently, the upper portion of the polysilicon layer 711 is retracted (also referred to as recess) to form a groove, and a barrier layer 712 made of a Ti or W metal or a metal compound is formed inside the groove. After that, the electrode layer 713 is formed by embedding the groove on the upper part of the polysilicon layer 711 with Cu or the like. The gate electrodes 25, 26, 27, 28 may be formed in such a configuration.

The gate electrodes 25, 26, 27, and 28 having such a structure have channels formed around the polysilicon layer 711 embedded in the semiconductor layer 48, so that the gate length can be made longer. According to this, since the gate electrodes 25, 26, 27, and 28 can reduce the area occupied by the circuit layer 21, the degree of freedom in layout of each configuration in the pixel circuit can be further increased. Further, since the gate electrodes 25, 26, 27, and 28 are provided as a laminated structure of the polysilicon layer 711 and the electrode layer 713, deterioration of the interface state due to the use of the metal gate is suppressed, and the wiring resistance is reduced. The rise can be suppressed. Further, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 713 formed of the metal material, the difficulty of the forming process of the gate electrodes 25, 26, 27, 28 can be reduced. Can be lowered.

Further, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplification transistor AMP, and the gate electrode 28 of the selection transistor SEL are provided in the cross-sectional structure shown in FIG. May be good.

As shown in FIG. 7, these gate electrodes 25, 26, 27, 28 are composed of an electrode layer 721 made of a metal material embedded in the semiconductor layer 48 via a gate insulating film (not shown). May be good. For example, after an interlayer insulating film is formed on the semiconductor layer 48, a groove is formed in the semiconductor layer 48 by etching or the like. Next, a gate insulating film (not shown) is formed inside the groove, and the electrode layer 721 is formed by embedding the groove with Cu or the like. The gate electrodes 25, 26, 27, 28 may be formed in such a configuration.

The gate electrodes 25, 26, 27, and 28 having such a structure have a longer gate length because channels are formed around the electrode layer 721 embedded in the semiconductor layer 48. According to this, since the gate electrodes 25, 26, 27, and 28 can reduce the occupied area in the circuit layer 21, the degree of freedom in layout of each configuration in the pixel circuit can be further increased. Further, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 721 formed of a metal material, the difficulty of the forming process of the gate electrodes 25, 26, 27, 28 can be reduced. Can be lowered.

As shown in FIG. 8, on the semiconductor layer 48 and the gate electrode 27 of the amplification transistor AMP, the drain, source, or gate of each transistor is electrically connected to the wiring formed in the upper layer. The contacts 631, 632, 633, 634, 635, 636, and 637 are provided so as to penetrate a part of the second insulating layer 57. Specifically, the contacts 631 and 632 are provided on the semiconductor layers 48 on both sides of the gate electrode 25 of the reset transistor RST, respectively. Further, the contact 633 is provided on the semiconductor layer 48 on the side opposite to the side where the gate electrode 25 is provided, sandwiching the gate electrode 26 of the FD conversion gain switching transistor FDG. Further, the contact 637 is provided on the semiconductor layer 48 on the side opposite to the side where the gate electrode 27 is provided, sandwiching the gate electrode 28 of the selection transistor SEL. Further, the contacts 634 and 636 are provided on the semiconductor layer 48 protruding from the gate electrode 27 of the amplification transistor AMP, respectively, and the contacts 635 are provided on the gate electrode 27 of the amplification transistor AMP.

Further, as shown in FIG. 8, the contact plugs 620, 621, 622, 623, 624, 625, 626, 627, and 628 are provided so as to penetrate a part of the circuit insulating layer 47 and the second insulating layer 57. ..

As shown in FIGS. 9A and 9B, the contacts 631, 632, 633, 634, 635, 636, 637, and the contact plugs 620, 621, 622, 623, 624, 625, 626, 627, 628 are second insulated. It is embedded in layers 57A and 57B. First wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, 654 are provided on these contacts and contact plugs, respectively.

Specifically, the first wiring layer 641 is provided on the contact plug 625, and the first wiring layer 642 is provided on the contact plug 626. The first wiring layer 643 is provided on the contact plug 622, the first wiring layer 644 is provided on the contact plug 624, and the first wiring layer 645 is provided on the contact plug 627. The first wiring layer 646 is provided on the contact plug 623, the first wiring layer 647 is provided on the contact plug 628, and the first wiring layer 648 is provided on the contact plug 621. The first wiring layer 654 is provided above the contact 637, and the first wiring layer 653 is provided above the contact 634. Further, the first wiring layer 651 is provided so as to electrically connect the contacts 632 and 636, and the first wiring layer 652 electrically connects the contacts 631, 633, 635 and the contact plug 620. Provided.

Here, the first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, 654 may be provided in the cross-sectional structure shown in FIG. 9B.

Specifically, these first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, 654 are the metal layers 733 embedded in the second insulating layer 57B. It may be composed of a barrier layer 732 provided so as to cover the side surface and the bottom surface of the metal layer 733. For example, after the second insulating layers 57A and 57B are formed, a groove is formed in the second insulating layer 57B by etching or the like, and a barrier layer 732 made of a Ti or W metal or a metal compound is formed inside the groove. Is formed. After that, the metal layer 733 is formed by embedding the groove with Cu or the like. The first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, 654 may be formed in such a configuration.

As shown in FIG. 10, above the first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 653, 654, the contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, 673 are provided. Specifically, the contact 661 is provided on the first wiring layer 641, the contact 662 is provided on the first wiring layer 646, and the contact 663 is provided on the first wiring layer 642. The contact 664 is provided on the first wiring layer 643, the contact 665 is provided on the first wiring layer 644, and the contact 666 is provided on the first wiring layer 645. The contact 667 is provided on the first wiring layer 653, the contact 673 is provided on the first wiring layer 654, and the contact 668 is provided on the first wiring layer 647. The contact 671 is provided on the first wiring layer 648, and the contact 672 is provided on the first wiring layer 651.

As shown in FIG. 11, the contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, 673 extend in the second direction (horizontal direction facing FIG. 11). Second wiring layers 681, 682, 683, 684, 685, 686, 687, 688 are provided. The contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, and 673 are embedded in the second insulating layer 57.

Specifically, the second wiring layer 681 is provided on the contacts 661 and 663, and the second wiring layer 688 is provided on the contacts 668, 667 and 666. The second wiring layers 681 and 688 are electrically connected to the reference potential line VSS. The second wiring layer 682 is provided on the contact 662 and supplies an electric potential to the vertical gate electrode TG1. The second wiring layer 683 is provided on the contact 671 and supplies an electric potential to the vertical gate electrode TG2. The second wiring layer 685 is provided on the contact 664 and supplies an electric potential to the vertical gate electrode TG3. The second wiring layer 686 is provided on the contact 665 and supplies an electric potential to the vertical gate electrode TG4. The second wiring layer 684 is provided on the contact 672 and is electrically connected to the power supply line VDD. The second wiring layer 687 is provided on the contact 673 and is electrically connected to the vertical signal line.

As shown in FIG. 12, on the second wiring layer 681, 682, 683, 684, 685, 686, 687, 688 via the contacts 674, 675, 676, 677, 678, 679, the first direction. Third wiring layers 692, 693, 694, 695, 696, 697, 698 extending in (vertical direction facing FIG. 12) are provided. These contacts and the wiring layer are embedded in the second insulating layer 57.

Specifically, the third wiring layer 692 is provided so as to be electrically connected to the reference potential line VSS and electrically connected to the second wiring layers 681 and 688 via the contacts 676 and 677. The third wiring layer 693 is provided so as to be electrically connected to the vertical signal line and electrically connected to the second wiring layer 687 via the contact 679. The third wiring layers 694, 695, 696 are provided so as to be electrically connected to the vertical signal line. The third wiring layer 697 is provided so as to be electrically connected to the reference potential line VSS and electrically connected to the second wiring layers 681 and 688 via the contacts 674 and 675. The third wiring layer 698 is provided so as to be electrically connected to the power supply line VDD and electrically connected to the second wiring layer 684 via the contact 678.

The specific structure of the image pickup apparatus 1 according to the present embodiment has been described above. In the image pickup apparatus 1 according to the present embodiment, among the wiring provided over the plurality of repeating units RU, the wiring connecting each of the gate electrodes 25 of the reset transistor RST and the gate electrode 26 of the FD conversion gain switching transistor FDG, respectively. At least one or more of the wirings connecting the above or the gate electrodes 28 of the selection transistor SEL are provided on the circuit layer 21. As a result, these wirings are not provided in the same layer as the second wiring layers 681, 682, 683, 684, 685, 686, 687, 688, so that the image pickup apparatus 1 has the second wiring layers 681, 682, 683, The width and pitch of 684, 685, 686, 687, 688 can be further increased. That is, the image pickup apparatus 1 can relax the design rules in the second wiring layers 681, 682, 683, 684, 685, 686, 687, and 688.

<4. Modification example>
Subsequently, a modified example of the image pickup apparatus 1 according to the present embodiment will be described with reference to FIGS. 13A to 17C. A modification of the image pickup apparatus 1 according to the present embodiment is a cross-sectional structure of the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplification transistor, and the gate electrode 28 of the selection transistor SEL. This is an example showing a variation of.

FIG. 13A is a plan view showing variations in the plan arrangement of the gate electrodes 25, 26, 27, 28 of the pixel circuit. FIG. 13B is a vertical cross-sectional view of the B-BB cutting line of FIG. 13A. 14 to 16 are vertical cross-sectional views showing a partial variation of the cross-sectional structure in the B-BB cutting line of FIG. 13A.

As shown in FIGS. 13A and 13B, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplification transistor, and the gate electrode 28 of the selection transistor SEL are gate insulating films 740. The polysilicon layer 741 provided on the semiconductor layer 48, the electrode layer 743 provided on the polysilicon layer 741, and the barrier layer 742 provided so as to cover the side surfaces and the bottom surface of the electrode layer 743. It may be composed of and.

For example, after the interlayer insulating film 744 is formed on the semiconductor layer 48, a groove is formed in the interlayer insulating film 744 by etching or the like. Next, the gate insulating film 740 and the polysilicon layer 741 are sequentially laminated on the bottom surface of the groove. Subsequently, the upper portion of the polysilicon layer 711 is retracted (also referred to as recess) to form a groove, and a barrier layer 742 made of a Ti or W metal or a metal compound is formed inside the groove. After that, the electrode layer 743 is formed by embedding the groove on the upper part of the polysilicon layer 741 with Cu or the like. Thereby, the gate electrodes 25, 26, 27 and 28 can be formed.

The gate electrodes 25, 26, 27, and 28 having such a structure are provided as a laminated structure of the polysilicon layer 741 and the electrode layer 743, thereby suppressing deterioration of the interface state due to the use of the metal gate and at the same time. It is possible to suppress an increase in wiring resistance. Further, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 743 formed of the metal material, the difficulty of the forming process of the gate electrodes 25, 26, 27, 28 can be reduced. Can be lowered. Since the width required for the gate electrode and the width required for wiring are different between the gate electrodes 25, 26, 27, and 28, the width provided on the semiconductor layer 48 and the width provided on the circuit insulating layer 47 are different. Is provided so as to be different from.

Further, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplification transistor AMP, and the gate electrode 28 of the selection transistor SEL have a cross-sectional structure shown in FIGS. 14 to 16. It may be provided.

As shown in FIG. 14, these gate electrodes 25, 26, 27, 28 may be composed of an electrode layer 751 made of a metal material provided on the semiconductor layer 48 via the gate insulating film 750. .. For example, the gate electrodes 25, 26, 27, and 28 may be configured by sequentially laminating a gate insulating film 750 and an electrode layer 751 made of a metal material on the semiconductor layer 48.

The gate electrodes 25, 26, 27, 28 having such a structure can be formed as a simpler structure. Further, since the widths required for the gate electrodes and the widths required for wiring are different between the gate electrodes 25, 26, 27, and 28, the gate electrodes 25, 26, 27, and 28 are provided on the semiconductor layer 48 and the circuit insulating layer 47. It is provided so as to be different from the width to be provided. Since the gate electrodes 25, 26, 27, and 28 having such a structure are formed as a metal gate, the gate insulating film 750 is made of a so-called High-k material.

As shown in FIG. 15, these gate electrodes 25, 26, 27, 28 are provided on the polysilicon layer 761 provided on the semiconductor layer 48 and the polysilicon layer 711 via the gate insulating film 760. It may be composed of the barrier layer 762 provided and the electrode layer 763 provided on the barrier layer 762. For example, the gate electrodes 25, 26, 27, and 28 have a gate insulating film 760, a polysilicon layer 761, a barrier layer 762 made of a metal or a metal compound of Ti or W, and an electrode layer 763 made of Cu or the like on the semiconductor layer 48. May be configured by sequentially laminating.

The gate electrodes 25, 26, 27, and 28 having such a structure are provided as a laminated structure of the polysilicon layer 761 and the electrode layer 763, thereby suppressing deterioration of the interface state due to the use of the metal gate and at the same time. It is possible to suppress an increase in wiring resistance. Since the width required for the gate electrode and the width required for wiring are different between the gate electrodes 25, 26, 27, and 28, the width provided on the semiconductor layer 48 and the width provided on the circuit insulating layer 47 are different. Is provided so as to be different from.

As shown in FIG. 16, these gate electrodes 25, 26, 27, 28 have an electrode layer 772 embedded in an interlayer insulating film 770 provided on the semiconductor layer 48, and side surfaces and bottom surfaces of the electrode layer 772. It may be composed of a barrier layer 771 provided so as to cover the barrier layer 771. For example, after the interlayer insulating film 770 is formed on the semiconductor layer 48, a groove is formed in the interlayer insulating film 770 by etching or the like. Next, the electrode layer 772 is formed by embedding the groove with Cu or the like. The gate electrodes 25, 26, 27, 28 may be formed in such a configuration.

Since the gate electrodes 25, 26, 27, 28 having such a structure can be formed without etching the electrode layer 713 formed of the metal material, the process of forming the gate electrodes 25, 26, 27, 28 Difficulty can be reduced. Since the width required for the gate electrode and the width required for wiring are different between the gate electrodes 25, 26, 27, and 28, the width provided on the semiconductor layer 48 and the width provided on the circuit insulating layer 47 are different. Is provided so as to be different from.

FIG. 17A is a plan view showing variations in the plan arrangement of the gate electrodes 25, 26, 27, 28 of the pixel circuit. 17B is a vertical cross-sectional view of the B-BB cutting line of FIG. 17A, and FIG. 17C is a vertical cross-sectional view of the C-CC cutting line of FIG. 17A.

As shown in FIGS. 17A to 17C, these gate electrodes 25, 26, 28 have a semiconductor layer (not shown) via a gate insulating film (not shown), similarly to the gate electrodes 25, 26, 28 shown in FIG. 6B. It may be composed of a polysilicon layer 711 embedded in 48, an electrode layer 713 provided on the polysilicon layer 711, and a barrier layer 712 provided so as to cover the side surface and the bottom surface of the electrode layer 713. ..

Further, the gate electrode 27 of the amplification transistor AMP has a polysilicon layer 781 in which the first opening 781A and the second opening 781B formed in the semiconductor layer 48 are embedded via a gate insulating film (not shown). It may be composed of an electrode layer 783 provided on the polysilicon layer 781 and a barrier layer 782 provided so as to cover the side surface and the bottom surface of the electrode layer 783.

That is, the amplification transistor AMP may be provided in a so-called FinFET structure in which the semiconductor layer 48 sandwiched between the first opening 781A and the second opening 781B is used as a channel. Specifically, in the FinFET structure amplification transistor AMP, the semiconductor layer 48 sandwiched between the first opening 781A and the second opening 781B has a channel perpendicular to the paper surface of FIG. 17C. It is formed. In the Accelerated Transistor AMP having a FinFET structure, electrons flow in the center of the channel away from the interface of the semiconductor layer 48, so that random telegraph noise (Random Telegraph Noise: RTN) can be further suppressed.

The gate electrodes 25, 26, 27, 28 having such a structure can be formed by the same process. For example, after forming an interlayer insulating film on the semiconductor layer 48, a groove, a first opening 781A, and a second opening 781B are formed in the semiconductor layer 48 by etching or the like. Next, a gate insulating film (not shown) is formed inside the groove, and the groove, the first opening 781A, and the second opening 781B are embedded in the polysilicon layers 711 and 781. Subsequently, the upper portions of the polysilicon layers 711 and 781 are retracted (also referred to as recesses) to form a groove, and the barrier layers 712 and 782 made of a Ti or W metal or a metal compound are formed inside the groove. To. After that, the electrode layers 713 and 783 are formed by embedding the groove on the upper part of the polysilicon layer 711 with Cu or the like. The gate electrodes 25, 26, 27, 28 may be formed in such a configuration.

Since the gate electrodes 25, 26, and 28 have channels formed around the polysilicon layer 711 embedded in the semiconductor layer 48, the gate length can be made longer. According to this, since the gate electrodes 25, 26, and 28 can reduce the area occupied by the circuit layer 21, the degree of freedom in layout of each configuration in the pixel circuit can be further increased. Further, since the gate electrode 27 can form the amplification transistor AMP as a FinFET structure, the electrons flowing through the channel can be separated from the interface of the semiconductor layer 48. According to this, the gate electrode 27 can further suppress the RTN and can reduce the area occupied by the circuit layer 21, so that the degree of freedom in layout of each configuration in the pixel circuit can be further increased. it can.

Further, since the gate electrodes 25, 26, 27, and 28 are provided as a laminated structure of the polysilicon layer 711 and the electrode layer 713, deterioration of the interface state due to the use of the metal gate is suppressed, and the wiring resistance is reduced. The rise can be suppressed. Further, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 713 formed of the metal material, the difficulty of the forming process of the gate electrodes 25, 26, 27, 28 can be reduced. Can be lowered.

<5. Application example>
Hereinafter, an application example of the image pickup apparatus 1 according to the present embodiment will be described with reference to FIGS. 18 to 23.

(Application to imaging system)
First, an example of application of the imaging apparatus according to the embodiment of the present disclosure to an imaging system will be described with reference to FIGS. 18 and 19. FIG. 18 is a block diagram showing an example of a schematic configuration of an imaging system 900 including the imaging device 1 according to the present embodiment. FIG. 19 is a flowchart showing the flow of the imaging operation in the imaging system 900.

As shown in FIG. 18, the imaging system 900 is, for example, an imaging device such as a digital still camera or a video camera, or an electronic device such as a mobile terminal device such as a smartphone or a tablet terminal.

The image pickup system 900 includes, for example, a lens group 941, a shutter 942, an image pickup device 1 according to the present embodiment, a DSP circuit 943, a frame memory 944, a display unit 945, a storage unit 946, and an operation unit 947. , A power supply unit 948 is provided. In the image pickup system 900, the image pickup device 1, the DSP circuit 943, the frame memory 944, the display unit 945, the storage unit 946, the operation unit 947, and the power supply unit 948 are connected to each other via the bus line 949.

The image pickup device 1 outputs image data according to the incident light that has passed through the lens group 941 and the shutter 942. The DSP circuit 943 is a signal processing circuit that processes a signal (that is, image data) output from the image pickup apparatus 1. The frame memory 944 temporarily holds the image data processed by the DSP circuit 943 in frame units. The display unit 945 is a panel-type display device such as a liquid crystal panel or an organic EL (Electroluminescence) panel, and displays a moving image or a still image captured by the image pickup device 1. The storage unit 946 includes a recording medium such as a semiconductor memory or a hard disk, and records image data of a moving image or a still image captured by the imaging device 1. The operation unit 947 outputs operation commands for various functions of the image pickup system 900 based on the operation by the user. The power supply unit 948 is various power sources that supply the operating power of the image pickup device 1, the DSP circuit 943, the frame memory 944, the display unit 945, the storage unit 946, and the operation unit 947.

Next, the imaging procedure in the imaging system 900 will be described.

As shown in FIG. 19, the user instructs the start of imaging by operating the operation unit 947 (S101). As a result, the operation unit 947 transmits an imaging command to the imaging device 1 (S102). Upon receiving an imaging command, the imaging device 1 executes imaging by a predetermined imaging method (S103).

The image pickup device 1 outputs the captured image data to the DSP circuit 943. The DSP circuit 943 performs predetermined signal processing (for example, noise reduction processing) on the image data output from the image pickup apparatus 1 (S104). The DSP circuit 943 holds the image data to which the predetermined signal processing has been performed in the frame memory 944. After that, the frame memory 944 stores the image data in the storage unit 946 (S105). In this way, the imaging in the imaging system 900 is performed.

(Application to mobile control system)
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving, etc., which runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 20, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 21, the vehicle 12100 has image pickup units 12101, 12102, 12103, 12104, 12105 as the image pickup unit 12031.

The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100, for example. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The images in front acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 21 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and a temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a mobile control system to which the technology according to the present disclosure can be applied. The technique according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. According to the technique according to the present disclosure, the wiring design rule provided in the multilayer wiring layer is relaxed, so that the wiring resistance and the wiring capacity are reduced, so that higher speed photography can be performed. According to this, in the moving body control system, even when the moving body is moving at a higher speed, the control using the captured image can be performed with higher accuracy.

(Application to endoscopic surgery system)
FIG. 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technique according to the present disclosure (the present technique) can be applied.

FIG. 22 shows a surgeon (doctor) 11131 performing surgery on patient 11132 on patient bed 11133 using the endoscopic surgery system 11000. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as an abdominal tube 11111 and an energy treatment tool 11112, and a support arm device 11120 that supports the endoscope 11100. , A cart 11200 equipped with various devices for endoscopic surgery.

The endoscope 11100 is composed of a lens barrel 11101 in which a region having a predetermined length from the tip is inserted into the body cavity of the patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 configured as a so-called rigid mirror having a rigid barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible mirror having a flexible barrel. Good.

An opening in which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101 to be an objective. It is irradiated toward the observation target in the body cavity of the patient 11132 through the lens. The endoscope 11100 may be a direct endoscope, a perspective mirror, or a side endoscope.

An optical system and an image pickup element are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is focused on the image pickup element by the optical system. The observation light is photoelectrically converted by the image sensor, and an electric signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated. The image signal is transmitted as RAW data to the camera control unit (CCU: Camera Control Unit) 11201.

The CCU11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal for displaying an image based on the image signal, such as development processing (demosaic processing).

The display device 11202 displays an image based on the image signal processed by the CCU 11201 under the control of the CCU 11201.

The light source device 11203 is composed of, for example, a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operating part or the like.

The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information and input instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100.

The treatment tool control device 11205 controls the drive of the energy treatment tool 11112 for cauterizing, incising, sealing a blood vessel, or the like of a tissue. The pneumoperitoneum device 11206 uses a gas in the pneumoperitoneum tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing the field of view by the endoscope 11100 and securing the work space of the operator. To send. The recorder 11207 is a device capable of recording various information related to surgery. The printer 11208 is a device capable of printing various information related to surgery in various formats such as text, images, and graphs.

The light source device 11203 that supplies the irradiation light to the endoscope 11100 when photographing the surgical site can be composed of, for example, an LED, a laser light source, or a white light source composed of a combination thereof. When a white light source is configured by combining RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. Therefore, the light source device 11203 adjusts the white balance of the captured image. It can be carried out. Further, in this case, the laser light from each of the RGB laser light sources is irradiated to the observation target in a time-division manner, and the drive of the image sensor of the camera head 11102 is controlled in synchronization with the irradiation timing to correspond to each of RGB. It is also possible to capture the image in a time-division manner. According to this method, a color image can be obtained without providing a color filter on the image sensor.

Further, the drive of the light source device 11203 may be controlled so as to change the intensity of the output light at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of changing the light intensity to acquire an image in a time-divided manner and synthesizing the image, so-called high dynamic without blackout and overexposure. A range image can be generated.

Further, the light source device 11203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate light in a narrow band as compared with the irradiation light (that is, white light) in normal observation, the surface layer of the mucous membrane. A so-called narrow band imaging (Narrow Band Imaging) is performed in which a predetermined tissue such as a blood vessel is photographed with high contrast. Alternatively, in the special light observation, fluorescence observation may be performed in which an image is obtained by fluorescence generated by irradiating with excitation light. In fluorescence observation, the body tissue is irradiated with excitation light to observe the fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and the body tissue is injected. It is possible to obtain a fluorescence image by irradiating excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 may be configured to be capable of supplying narrow band light and / or excitation light corresponding to such special light observation.

FIG. 23 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU11201 shown in FIG. 22.

The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. CCU11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and CCU11201 are communicatively connected to each other by a transmission cable 11400.

The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. The observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

The image pickup unit 11402 is composed of an image pickup element. The image sensor constituting the image pickup unit 11402 may be one (so-called single plate type) or a plurality (so-called multi-plate type). When the image pickup unit 11402 is composed of a multi-plate type, for example, each image pickup element may generate an image signal corresponding to each of RGB, and a color image may be obtained by synthesizing them. Alternatively, the image pickup unit 11402 may be configured to have a pair of image pickup elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display, respectively. The 3D display enables the operator 11131 to more accurately grasp the depth of the biological tissue in the surgical site. When the image pickup unit 11402 is composed of a multi-plate type, a plurality of lens units 11401 may be provided corresponding to each image pickup element.

Further, the imaging unit 11402 does not necessarily have to be provided on the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

The drive unit 11403 is composed of an actuator, and the zoom lens and focus lens of the lens unit 11401 are moved by a predetermined distance along the optical axis under the control of the camera head control unit 11405. As a result, the magnification and focus of the image captured by the imaging unit 11402 can be adjusted as appropriate.

The communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU11201. The communication unit 11404 transmits the image signal obtained from the image pickup unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

Further, the communication unit 11404 receives a control signal for controlling the drive of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes, for example, information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image, and the like. Contains information about the condition.

The above-mentioned imaging conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of CCU11201 based on the acquired image signal. Good. In the latter case, the so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are mounted on the endoscope 11100.

The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.

The communication unit 11411 is composed of a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

Further, the communication unit 11411 transmits a control signal for controlling the drive of the camera head 11102 to the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communication, or the like.

The image processing unit 11412 performs various image processing on the image signal which is the RAW data transmitted from the camera head 11102.

The control unit 11413 performs various controls related to the imaging of the surgical site and the like by the endoscope 11100 and the display of the captured image obtained by the imaging of the surgical site and the like. For example, the control unit 11413 generates a control signal for controlling the drive of the camera head 11102.

Further, the control unit 11413 causes the display device 11202 to display an image captured by the surgical unit or the like based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image by using various image recognition techniques. For example, the control unit 11413 detects the shape, color, and the like of the edge of an object included in the captured image to remove surgical tools such as forceps, a specific biological part, bleeding, and mist when using the energy treatment tool 11112. Can be recognized. When displaying the captured image on the display device 11202, the control unit 11413 may superimpose and display various surgical support information on the image of the surgical unit by using the recognition result. By superimposing and displaying the surgical support information and presenting it to the surgeon 11131, it is possible to reduce the burden on the surgeon 11131 and to allow the surgeon 11131 to proceed with the surgery reliably.

The transmission cable 11400 that connects the camera head 11102 and CCU11201 is an electric signal cable that supports electric signal communication, an optical fiber that supports optical communication, or a composite cable thereof.

Here, in the illustrated example, the communication is performed by wire using the transmission cable 11400, but the communication between the camera head 11102 and the CCU11201 may be performed wirelessly.

The above is an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Among the configurations described above, the technique according to the present disclosure can be suitably applied to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100. According to the technique according to the present disclosure, the wiring design rule provided in the multilayer wiring layer is relaxed, so that the wiring resistance and the wiring capacity are reduced, so that higher speed photography can be performed. According to this, in the endoscopic surgery system, even when the endoscope 11100 is moved at high speed, it is possible to acquire a photographed image with high accuracy, so that the operability of the user can be improved.

The techniques related to the present disclosure have been described above with reference to embodiments and modifications. However, the technique according to the present disclosure is not limited to the above-described embodiment and the like, and various modifications can be made.

Furthermore, not all of the configurations and operations described in each embodiment are essential as the configurations and operations of the present disclosure. For example, among the components in each embodiment, the components not described in the independent claims indicating the highest level concept of the present disclosure should be understood as arbitrary components.

The terms used throughout this specification and the appended claims should be construed as "non-limiting" terms. For example, the term "contains" or "contains" should be construed as "not limited to the mode described as being included." The term "have" should be construed as "not limited to the mode described as having."

The terms used in this specification include terms used solely for convenience of explanation and not used for the purpose of limiting the configuration and operation. For example, terms such as "right", "left", "top", and "bottom" only indicate the direction on the referenced drawing. Further, the terms "inside" and "outside" merely indicate the direction toward the center of the attention element and the direction away from the center of the attention element, respectively. The same applies to terms similar to these and terms having a similar purpose.

The technology according to the present disclosure can also have the following configuration. According to the technique according to the present disclosure having the following configuration, by extending the gate electrodes of at least one or more transistors provided in the circuit layer to a plurality of pixel circuits, the gate electrodes are provided for each of the plurality of pixel circuits. It can function as a wiring for electrically connecting the gate electrodes of the same type of transistor. Thereby, for example, the image pickup apparatus can reduce the number of wirings extending to the plurality of pixel circuits in the multilayer wiring layer provided above the circuit layer. Therefore, the image pickup apparatus can relax the design rule in the multilayer wiring layer. The effects produced by the techniques according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
(1)
A semiconductor substrate in which a plurality of sensor pixels for photoelectric conversion are arranged in a matrix and
It has a plurality of pixel circuits that output pixel signals based on the charges output from each of the sensor pixels, and includes a circuit layer provided on the semiconductor substrate via an interlayer insulation layer.
The gate electrodes of at least one or more transistors included in the pixel circuit are provided so as to extend to the plurality of the pixel circuits in the plane of the circuit layer, and are provided for each of the plurality of pixel circuits of the same type. An imaging device that is electrically connected to the gate electrode of the transistor.
(2)
The imaging device according to (1) above, wherein the pixel circuit is provided for each of a predetermined number of the sensor pixels.
(3)
The above (1) or (2), wherein the gate electrodes of the plurality of transistors included in the pixel circuit are provided so as to extend to the plurality of pixel circuits in the same direction in the plane of the circuit layer. Imaging device.
(4)
The imaging device according to any one of (1) to (3) above, wherein the gate electrode is provided in a band shape extending in one direction in the plane of the circuit layer.
(5)
The imaging device according to any one of (1) to (4) above, wherein the gate electrode is embedded from above the circuit layer to the inside of the circuit layer.
(6)
The imaging device according to (5) above, wherein a portion of the gate electrode embedded inside the circuit layer is provided with polysilicon.
(7)
The imaging device according to any one of (1) to (4) above, wherein the gate electrode is provided on the circuit layer.
(8)
The imaging device according to any one of (1) to (4) above, wherein the gate electrode is provided so as to embed an opening formed in an insulating layer provided on the circuit layer.
(9)
The imaging device according to any one of (1) to (8) above, wherein the gate electrode includes a metal layer and a polysilicon layer.
(10)
The imaging device according to (9) above, wherein barrier layers are provided on the bottom surface and side surfaces of the metal layer.
(11)
The imaging device according to any one of (1) to (10) above, wherein the transistor is a transistor other than an amplification transistor that converts a charge signal output from the sensor pixel into a voltage signal.
(12)
The imaging device according to (11) above, wherein the gate electrode of the amplification transistor is provided so as to embed a first opening and a second opening provided in the semiconductor layer included in the circuit layer.
(13)
A semiconductor substrate in which a plurality of sensor pixels for photoelectric conversion are arranged in a matrix and
It has a plurality of pixel circuits that output pixel signals based on the charges output from the plurality of sensor pixels, and includes a circuit layer provided on the semiconductor substrate via an interlayer insulation layer.
An image pickup apparatus in which gate electrodes of at least one or more transistors included in the pixel circuit are embedded from above the semiconductor layer included in the circuit layer to the inside of the semiconductor layer.

This application claims priority on the basis of Japanese Patent Application No. 2019-226397 filed at the Japan Patent Office on December 16, 2019, and the entire contents of this application are referred to in this application. Incorporate for application.

One of ordinary skill in the art can conceive of various modifications, combinations, sub-combinations, and changes, depending on design requirements and other factors, which are included in the appended claims and their equivalents. It is understood that it is something to be done.

Claims (13)

1. A semiconductor substrate in which a plurality of sensor pixels for photoelectric conversion are arranged in a matrix and
   It has a plurality of pixel circuits that output pixel signals based on the charges output from each of the sensor pixels, and includes a circuit layer provided on the semiconductor substrate via an interlayer insulation layer.
   The gate electrodes of at least one or more transistors included in the pixel circuit are provided so as to extend to the plurality of the pixel circuits in the plane of the circuit layer, and are provided for each of the plurality of pixel circuits of the same type. An imaging device that is electrically connected to the gate electrode of the transistor.
2. The imaging device according to claim 1, wherein the pixel circuit is provided for each of a predetermined number of the sensor pixels.
3. The imaging device according to claim 1, wherein the gate electrodes of the plurality of transistors included in the pixel circuit are provided so as to extend to the plurality of pixel circuits in the same direction in the plane of the circuit layer.
4. The imaging device according to claim 1, wherein the gate electrode is provided in a band shape extending in one direction in the plane of the circuit layer.
5. The imaging device according to claim 1, wherein the gate electrode is embedded from above the circuit layer to the inside of the circuit layer.
6. The imaging device according to claim 5, wherein a portion of the gate electrode embedded inside the circuit layer is provided with polysilicon.
7. The imaging device according to claim 1, wherein the gate electrode is provided on the circuit layer.
8. The imaging device according to claim 1, wherein the gate electrode is provided so as to embed an opening formed in an insulating layer provided on the circuit layer.
9. The imaging device according to claim 1, wherein the gate electrode includes a metal layer and a polysilicon layer.
10. The imaging device according to claim 9, wherein barrier layers are provided on the bottom surface and the side surfaces of the metal layer.
11. The imaging device according to claim 1, wherein the transistor is a transistor other than an amplification transistor that converts a charge signal output from the sensor pixel into a voltage signal.
12. The imaging device according to claim 11, wherein the gate electrode of the amplification transistor is provided so as to embed a first opening and a second opening provided in the semiconductor layer included in the circuit layer.
13. A semiconductor substrate in which a plurality of sensor pixels for photoelectric conversion are arranged in a matrix and
    It has a plurality of pixel circuits that output pixel signals based on the charges output from the plurality of sensor pixels, and includes a circuit layer provided on the semiconductor substrate via an interlayer insulation layer.
    An image pickup apparatus in which gate electrodes of at least one or more transistors included in the pixel circuit are embedded from above the semiconductor layer included in the circuit layer to the inside of the semiconductor layer.

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