TW202139447A - Imaging device - Google Patents

Abstract

This imaging device is provided with a semiconductor substrate having a plurality of sensor pixels for performing photoelectric conversion arrayed in a matrix, and a circuit layer including a plurality of pixel circuits that output pixel signals on the basis of charges output from each of the sensor pixels, the circuit layer being disposed on the semiconductor substrate with an interlayer dielectric layer therebetween. A gate electrode of at least one transistor included in the pixel circuits extends across the plurality of pixel circuits in the plane of the circuit layer, and electrically connects to the gate electrode of the same type of the transistor provided in each of the plurality of the pixel circuits.

Description

Camera device

This disclosure relates to a camera device.

Previously, the area of each pixel of a two-dimensional imaging device was miniaturized by introducing a fine process and increasing the mounting density. In recent years, in order to achieve further miniaturization of imaging devices and higher pixel density, imaging devices with a three-dimensional structure have been developed. An imaging device with a three-dimensional structure is composed of, for example, a semiconductor substrate having a plurality of sensor pixels, and a semiconductor layer having a pixel circuit that converts the charge obtained by each sensor pixel into a pixel signal. (Refer to Patent Literature 1). [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2010-245506

In this type of imaging device, since the area of each pixel is miniaturized, the interval between wirings and the like extending across a plurality of pixels becomes narrower, so the difficulty in the process of forming wirings increases. Therefore, it is desirable to ease the design rules of wiring by reducing the density of wiring arranged across a plurality of pixels.

Therefore, it is desirable to provide an imaging device that relaxes the wiring design rules.

An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and a circuit layer having a plurality of sensor pixels based on each output The pixel circuit that outputs the pixel signal through the interlayer insulating layer is arranged on the semiconductor substrate; and the gate electrode of at least one transistor included in the pixel circuit is in the plane of the circuit layer, in the plurality of One of the above-mentioned pixel circuits is extended, and is electrically connected to the above-mentioned gate electrode of the same type of the above-mentioned transistor provided in each of the plurality of the above-mentioned pixel circuits.

In addition, an imaging device according to another embodiment of the present disclosure includes: a semiconductor substrate arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and a circuit layer having a plurality of sensor pixels based on the plurality of sensors The pixel circuit that outputs the charge from the pixel of the device and outputs the pixel signal respectively, the interlayer insulating layer is disposed on the semiconductor substrate; and the gate electrode of at least one transistor included in the pixel circuit is derived from the circuit layer. The semiconductor layer is embedded into the inside of the semiconductor layer.

According to the imaging device of one embodiment of the present disclosure, a semiconductor substrate having a plurality of sensor pixels arranged in a matrix; and a pixel circuit having a plurality of pixel circuits that output pixel signals based on the charges output from each of the sensor pixels The circuit layers are stacked; and the gate electrode of at least one transistor included in the pixel circuit is extended in the plurality of pixel circuits, and the gate electrode of the same type of transistor is provided in each of the plurality of pixel circuits Electrical connection. Thereby, for example, the imaging device can reduce the number of wirings extended to a plurality of pixel circuits in the multilayer wiring layer provided on the upper layer of the circuit layer.

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of this disclosure, and the technology of this disclosure is not limited to the following aspects. In addition, the arrangement, size, and size ratio of the constituent elements of the present disclosure are not limited to the aspects shown in the drawings.

In addition, the description is given in the following order. 1. Technical background 2. Summary 3. Example 4. Variations 5. Application examples

＜1. Technical background＞ First, referring to FIG. 1 and FIG. 2, the technical background of the present disclosure will be described.

FIG. 1 is a longitudinal cross-sectional view illustrating the laminated structure of an imaging device 1 to which the technology of the present disclosure is applied. As shown in FIG. 1, the imaging device 1 has a first multilayer body 10 including sensor pixels for photoelectric conversion, and a second multilayer body including a pixel circuit that converts the charge output from the sensor pixels into pixel signals. 20 and constitute. The imaging device 1 is a so-called back-illuminated imaging device, and the light incident surface (also referred to as the back surface) of the first laminate 10 is provided with, for example, a color filter 40 and a light receiving lens 50.

The first laminated body 10 is configured by laminating a first insulating layer 46 on a semiconductor substrate 11. The semiconductor substrate 11 is, for example, a silicon substrate, and an n-type semiconductor region, that is, a photodiode PD, is provided in each sensor pixel 12. The light incident on the first multilayer body 10 through the light receiving lens 50 and the color filter 40 is photoelectrically converted by the photodiode PD.

Each of the sensor pixels 12 is separated by the element separation part 43. The element separation portion 43 is provided with an insulating material in a manner extending in the normal direction of a main surface of the semiconductor substrate 11 to electrically separate adjacent sensor pixels 12. The element isolation portion 43 may also be provided in such a way that SiO ₂ penetrates the semiconductor substrate 11, for example.

In addition, on the semiconductor substrate 11, for example, a p-type semiconductor region, that is, a p-well layer 42 is provided in a partial region on the surface side of the laminated first insulating layer 46, and a p-well layer 44 is provided on the side surface of the element isolation portion 43. The p-well layer 44 is a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode PD, and suppresses the generation of dark current due to defects generated in the interface between the semiconductor substrate 11 and the element separation portion 43.

Furthermore, a fixed charge film 45 is provided on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is provided with an insulating film having a negative fixed charge, and suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 may be provided by, for example, hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

In the first layered body 10, each sensor pixel 12 is provided with a transmission transistor TR and a floating diffusion FD. Specifically, the transmission transistor TR and the floating diffusion FD are provided on the side of the semiconductor substrate 11 opposite to the light incident surface side. The transmission transistor TR is a so-called vertical transistor, which extracts the charge that is photoelectrically converted by the photodiode PD disposed inside the semiconductor substrate 11. The floating diffusion region FD is provided inside the P-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42 and accumulates the charges read by the transfer transistor TR.

The color filter 40 is provided on the surface on the opposite side (the so-called back surface) of the semiconductor substrate 11 and the surface on which the first insulating layer 46 is provided (the so-called front surface). Specifically, the color filter 40 is disposed in contact with the fixed charge film 45 in each sensor pixel 12, for example. The light receiving lens 50 is provided in contact with the color filter 40 at every one or every plural sensor pixels 12, for example.

The second laminated body 20 is configured by laminating a second insulating layer 57 on the circuit layer 21. The circuit layer 21 includes a semiconductor layer 48 made of a semiconductor material such as silicon, and a circuit insulating layer 47 made of an insulating material.

A through wiring 54 is provided on the circuit insulating layer 47. The through wiring 54 is electrically insulated from the semiconductor layer 48 by covering the side surface with the circuit insulating layer 47. The through wiring 54 extends in the normal direction of one main surface of the circuit layer 21 and electrically connects the floating diffusion FD provided on the semiconductor substrate 11 and the multilayer wiring layer 23 provided on the second insulating layer 57. For example, one through wiring 54 may be provided for each sensor pixel 12.

In addition, the second laminated body 20 may be provided by sequentially laminating the semiconductor layer 48, the circuit insulating layer 47, and the second insulating layer 57 on the first insulating layer 46. Alternatively, the second layered body 20 may be formed by arranging a silicon substrate on which the circuit layer 21 and the second insulating layer 57 are formed in advance with the circuit layer 21 and the first insulating layer 46 opposed to each other (that is, facing and back) The first laminated body 10 is attached and installed.

On the circuit layer 21 and the second insulating layer 57 of the second laminated body 20, pixel circuits are provided. The pixel circuit is composed of, for example, a through wiring 54 electrically connected to the floating diffusion FD, a multilayer wiring layer 23 and contact plugs 59 provided on the second insulating layer 57, and a field effect transistor 22 provided on the circuit layer 21. For example, one pixel circuit is provided for every sensor pixel 12 or every plural sensor pixels 12. The pixel circuit converts the charge output from each of the sensor pixels 12 and accumulated in the floating diffusion FD into a pixel signal. For example, one pixel circuit may be provided for every four sensor pixels 12.

FIG. 2 is an equivalent circuit diagram illustrating the circuit structure of the imaging device 1. As shown in FIG. 2, the imaging device 1 includes, for example, a photodiode PD, a transmission transistor TR, a floating diffusion region FD, an FD conversion gain switching transistor FDG, a reset transistor RST, an amplifier transistor AMP, and a selection transistor. SEL.

As described above, the photodiode PD, the transmission transistor TR, and the floating diffusion region FD are provided in the first laminated body 10. The FD conversion gain switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided in the second multilayer body 20.

The photodiode PD performs photoelectric conversion to generate electric charges corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transmission transistor TR, and the anode of the photodiode PD is electrically connected to the reference potential line (for example, ground).

The transfer transistor TR is, for example, a vertical MOS (Metal Oxide Semiconductor) transistor, and transfers the electric charges photoelectrically converted by the photodiode PD to the floating diffusion region FD. The source of the transmission transistor TR is electrically connected to the cathode of the photodiode PD. The drain of the transmission transistor TR is electrically connected to the floating diffusion FD, and the gate of the transmission transistor TR is electrically connected to the pixel driving line.

The floating diffusion FD temporarily holds the electric charge output from the photodiode PD via the transmission transistor TR. The floating diffusion FD is electrically connected to the drain of the transmission transistor TR, the gate of the amplifying transistor AMP, and the source of the reset transistor RST.

The FD conversion gain switching transistor FDG is, for example, a MOS transistor, which is provided for switching the charge-voltage conversion efficiency in the pixel circuit. When the FD conversion gain switching transistor FDG becomes the on state, the capacitance C of the floating diffusion FD can be increased by the gate capacitance of the FD conversion gain switching transistor FDG compared with the off state.

Since the charge Q accumulated in the floating diffusion FD is represented by the product of the capacitance C and the voltage V, when the capacitance C of the floating diffusion FD is large, the voltage V converted by the amplifier transistor AMP becomes lower. On the other hand, when the charge Q output from the photodiode PD is large, if the capacitance C of the floating diffusion FD is not sufficiently large, the floating diffusion FD cannot fully retain the charge from the photodiode PD. Q. In addition, in order to prevent the voltage V converted by the amplifier transistor AMP from being too high, it is also important that the capacitance C of the floating diffusion FD is appropriately large.

Therefore, the FD conversion gain switching transistor FDG is switched on or off to make the capacitance C of the floating diffusion FD variable, thereby switching the charge-voltage conversion efficiency in the pixel circuit.

The reset transistor RST is, for example, a MOS transistor, and resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The source of the reset transistor RST is electrically connected to the floating diffusion FD. The drain of the reset transistor RST is electrically connected to the power line VDD, and the gate of the reset transistor RST is electrically connected to the pixel driving line.

The amplifier transistor AMP is, for example, a MOS transistor, and generates a voltage signal corresponding to the level of the charge held by the floating diffusion region FD as a pixel signal. The amplifier transistor AMP constitutes a so-called source follower type amplifier, which outputs a pixel signal of a voltage corresponding to the level of the charge generated by the photodiode PD. The drain of the amplifier transistor AMP is electrically connected to the power line VDD. The source of the amplifying transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST.

The selection transistor SEL is, for example, a MOS transistor, which controls the output timing of the pixel signal from the pixel circuit. By selecting the transistor SEL to turn on, the amplifying transistor AMP can amplify the potential of the floating diffusion FD, and output a voltage corresponding to the amplified potential through the vertical signal line. The drain of the selection transistor SEL is electrically connected to the source of the amplifying transistor AMP. The source of the selection transistor SEL is electrically connected to the vertical signal line, and the gate of the selection transistor SEL is electrically connected to the pixel driving line.

With the above configuration, the imaging device 1 can output a pixel signal corresponding to the amount of light incident on the sensor pixel 12 of the first multilayer body 10 from the pixel circuit.

＜2. Summary＞ Next, referring to FIG. 3, the outline of the technology of the present disclosure will be described. 3 is a schematic explanatory diagram showing the planar configuration of the transistors in the circuit layer 21 of the imaging device 1 according to one embodiment of the present disclosure.

As explained with reference to FIGS. 1 and 2, in the imaging device 1, the circuit layer 21 of the second laminate 20 is provided with, for example, an FD conversion gain switching transistor FDG, a reset transistor RST, an amplifier transistor AMP, and a selection transistor. SEL. In the imaging device 1 of this embodiment, the gate electrode of at least one transistor other than the amplifier transistor AMP is extended across a plurality of pixel circuits to serve as the gate electrode of the same transistor of the plurality of pixel circuits. Use the wiring for the electrical connection of the electrodes.

Specifically, as shown in the equivalent circuit diagram of Figure 2, in addition to the amplifier transistor AMP, the FD conversion gain switching transistor FDG, reset transistor RST, and the gate electrode of the selection transistor SEL are the same as other pixel circuits. The gate electrode of the transistor is electrically connected to the pixel driving line or the vertical signal line. The wiring that electrically connects each of the gate electrodes may also be provided in the multilayer wiring layer 23 inside the second insulating layer 57, for example. However, with the miniaturization of the sensor pixel 12, the miniaturization of the area for disposing the pixel circuit has been continuously developed, and as a result, the width and pitch of the wiring provided on the multilayer wiring layer 23 have become narrower. Therefore, the difficulty in the process of forming wiring in the multilayer wiring layer 23 increases.

In the imaging device 1 of the present embodiment, at least one gate electrode of the FD conversion gain switching transistor FDG, reset transistor RST, or selection transistor SEL, and gate electrodes of the same type of transistor as the plural pixel circuits The wiring that electrically connects the electrode and the gate electrode are integrally arranged on the circuit layer 21. As a result, the imaging device 1 reduces the number of wires formed on the multilayer wiring layer 23, thereby expanding the width and pitch of the wires formed on the multilayer wiring layer 23, thereby reducing the difficulty of the process when forming the multilayer wiring layer 23. In addition, the imaging device 1 can reduce the resistance and capacitance of the wiring formed on the multilayer wiring layer 23 by expanding the width and pitch of the wiring formed on the multilayer wiring layer 23.

In a two-dimensional imaging device, since the sensor pixels 12 and pixel circuits are arranged in the same plane, it is difficult to form wiring extending across a plurality of pixel circuits in order to arrange each pixel. On the other hand, since the imaging device 1 of this embodiment has a three-dimensional structure, the sensor pixels 12 and pixel circuits can be stacked in the vertical direction. As a result, since the imaging device 1 can reduce the number of elements provided on the circuit layer 21, it is possible to form wiring that extends across a plurality of pixel circuits. In addition, in the imaging device 1, four sensor pixels share one pixel circuit, so that the size of the area that forms one pixel circuit can be reduced compared with the case where each sensor pixel 12 forms a pixel circuit. Zoom in 4 times. Thereby, the imaging device 1 can more easily ensure the area where the wiring extending across the plurality of pixel circuits is formed.

For example, as shown in FIG. 3, in the imaging device 1 to which the technology of the present disclosure is applied, the overlapping area RU provided with the pixel circuit is bent twice in the first direction (for example, it is directly opposite to the top and bottom direction of FIG. 3). ) The semiconductor layer 48 is arranged in an extended manner. In addition, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL are placed in a second direction orthogonal to the first direction (for example, 3) extending in the left-right direction directly opposite to FIG. 3 and crossing the semiconductor layer 48, thereby forming various transistors.

Thereby, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL extend in the second direction across a plurality of repeating regions RU, by This functions as a wiring that electrically connects the gate electrodes 25 of the reset transistor RST, the gate electrodes 26 of the FD conversion gain switching transistor FDG, and the gate electrodes 28 of the selection transistor SEL to each other. Therefore, since the imaging device 1 can form a part of the wiring of the multilayer wiring layer 23 provided inside the second insulating layer 57 on the circuit layer 21, the number of wirings provided on the multilayer wiring layer 23 can be reduced. Therefore, the imaging device 1 can relax the design rule of the multilayer wiring layer 23.

In FIG. 3, the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL are arranged in a manner extending in the second direction, but this The disclosed technique is not limited to this illustration. As long as at least one of the gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the select transistor SEL is set in such a way that it extends in the second direction. Can.

In addition, the gate electrode 27 of the amplifying transistor AMP is not electrically connected to the gate electrode of the amplifying transistor AMP of other pixel circuits, but is electrically connected to the floating diffusion FD. Therefore, the gate electrode 27 of the amplifying transistor AMP is arranged in a rectangular shape so as to overlap with the bending point of the semiconductor layer 48, for example. In this way, the gate electrode 27 of the amplifying transistor AMP can further increase the length of the gate, so that random telegraph noise (Random Telegraph Nosise: RTN) can be suppressed.

<3. Example> Next, referring to FIGS. 4A to 12, the specific structure of the imaging device 1 of the present embodiment will be described. 4A, FIG. 5A, FIG. 6A, FIG. 8, FIG. 9A, and FIG. 10 to FIG. 12 are top views showing the planar configuration of each component in a cross section of the pixel circuit. 4A, FIG. 5A, FIG. 6A, FIG. 8, FIG. 9A, and FIG. 10 to FIG. 12, only the structure of the layer of interest is shown, and the drawings of the structure of the unfocused layer are omitted. The sensor pixel 12 and the pixel circuit of the imaging device 1 are formed by repeatedly arranging the repeating unit RU shown in FIGS. 4A, 5A, 6A, 8, 9A, and 10-12 on a plane.

In addition, FIG. 4B is a longitudinal cross-sectional view of the A-AA cut line of FIG. 4A, FIG. 5B is a longitudinal cross-sectional view of the A-AA cut line of FIG. 5A, and FIG. 6B is a B-BB cut line of FIG. 6A Longitudinal cross-sectional view, Fig. 9B is a longitudinal cross-sectional view taken along the B-BB cut line of Fig. 9A.

As shown in FIGS. 4A and 4B, on the semiconductor substrate 11, the element separation portion 43 is arranged in a dot matrix to separate the sensor pixels 12 arranged in a matrix. At the intersection of the element separation part 43 at the center of the repeating unit RU, a polysilicon layer 602 electrically connecting each of the four sensor pixels 12 and the semiconductor substrate 11 is provided. The polysilicon layer 602 functions as a floating diffusion FD shared by the four sensor pixels 12. On the polysilicon layer 602, a contact plug 620 that penetrates the circuit insulating layer 47 in the subsequent stage is provided.

In addition, at the intersection of the polysilicon layer 602 and the element separation portion 43 on the diagonal, a polysilicon layer 601 electrically connected to the semiconductor substrate 11 is provided. The polysilicon layer 601 is provided for electrically connecting the anode of the photodiode PD and the reference potential line VSS. On the polysilicon layer 601, contact plugs 625, 626, 627, and 628 that penetrate the circuit insulating layer 47 in the subsequent stage are provided.

Furthermore, at the center of each of the four sensor pixels 12, vertical gate electrodes TG1, TG2, TG3, and TG4 of the transmission transistor TR are respectively provided. On the vertical gate electrodes TG1, TG2, TG3, and TG4, wiring layers 611, 612, 613, and 614 that are routed to the element separation portion 43 are provided with an insulating edge layer 46A. The wiring layers 611, 612, 613, and 614 on the element separation portion 43 are provided in the contact plugs 621, 622, 623, and 624 that penetrate the circuit insulating layer 47 in the subsequent stage.

As shown in FIGS. 5A and 5B, the respective components shown in FIGS. 4A and 4B are embedded by the first insulating layer 46. On the first insulating layer 46, a semiconductor layer 48 is provided. The semiconductor layer 48 is bent twice and extends in the first direction (for example, in the upper and lower direction directly opposite to FIG. 5A) to avoid setting the contact plugs 620, 621, 622, 623, and 624 in the subsequent stages. , 625, 626, 627, 628 area. The semiconductor layer 48 is provided by, for example, depositing silicon equal to the above-mentioned specific area in an island shape.

As shown in FIGS. 6A and 6B, the semiconductor layer 48 shown in FIGS. 5A and 5B is embedded with a circuit insulating layer 47, and the circuit layer 21 is composed of the semiconductor layer 48 and the circuit insulating layer 47. On the circuit layer 21, in the second direction orthogonal to the first direction in which the semiconductor layer 48 extends (for example, the left and right direction opposite to FIG. 6A), the gate electrode 25 of the reset transistor RST and the FD conversion gain switch are provided The gate electrode 26 of the transistor FDG and the gate electrode 28 of the selection transistor SEL. The gate electrode 25 of the reset transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, and the gate electrode 28 of the selection transistor SEL extend beyond the repeating unit RU, which is the same as other repeating unit RU of the same type of transistor. The gate electrode is electrically connected. In other words, the gate electrodes 25, 26, and 28 also function as wirings that electrically connect the gate electrodes of the same type of transistors in the repeating unit RU.

In addition, the gate electrode 27 of the amplifying transistor AMP is provided in a rectangular shape, for example, in a region overlapping with the bending point of the semiconductor layer 48.

Here, resetting the gate electrode 25 of the transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplifying transistor AMP, and the gate electrode 28 of the selection transistor SEL can also be shown in FIG. 6B The section structure shown is set.

Specifically, the gate electrodes 25, 26, 27, and 28 can also be embedded in the polysilicon layer 711 of the semiconductor layer 48, and the electrode layer 713 disposed on the polysilicon layer 711 via a gate insulating film (not shown). And it is composed of a barrier layer 712 arranged to cover the side and bottom surfaces of the electrode layer 713.

For example, after forming an interlayer insulating film on the semiconductor layer 48, etching or the like is used to form a groove in the semiconductor layer 48. Next, a gate insulating film (not shown) is formed inside the groove, and the groove is embedded by the polysilicon layer 711. Then, the upper part of the polysilicon layer 711 is retreated (also referred to as a groove) to form a groove, and a barrier layer 712 containing Ti or W metal or metal compound is formed inside the groove. After that, the electrode layer 713 is formed by inserting Cu or the like into the groove on the upper portion of the polysilicon layer 711. The gate electrodes 25, 26, 27, and 28 may also be formed with this structure.

Since the gate electrodes 25, 26, 27, 28 of this structure form channels around the polysilicon layer 711 embedded in the semiconductor layer 48, the gate length can be further increased. Accordingly, since the gate electrodes 25, 26, 27, and 28 can reduce the occupied area in the circuit layer 21, the degree of freedom in the layout of the various components of the pixel circuit can be further improved. In addition, by providing the gate electrodes 25, 26, 27, and 28 in a laminated structure of the polysilicon layer 711 and the electrode layer 713, the deterioration of the interface level due to the use of metal gates can be suppressed, and the increase in wiring resistance can be suppressed . Furthermore, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 713 formed of a metal material, the difficulty of the formation process of the gate electrodes 25, 26, 27, 28 can be reduced.

In addition, resetting the gate electrode 25 of the transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplifying transistor AMP, and the gate electrode 28 of the selection transistor SEL can also be as shown in FIG. 7 The section structure setting shown.

As shown in FIG. 7, the gate electrodes 25, 26, 27, and 28 may also be composed of an electrode layer 721 containing a metal material embedded in the semiconductor layer 48 via a gate insulating film (not shown). For example, after forming an interlayer insulating film on the semiconductor layer 48, etching or the like is used to form a groove in the semiconductor layer 48. Next, a gate insulating film (not shown) is formed inside the groove, and Cu or the like is embedded in the groove to form the electrode layer 721. The gate electrodes 25, 26, 27, and 28 may also be formed with this structure.

Since the gate electrodes 25, 26, 27, 28 of this structure form channels around the electrode layer 721 embedded in the semiconductor layer 48, the gate length can be further increased. As a result, since the gate electrodes 25, 26, 27, and 28 can reduce the occupied area on the circuit layer 21, the degree of freedom in the layout of the various components of the pixel circuit can be further improved. In addition, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 721 formed of a metal material, the difficulty of the formation process of the gate electrodes 25, 26, 27, 28 can be reduced.

As shown in FIG. 8, the contacts 631, 632, 633, 634, 635, 636, 637 used to electrically connect the drain, source or gate of each transistor to the wiring formed on the upper layer penetrate the second insulation A part of the layer 57 is disposed on the semiconductor layer 48 and the gate electrode 27 of the amplifying transistor AMP. Specifically, the contacts 631 and 632 are respectively disposed on the semiconductor layer 48 on both sides via the gate electrode 25 of the reset transistor RST. In addition, the contact 633 is provided on the semiconductor layer 48 on the side opposite to the side where the gate electrode 25 is provided via the gate electrode 26 of the FD conversion gain switching transistor FDG. In addition, the contact point 637 is provided on the semiconductor layer 48 on the side opposite to the side on which the gate electrode 27 is provided via the gate electrode 28 of the selection transistor SEL. Furthermore, the contacts 634 and 636 are respectively disposed on the semiconductor layer 48 protruding from the gate electrode 27 of the amplifying transistor AMP, and the contact 635 is disposed on the gate electrode 27 of the amplifying transistor AMP.

Moreover, as shown in FIG. 8, the contact plugs 620, 621, 622, 623, 624, 625, 626, 627, and 628 are provided so as to penetrate through a part of the circuit insulating layer 47 and the second insulating layer 57.

As shown in Figure 9A and Figure 9B, the contacts 631, 632, 633, 634, 635, 636, 637 and the contact plugs 620, 621, 622, 623, 624, 625, 626, 627, 628 are insulated by the second Layers 57A, 57B are embedded. On the contacts and the contact plugs, first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, and 654 are respectively provided.

Specifically, the first wiring layer 641 is provided on the contact plug 625, and the first wiring layer 642 is provided on the contact plug 626. The first wiring layer 643 is provided on the contact plug 622, the first wiring layer 644 is provided on the contact plug 624, and the first wiring layer 645 is provided on the contact plug 627. The first wiring layer 646 is provided on the contact plug 623, the first wiring layer 647 is provided on the contact plug 628, and the first wiring layer 648 is provided on the contact plug 621. The first wiring layer 654 is provided on the contact 637, and the first wiring layer 653 is provided on the contact 634. In addition, the first wiring layer 651 is provided to electrically connect the contacts 632 and 636, and the first wiring layer 652 is provided to electrically connect the contacts 631, 633, 635 and the contact plug 620.

Here, the first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, and 654 may also be provided with the cross-sectional structure shown in FIG. 9B.

Specifically, the first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, and 654 may also be embedded in the metal layer 733 of the second insulating layer 57B and covered The side and bottom of the metal layer 733 are formed by a barrier layer 732 arranged in a manner. For example, after forming the second insulating layers 57A and 57B, etching or the like is used to form a groove in the second insulating layer 57B, and a barrier layer 732 containing a metal or metal compound of Ti or W is formed inside the groove. After that, the metal layer 733 is formed by inserting Cu or the like into the groove. The first wiring layers 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, and 654 may also be formed with such a configuration.

As shown in Figure 1, on the first wiring layer 641, 642, 643, 644, 645, 646, 647, 648, 651, 652, 653, 654, contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, 673. Specifically, the contact 661 is provided on the first wiring layer 641, the contact 662 is provided on the first wiring layer 646, and the contact 663 is provided on the first wiring layer 642. The contact 664 is provided on the first wiring layer 643, the contact 665 is provided on the first wiring layer 644, and the contact 666 is provided on the first wiring layer 645. The contact 667 is provided on the first wiring layer 653, the contact 673 is provided on the first wiring layer 654, and the contact 668 is provided on the first wiring layer 647. The contact 671 is provided on the first wiring layer 648, and the contact 672 is provided on the first wiring layer 651.

As shown in Fig. 11, on the contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, 673, they are arranged in the second direction (the left and right direction opposite to Fig. 11) and extend The second wiring layers 681, 682, 683, 684, 685, 686, 687, 688. In addition, the contacts 661, 662, 663, 664, 665, 666, 667, 668, 671, 672, and 673 are embedded by the second insulating layer 57.

Specifically, the second wiring layer 681 is provided on the contacts 661 and 663, and the second wiring layer 688 is provided on the contacts 668, 667, and 666. The second wiring layers 681 and 688 are electrically connected to the reference potential line VSS. The second wiring layer 682 is provided on the contact 662, and supplies a potential to the vertical gate electrode TG1. The second wiring layer 683 is provided on the contact 671, and supplies a potential to the vertical gate electrode TG2. The second wiring layer 685 is provided on the contact 664 and supplies a potential to the vertical gate electrode TG3. The second wiring layer 686 is provided on the contact 665 and supplies a potential to the vertical gate electrode TG4. The second wiring layer 684 is disposed on the contact 672 and is electrically connected to the power line VDD. The second wiring layer 687 is disposed on the contact 673 and is electrically connected to the vertical signal line.

As shown in FIG. 12, on the second wiring layers 681, 682, 683, 684, 685, 686, 687, 688, they are provided in the first direction ( The third wiring layers 692, 693, 694, 965, 696, 697, 698 extending in the up and down direction directly opposite to FIG. In addition, these contacts and wiring layers are embedded by the second insulating layer 57.

Specifically, the third wiring layer 692 is electrically connected to the reference potential line VSS and electrically connected to the second wiring layers 681 and 688 via the contacts 676 and 677. The third wiring layer 693 is electrically connected to the vertical signal line and electrically connected to the second wiring layer 687 via the contact 679. The third wiring layers 694, 695, and 696 are arranged in a manner of being electrically connected to the vertical signal lines. The third wiring layer 697 is electrically connected to the reference potential line VSS and electrically connected to the second wiring layers 681 and 688 via the contacts 674 and 675. The third wiring layer 698 is electrically connected to the power line VDD, and is electrically connected to the second wiring layer 684 via the contact 678.

The specific structure of the imaging device 1 of this embodiment has been described above. In the imaging device 1 of the present embodiment, among the wirings arranged across a plurality of repeating units RU, the wiring connected to the gate electrode 25 of the reset transistor RST and the gate electrode 26 of the FD conversion gain switching transistor FDG are connected to each At least one of the wiring or the wiring connecting each of the gate electrodes 28 of the selective transistor SEL is provided on the circuit layer 21. Thereby, since these wirings are not provided on the same layer as the second wiring layers 681, 682, 683, 684, 685, 686, 687, and 688, the imaging device 1 can further expand the second wiring layers 681, 682, 683, The width and spacing of 684, 685, 686, 687, 688. That is, the imaging device 1 can relax the design rules of the second wiring layers 681, 682, 683, 684, 685, 686, 687, and 688.

＜4. Examples of changes＞ Next, a modification example of the imaging device 1 of this embodiment will be described with reference to FIGS. 13A to 17C. The modification example of the imaging device 1 of this embodiment is to reset the gate electrode 25 of the transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplifying transistor, and the selection transistor SEL An example of a change in the cross-sectional structure of the gate electrode 28.

FIG. 13A is a top view showing the changes in the planar configuration of the gate electrodes 25, 26, 27, and 28 of the pixel circuit. Fig. 13B is a longitudinal cross-sectional view taken along the line B-BB of Fig. 13A. 14-16 are longitudinal cross-sectional views showing changes in a part of the cross-sectional structure at the B-BB cut line in FIG. 13A.

13A and 13B, reset the gate electrode 25 of the transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplifying transistor, and the gate of the selection transistor SEL The electrode 28 may also be a polysilicon layer 741 disposed on the semiconductor layer 48 via a gate insulating film 740, an electrode layer 743 disposed on the polysilicon layer 741, and a barrier layer 742 disposed to cover the side and bottom surfaces of the electrode layer 743 constitute.

For example, after the interlayer insulating film 744 is formed on the semiconductor layer 48, a groove is formed in the interlayer insulating film 744 using etching or the like. Next, a gate insulating film 740 and a polysilicon layer 741 are sequentially laminated on the bottom surface of the groove. Next, the upper part of the polysilicon layer 711 is retreated (also called a groove) to form a groove, and a barrier layer 742 containing Ti or W metal or metal compound is formed inside the groove. After that, the electrode layer 743 is formed by inserting Cu or the like into the groove on the upper portion of the polysilicon layer 741. Thereby, gate electrodes 25, 26, 27, 28 can be formed.

The gate electrodes 25, 26, 27, and 28 of this structure are arranged in a laminated structure of the polysilicon layer 741 and the electrode layer 743, which can suppress the deterioration of the interface state due to the use of metal gates and suppress the wiring resistance. rise. Furthermore, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 743 formed of a metal material, the difficulty of the formation process of the gate electrodes 25, 26, 27, 28 can be reduced. Since the gate electrodes 25, 26, 27, 28 require different widths as gate electrodes and the widths required as wiring, the width provided on the semiconductor layer 48 is different from the width provided on the circuit insulating layer 47 set up.

In addition, resetting the gate electrode 25 of the transistor RST, the gate electrode 26 of the FD conversion gain switching transistor FDG, the gate electrode 27 of the amplifying transistor AMP, and the gate electrode 28 of the selection transistor SEL can also be shown in Fig. 14~ The cross-sectional structure shown in Figure 16 is set up.

As shown in FIG. 14, the gate electrodes 25, 26, 27, and 28 can also be composed of an electrode layer 751 containing a metal material that is disposed on the semiconductor layer 48 via a gate insulating film 750. For example, the gate electrodes 25, 26, 27, and 28 may be formed by sequentially stacking a gate insulating film 750 and an electrode layer 751 containing a metal material on the semiconductor layer 48.

The gate electrodes 25, 26, 27, 28 of this structure can be formed with a simpler structure. In addition, since the gate electrodes 25, 26, 27, 28 require different widths as gate electrodes and wiring requirements, the widths provided on the semiconductor layer 48 are different from the widths provided on the circuit insulating layer 47. The way to set. In addition, since the gate electrodes 25, 26, 27, and 28 of this structure are made of metal gates, the gate insulating film 750 can be made of a so-called High-k material.

As shown in FIG. 15, the gate electrodes 25, 26, 27, 28 can also be provided with a polysilicon layer 761 on the semiconductor layer 48 via a gate insulating film 760, a barrier layer 762 on the polysilicon layer 711, and The electrode layer 763 provided on the barrier layer 762 is constituted by the electrode layer 763. For example, the gate electrodes 25, 26, 27, 28 can also be formed by sequentially stacking a gate insulating film 760, a polysilicon layer 761, a barrier layer 762 of a metal or metal compound containing Ti or W on the semiconductor layer 48, and a barrier layer containing Cu, etc. The electrode layer 763 is formed.

The gate electrodes 25, 26, 27, and 28 of this structure are arranged in a laminated structure of the polysilicon layer 761 and the electrode layer 763, which can suppress the deterioration of the interface state due to the use of metal gates and suppress the wiring resistance. rise. Since the gate electrodes 25, 26, 27, 28 require different widths as gate electrodes and the widths required as wiring, the width provided on the semiconductor layer 48 is different from the width provided on the circuit insulating layer 47 set up.

As shown in FIG. 16, the gate electrodes 25, 26, 27, 28 can also be embedded in the electrode layer 772 of the interlayer insulating film 770 provided on the semiconductor layer 48, and cover the side and bottom surfaces of the electrode layer 772. The barrier layer 771 is provided. For example, after forming the interlayer insulating film 770 on the semiconductor layer 48, etching or the like is used to form a groove in the interlayer insulating film 770. Next, the electrode layer 772 is formed by inserting Cu or the like into the groove. The gate electrodes 25, 26, 27, and 28 may also be formed with this structure.

Since the gate electrodes 25, 26, 27, 28 of this structure can be formed without etching the electrode layer 713 formed of a metal material, the difficulty of the formation process of the gate electrodes 25, 26, 27, 28 can be reduced. Since the gate electrodes 25, 26, 27, 28 require different widths as gate electrodes and the widths required as wiring, the width provided on the semiconductor layer 48 is different from the width provided on the circuit insulating layer 47 set up.

FIG. 17A is a top view showing the changes in the planar configuration of the gate electrodes 25, 26, 27, and 28 of the pixel circuit. Fig. 17B is a longitudinal sectional view at the B-BB cut line of Fig. 17A, and Fig. 17C is a longitudinal sectional view at the C-CC cut line of Fig. 17A.

As shown in FIGS. 17A to 17C, the gate electrodes 25, 26, 27, 28 are the same as the gate electrodes 25, 26, 28 shown in FIG. 6B, and a gate insulating film (not shown) may also be interposed. A polysilicon layer 711 embedded in the semiconductor layer 48, an electrode layer 713 arranged on the polysilicon layer 711, and a barrier layer 712 arranged to cover the side and bottom surfaces of the electrode layer 713 are constituted.

In addition, the gate electrode 27 of the amplifying transistor AMP can also be embedded in the polysilicon layer 781 formed in the first opening 781A and the second opening 781B of the semiconductor layer 48 through a gate insulating film (not shown), and disposed on the polysilicon layer. The electrode layer 783 on the layer 781 is composed of a barrier layer 782 arranged to cover the side and bottom surfaces of the electrode layer 783.

That is, the amplifying transistor AMP may also be provided in a so-called FinFET structure in which the semiconductor layer 48 sandwiched between the first opening 781A and the second opening 781B serves as a channel. Specifically, in the amplifier transistor AMP of the FinFET structure, the semiconductor layer 48 sandwiched between the first opening 781A and the second opening 781B forms a channel in a direction perpendicular to the paper surface of FIG. 17C. In the amplifier transistor AMP of the FinFET structure, since electrons flow in the center of the channel leaving from the interface of the semiconductor layer 48, random telegraph noise (RTN) can be further suppressed.

The gate electrodes 25, 26, 27, 28 of this structure can be formed in the same steps. For example, after forming an interlayer insulating film on the semiconductor layer 48, etching or the like is used to form a groove, a first opening 781A, and a second opening 781B in the semiconductor layer 48. Next, a gate insulating film (not shown) is formed inside the groove, and the groove, the first opening 781A, and the second opening 781B are inserted into the groove with polysilicon layers 711 and 781. Then, the upper portions of the polysilicon layers 711, 781 are retreated (also called grooves) to form grooves, and barrier layers 712, 782 containing Ti or W metals or metal compounds are formed inside the grooves. Thereafter, the electrode layers 713 and 783 are formed by inserting Cu or the like into the grooves on the upper portion of the polysilicon layer 711. The gate electrodes 25, 26, 27, and 28 may also be formed with this structure.

Since the gate electrodes 25, 26, 28 form channels around the polysilicon layer 711 embedded in the semiconductor layer 48, the gate length can be further increased. Thereby, since the area occupied by the gate electrodes 25, 26, and 28 on the circuit layer 21 can be reduced, the degree of freedom in the layout of the various components of the pixel circuit can be further improved. In addition, since the gate electrode 27 can be configured with the amplifying transistor AMP in a FinFET structure, the electrons flowing in the channel can leave the interface of the semiconductor layer 48. As a result, since the gate electrode 27 can further suppress RTN and can reduce the area occupied by the circuit layer 21, the degree of freedom of layout of the various components of the pixel circuit can be further improved.

In addition, by providing the gate electrodes 25, 26, 27, 28 in a laminated structure of the polysilicon layer 711 and the electrode layer 713, the deterioration of the interface state due to the use of metal gates can be suppressed, and the increase in wiring resistance can be suppressed. Furthermore, since the gate electrodes 25, 26, 27, 28 can be formed without etching the electrode layer 713 formed of a metal material, the difficulty of the formation process of the gate electrodes 25, 26, 27, 28 can be reduced.

＜5. Application example＞ Hereinafter, an application example of the imaging device 1 of this embodiment will be described with reference to FIGS. 18 to 23.

(Applicable to camera system) First, referring to FIGS. 18 and 19, an application example of the imaging system of the imaging device according to one embodiment of the present disclosure will be described. FIG. 18 is a block diagram showing an example of a schematic configuration of an imaging system 900 provided with the imaging device 1 of this embodiment. FIG. 19 is a flowchart showing the flow of the camera operation of the camera system 900.

As shown in FIG. 18, the imaging system 900 is, for example, an imaging device such as a digital still camera or a video camera, or an electronic device such as a portable terminal device such as a smartphone or a tablet terminal.

The imaging system 900 includes, for example, a lens group 941, a shutter 942, the imaging device of this embodiment 1, a DSP (Digital Signal Processing) circuit 943, a frame memory 944, a display unit 945, a memory unit 946, and an operation unit 947 And the power supply department 948. In the imaging system 900, the imaging device 1, the DSP circuit 943, the frame memory 944, the display unit 945, the memory unit 946, the operation unit 947, and the power supply unit 948 are connected to each other via a bus line 949.

The imaging device 1 outputs image data corresponding to the incident light passing through the lens group 941 and the shutter 942. The DSP circuit 943 is a signal processing circuit that processes the signal (ie, image data) output from the imaging device 1. The frame memory 944 temporarily holds the image data processed by the DSP circuit 943 in frame units. The display unit 945 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging device 1. The storage unit 946 includes a recording medium such as a semiconductor memory or a hard disk, and records image data of moving images or still images captured by the imaging device 1. The operation unit 947 outputs operation instructions related to various functions of the camera system 900 based on the operation of the user. The power supply unit 948 is various power supplies for supplying operating power of the camera device 1, the DSP power 943, the frame memory 944, the display unit 945, the memory unit 946, and the operation unit 947.

Next, the imaging sequence of the imaging system 900 will be described.

As shown in FIG. 19, the user instructs the start of imaging by operating the operation part 947 (S101). Thereby, the operation unit 947 sends an imaging command to the imaging device 1 (S102). The imaging device 1 executes imaging in a specific imaging mode by receiving an imaging command (S103).

The imaging device 1 outputs the captured image data to the DSP circuit 943. The DSP circuit 943 performs specific signal processing (for example, noise reduction processing, etc.) on the image data output from the imaging device 1 (S104). The DSP circuit 943 enables the frame memory 944 to hold the image data processed by the specific signal. After that, the frame memory 944 causes the memory section 946 to store the image data (S105). In this way, the imaging of the imaging system 900 can be performed.

(Applicable to mobile control system) The technique of the present disclosure (this technique) can be applied to various products. For example, the technology of the present disclosure can also be implemented as a device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, locomotives, bicycles, personal mobile vehicles, airplanes, drones, ships, and robots.

FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown in the figure.

The drive system control unit 12010 controls the actions of devices associated with the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 serves as a driving force generating device for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the rudder angle of the vehicle, And the control device such as the brake device that generates the braking force of the vehicle functions.

The vehicle body system control unit 12020 controls the actions of various devices equipped on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a keyless start system, a smart key system, a power window device, or a control device for various lamps such as headlights, taillights, brake lights, direction lights, or fog lights. In this case, the car body system control unit 12020 can be inputted to the vehicle body system control unit 12020 from the radio wave sent from the portable device instead of the key or the signal of various switches. The vehicle body system control unit 12020 accepts the input of these radio waves or signals, and controls the door lock devices, power window devices, lamps, etc. of the vehicle.

The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 can also perform object detection processing or distance detection processing of people, vehicles, obstacles, signs, or characters on the road based on the received images.

The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received by the light. The camera unit 12031 can output the electrical signal as an image or as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.

The in-vehicle information detection unit 12040 detects the information in the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. The in-vehicle information detection unit 12040 can calculate the driver’s fatigue level or mental concentration based on the detection information input from the driver state detection unit 12041, and can also determine the driver Whether you are dozing off.

The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can implement ADAS (Advanced Driver Assistance System) including avoiding vehicle collisions or mitigating impacts, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning or vehicle departure warning, etc. The function is coordinated control for the purpose.

In addition, the microcomputer 12051 controls the driving force generation device, the steering mechanism, or the braking device based on the information around the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, so as to be independent of the driver’s operation. Coordinated control for the purpose of automatic driving, etc.

In addition, the microcomputer 12051 can output control commands to the vehicle body system control unit 12020 based on the outside information obtained by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the preceding or oncoming car detected by the exterior information detection unit 12030, and perform coordinated control for the purpose of anti-glare, such as switching the high beam to the low beam.

The audio and image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to passengers of the vehicle or outside the vehicle. In the example of FIG. 20, as output devices, a loudspeaker 12061, a display unit 12062, and a dashboard 12063 are exemplified. The display unit 12062 may also include at least one of a vehicle-mounted display and a head-up display, for example.

FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 21, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as imaging units 12031.

The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, installed in the front bumper, side view mirror, rear bumper, tailgate, and upper part of the windshield in the vehicle compartment of the vehicle 12100. The camera unit 12101 equipped on the front bumper and the camera unit 12105 equipped on the upper part of the windshield in the cabin mainly obtain images of the front of the vehicle 12100. The imaging units 12102 and 12103 equipped in the side-view mirrors mainly acquire images of the side of the vehicle 12100. The camera 12104 equipped on the rear bumper or tailgate mainly obtains the image of the rear of the vehicle 12100. The front image obtained by the camera units 12101 and 12105 is mainly used to detect vehicles or pedestrians, obstacles, sign machines, traffic signs, or lane lines in front.

In addition, FIG. 21 shows an example of the imaging range of the imaging units 12101 to 12104. The camera range 12111 represents the camera range of the camera unit 12101 located on the front bumper. The camera range 12112 and 12113 represent the camera range of the camera units 12102 and 12103 located on the side mirror, respectively. The camera range 12114 represents the camera located on the rear bumper or rear. The camera range of the door camera section 12104. For example, by superimposing the image data captured by the camera units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the camera units 12101 to 12104 may also have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 obtains the distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the camera units 12101 to 12104, and the time change of the distance (relative speed relative to the vehicle 12100), thereby In particular, it is possible to capture the closest three-dimensional object on the traveling path of the vehicle 12100, and the three-dimensional object traveling at a specific speed (for example, above 0 km/h) in substantially the same direction as the vehicle 12100, as the front vehicle. Furthermore, the microcomputer 12051 can set the distance between the vehicle and the vehicle ahead, and perform automatic braking control (including stop following control) or automatic acceleration control (including following start control). In this way, it is possible to perform coordinated control for the purpose of autonomous driving without depending on the operation of the driver.

For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, telephone poles and other three-dimensional objects based on the distance information obtained from the camera units 12101 to 12104, and capture them, and Used to automatically avoid obstacles. For example, the microcomputer 12051 can recognize obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. In addition, the microcomputer 12051 judges the risk of collision indicating the risk of collision with each obstacle. When the risk of collision is higher than the set value and a collision is likely to occur, it outputs an alarm to the driver through the loudspeaker 12061 or the display unit 12062, or Forced deceleration or avoidance steering is performed through the drive system control unit 12010, thereby enabling driving assistance for collision avoidance.

At least one of the imaging parts 12101 to 12104 may also be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether there are pedestrians in the captured images of the imaging units 12101 to 12104. The identification of the pedestrian is performed, for example, based on the sequence of capturing feature points of the captured images of the imaging units 12101 to 12104 as infrared cameras, and the sequence of performing pattern matching processing on a series of feature points representing the contour of the object to determine whether it is a pedestrian. If the microcomputer 12051 determines that there are pedestrians in the captured images of the camera sections 12101 to 12104, and recognizes the pedestrians, the audio image output section 12052 superimposes and displays the square contour lines for emphasizing the recognized pedestrians, and controls Display unit 12062. In addition, the audio and image output unit 12052 may also control the display unit 12062 in such a way that an icon or the like representing a pedestrian is displayed at a desired position.

Above, an example of a mobile body control system to which the technology of the present disclosure can be applied has been described. The technology of the present disclosure can be applied to the imaging unit 12031 in the configuration described above. According to the technology of the present disclosure, by relaxing the design rules of the wiring provided in the multilayer wiring layer, the wiring resistance and the wiring capacitance are reduced, so higher-speed photography can be performed. Thereby, in the moving body control system, even when the moving body is moving at a higher speed, the control using the photographic image can be performed with higher precision.

＜Applicable to endoscopic surgery system＞ FIG. 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technique of the present disclosure (this technique) can be applied.

In FIG. 22, the operator (doctor) 11131 uses the endoscopic surgery system 11000 to perform an operation on the patient 11132 on the hospital bed 11133. As shown in the figure, the endoscopic surgery system 11000 consists of an endoscope 11100, a pneumoperitoneum 11111, or other surgical instruments 11110 such as an energy treatment instrument 11122, a support arm device 11120 that supports the endoscope 11100, and a support arm device 11120 that supports the endoscope 11100. The trolley 11200 is composed of various devices for surgery.

The endoscope 11100 is composed of a lens barrel 11101 inserted into the body cavity of the patient 11132 with an area of a specific length from the front end, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown in the figure, an endoscope 11100 having a so-called rigid lens configuration having a rigid lens barrel 11101 is shown, but the endoscope 11100 may also be formed as a so-called flexible lens having a flexible lens barrel.

At the front end of the lens barrel 11101, an opening into which the objective lens is embedded is provided. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the front end of the lens barrel by the light guide extending inside the lens barrel 11101, and is directed toward the body cavity of the patient 11132 through the objective lens The observation object inside is illuminated. In addition, the endoscope 11100 can be a direct-view mirror, a squint mirror or a side-view mirror.

An optical system and an imaging element are arranged inside the camera head 11102, and the reflected light (observation light) from the observation object is condensed on the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is sent to the camera controller unit (CCU: Camera Control Unit) 11201 as RAW data.

The CCU 11201 is composed of a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), etc., and collectively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing such as development processing (demosaic processing) on the image signal to display an image based on the image signal.

The display device 11202 is controlled by the CCU 11201 to display an image based on the image signal after image processing performed by the CCU 11201.

The light source device 11203 is constituted by, for example, a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light for imaging the operation part or the like.

The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions of the endoscope 11100 (type of irradiated light, magnification, focal length, etc.).

The treatment instrument control device 11205 controls the driving of the energy treatment instrument 11112 used for tissue cauterization, incision, or blood vessel sealing. The pneumoperitoneum device 11206 is for the purpose of ensuring the field of vision of the endoscope 11100 and the working space of the operator. In order to bulge the body cavity of the patient 11132, the pneumoperitoneum tube 11111 delivers air into the body cavity. The recorder 11207 is a device that can record various information related to surgery. The printer 11208 is a device that can print various information related to surgery in various forms such as text, images, or charts.

In addition, the light source device 11203 that supplies the endoscope 11100 with irradiated light when photographing the surgical part may be composed of, for example, an LED, a laser light source, or a white light source composed of a combination of these. When a white light source is formed by a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the light source device 11203 can adjust the white balance of the captured image. Moreover, in this situation, the observation object is irradiated with laser light from each of the RGB laser sources in a time-sharing manner, and the driving of the imaging element of the camera head 11102 is controlled in synchronization with the illumination timing, so that time-sharing shooting can also correspond to each of the RGB Of the image. According to this method, even if a color filter is not provided in the imaging element, a color image can be obtained.

In addition, the light source device 11203 can also control its driving by changing the intensity of the light to be output every specific time. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the change timing of the light intensity, the image is obtained in time-sharing, and the image is synthesized, so that an image with a high dynamic range without underexposure and overexposure can be generated.

In addition, the light source device 11203 may also be configured to supply light of a specific wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow band imaging (Narrow Band Imaging) is performed, that is, the wavelength dependence of light absorption by body tissues is used to irradiate compared with the irradiated light (ie white light) during normal observation A narrower band of light can capture specific tissues such as blood vessels on the surface of the mucosa with high contrast. Or, in special light observation, fluorescence observation in which images are obtained by fluorescence generated by irradiating excitation light can also be performed. In fluorescence observation, the body tissue can be irradiated with excitation light to observe the fluorescence from the body tissue (self-fluorescence observation), or indocyanine green (ICG) and other reagents can be locally injected into the body tissue and irradiated to the body tissue The excitation light corresponding to the fluorescent wavelength of the reagent can be used to obtain fluorescent images. The light source device 11203 may be configured to supply narrow-band light and/or excitation light corresponding to such special light observation.

FIG. 23 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG. 22.

The camera head 11102 has a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 can be communicably connected to each other through a transmission cable 11400.

The lens unit 11401 is an optical system installed at the connection part with the lens barrel 11101. The observation light extracted from the front end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is composed of a combination of a plurality of lenses including a zoom lens and a focus lens.

The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or plural (so-called multi-plate type). When the imaging unit 11402 is configured in a multi-plate type, for example, each imaging element can generate image signals corresponding to each of RGB, and synthesize them, thereby obtaining a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for respectively acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissues of the operating department. In addition, when the imaging unit 11402 is configured in a multi-plate type, a plurality of lens units 11401 of the system may be provided corresponding to each imaging element.

In addition, the imaging unit 11402 is not necessarily provided in the camera head 11102. For example, the imaging unit 11402 can also be arranged inside the lens barrel 11101 immediately behind the objective lens.

The driving unit 11403 is composed of an actuator, and is controlled by the camera head control unit 11405 to move the zoom lens and the focus lens of the lens unit 11401 by a specific distance along the optical axis. Thereby, the magnification and focus of the captured image of the imaging unit 11402 can be adjusted appropriately.

The communication unit 11404 is composed of a communication device for sending and receiving various information with the CCU 11201. The communication unit 11404 uses the image signal obtained from the imaging unit 11402 as RAM data and sends it to the CCU 11201 via the transmission cable 11400.

In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies it to the camera head control unit 11405. The control signal includes, for example, information related to the subject of specifying the frame rate of the captured image, information specifying the subject of the exposure value at the time of shooting, and/or information related to the subject of specifying the magnification and focus of the captured image, etc. News.

In addition, the imaging conditions such as the frame rate, exposure value, magnification, focus, etc. can be appropriately specified by the user, and can also be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are installed in the endoscope 11100.

The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.

The communication unit 11411 is composed of a communication device for sending and receiving various information with the camera head 11102. The communication unit 11411 receives the image signal sent from the camera head 11102 via the transmission cable 11400.

In addition, the communication unit 11411 sends a control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal or control signal can be sent by electric communication or optical communication.

The image processing unit 11412 performs various image processing on the image signal that is the RAM data sent from the camera head 11102.

The control unit 11413 performs various controls related to the imaging of the operation part and the like with the endoscope 11100 and the display of the captured image obtained by imaging the operation part and the like. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

In addition, the control unit 11413 causes the display device 11202 to display the captured image mapped by the surgery unit or the like based on the image signal after the image processing is performed by the image processing unit 11412. At this time, the control unit 11413 may also use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological body parts, bleeding, and fog when the energy treatment instrument 11122 is used by detecting the edge shape or color of the object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, the recognition result can also be used to superimpose various surgical support information with the image of the operating part. By overlaying the operation support information and prompting the operator 11131, the burden on the operator 11131 can be reduced, or the operator 11131 can perform the operation reliably.

The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the example shown in the figure, the transmission cable 11400 is used for wired communication, but the communication between the camera head 11102 and the CCU 11201 can also be performed wirelessly.

Above, an example of an endoscopic surgery system to which the technology of the present disclosure can be applied has been described. The technology of the present disclosure can be preferably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100 in the configuration described above. According to the technology of the present disclosure, by relaxing the design rules of the wiring provided in the multilayer wiring layer, the wiring resistance and the wiring capacitance are reduced, so higher-speed photography can be performed. Thereby, in the endoscopic surgery system, even when the endoscope 11100 is moved at a high speed, a high-precision photographic image can be obtained, so the user's operability can be improved.

In the above, the embodiment and modification examples have been given to explain the technology of the present disclosure. However, the technology of the present disclosure is not limited to the above-mentioned embodiment and the like, and various changes can be made.

Furthermore, all the configurations and actions described in each embodiment are not necessary for the configurations and actions of this disclosure. For example, among the constituent elements of each embodiment, the constituent elements that are not described in the independent claim for the scope of patent application showing the top-level concept of this disclosure should be understood as arbitrary constituent elements.

The terms used in this specification and the attached patent application scope shall be interpreted as "non-limiting" terms. For example, terms such as "contains" or "contains" should be interpreted as "not limited to the state of being contained." The term "have" should be interpreted as "not limited to the state of being recorded."

The terms used in this manual are used only for convenience of description, and include terms not used for the purpose of limiting the structure and actions. For example, the terms "right", "left", "up", "down" and other terms only indicate the direction above the referenced schema. In addition, terms such as "inside" and "outside" only indicate directions toward and away from the center of the attention element, respectively. The same is true for similar terms or terms with the same subject.

In addition, the technology of the present disclosure may also adopt the following constitutions. According to the technology of the present disclosure having the following constitution, by extending the gate electrode of at least one transistor provided on the circuit layer on a plurality of pixel circuits, it will be provided in each of the plurality of pixel circuits. The wiring that electrically connects the gate electrode of the same type of transistor functions. Thereby, for example, the imaging device can reduce the number of wirings extended to a plurality of pixel circuits among the multilayer wirings provided on the upper layer of the circuit layer. Therefore, the imaging device can relax the design rules in the multilayer wiring layer. The effects exerted by the technology of the present disclosure are not limited to the effects described here, and may be any effects described in this disclosure. (1) A camera device including: A semiconductor substrate, which is arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and A circuit layer having a plurality of pixel circuits that output pixel signals based on the charges output from each of the sensor pixels, and an interlayer insulating layer is provided on the semiconductor substrate; and The gate electrode of at least one transistor included in the pixel circuit is extended on the plurality of pixel circuits in the plane of the circuit layer, and the same type of the transistor is provided on each of the plurality of pixel circuits. The above-mentioned gate electrode is electrically connected. (2) The imaging device of (1) above, wherein the pixel circuit is provided in a specific number of each of the sensor pixels. (3) The imaging device of (1) or (2) above, wherein the gate electrodes of the plurality of transistors included in the pixel circuit are in the plane of the circuit layer, and the plurality of pixel circuits in the same direction are extended. (4) The imaging device according to any one of (1) to (3) above, wherein the gate electrode is provided in a strip shape extending in one direction within the plane of the circuit layer. (5) The imaging device according to any one of (1) to (4) above, wherein the gate electrode is embedded from above the circuit layer to the inside of the circuit layer. (6) The imaging device of (5) above, wherein the part of the gate electrode embedded in the circuit layer is made of polysilicon. (7) The imaging device according to any one of (1) to (4) above, wherein the gate electrode is disposed on the circuit layer. (8) The imaging device according to any one of (1) to (4) above, wherein the gate electrode is provided so as to be embedded in an opening formed in an insulating layer provided on the circuit layer. (9) The imaging device of any one of (1) to (8) above, wherein the gate electrode includes a metal layer and a polysilicon layer. (10) The imaging device of (9) above, wherein barrier layers are provided on the bottom and side surfaces of the metal layer. (11) The imaging device according to any one of (1) to (10) above, wherein the transistor is a transistor other than an amplifier transistor that converts the charge signal output from the sensor pixel into a voltage signal. (12) The imaging device of (11) above, wherein the gate electrode of the amplifying transistor is provided in a manner of being embedded in the first opening and the second opening of the semiconductor layer included in the circuit layer. (13) A camera device including: A semiconductor substrate, which is arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and A circuit layer having a plurality of pixel circuits that respectively output pixel signals based on the charges output from the plurality of sensor pixels, and an interlayer insulating layer is provided on the semiconductor substrate; and The gate electrode of at least one transistor included in the pixel circuit is embedded from the semiconductor layer included in the circuit layer to the inside of the semiconductor layer.

This application is based on the Japanese Patent Application No. 2019-226397 filed with the Japan Patent Office on December 16, 2019, which claims priority, and the entire content of this application is incorporated herein by reference.

If you are a person skilled in the art, you can think of various modifications, combinations, sub-combinations and changes based on the design requirements or other reasons, but you should understand that these are all included in the attached patent application Those within the range or its equivalent.

1: camera device 10: The first layered body 11: Semiconductor substrate 12: sensor pixels 20: The second layered body 21: circuit layer 22: Field Effect Transistor 23: Multilayer wiring layer 25: Gate electrode 26: gate electrode 27: Gate electrode 28: Gate electrode 40: Color filter 42: p well layer 43: component separation part 44: p well layer 45: fixed charge film 46: The first insulating layer 46A: Insulation layer 47: Circuit insulation layer 48: semiconductor layer 50: Receiver lens 54: Through wiring 57: 2nd insulating layer 57A: 2nd insulating layer 57B: 2nd insulating layer 59: Contact plug 601: polysilicon layer 602: polysilicon layer 611: Wiring layer 612: Wiring layer 613: Wiring layer 614: Wiring Layer 620: contact plug 621: contact plug 622: contact plug 623: contact plug 624: contact plug 625: contact plug 626: contact plug 627: contact plug 628: contact plug 631: contact 632: contact 633: Contact 634: Contact 635: contact 636: Contact 637: contact 641: first wiring layer 642: first wiring layer 643: first wiring layer 644: first wiring layer 645: first wiring layer 646: first wiring layer 647: first wiring layer 648: first wiring layer 651: first wiring layer 652: first wiring layer 653: first wiring layer 654: first wiring layer 661: contact 662: Contact 663: contact 664: Contact 665: Contact 666: Contact 667: Contact 668: contact 671: contact 672: contact 673: contact 674: contact 675: Contact 676: Contact 677: contact 678: contact 679: Contact 681: 2nd wiring layer 682: 2nd wiring layer 683: 2nd wiring layer 684: 2nd wiring layer 685: 2nd wiring layer 686: 2nd wiring layer 687: 2nd wiring layer 688: 2nd wiring layer 692: third wiring layer 693: 3rd wiring layer 694: 3rd wiring layer 695: 3rd wiring layer 696: third wiring layer 697: third wiring layer 698: third wiring layer 711: polysilicon layer 712: Barrier Layer 713: Electrode layer 721: electrode layer 732: Barrier Layer 733: metal layer 740: gate insulating film 741: polysilicon layer 742: Barrier Layer 743: electrode layer 744: Interlayer insulating film 750: Gate insulating film 751: Electrode layer 760: gate insulating film 761: polysilicon layer 762: Barrier Layer 763: electrode layer 770: Interlayer insulating film 771: Barrier Layer 772: electrode layer 781: polysilicon layer 781A: first opening 781B: second opening 782: barrier layer 783: Electrode layer 900: camera system 941: lens group 942: Shutter 943: DSP circuit 944: frame memory 945: Display 946: Memory Department 947: Operation Department 948: Power Department 949: bus line 11000: Endoscopic surgery system 11100: Endoscope 11101: lens barrel 11102: camera head 11110: surgical instruments 11111: Pneumoperitoneum 11112: energy disposal equipment 11120: Support arm device 11131: caster 11132: patient 11133: hospital bed 11200: Trolley 11201: CCU 11202: display device 11203: light source device 11204: input device 11205: Disposal equipment control device 11206: Pneumoperitoneum device 11207: Logger 11208: Printer 11400: Transmission cable 11401: lens unit 11402: Camera Department 11403: Drive 11404: Ministry of Communications 11405: Camera head control unit 11411: Ministry of Communications 11412: Image Processing Department 11413: Control Department 12000: Vehicle control system 12001: Communication network 12010: Drive system control unit 12020: car body system control unit 12030: Out-of-car information detection unit 12031: Camera Department 12040: In-car information detection unit 12041: Driver State Detection Department 12050: Integrated control unit 12051: Microcomputer 12052: Sound and image output section 12053: In-vehicle network I/F 12061: Loudspeaker 12062: Display 12063: Dashboard 12100: Vehicle 12101～12105: Camera department 12111～12114: Camera range AMP: Amplified transistor FD: Floating diffusion zone FDG: FD conversion gain switching transistor PD: photodiode RST: reset transistor RU: Repeat area S101～S105: steps SEL: select transistor TG: Vertical gate electrode TG1: Vertical gate electrode TG2: Vertical gate electrode TG3: Vertical gate electrode TG4: Vertical gate electrode TR: Transmission Transistor VDD: power line

FIG. 1 is a longitudinal cross-sectional view illustrating the multilayer structure of an imaging device to which the technology of the present disclosure is applied. Fig. 2 is an equivalent circuit diagram illustrating the circuit structure of the imaging device. FIG. 3 is a schematic explanatory diagram showing the planar configuration of each transistor in the circuit layer of the imaging device according to an embodiment of the present disclosure. FIG. 4A is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. Fig. 4B is a longitudinal cross-sectional view taken along the line A-AA of Fig. 4A. FIG. 5A is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. Fig. 5B is a longitudinal cross-sectional view taken along the line A-AA of Fig. 5A. FIG. 6A is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. Fig. 6B is a longitudinal cross-sectional view at the B-BB cut line of Fig. 6A. Fig. 7 is a longitudinal cross-sectional view showing the change of the cross-sectional structure of the gate electrode. FIG. 8 is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. FIG. 9A is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. Fig. 9B is a longitudinal cross-sectional view at the B-BB cut line of Fig. 9A. FIG. 10 is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. FIG. 11 is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. FIG. 12 is a top view showing the planar configuration of each component in a cross-section of the pixel circuit. FIG. 13A is a top view showing the change of the planar configuration of the gate electrode of the pixel circuit. Fig. 13B is a longitudinal sectional view taken along the line B-BB of Fig. 13A. Fig. 14 is a longitudinal cross-sectional view showing a change of a part of the cross-sectional structure at the B-BB cut line of Fig. 13A. Fig. 15 is a longitudinal cross-sectional view showing a change of a part of the cross-sectional structure at the B-BB cut line of Fig. 13A. Fig. 16 is a longitudinal cross-sectional view showing a change of a part of the cross-sectional structure at the B-BB cut line of Fig. 13A. FIG. 17A is a top view showing the change of the planar configuration of the gate electrode of the pixel circuit. Fig. 17B is a longitudinal cross-sectional view taken along the line B-BB of Fig. 17A. Fig. 17C is a longitudinal cross-sectional view at the C-CC cut line of Fig. 17A. FIG. 18 is a block diagram showing an example of the schematic configuration of an imaging system equipped with the imaging device of this embodiment. Fig. 19 is a flowchart showing the camera operation flow of the camera system. Fig. 20 is a block diagram showing an example of the schematic configuration of the vehicle control system. Fig. 21 is an explanatory diagram showing an example of the installation positions of the exterior information detection unit and the camera unit. Fig. 22 is a diagram showing an example of the schematic configuration of the endoscopic surgery system. Fig. 23 is a block diagram showing an example of the functional configuration of the camera head and CCU.

1: camera device

10: The first layered body

11: Semiconductor substrate

12: sensor pixels

20: The second layered body

21: circuit layer

22: Field Effect Transistor

23: Multilayer wiring layer

40: Color filter

42: p well layer

43: component separation part

44: p well layer

45: fixed charge film

46: The first insulating layer

47: Circuit insulation layer

48: semiconductor layer

50: Receiver lens

54: Through wiring

57: 2nd insulating layer

59: Contact plug

FD: Floating diffusion zone

PD: photodiode

TG: Vertical gate electrode

TR: Transmission Transistor

Claims (13)

A camera device including: A semiconductor substrate, which is arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and A circuit layer having a plurality of pixel circuits that output pixel signals based on the charges output from each of the sensor pixels, and an interlayer insulating layer is provided on the semiconductor substrate; and The gate electrode of at least one transistor included in the pixel circuit is located on the surface of the circuit layer, and is extended on the plurality of pixel circuits, and is of the same type as that provided in each of the plurality of pixel circuits. The gate electrode of the crystal is electrically connected. The imaging device of claim 1, wherein the pixel circuit is provided in a specific number of each of the sensor pixels. The imaging device of claim 1, wherein the gate electrodes of the plurality of transistors included in the pixel circuit are arranged in the plane of the circuit layer, and the plurality of pixel circuits in the same direction are extended. The imaging device of claim 1, wherein the gate electrode is provided in a strip shape extending in one direction within the plane of the circuit layer. The imaging device of claim 1, wherein the gate electrode is embedded from above the circuit layer to the inside of the circuit layer. The imaging device of claim 5, wherein the part of the gate electrode embedded in the circuit layer is provided with polysilicon. The imaging device of claim 1, wherein the gate electrode is disposed on the circuit layer. The imaging device of claim 1, wherein the gate electrode is provided in a manner of being embedded in an opening, and the opening is formed in an insulating layer provided on the circuit layer. The imaging device of claim 1, wherein the gate electrode includes a metal layer and a polysilicon layer. The imaging device of claim 9, wherein barrier layers are provided on the bottom surface and the side surface of the metal layer. The imaging device of claim 1, wherein the transistor is a transistor other than an amplifier transistor that converts the charge signal output from the sensor pixel into a voltage signal. The imaging device of claim 11, wherein the gate electrode of the amplifying transistor is provided in a manner of being embedded in the first opening and the second opening of the semiconductor layer included in the circuit layer. A camera device including: A semiconductor substrate, which is arranged in a matrix with a plurality of sensor pixels for photoelectric conversion; and A circuit layer having a plurality of pixel circuits respectively outputting pixel signals based on the charges output from the plurality of sensor pixels, and the interlayer insulating layer is disposed on the semiconductor substrate; and The gate electrode of at least one transistor included in the pixel circuit is embedded from the semiconductor layer included in the circuit layer into the semiconductor layer.

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