JP2001177084A - Solid state imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging element in which low noise and high image quality can be realized by suppressing reset noise produced in the reset operation of pixel without deviating significantly from a general purpose CMOS process. SOLUTION: Each solid state imaging element comprises a photodiode, a field effect transistor having a gate electrode connected with the output of the photodiode, a first feedback circuit connecting the gate electrode and the drain electrode of the field effect transistor and inserted in series with a first switch means, a second feedback circuit connecting the gate electrode and the drain electrode of the field effect transistor and inserted in series with a second switch means and a first capacitor, and a second capacitor having one end connected between the first capacitor and the second switch and the other end of fixed potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to a low noise amplification type CMO capable of realizing high image quality.
The present invention relates to a solid-state imaging device using an S image sensor.

[0002]

2. Description of the Related Art Hitherto, a solid-state imaging device has been provided with a function of amplifying a charge signal photoelectrically converted in a pixel, thereby improving the characteristics of an image sensor, and has been put to practical use.

As a pixel having a function of amplifying a photoelectrically converted signal as described above, for example, IEEE Jou
rnal of S0lid-State Circuit
its, vol. SC-4, no. 6 (1969) "P
photosensitivity and Scann
ing of Silicon Image Dete
ct Arrays ”and Japanese Patent Laid-Open No. 50-134393.
As disclosed in Japanese Unexamined Patent Publication, a method has been proposed in which a pixel is provided with a signal amplifier circuit formed of a MOS field effect transistor.

A MOS image sensor in which a pixel is constituted by a MOS field effect transistor can be manufactured by a process close to a general-purpose CMOS, so that it is easy to manufacture and requires only a normal CMOS clock for a drive pulse and a single drive. Powered by a power supply, the power supply is simple, and
It is easy to integrate CMOS digital circuits and analog circuits on the same chip.

In recent years, such a MOS image sensor has several advantages over a CCD image sensor, such as being capable of forming a multifunctional image sensor. It is drawing attention as an image sensor to be incorporated in a portable imaging device or the like that requires power and miniaturization.

FIG. 5 shows a conventional amplification type pixel constituted by a MOS type field effect transistor.

First, an amplifying pixel constituted by a conventional MOS field effect transistor will be described with reference to FIG.

FIG. 5 shows the configuration of a unit pixel using an equivalent circuit.

In FIG. 5, reference numeral 10-1 is:
It is a photodiode that generates electric charges by irradiating light.

Reference numeral 10-2 denotes a reset MOS field-effect transistor for connecting the N-side electrode 10-3 of the photodiode 10-1 to the voltage wiring 10-4 of the reset voltage (source) VRS. is there.

Reference numeral 10-5 indicates that the gate electrode is connected to the N-side electrode 10-3 of the photodiode 10-1, and the drain electrode side is connected to the voltage wiring 10-6 of the voltage power supply VD. This is an amplification type MOS field effect transistor.

Reference numeral 10-7 indicates that the drain electrode of the amplifying MOS field effect transistor 10
-5, which is connected to a source electrode of a pixel selection MOS transistor, the source electrode of which is connected to the signal output wiring 10-8
Type field effect transistor.

The signal output wiring 10-8 is equivalently grounded at its output end via a load circuit 10-9, so that it is equivalent to the amplifying MOS field effect transistor 10-.
A signal voltage dependent on the voltage (VPIX) of the N-side electrode 10-3 of the photodiode 10-1 is output via a source follower circuit composed of a load circuit 5 and a load circuit 10-9.

Next, the operation of the pixel shown in FIG. 5 will be described.

FIG. 6 is a timing chart for explaining the operation of a conventional pixel.

In FIG. 6, ΦRS indicates a pulse inputted to the gate electrode of the reset MOS field effect transistor 10-2.

ΦRD indicates a pulse inputted to the gate electrode of the MOS field effect transistor 10-7 for pixel selection.

VPIX indicates a potential change of the N-side electrode 10-3 of the photodiode 10-1.

First, at time t0, ΦRS becomes H, and the potential VPIX of the N-side electrode 10-3 of the photodiode 10-2.
Are set to the reset voltage VRS.

Next, at time t1, the reset MOS transistor 10-2 turns off, and the N-side electrode 10-3 of the photodiode enters a floating state.

When light enters the pixel, a light-generating current flows through the photodiode 10-1 and the photodiode 10-1
As the charge of the photo-generated electrons is accumulated in the -1 N-side electrode 10-3, the potential VPIX gradually decreases.

Next, when the pixel selecting MOS field effect transistor 10-7 is turned on at time t2, a voltage output corresponding to the potential VPIX of the N-side electrode 10-3 of the photodiode 10-1 at time t2 is output to the signal output wiring. 10-8
Is output to

Here, VPIX is the photodiode 1
Since it depends on the amount of charge stored in the 0-side N-side electrode 10-3, the amount of stored charge is estimated by monitoring the output of the signal output wiring 10-8, and eventually the amount of incident light is detected. It becomes possible.

By the way, when providing a signal amplification function for each pixel as described above, it is necessary to consider that noise due to offset variation occurs in the output and the image quality of the output image is significantly deteriorated. It is necessary to avoid.

Such noise becomes noise fixed at the pixel position and is called fixed pattern noise (hereinafter abbreviated as FPN).

A general method for suppressing the generation of the FPN is disclosed in, for example, Japanese Patent Application Laid-Open No. 56-46374.

As an example of suppressing the occurrence of FPN applied to an amplification type imaging device, Japanese Patent Publication No. 08-004127
Is disclosed in Japanese Unexamined Patent Application Publication No. 2000-205,878.

Hereinafter, these FPN canceling methods will be described.

FIG. 7 schematically shows the configuration of an image pickup apparatus having a readout circuit for canceling FPN.

In FIG. 7, reference numeral 12-1 is
This is a pixel array section in which a plurality of pixels 12-2 are arranged two-dimensionally, for example, in a matrix.

Reference numeral 12-3 denotes a vertical scanning circuit for selecting a row of the pixel array section 12-2.

Reference numeral 12-4 denotes a horizontal scanning circuit for selecting an output column of the pixel array section 12-2.

The selection pulse input terminal and the reset pulse input terminal of the pixel 12-2 are connected to a horizontal selection line 12-5 and a row reset line 12-6, respectively, and output by the vertical scanning circuit 12-3. Controlled by the scanning signal.

The signal output terminal of the pixel 12-2 is connected to a signal output line 12-7, and the signal output to the signal output line 12-7 is sent to an FPN canceling unit 12-18 provided in column parallel. Is entered.

This FPN cancel circuit 12-18 is
Switch 12-9, capacitor 12-11 and switch 12
-10 and a capacitor 12-12.

The capacitor 12-11 is connected to a first video signal line 12-15 via a horizontal selection switch 12-13, and the capacitor 12-12 is connected via a horizontal selection switch 12-14. And the second video signal line 12
-16.

The first video output line 12-15 and the second video output line 12-16 are connected to a positive input terminal and a negative input terminal of a differential amplifier (amplifier) 12-17, respectively. ing.

The differential amplifier 12-17 is input to the positive input terminal and the negative input terminal, respectively.
The difference between the two signals is output.

FIG. 8 is a timing chart for explaining the operation of the image pickup apparatus having the FPN cancel readout circuit configured as described above.

Next, the FPN cancel operation will be described based on the chart timing shown in FIG.

First, at time t0 in the horizontal blanking period,
, The row selection pulse ΦR from the vertical scanning circuit 12-3.
D-1 is output, and the pixels 12-1 in the first row are selected.

Next, at time t1, the sample-and-hold pulse ΦSH1 becomes H, and the pixel 12
The output voltage of -1 is stored in the capacitor 12-11.

Next, after resetting the pixel 12-1 at time t2, the sample hold pulse ΦSH2 is set to H at time t3, and the output after the pixel reset, that is, the offset output voltage is stored in the capacitor 12-12.

Thereafter, at time t4, within the horizontal scanning period, the horizontal selection pulse ΦH-
J is output, and the signal stored in the capacitor 12-11 is output to the first video signal line 12-15 via the horizontal selection switch 12-13 and the horizontal selection switch 12-14. 12 is the second signal
To the video signal line 12-16.

The differential amplifier 12-17 has a first input terminal and a first input terminal, which are input to the negative input terminal, respectively.
Video signal line 12-15 and second video signal line 1
The difference between the two signals from 2-16 is output.

With this configuration, it is possible to suppress FPN caused by variations in characteristics of pixels and selection switches.

[0047]

However, even in the solid-state imaging device which performs the readout with the improved FPN as described above, there is a problem due to the remaining random noise.

As a main cause of the random noise, thermal noise generated when the photodiode section of the pixel is reset has the greatest influence.

More specifically, in FIG. 5, when the photodiode 10-1 is reset, at the moment when the reset MOS field effect transistor 10-2 is turned off, the N-side electrode 10 of the photodiode 10-1 is turned off. The cause is that the voltage of −3 fluctuates.

Here, the N-side electrode 10-3 of the photodiode 10-1 is connected to the gate electrode of the amplifying MOS field effect transistor 10-5 for reading, so that the amplifying for reading is performed. Field effect MOS
When the voltage of the gate electrode of the transistor 10-5 fluctuates, offset fluctuation occurs in the output, which causes a problem that the image quality of the output image is significantly deteriorated.

The standard deviation of the voltage fluctuation of the N-side electrode 10-3 of the photodiode 10-1 is (kT /
C) It becomes ^1/2 .

Here, k is the Boltzmann constant, T is the absolute temperature, C is the N-side electrode 10-3 of the photodiode 10-1.
Is the sum of the total capacitance with respect to the ground which is equivalent to

Since this voltage fluctuation occurs randomly every reset operation, the voltage fluctuation shown in FIG. 7 and FIG.
By calculating the difference between the two reset operations, the operation of suppressing the FPN is further multiplied by ^21/2 , and in actuality, noise of (2kT / C) ^1/2 is mixed into the video output.

Generally, this noise is reset noise,
Or kTC noise.

In order to improve such reset noise so as not to be suppressed or generated, for example, the photodiode section of the pixel is constituted by a CCD element, and after reset, the charge is stored in the charge storage section so that no charge exists in the charge storage section. ,
A method of completely transferring charges like a CCD is also conceivable.

However, the conventional amplification type CMOS pixel has a problem in that good sensitivity cannot be obtained due to reset noise generated when the photodiode is reset, and it is not suitable for high image quality applications.

For example, when the value of C is a pixel of 10 fF,
The value of the reset noise at room temperature is approximately 60 e− in terms of the number of equivalent input charges, which is several times larger than the noise of a normal CCD, and there is a problem that high image quality cannot be obtained.

When the photodiode is to be realized in a CCD configuration, the MO constituting the photodiode is required.
It is necessary to make the gate electrode of the S-capacitor transparent so that light can enter and to provide a transfer gate, which greatly changes from a general-purpose CMOS process.
There is a problem that the original feature of ease of manufacture is lost.

In the prior art, no method has been proposed for suppressing reset noise without greatly deviating from a general-purpose CMOS process.

The present invention has been made in view of the above-described problems, and suppresses reset noise generated in a pixel reset operation without largely deviating from a general-purpose CMOS process. It is an object of the present invention to provide a solid-state imaging device having a pixel structure and operation capable of realizing low noise and high image quality.

[0061]

According to the present invention, in order to solve the above-mentioned problems, (1) a solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode and an output of the photodiode. A field-effect transistor having a gate electrode connected thereto, a first feedback circuit connecting a gate electrode and a drain electrode of the field-effect transistor, and first switching means inserted in series on the way; A second feedback circuit in which a second switch means and a first capacitor are inserted in series in the middle between the first capacitor and the second switch; A second capacitor having one end connected and a fixed potential at the other end.

According to the present invention, in order to solve the above-mentioned problems, (2) in the operation of resetting the output-side potential of the photodiode by the reset potential applied to the drain electrode of the field-effect transistor, The first switch means and the second switch means are turned on, and at the end, the first switch means is turned off first, and then the second switch means is turned off. The solid-state imaging device according to (1), further comprising circuit means is provided.

According to the present invention, in order to solve the above-mentioned problems, there is provided (3) a solid-state image pickup device having a plurality of pixels, and a first image pickup device which is inserted in series in the middle of an output line from the pixel.
And a second capacitor, and an output based on light reception from the pixel is applied only to the first capacitor, and the output after resetting the pixel is connected in series with the first and second capacitors. And a switching means for switching the application of the output so as to apply the output to the solid-state imaging device.

[0064]

Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment of the present invention will be specifically described.

(First Embodiment) FIG. 1 shows the configuration of a solid-state imaging device according to a first embodiment of the present invention.

That is, as shown in FIG. 1, a pixel unit 1 serving as a unit of the pixel array 2 includes a photodiode 10
A read-amplification MOS field-effect transistor 11 of a predetermined first conductivity type having a gate electrode connected to the N-side electrode of the photodiode 10; and a serial connection with the read-amplification MOS field-effect transistor 11. A row-selecting MOS field-effect transistor 12 of a predetermined first conductivity type connected to the photodiode 10;
And the read-out amplification MOS field effect transistor 1
A first reset switch 13 provided between the drain electrode of the first MOS transistor and the feedback capacitor 14 provided between the drain electrode of the MOS field effect transistor for readout amplification 11 and the photodiode 10; , And a buffer capacitor 16 connected between a connection point between the feedback capacitor 14 and the second reset switch 15 and a ground terminal.

Also, as shown in FIG.
Is configured by arranging the unit pixels 1 two-dimensionally, for example, in a matrix.

The row selecting MOS of the unit pixel 1
The gate electrodes of the field effect transistors 12 are commonly connected to each other via a row selection line 20.

The control electrode of the first reset switch 13 is commonly connected to each row via a first horizontal reset wiring 21, and the control electrode of the second reset switch 15 is 2 horizontal reset wiring 22
Are connected in common for each row.

The row selection line 20, the first reset wiring 21, and the second reset wiring 22 are connected to the vertical scanning circuit 3, respectively.

The drain electrodes of the read-amplifying MOS field effect transistors 11 of the pixel unit 1 are connected in common to each column via a pixel drain wiring 23, and each column has a constant current. The power supply 30 is connected to a positive power supply.

At both ends of the constant current source 30, switches 31 are provided in parallel with the constant current source 30.

On the other hand, the source electrode of the row-selecting MOS field effect transistor 12 is connected in common to each column via a pixel source line 24 and is independently connected to the second constant current source 32 for each column. Connected to the negative power supply.

At both ends of the constant current source 32, switches 33 are provided in parallel with the constant current source 32.

In the present embodiment, for simplicity of description, only the pixels of the coordinates of the I-th row and the J-th column among the pixels constituting the pixel array 2 are described.

The pixel source wiring 24 in each column is connected to a sample / hold capacitor 35 via a sample / hold switch 34.

A horizontal selection switch 36 is provided between the sample hold capacitor 35 and the video output line 40.

The control terminal of the horizontal selection switch 36 is connected to the horizontal scanning circuit 4.

FIG. 2 is a timing chart shown for explaining the operation of the image pickup device thus configured.

Next, the operation of the image pickup device having the above configuration will be described with reference to the timing chart shown in FIG.

In FIG. 2, ΦRD-I is a pulse output to the row selection line 20 of the pixel on the I-th row.
1-I is a pulse output to the first reset wiring 21 of the pixel on the I-th row, and ΦRS2-I is a pulse output to the second reset wiring 22 of the pixel on the I-th row. ΦDSW is a pulse input to the control electrode of the switch 31 on the pixel drain wiring side, ΦSSW is a pulse input to the control electrode of the switch 33 on the pixel source wiring side, and ΦSH is a pulse of the sample hold switch 34. ΦH-J is a horizontal selection pulse input to the control terminal of the horizontal selection switch 36 in the J-th column.

In FIG. 2, VPIX is the potential of the gate electrode of the read-out amplification MOS field effect transistor 11 of the pixel located at the I-th row and the J-th column, and VDP
IX is the potential of the pixel drain wiring in the J-th column, VS
PIX is the potential of the pixel source wiring in the J-th column.

For the sake of simplicity, each of the above-mentioned switches has a high-level (H) input at its control terminal.
At the low level (L) and non-conductive at the low level (L).

Each switch is an ideal switch, and the effects of the injection of feed-through charge and the parasitic capacitance with the control pulse accompanying the switching operation are shown as being negligible.

First, at time t0 in the horizontal blanking period, ΦRD-I becomes H, and the row-selecting MOS field effect transistor 12 of the pixel on the I-th row is turned on.

At this time, ΦSSW is L and ΦDSW is H
Therefore, a source follower circuit is configured by the read-out amplification MOS field effect transistor 11 of the pixel 1 and the source side constant current source 32, and the VPI
A voltage proportional to the potential of X is output as a follower output.

Next, at time t1, ΦSH becomes H, and the follower output output to the pixel source wiring 24 is stored in the sample hold capacitor 35.

When ΦSSW becomes H and ΦDSW becomes L at time t2, the drain-side constant current source 30 and the read-amplification MOS field effect transistor 11 of the pixel 1 constitute an inverter circuit.

In this state, at time t3, ΦRS1-
When both I and ΦRS2-I become H and the first reset switch 13 and the second reset switch 15 are turned on, the input terminal and the output terminal of the inverter circuit are short-circuited, and the read amplification MOS The potential VPIX of the gate electrode of the field effect transistor 11 is reset to a predetermined voltage VRS.

In this state, at time t4, ΦRS
When only 1 becomes L and the first reset switch 13 is turned off, a reset noise ΔV1 appears in VPIX.

However, at this time, since the second reset switch 15 is on, the inverter circuit composed of the drain-side constant current source 30 and the read-out amplification type MOS field effect transistor 11 of the pixel 1 has: It functions as an inverting amplifier circuit, and VPIX
Apply negative feedback so that VRS becomes VRS.

Then, at time t5 when this feedback operation is sufficiently stabilized, ΦRS2-I is switched to L, and the second reset switch 15 is turned off, thereby generating reset noise ΔV2 again.

However, the voltage fluctuation due to the reset noise ΔV2 is suppressed by the buffer capacitance 16, and the generated voltage fluctuation is further suppressed as an amount transmitted to the VPIX by the series connection of the feedback capacitance 14 and the photodiode. Will be.

Then, at t6, the horizontal blanking period ends, and the horizontal scanning period starts.

Next, at time t7, the horizontal selection pulse ΦH-J in the J-th column is output from the horizontal scanning circuit 4, and the signal of the pixel in the I-th row and the J-th column is output to the video output line 40.

At this time, since the reset noise generated when the pixel unit 1 is reset is suppressed, the influence of the reset noise on the output of the read pixel is smaller than that of the conventional pixel structure.

Next, a supplementary explanation of the reset noise suppressing effect according to the present invention will be added.

Now, let the storage capacity of the photodiode 10 be C
Assuming that the capacitance value of the PD and the feedback capacitance 14 is CFB and the capacitance value of the buffer capacitance 16 is CP, the standard deviation of the voltage fluctuation of VPIX caused by the closing operation of the second reset switch 15 is given by the following equation.

ΔVPIX = SQR [kT / ((CPD +
CFB) × CPD / CFB) + (CPD + CFB) ×
(CPD + CFB) × CP / (CFB × CFB))] Here, for convenience, VPI when capacitance feedback is not performed
Assuming that the voltage fluctuation ΔPIX0 of X is ΔPIXO = SQR [kT / (CPD + CFB)], the suppression ratio is as follows: suppression ratio = SQR [1 / (CPD / CFB + (CPD + C
FB) × CP / (CFB × CFB)].

For example, CPD: CFB: CP = 5: 1:
When it is set to 2, the suppression ratio of the reset noise becomes about 1/4, and the fluctuation due to the reset operation of the pixel electrode can be greatly improved.

(Second Embodiment) FIG. 3 is a diagram shown to explain a configuration of a solid-state image pickup device according to a second embodiment of the present invention.

In FIG. 3 showing the second embodiment, the same reference numerals are given to portions having the same structure and function as those shown in the above-described first embodiment. .

FIG. 3 shows the second embodiment.
In the following, a description will be given of portions whose configuration and functions are different from those shown in the first embodiment described above.

First, in FIG. 3 showing the second embodiment, a pixel source line 24 connected from a pixel unit 1 is provided in parallel with a second constant current source 32 and the second constant current source 32. The configuration up to connection to the switch 33 is the same as that of the first embodiment, but a circuit for recording a voltage signal of the pixel source line 24 is different.

That is, the pixel source wiring 24 of each column is
First sample and hold switch 37 and capacitive element 3
The sample and hold capacitor 35 is connected to the sample and hold capacitor 35 via a second sample and hold switch 8.

A horizontal selection switch 36 is provided between the sample hold capacitor 35 and the video output line 40.

The control terminal of the horizontal selection switch 36 is connected to the horizontal scanning circuit 4.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

Next, the operation of the second embodiment will be described with reference to the timing chart of FIG.

In FIG. 4, ΦSH1 is a pulse input to the control terminal of the first sample and hold switch 37, and ΦSH2 is a pulse input to the control terminal of the second sample and hold switch 39.

First, at time t0 in the horizontal blanking period, φRD-I becomes H, and the row-selecting MOS field effect transistor 12 of the pixel on the I-th row is turned on.

At this time, ΦSSW is L and ΦDSW is H
Therefore, a source follower circuit is configured by the read-out amplification MOS field effect transistor 11 of the pixel unit 1 and the source side constant current source 32, and the pixel source line 24 has V
A voltage proportional to the potential of PIX is output as a follower output.

At this time, ΦSH1 is always H.

Next, at time t1, ΦSH2 becomes H, and a signal corresponding to the follower output output to the pixel source wiring 24 is stored in the sample hold capacitor 38.

Next, at time t2, when ΦSSW becomes H and ΦDSW becomes L, the drain-side constant current source 30 and the read-out amplification type MOS field effect transistor 11 of the pixel unit 1 constitute an inverter circuit. .

In this state, at time t3, ΦRS1-
When I and ΦRS2-I become H and the first reset switch 13 and the second reset switch 15 are turned on, the input terminal and the output terminal of the inverter circuit are short-circuited. As in the embodiment, the potential VPIX of the gate electrode of the readout amplification MOS field effect transistor 11 of the pixel unit 1 is reset to a predetermined voltage VRS.

In this state, at time t4, when only ΦRSI becomes L and the first reset switch 13 is turned off, a reset noise ΔV1 appears in VPIX.

However, since the second reset switch 15 is turned on at this time, the inverter circuit composed of the drain-side constant current source 30 and the read-out amplification type MOS field effect transistor 11 of the pixel unit 1 performs inversion amplification. It functions as a circuit and applies negative feedback via the feedback capacitor 14 so that VPIX becomes VRS.

When the feedback operation is sufficiently stabilized at time t5, ΦRS2-I is switched to L and the second reset switch 15 is turned off.
V2 is generated.

However, the voltage fluctuation due to the reset noise ΔV 2 is suppressed by the buffer capacitor 16, and the amount transmitted to the VPIX is further suppressed by the series coupling of the feedback capacitor 14 and the photodiode 10.

At time t5, ΦSSW changes to L and ΦDSW switches to H, so that the read-amplification MOS field-effect transistor 11
And a second constant current source 32, a source follower circuit is formed.
A follower output of the gate voltage of the field effect transistor 11 appears.

Subsequently, at time t6, ΦSH1 becomes L,
The difference voltage between the signal stored at time t1 and the pixel source wiring 24 after resetting the pixel, that is, the offset signal of the pixel is stored in the sample hold capacitor 35.

Thereafter, at time t7, the horizontal blanking period ends and the horizontal scanning period starts.

Next, at time t8, the horizontal selection pulse ΦH-J of the J-th column is output from the horizontal scanning circuit 4, and the readout signal after the pixel photocharge accumulation on the I-th row and the J-th column is output to the video signal line 4.
Output to 0.

As described above, according to the second embodiment of the present invention, the reset noise of the pixel can be effectively suppressed, and the read signal and the reset pixel signal can be reduced. By taking the difference, it is possible to realize a solid-state imaging device with higher image quality in which offset variation does not occur.

[0127] In the present specification described in the above embodiments, in addition to claims 1 to 3 described in the claims, the inventions shown below as supplementary notes 1 and 2 will be described. include.

(Supplementary Note 1) The other electrode of the photodiode whose one electrode is grounded is the first MOS transistor of the first conductivity type.
A transistor, a second MOS transistor of a first conductivity type connected to a gate electrode of the first MOS transistor, and a drain electrode connected to a source electrode of the first MOS transistor; and the first MOS transistor. A first switch provided between the drain electrode and the gate electrode of the first MOS transistor, a first capacitor having one electrode connected to the gate electrode of the first MOS transistor, and a first switch connected to the first capacitor. A second switch provided between the other electrode and the drain electrode of the first MOS transistor, and a second switch connected between the first capacitor and the second switch and a ground electrode. , The first and second MOS transistors, the first and second switches, and the first and second capacitors. A plurality of pixels configured, a drain electrode of the first MOS transistor in each pixel of the plurality of pixels connected in common for each column, and a pixel drain line wired in a vertical direction; , A source electrode of the second transistor of each pixel is connected in common for each column, and a pixel source line vertically wired, and a gate electrode of the second MOS transistor of each pixel in the plurality of pixels A first row reset, which is commonly connected to each row and connects a column selection line wired in the horizontal direction and a control electrode of the first switch commonly to each row, and is wired in the horizontal direction And a control terminal of the second switch, which is commonly connected to each row, and a second row reset line wired in the horizontal direction, and the pixel drain. And down line, and the pixel source wiring, and the column select lines, said first and second
A pixel array unit including a row reset line, a vertical scanning circuit connected to the column selection line and the first and second row reset lines, a pixel drain line and a first power supply electrode. And a third constant current generating circuit provided between the first and second constant current generating circuits.
A second constant current generating circuit provided between the pixel source line and a second power supply electrode; a fourth switch provided in parallel with the second constant current circuit; A sample-and-hold circuit provided to store the voltage of the wiring in parallel for each column; a fifth switch provided between an output terminal of the sample-and-hold circuit and a video signal output line; A solid-state imaging device connected to the control electrode and configured with a horizontal scanning circuit for selecting a column of pixel output;

(Function and Effect) According to the present invention, the reset noise generated by the reset operation of the photodiode is converted into a feedback circuit composed of the first current source, the first MOS transistor and the first capacitor. Thus, a high-performance amplifying MOS pixel with little random noise can be realized.

Further, the pixel according to the present invention has a normal C
Since only general-purpose elements are formed by the MOS process, there is little change from the conventional general-purpose CMOS process, and the manufacturing cost can be reduced.

(Supplementary Note 2) The other electrode of the photodiode whose one electrode is grounded is the first MOS transistor of the first conductivity type.
A transistor, a second MOS transistor of a first conductivity type connected to a gate electrode of the first MOS transistor, and a drain electrode connected to a source electrode of the first MOS transistor; and the first MOS transistor. A first switch provided between the drain electrode and the gate electrode of the first MOS transistor, a first capacitor having one electrode connected to the gate electrode of the first MOS transistor, and a first switch connected to the first capacitor. A second switch provided between the other electrode and the drain electrode of the first MOS transistor, and a second switch connected between the first capacitor and the second switch and a ground electrode. , The first and second MOS transistors, the first and second switches, and the first and second capacitors. A plurality of pixels configured, a drain electrode of the first MOS transistor in each pixel of the plurality of pixels connected in common for each column, and a pixel drain line wired in a vertical direction; , A source electrode of the second transistor of each pixel is connected in common for each column, and a pixel source line vertically wired, and a gate electrode of the second MOS transistor of each pixel in the plurality of pixels A first row reset, which is commonly connected to each row and connects a column selection line wired in the horizontal direction and a control electrode of the first switch commonly to each row, and is wired in the horizontal direction And a control terminal of the second switch, which is commonly connected to each row, and a second row reset line wired in the horizontal direction, and the pixel drain. And down line, and the pixel source wiring, and the column select lines, said first and second
A pixel array unit including a row reset line, a vertical scanning circuit connected to the column selection line and the first and second row reset lines, a pixel drain line and a first power supply electrode. And a third constant current generating circuit provided between the first and second constant current generating circuits.
A second constant current generating circuit provided between the pixel source line and a second power supply electrode; a fourth switch provided in parallel with the second constant current circuit; A first sample-and-hold circuit provided for storing the voltage of the wiring in parallel for each column; a signal stored in the first sample-and-hold circuit at a first time; A difference circuit for obtaining a difference from the input signal at a second time, a second sample and hold circuit provided for sampling and holding the output of the difference circuit, and an output and a terminal of the second sample and hold circuit. A solid-state imaging device comprising: a fifth switch provided between the video signal output line; and a horizontal scanning circuit connected to a control electrode of the fifth switch and selecting a column of a pixel output.

(Effects) According to the present invention, the above-mentioned additional statement 1
In addition to the reset noise suppression effect that can be achieved with the invention of
It is possible to realize a solid-state imaging device using a higher performance amplifying MOS pixel that can suppress offset variation for each pixel.

[0133]

As described above, according to the first and second aspects of the present invention, the reset noise generated in the pixel reset operation can be suppressed without greatly deviating from the general-purpose CMOS process. A solid-state imaging device having a pixel structure and operation capable of realizing low noise and high image quality, which cannot be obtained with the amplifying MOS type pixel, can be provided.

According to the third aspect of the present invention, it is possible to provide a solid-state imaging device in which offset variations are suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention;

FIG. 2 is a timing chart shown for explaining a solid-state operation according to the first embodiment of the present invention.

FIG. 3 is a diagram shown for explaining a configuration of a solid-state imaging device according to a second embodiment of the present invention;

FIG. 4 is a timing chart shown to explain a solid-state operation according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a conventional amplifying pixel constituted by a MOS field-effect transistor.

FIG. 6 is a timing chart illustrating the operation of a conventional pixel.

FIG. 7 schematically shows a configuration of a conventional imaging apparatus including a readout circuit for canceling FPN.

FIG. 8 is a timing chart for explaining the operation of a conventional imaging device having an FPN cancel readout circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Pixel unit, 2 ... Pixel array, 10 ... Photodiode, 11 ... MOS field effect transistor for readout amplification, 12 ... MOS field effect transistor for row selection, 13 ... 1st reset switch, 14 ... Feedback capacitance, 15: second reset switch, 16: buffer capacitance, 20: row selection line, 21: first horizontal reset wiring, 22: second horizontal reset wiring, 3: vertical scanning circuit, 23: pixel drain wiring, 30 ... constant current source, 31 ... switch, 24 ... pixel source wiring, 32 ... second constant current source, 33 ... switch, 34 ... sample hold switch, 35 ... sample hold capacity, 40 ... video output line, 36 ... horizontal selection Switch 4: horizontal scanning circuit 37: first sample and hold switch 38: capacitive element 39: second sampler Field switch.

Claims (3)

[Claims] 1. A solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode, a field-effect transistor having a gate electrode connected to an output of the photodiode, and a gate electrode of the field-effect transistor. A first feedback circuit for connecting a drain electrode, a first switch means being inserted in series on the way, a second feedback means for connecting a gate electrode and a drain electrode of the field effect transistor, A second feedback circuit having a first capacitor connected in series with a second capacitor having one end connected between the first capacitor and the second switch and having a fixed potential at the other end. A solid-state imaging device comprising: 2. An operation for resetting an output-side potential of said photodiode by a reset potential applied to a drain electrode of said field-effect transistor, wherein said first switch means and said second switch means are electrically connected at the start. 2. A circuit according to claim 1, further comprising a circuit means for bringing said first switch means into a non-conductive state at the end of said first switch means and then bringing said second switch means into a non-conductive state at the time of termination. Solid-state imaging device. 3. A solid-state imaging device having a plurality of pixels, the first and second capacitors inserted in series in the middle of an output line from the pixel, and an output based on light reception from the pixel. Switching means for switching the application of the output so that the output after resetting the pixel is applied to only the first capacitor and the output after resetting the pixel is applied to the series connection of the first capacitor and the second capacitor. A solid-state imaging device characterized by the above-mentioned.