WO2018216309A1 - Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device - Google Patents

Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device Download PDF

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Publication number
WO2018216309A1
WO2018216309A1 PCT/JP2018/008806 JP2018008806W WO2018216309A1 WO 2018216309 A1 WO2018216309 A1 WO 2018216309A1 JP 2018008806 W JP2018008806 W JP 2018008806W WO 2018216309 A1 WO2018216309 A1 WO 2018216309A1
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solid
state imaging
imaging device
fluorine
gate electrode
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PCT/JP2018/008806
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French (fr)
Japanese (ja)
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裕史 岩田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • the present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus.
  • CMOS Complementary Metal Oxide Semiconductor
  • a CMOS (Complementary Metal Oxide Semiconductor) type image sensor has been attracting attention as a solid-state imaging device that can be produced at low cost because it can be produced by a semiconductor formation process that is a general-purpose CMOS process.
  • Baseline noise is known to have a strong correlation with 1 / f noise (also referred to as “flicker noise”) generated in an amplification transistor included in a pixel.
  • 1 / f noise also referred to as “flicker noise”
  • Patent Document 1 CMOS type image sensor that reduces 1 / f noise by injecting fluorine into an amplification transistor has been proposed.
  • CMOS image sensor disclosed in Patent Document 1 also has a problem that 1 / f noise is not sufficiently reduced.
  • Patent Document 1 is a method for reducing 1 / f noise caused by a pixel region by injecting fluorine exclusively into an amplification transistor.
  • the present inventor has considered that the performance of the solid-state imaging device has been improved by reducing the 1 / f noise caused by the pixel region, but it has been considered that there is a limit to reducing the 1 / f noise by itself.
  • An object of one embodiment of the present invention is to provide a further method for improving the performance of a solid-state imaging device in view of the above problems.
  • a solid-state imaging device includes a pixel region and an analog-digital conversion circuit that performs analog-digital conversion on a voltage signal output from the pixel disposed in the pixel region.
  • the analog-digital conversion circuit unit includes a MOS transistor in which fluorine is integrated in the vicinity of the interface between the semiconductor substrate and the gate oxide film disposed on the semiconductor substrate.
  • the solid-state imaging device has an effect that a performance that has never been achieved can be obtained.
  • FIG. 1 It is a top view which shows schematic structure of the solid-state image sensor which concerns on one Embodiment of this invention. It is a top view which shows schematic structure of the ADC circuit part contained in the said solid-state image sensor. It is a circuit diagram which shows the structure of the Comparator contained in the said ADC circuit part.
  • (A)-(e) is sectional drawing which shows the manufacturing process of the n-type MOS transistor contained in the said comparator. It is a graph which shows the fluorine concentration profile in the said n-type MOS transistor in each after a fluorine injection
  • the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Also included in the drawings are portions having different dimensional relationships and ratios.
  • the solid-state imaging device 1 is a CMOS image sensor.
  • a CMOS type image sensor generally has a light receiving region, a floating diffusion part (FD part), and an analog-digital conversion circuit part (Analog Digital Converter, hereinafter referred to as “ADC circuit part”).
  • the light receiving region performs photoelectric conversion of image light
  • the floating diffusion unit converts signal charges obtained by the photoelectric conversion into voltage signals
  • the ADC circuit unit performs analog-digital conversion on the converted signal charges.
  • the light receiving region, the floating diffusion portion, and the ADC circuit portion are provided on a common substrate.
  • a plurality of photodiodes as light receiving portions that generate charges by light irradiation are provided for each pixel.
  • charges generated in each light receiving portion of the light receiving region are signal charges.
  • Read from. The read signal charge is converted into a voltage signal which is an analog signal in the pixel.
  • the voltage signal is read out for each pixel through the signal wiring and input to the ADC circuit unit.
  • the ADC circuit unit converts the input voltage signal into a digital signal.
  • FIG. 1 is a plan view showing a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention.
  • the solid-state imaging device 1 includes a pixel region 11, an ADC circuit unit 12, and a peripheral circuit unit 13.
  • the pixel region 11 includes a plurality of pixels 51 (see FIG. 2) arranged in a two-dimensional matrix (array), and forms a rectangular imaging region.
  • an ADC circuit unit 12 and a peripheral circuit unit 13 are arranged around the pixel region 11.
  • the ADC circuit unit 12 performs analog-to-digital conversion on the voltage signal output from each pixel in the pixel region 11 for each column in the pixel region 11.
  • the peripheral circuit unit 13 generates a captured image by performing logic processing on the voltage signal analog-digital converted by the ADC circuit unit 12.
  • FIG. 2 is a plan view showing a schematic configuration of the ADC circuit unit 12.
  • a sensor array 50 in which a plurality of pixels 51 are arranged in a two-dimensional matrix is arranged in the pixel region 11.
  • the ADC circuit unit 12 performs analog-digital conversion of the voltage signal output from each pixel 51 of the Sensor Array 50 arranged in the pixel region 11 for each column.
  • the ADC circuit unit 12 corresponds to each column of the RAMP 22 and the pixel region 11 (more specifically, Sensor Array 50), and a plurality of Column A / Ds 23 provided for each column, and Gray. Including Code Counter24.
  • the Gray Code Counter 24 is a member that is not directly related to the present embodiment, so that the description thereof is omitted, but it may be understood that it is the same as a known one.
  • a voltage signal output from the pixel 51 included in the column of the pixel region 11 corresponding to itself is input to each Column A / D 23 via the Capacitor 25.
  • the comparator 26 (comparator) compares the input voltage signal with the RAMP waveform (reference value) generated by the RAMP 22 and outputs the comparison result to the W-Latch 27.
  • FIG. 3 is a circuit diagram showing a configuration of the comparator 26.
  • the comparator 26 includes an inverter circuit 31 that is a CMOS transistor including a p-type MOS transistor 32 and an n-type MOS transistor 33.
  • FIGS. 4A to 4E are cross-sectional views showing the manufacturing process of the n-type MOS transistor 33.
  • FIG. The manufacturing steps shown in FIGS. 4A to 4E use a general MOS transistor manufacturing method. Therefore, detailed description is omitted.
  • an element isolation region 101, a gate oxide film 102, a gate electrode 103 made of polysilicon, a low-concentration impurity diffusion region 104 as a source region and a drain region, and implantation are implanted into a silicon substrate 100 (semiconductor substrate).
  • a protective film 105 and sidewall spacers 106 are sequentially formed.
  • a resist film 107 is formed so as to open the low concentration impurity diffusion region 104, the gate electrode 103, and the sidewall spacer 106. Fluorine ions are implanted through the implantation protective film 105 using the resist film 107 as a mask. Ion implantation conditions, an implantation energy 50 keV ⁇ 60 keV, it is preferable that the range a dose of 1 ⁇ 10 15 / cm 2 ⁇ 1 ⁇ 10 16 / cm 2.
  • the ion implantation conditions are selected from the viewpoint of efficiently integrating fluorine at the interface between the gate oxide film 102 and the silicon substrate 100.
  • this point will be described.
  • FIG. 5 is a graph showing the fluorine concentration profile in the n-type MOS transistor 33 immediately after fluorine implantation and after the final process.
  • the fluorine concentration profile is a SIMS (Secondary Ion Mass Spectrometry) profile.
  • Fluorine ions 19F + were ion-implanted at an implantation energy of 50 keV and a dose of 5 ⁇ 10 15 / cm 2 .
  • the average range (fluorine implantation range depth) was about 110 nm.
  • the film thickness of the gate electrode 103 was 200 nm.
  • the average range means an average value of the range in which each ion travels through the object when a plurality of ions are implanted into the object.
  • the ion-implanted ions finally become neutral atoms and stop, and are Gaussian distributed in the ion-implanted object. Therefore, the average range of ions indicates the peak position of the Gaussian distribution of impurities stopped in the object.
  • the peak (maximum value) of the fluorine concentration profile remains in the vicinity of the average range even after the final manufacturing process of the inverter circuit 31, and is shallower than the average range ( It is presumed that the fluorine on the gate electrode 103 side as viewed from the gate oxide film 102 diffused outward to the surface side of the gate electrode 103. On the other hand, it has been found that fluorine on the side deeper than the average range (on the side of the gate oxide film 102 as viewed from the gate electrode 103) is accumulated in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100.
  • the accumulation of fluorine in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100 indicates that dangling bonds existing at the interface are terminated by Si—F bonds.
  • the inventor further confirmed that the 1 / f noise is saturated by setting the dose amount to a range of 1 ⁇ 10 15 / cm 2 or more and 1 ⁇ 10 16 / cm 2 or less. I found out that it was well done.
  • the average range is located closer to the gate oxide film 102 than the intermediate thickness position of the gate electrode 103, and the gate oxide film is more than the peak of the fluorine concentration profile.
  • the fluorine on the 102 side can be efficiently integrated in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100.
  • the implantation energy is set in accordance with the film thickness of the gate electrode 103 so that the average range is in the range from the intermediate thickness position of the gate electrode 103 to the interface between the gate electrode 103 and the gate oxide film 102. Is desirable.
  • fluorine is implanted with a fluorine, whereby an implantation damage layer 108 is formed in the low-concentration impurity diffusion region 104 and the gate electrode 103.
  • the implantation damage layer 108 causes a defect-induced leak in the low-concentration impurity diffusion region 104, but the junction leak level of the low-concentration impurity diffusion region 104 is almost constant regardless of the presence or absence of fluorine implantation. there were. Therefore, it can be said that no particular problem occurs within the range of the implantation conditions of this embodiment.
  • the implantation protective film 109 is deposited to form the high-concentration impurity diffusion region 110.
  • an implanted ion species is selected so as to form an n-type region.
  • the implanted ion species is selected so as to form the p-type region.
  • the depth of the implantation damage layer 108 from the surface of the silicon substrate 100 exists at a position deeper than the bottom surface of the high concentration impurity diffusion region 110.
  • a silicide film 111 is formed on the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110. Thereafter, a stopper film 112 serving as an etching stopper when forming the contact plug 114 is formed by CVD (Chemical Vapor Deposition).
  • the silicide film 111 is, for example, a titanium silicide film, a cobalt silicide film, or a nickel silicide film.
  • the stopper film 112 is, for example, a silicon nitride film.
  • an interlayer insulating film 113 made of, for example, a silicon oxide film is formed on the stopper film 112. Then, a contact hole that penetrates through the interlayer insulating film 113 and reaches the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110 is formed, and a contact plug 114 is formed so as to fill the contact hole.
  • the contact plug 114 can be composed of, for example, a titanium / titanium nitride film formed on the inner wall of the contact hole and a tungsten film filling the contact hole.
  • a wiring 115 is formed over the interlayer insulating film 113, and the wiring 115 is formed so as to be electrically connected to the contact plug 114.
  • a multilayer wiring structure is formed above the wiring 115, but the description thereof is omitted.
  • the solid-state imaging device 1 uses, for example, a digital camera such as a digital video camera and a digital still camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television using the solid-state imaging device 1 as an image input device.
  • a digital camera such as a digital video camera and a digital still camera
  • an image input camera such as a surveillance camera
  • a scanner device such as a scanner device
  • facsimile device such as a surveillance camera
  • a television such as an image input device.
  • the present invention can be applied to electronic devices such as telephone devices and camera-equipped mobile phone devices.
  • 1 / f noise caused by the ADC circuit unit can be reduced by injecting fluorine into a circuit constituting the ADC circuit unit 12, in particular, an inverter circuit included in the comparator 26.
  • an inverter circuit included in the comparator 26 it is possible to realize a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus using the solid-state imaging device having low noise performance.
  • the solid-state imaging device 1 includes a pixel region 11 and an analog-digital conversion circuit unit 12 that performs analog-digital conversion on a voltage signal output from the pixel 51 arranged in the pixel region 11;
  • the analog-digital conversion circuit unit 12 includes a MOS transistor (p-type MOS transistor 32 and / or n-type) in which fluorine is integrated in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102 disposed on the silicon substrate 100. MOS transistor 33).
  • the solid-state imaging device 1 according to aspect 2 of the present invention is the above-described aspect 1, wherein the MOS transistor (p-type MOS transistor 32 and / or n-type MOS transistor 33) has a dangling bond existing at the interface terminated with fluorine. It is preferable.
  • the solid-state imaging device 1 according to Aspect 3 of the present invention is perpendicular to the silicon substrate 100 in the silicon substrate 100, the gate oxide film 102, and the gate electrode 103 disposed on the gate oxide film 102 in the above aspect 1 or 2. It is preferable that the fluorine concentration profile along any direction has a maximum value in the vicinity of the interface.
  • the average range of fluorine by ion implantation along the direction from the gate electrode 103 toward the silicon substrate 100 in the aspect 3 is the gate electrode in the gate electrode 103. It is preferable to be in the range from the intermediate thickness position of 103 to the interface between the gate electrode 103 and the gate oxide film 102.
  • the analog-digital conversion circuit unit 12 determines whether or not the level of the voltage signal output from the pixel 51 has reached the reference value.
  • the comparator (Comparator 26) is an inverter circuit 31 composed of CMOS transistors including MOS transistors (p-type MOS transistor 32 and / or n-type MOS transistor 33). Is preferred.
  • the manufacturing method of the solid-state imaging device 1 according to Aspect 6 of the present invention includes a formation step in which the gate oxide film 102 and the gate electrode 103 are formed in this order on the silicon substrate 100 in any one of the above Aspects 1 to 5. And an integration step of integrating fluorine in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102.
  • the dangling bond in which fluorine contained in the gate electrode 103 exists at the interface is terminated with fluorine in the integration step. .
  • the manufacturing method of the solid-state imaging device 1 according to aspect 8 of the present invention is the method of manufacturing the solid-state imaging device 1 according to aspect 7, in which fluorine is introduced into the gate electrode 103 by ion implantation along the direction from the gate electrode 103 toward the gate oxide film 102 in the integration step. It is preferable to do.
  • the dose amount of the ion implantation is 1 ⁇ 10 15 / cm 2 or more and 1 ⁇ 10 16 / cm 2 or less. preferable.
  • the electronic device includes the solid-state imaging device 1 according to any one of the first to fifth aspects.

Abstract

This solid-state imaging device (1) is provided with: a pixel region (11); and an analog-to-digital conversion circuit unit (12) for analog-to-digital converting voltage signals output from pixels disposed in the pixel region (11), wherein the analog-to-digital conversion circuit unit (12) includes an MOS transistor in which fluorine is accumulated in the vicinity of an interface between a semiconductor substrate and a gate oxide film disposed on the semiconductor substrate.

Description

固体撮像素子、固体撮像素子の製造方法及び電子機器Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic apparatus
　本発明は、固体撮像素子、固体撮像素子の製造方法及び電子機器に関する。 The present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus.
　ＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型イメージセンサは、汎用ＣＭＯＳプロセスである半導体形成プロセスにより生産可能であることから、安価に生産可能な固体撮像素子として注目されている。 A CMOS (Complementary Metal Oxide Semiconductor) type image sensor has been attracting attention as a solid-state imaging device that can be produced at low cost because it can be produced by a semiconductor formation process that is a general-purpose CMOS process.
　ところで、高画質静止画や動画を生成する上で、縦線ノイズ（「列毎ノイズ」とも称される。）を低減することにより電圧信号とノイズとの出力比（Ｓ／Ｎ比）を向上させることが重要な事柄となっている。 By the way, when generating high-quality still images and moving images, the output ratio (S / N ratio) between voltage signal and noise is improved by reducing vertical line noise (also called “noise per column”). It is an important matter.
　特に、ＣＭＯＳ型イメージセンサでは、暗時においても画像が真黒にならない現象として把握されるベースラインノイズを低減することが大きな課題となっている。ベースラインノイズは、画素に含まれる増幅トランジスタで発生する１／ｆノイズ（「フリッカーノイズ」とも称される。）と強い相関を持つことが知られている。ベースラインノイズを低減するためには、増幅トランジスタで発生する１／ｆノイズを低減することが重要である。 Especially, in the CMOS type image sensor, it is a big problem to reduce the baseline noise that is grasped as a phenomenon that the image does not become black even in the dark. Baseline noise is known to have a strong correlation with 1 / f noise (also referred to as “flicker noise”) generated in an amplification transistor included in a pixel. In order to reduce the baseline noise, it is important to reduce the 1 / f noise generated in the amplification transistor.
　１／ｆノイズを低減するためには、増幅トランジスタのシリコン及びゲート酸化膜に存在するダングリングボンド（未結合手）を減らすことが有効であることが知られている。ダングリングボンドを低減する一手法として、フッ素をダングリングボンドに結合させる方法がある。例えば、イオン注入法によって、増幅トランジスタにフッ素を導入することが考えられる。 In order to reduce 1 / f noise, it is known that it is effective to reduce dangling bonds (unbonded hands) existing in the silicon and gate oxide film of the amplification transistor. One method for reducing dangling bonds is to bond fluorine to dangling bonds. For example, it is conceivable to introduce fluorine into the amplification transistor by an ion implantation method.
　こうした状況を鑑みて、増幅トランジスタにフッ素を注入することにより１／ｆノイズを低減するＣＭＯＳ型イメージセンサが提案されている（特許文献１）。 In view of such a situation, a CMOS type image sensor that reduces 1 / f noise by injecting fluorine into an amplification transistor has been proposed (Patent Document 1).
日本国公開特許公報「特開２０１５－９０９７１号公報（２０１５年５月１１日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2015-90971 (published on May 11, 2015)”
　しかしながら、特許文献１のＣＭＯＳ型イメージセンサでも、１／ｆノイズの低減が十分ではないという問題がある。 However, the CMOS image sensor disclosed in Patent Document 1 also has a problem that 1 / f noise is not sufficiently reduced.
　特許文献１は、増幅トランジスタに限定的にフッ素を注入し、画素領域起因の１／ｆノイズを低減する手法であった。本発明者は、画素領域起因の１／ｆノイズの低減により固体撮像素子の性能向上が図られてきた一方で、それだけでは１／ｆノイズの低減に限界があると考えた。 Patent Document 1 is a method for reducing 1 / f noise caused by a pixel region by injecting fluorine exclusively into an amplification transistor. The present inventor has considered that the performance of the solid-state imaging device has been improved by reducing the 1 / f noise caused by the pixel region, but it has been considered that there is a limit to reducing the 1 / f noise by itself.
　そこで、別の視点から、１／ｆノイズを低減することができないか検討した。その結果、アナログ‐デジタル変換回路部起因の１／ｆノイズを低減することによって、さらなる性能向上が図られることを見出し、発明を完成させるに至った。 So, from another point of view, we examined whether 1 / f noise could be reduced. As a result, it has been found that further performance improvement can be achieved by reducing 1 / f noise caused by the analog-digital conversion circuit section, and the present invention has been completed.
　本発明の一態様は、上記問題点に鑑み、固体撮像素子の性能を向上させるさらなる方法を提供することを目的とする。 An object of one embodiment of the present invention is to provide a further method for improving the performance of a solid-state imaging device in view of the above problems.
　上記の課題を解決するために、本発明の一態様に係る固体撮像素子は、画素領域と、前記画素領域に配置された画素から出力される電圧信号をアナログ‐デジタル変換するアナログ‐デジタル変換回路部とを備え、前記アナログ‐デジタル変換回路部は、半導体基板と当該半導体基板上に配置されたゲート酸化膜との界面の近傍にフッ素が集積されているＭＯＳトランジスタを含む。 In order to solve the above-described problem, a solid-state imaging device according to an aspect of the present invention includes a pixel region and an analog-digital conversion circuit that performs analog-digital conversion on a voltage signal output from the pixel disposed in the pixel region. The analog-digital conversion circuit unit includes a MOS transistor in which fluorine is integrated in the vicinity of the interface between the semiconductor substrate and the gate oxide film disposed on the semiconductor substrate.
　本発明の一態様によれば、固体撮像素子において、これまで到底達し得なかった性能が得られるという効果を奏する。 According to one aspect of the present invention, the solid-state imaging device has an effect that a performance that has never been achieved can be obtained.
本発明の一実施形態に係る固体撮像素子の概略構成を示す平面図である。It is a top view which shows schematic structure of the solid-state image sensor which concerns on one Embodiment of this invention. 上記固体撮像素子に含まれるＡＤＣ回路部の概略構成を示す平面図である。It is a top view which shows schematic structure of the ADC circuit part contained in the said solid-state image sensor. 上記ＡＤＣ回路部に含まれるＣｏｍｐａｒａｔｏｒの構成を示す回路図である。It is a circuit diagram which shows the structure of the Comparator contained in the said ADC circuit part. （ａ）～（ｅ）は、上記Ｃｏｍｐａｒａｔｏｒに含まれるｎ型ＭＯＳトランジスタの製造工程を示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing process of the n-type MOS transistor contained in the said comparator. フッ素注入直後及びプロセス最終処理後の各々における、上記ｎ型ＭＯＳトランジスタ内のフッ素濃度プロファイルを示すグラフ図である。It is a graph which shows the fluorine concentration profile in the said n-type MOS transistor in each after a fluorine injection | pouring and after a process final process.
　以下、本発明の実施の形態について、詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail.
　以下の説明に用いる図面では、同一の部分には同一の符号を付してある。それらの名称及び機能も同一である。したがって、それらについての詳細な説明は繰り返さない。 In the drawings used for the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.
　図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なるものである。図面相互間においても互いの寸法の関係や比率が異なる部分が含まれている。 The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Also included in the drawings are portions having different dimensional relationships and ratios.
　（固体撮像素子１の構成）
　本発明の一実施形態に係る固体撮像素子１は、ＣＭＯＳ型イメージセンサである。ＣＭＯＳ型イメージセンサは、一般に、受光領域と、フローティングディフュージョン部（ＦＤ部）と、アナログ‐デジタル変換回路部（Ａｎａｌｏｇ　Ｄｉｇｉｔａｌ　Ｃｏｎｖｅｒｔｅｒ、以下、「ＡＤＣ回路部」と称する。）とを有する。受光領域は、画像光の光電変換を行い、フローティングディフュージョン部は、光電変換により得られた信号電荷を電圧信号に変換し、ＡＤＣ回路部は、変換された信号電荷をアナログ‐デジタル変換する。受光領域、フローティングディフュージョン部及びＡＤＣ回路部は共通基板上に設けられる。 (Configuration of the solid-state imaging device 1)
The solid-state imaging device 1 according to an embodiment of the present invention is a CMOS image sensor. A CMOS type image sensor generally has a light receiving region, a floating diffusion part (FD part), and an analog-digital conversion circuit part (Analog Digital Converter, hereinafter referred to as “ADC circuit part”). The light receiving region performs photoelectric conversion of image light, the floating diffusion unit converts signal charges obtained by the photoelectric conversion into voltage signals, and the ADC circuit unit performs analog-digital conversion on the converted signal charges. The light receiving region, the floating diffusion portion, and the ADC circuit portion are provided on a common substrate.
　受光領域には、光照射により電荷を発生する複数の受光部としてのフォトダイオードが画素毎に設けられており、また、ＦＤ部では、受光領域の各受光部で発生した電荷が信号電荷として画素から読み出される。読み出された信号電荷は画素内にて、アナログ信号である電圧信号に変換される。電圧信号は画素毎に信号配線を介して読み出され、ＡＤＣ回路部に入力される。ＡＤＣ回路部は、入力された電圧信号をデジタル信号に変換する。 In the light receiving region, a plurality of photodiodes as light receiving portions that generate charges by light irradiation are provided for each pixel. In the FD portion, charges generated in each light receiving portion of the light receiving region are signal charges. Read from. The read signal charge is converted into a voltage signal which is an analog signal in the pixel. The voltage signal is read out for each pixel through the signal wiring and input to the ADC circuit unit. The ADC circuit unit converts the input voltage signal into a digital signal.
　以下、固体撮像素子１について、図１に基づいて具体的に説明する。図１は、本発明の一実施形態に係る固体撮像素子１の概略構成を示す平面図である。 Hereinafter, the solid-state imaging device 1 will be specifically described with reference to FIG. FIG. 1 is a plan view showing a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention.
　図１に示すように、固体撮像素子１は、画素領域１１と、ＡＤＣ回路部１２と、周辺回路部１３とを備える。 As shown in FIG. 1, the solid-state imaging device 1 includes a pixel region 11, an ADC circuit unit 12, and a peripheral circuit unit 13.
　画素領域１１は、２次元マトリックス状（アレイ状）に複数の画素５１（図２を参照）が配列されており、方形状の撮像領域を構成する。画素領域１１の周囲には、ＡＤＣ回路部１２及び周辺回路部１３が配置される。ＡＤＣ回路部１２は、画素領域１１の各画素から出力される電圧信号を画素領域１１の列毎にアナログ‐デジタル変換する。周辺回路部１３は、ＡＤＣ回路部１２によりアナログ‐デジタル変換された電圧信号をロジック処理することにより撮像画像を生成する。 The pixel region 11 includes a plurality of pixels 51 (see FIG. 2) arranged in a two-dimensional matrix (array), and forms a rectangular imaging region. Around the pixel region 11, an ADC circuit unit 12 and a peripheral circuit unit 13 are arranged. The ADC circuit unit 12 performs analog-to-digital conversion on the voltage signal output from each pixel in the pixel region 11 for each column in the pixel region 11. The peripheral circuit unit 13 generates a captured image by performing logic processing on the voltage signal analog-digital converted by the ADC circuit unit 12.
　（ＡＤＣ回路部１２の構成）
　図２は、ＡＤＣ回路部１２の概略構成を示す平面図である。 (Configuration of ADC circuit unit 12)
FIG. 2 is a plan view showing a schematic configuration of the ADC circuit unit 12.
　図２に示すように、画素領域１１には、複数の画素５１が２次元マトリックス状に配列されたＳｅｎｓｏｒ　Ａｒｒａｙ５０が配置されている。ＡＤＣ回路部１２は、画素領域１１に配置されたＳｅｎｓｏｒ　Ａｒｒａｙ５０の各画素５１から出力される電圧信号を列毎にアナログ‐デジタル変換する。 As shown in FIG. 2, a sensor array 50 in which a plurality of pixels 51 are arranged in a two-dimensional matrix is arranged in the pixel region 11. The ADC circuit unit 12 performs analog-digital conversion of the voltage signal output from each pixel 51 of the Sensor Array 50 arranged in the pixel region 11 for each column.
　具体的には、ＡＤＣ回路部１２は、ＲＡＭＰ２２と、画素領域１１（より具体的には、Ｓｅｎｓｏｒ　Ａｒｒａｙ５０）の各列に対応し、各列毎に設けられた、複数のＣｏｌｕｍｎＡ／Ｄ２３と、Ｇｒａｙ　Ｃｏｄｅ　Ｃｏｕｎｔｅｒ２４とを含む。なお、Ｇｒａｙ　Ｃｏｄｅ　Ｃｏｕｎｔｅｒ２４は、本実施形態とは直接関係しない部材であるので、説明を省略するが、公知のものと同様であると理解されてよい。 Specifically, the ADC circuit unit 12 corresponds to each column of the RAMP 22 and the pixel region 11 (more specifically, Sensor Array 50), and a plurality of Column A / Ds 23 provided for each column, and Gray. Including Code Counter24. The Gray Code Counter 24 is a member that is not directly related to the present embodiment, so that the description thereof is omitted, but it may be understood that it is the same as a known one.
　各ＣｏｌｕｍｎＡ／Ｄ２３には、自身に対応する画素領域１１の列に含まれる画素５１から出力される電圧信号が、Ｃａｐａｃｉｔｏｒ２５を介して、入力される。Ｃｏｍｐａｒａｔｏｒ２６（比較器）は、入力された電圧信号と、ＲＡＭＰ２２により生成されたＲＡＭＰ波形（基準値）とを比較し、その比較結果をＷ－Ｌａｔｃｈ２７に出力する。 A voltage signal output from the pixel 51 included in the column of the pixel region 11 corresponding to itself is input to each Column A / D 23 via the Capacitor 25. The comparator 26 (comparator) compares the input voltage signal with the RAMP waveform (reference value) generated by the RAMP 22 and outputs the comparison result to the W-Latch 27.
　（Ｃｏｍｐａｒａｔｏｒ２６の構成）
　図３は、Ｃｏｍｐａｒａｔｏｒ２６の構成を示す回路図である。図３に示すように、Ｃｏｍｐａｒａｔｏｒ２６は、ｐ型ＭＯＳトランジスタ３２及びｎ型ＭＯＳトランジスタ３３から構成されるＣＭＯＳトランジスタであるインバータ回路３１を含む。 (Configuration of Comparator 26)
FIG. 3 is a circuit diagram showing a configuration of the comparator 26. As shown in FIG. 3, the comparator 26 includes an inverter circuit 31 that is a CMOS transistor including a p-type MOS transistor 32 and an n-type MOS transistor 33.
　以下、ｎ型ＭＯＳトランジスタ３３を例として、インバータ回路３１の製造方法について説明する。図４の（ａ）～（ｅ）は、ｎ型ＭＯＳトランジスタ３３の製造工程を示す断面図である。なお、図４の（ａ）～（ｅ）に示す製造工程は、一般的なＭＯＳトランジスタの製造方法を使用している。このため、詳細説明は省略する。 Hereinafter, a method for manufacturing the inverter circuit 31 will be described using the n-type MOS transistor 33 as an example. 4A to 4E are cross-sectional views showing the manufacturing process of the n-type MOS transistor 33. FIG. The manufacturing steps shown in FIGS. 4A to 4E use a general MOS transistor manufacturing method. Therefore, detailed description is omitted.
　図４の（ａ）において、シリコン基板１００（半導体基板）に、素子分離領域１０１、ゲート酸化膜１０２、ポリシリコンからなるゲート電極１０３、ソース領域及びドレイン領域である低濃度不純物拡散領域１０４、注入保護膜１０５及びサイドウォールスペーサ１０６を順次形成する。 4A, an element isolation region 101, a gate oxide film 102, a gate electrode 103 made of polysilicon, a low-concentration impurity diffusion region 104 as a source region and a drain region, and implantation are implanted into a silicon substrate 100 (semiconductor substrate). A protective film 105 and sidewall spacers 106 are sequentially formed.
　次に、図４の（ｂ）において、低濃度不純物拡散領域１０４、ゲート電極１０３及びサイドウォールスペーサ１０６を開口するようにレジスト膜１０７を形成する。レジスト膜１０７をマスクとして注入保護膜１０５を介してフッ素をイオン注入する。イオン注入条件は、注入エネルギーを５０ｋｅＶ～６０ｋｅＶ、ドーズ量を１×１０１５／ｃｍ２～１×１０１６／ｃｍ２の範囲とすることが望ましい。 Next, in FIG. 4B, a resist film 107 is formed so as to open the low concentration impurity diffusion region 104, the gate electrode 103, and the sidewall spacer 106. Fluorine ions are implanted through the implantation protective film 105 using the resist film 107 as a mask. Ion implantation conditions, an implantation energy 50 keV ~ 60 keV, it is preferable that the range a dose of 1 × 10 15 / cm 2 ~ 1 × 10 16 / cm 2.
　ここで注目すべきは、ゲート酸化膜１０２とシリコン基板１００との界面にフッ素を効率的に集積するという観点から、上記イオン注入条件を選定する点にある。以下、この点について説明する。 It should be noted here that the ion implantation conditions are selected from the viewpoint of efficiently integrating fluorine at the interface between the gate oxide film 102 and the silicon substrate 100. Hereinafter, this point will be described.
　図５は、フッ素注入直後及びプロセス最終処理後の各々における、ｎ型ＭＯＳトランジスタ３３内のフッ素濃度プロファイルを示すグラフ図である。フッ素濃度プロファイルは、ＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）プロファイルである。フッ素イオン１９Ｆ＋を、注入エネルギーを５０ｋｅＶ、ドーズ量を５×１０１５／ｃｍ２、でイオン注入した。平均飛程（フッ素注入飛程深さ）は約１１０ｎｍであった。ゲート電極１０３の膜厚は２００ｎｍであった。 FIG. 5 is a graph showing the fluorine concentration profile in the n-type MOS transistor 33 immediately after fluorine implantation and after the final process. The fluorine concentration profile is a SIMS (Secondary Ion Mass Spectrometry) profile. Fluorine ions 19F + were ion-implanted at an implantation energy of 50 keV and a dose of 5 × 10 15 / cm 2 . The average range (fluorine implantation range depth) was about 110 nm. The film thickness of the gate electrode 103 was 200 nm.
　なお、平均飛程とは、ある物体中に複数のイオンがイオン注入された時、それぞれのイオンが物体内を進行する飛程の平均値のことをいう。イオン注入されたイオンは最終的に中性の原子となり停止し被イオン注入物体内でガウス分布する。したがって、イオンの平均飛程とは、物体内に停止した不純物のガウス分布のピーク位置を指すことになる。 Note that the average range means an average value of the range in which each ion travels through the object when a plurality of ions are implanted into the object. The ion-implanted ions finally become neutral atoms and stop, and are Gaussian distributed in the ion-implanted object. Therefore, the average range of ions indicates the peak position of the Gaussian distribution of impurities stopped in the object.
　図５に示すように、フッ素濃度プロファイルのピーク（最大値）は、インバータ回路３１の最終製造工程経過後であっても、平均飛程付近に残存しており、平均飛程よりも浅い側（ゲート酸化膜１０２から見てゲート電極１０３側）のフッ素は、ゲート電極１０３の表面側へ外方拡散したと推定される。一方、平均飛程よりも深い側（ゲート電極１０３から見てゲート酸化膜１０２側）のフッ素は、ゲート酸化膜１０２とシリコン基板１００との界面の近傍に集積していることが判明した。 As shown in FIG. 5, the peak (maximum value) of the fluorine concentration profile remains in the vicinity of the average range even after the final manufacturing process of the inverter circuit 31, and is shallower than the average range ( It is presumed that the fluorine on the gate electrode 103 side as viewed from the gate oxide film 102 diffused outward to the surface side of the gate electrode 103. On the other hand, it has been found that fluorine on the side deeper than the average range (on the side of the gate oxide film 102 as viewed from the gate electrode 103) is accumulated in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100.
　ゲート酸化膜１０２とシリコン基板１００との界面の近傍にフッ素が集積していることは、当該界面に存在するダングリングボンドをＳｉ－Ｆ結合で終端していることを示すものである。本発明者は、さらに、ドーズ量を、１×１０１５／ｃｍ２以上、１×１０１６／ｃｍ２以下の範囲とすることにより、１／ｆノイズが飽和することを確認し、終端性が充分に行われていることを見出した。 The accumulation of fluorine in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100 indicates that dangling bonds existing at the interface are terminated by Si—F bonds. The inventor further confirmed that the 1 / f noise is saturated by setting the dose amount to a range of 1 × 10 15 / cm 2 or more and 1 × 10 16 / cm 2 or less. I found out that it was well done.
　したがって、注入エネルギーを、５０ｋｅＶ以上、６０ｋｅＶ以下の範囲とすることにより、平均飛程がゲート電極１０３の中間厚位置よりもゲート酸化膜１０２側に位置し、フッ素濃度プロファイルのピークよりもゲート酸化膜１０２側のフッ素を効率的にゲート酸化膜１０２とシリコン基板１００との界面の近傍に集積することができる。 Therefore, by setting the implantation energy in the range of 50 keV or more and 60 keV or less, the average range is located closer to the gate oxide film 102 than the intermediate thickness position of the gate electrode 103, and the gate oxide film is more than the peak of the fluorine concentration profile. The fluorine on the 102 side can be efficiently integrated in the vicinity of the interface between the gate oxide film 102 and the silicon substrate 100.
　ただし、注入エネルギーが６０ｋｅＶを超えると注入時のダメージがゲート酸化膜１０２に影響を与えるようになり、逆に、ノイズが悪化する傾向が見えた。よって、ゲート電極１０３の膜厚に応じて、平均飛程がゲート電極１０３の中間厚位置から、ゲート電極１０３とゲート酸化膜１０２との界面までの範囲にあるように、注入エネルギーを設定することが望ましい。 However, when the implantation energy exceeds 60 keV, the damage during the implantation affects the gate oxide film 102, and conversely, the noise tends to deteriorate. Therefore, the implantation energy is set in accordance with the film thickness of the gate electrode 103 so that the average range is in the range from the intermediate thickness position of the gate electrode 103 to the interface between the gate electrode 103 and the gate oxide film 102. Is desirable.
　また、フッ素は、図４の（ｂ）に示したように、フッ素注入により、低濃度不純物拡散領域１０４及びゲート電極１０３には、注入ダメージ層１０８が形成される。注入ダメージ層１０８は、低濃度不純物拡散領域１０４の欠陥起因リークを招くことが懸念点として挙げられたが、フッ素注入の有無によらず、低濃度不純物拡散領域１０４の接合リークレベルはほぼ一定であった。したがって、本実施形態の注入条件の範囲では特に問題は発生しないものといえる。 Further, as shown in FIG. 4B, fluorine is implanted with a fluorine, whereby an implantation damage layer 108 is formed in the low-concentration impurity diffusion region 104 and the gate electrode 103. It has been pointed out that the implantation damage layer 108 causes a defect-induced leak in the low-concentration impurity diffusion region 104, but the junction leak level of the low-concentration impurity diffusion region 104 is almost constant regardless of the presence or absence of fluorine implantation. there were. Therefore, it can be said that no particular problem occurs within the range of the implantation conditions of this embodiment.
　再び、図４に戻ると、図４の（ｃ）において、注入保護膜１０９を堆積し、高濃度不純物拡散領域１１０を形成する。高濃度不純物拡散領域１１０の形成においては、ｎ型領域を形成するよう注入イオン種を選択する。なお、ｐ型ＭＯＳトランジスタ３２を製造する場合であればｐ型領域を形成するよう注入イオン種を選択することはいうまでもない。また、注入ダメージ層１０８のシリコン基板１００の表面からの深さは、高濃度不純物拡散領域１１０の底面よりも深い位置に存在することになる。 Returning to FIG. 4 again, in FIG. 4C, the implantation protective film 109 is deposited to form the high-concentration impurity diffusion region 110. In the formation of the high-concentration impurity diffusion region 110, an implanted ion species is selected so as to form an n-type region. Needless to say, in the case of manufacturing the p-type MOS transistor 32, the implanted ion species is selected so as to form the p-type region. Further, the depth of the implantation damage layer 108 from the surface of the silicon substrate 100 exists at a position deeper than the bottom surface of the high concentration impurity diffusion region 110.
　次に、図４の（ｄ）において、注入保護膜１０９を除去した後、ゲート電極１０３、低濃度不純物拡散領域１０４及び高濃度不純物拡散領域１１０上にシリサイド膜１１１を形成する。その後、コンタクトプラグ１１４の形成時のエッチングストッパとなるストッパ膜１１２をＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）により形成する。なお、シリサイド膜１１１は、例えば、チタンシリサイド膜、コバルトシリサイド膜又はニッケルシリサイド膜である。ストッパ膜１１２は、例えば、窒化シリコン膜である。 Next, in FIG. 4D, after removing the implantation protective film 109, a silicide film 111 is formed on the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110. Thereafter, a stopper film 112 serving as an etching stopper when forming the contact plug 114 is formed by CVD (Chemical Vapor Deposition). The silicide film 111 is, for example, a titanium silicide film, a cobalt silicide film, or a nickel silicide film. The stopper film 112 is, for example, a silicon nitride film.
　次に、図４の（ｅ）において、ストッパ膜１１２上に、例えば、酸化シリコン膜からなる層間絶縁膜１１３を形成する。そして、層間絶縁膜１１３を貫通して、ゲート電極１０３、低濃度不純物拡散領域１０４及び高濃度不純物拡散領域１１０に到達するコンタクトホールが形成され、コンタクトホールを埋め込むようにコンタクトプラグ１１４が形成される。コンタクトプラグ１１４は、例えば、コンタクトホールの内壁に形成されたチタン／窒化チタン膜と、コンタクトホールを埋め込むタングステン膜とから構成することができる。層間絶縁膜１１３上には、配線１１５が形成され、配線１１５は、コンタクトプラグ１１４と電気的に接続されるように形成される。配線１１５の上方には、多層配線構造が形成されるが、その説明は省略する。 Next, in FIG. 4E, an interlayer insulating film 113 made of, for example, a silicon oxide film is formed on the stopper film 112. Then, a contact hole that penetrates through the interlayer insulating film 113 and reaches the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110 is formed, and a contact plug 114 is formed so as to fill the contact hole. . The contact plug 114 can be composed of, for example, a titanium / titanium nitride film formed on the inner wall of the contact hole and a tungsten film filling the contact hole. A wiring 115 is formed over the interlayer insulating film 113, and the wiring 115 is formed so as to be electrically connected to the contact plug 114. A multilayer wiring structure is formed above the wiring 115, but the description thereof is omitted.
　（電子機器）
　固体撮像素子１は、固体撮像素子１を画像入力デバイスとして撮像部に用いた、例えばデジタルビデオカメラおよびデジタルスチルカメラなどのデジタルカメラや監視カメラなどの画像入力カメラ、スキャナ装置、ファクシミリ装置、テレビジョン電話装置、カメラ付き携帯電話装置などの電子機器に適用可能である。 (Electronics)
The solid-state imaging device 1 uses, for example, a digital camera such as a digital video camera and a digital still camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television using the solid-state imaging device 1 as an image input device. The present invention can be applied to electronic devices such as telephone devices and camera-equipped mobile phone devices.
　（本実施形態の効果）
　本実施形態によれば、ＡＤＣ回路部１２を構成する回路、特に、Ｃｏｍｐａｒａｔｏｒ２６に含まれるインバータ回路へフッ素注入することにより、ＡＤＣ回路部起因の１／ｆノイズを低減することができる。これにより、固体撮像素子及びその製造方法、並びに、低ノイズ性能を有する固体撮像素子を用いた電子機器を実現することができる。 (Effect of this embodiment)
According to the present embodiment, 1 / f noise caused by the ADC circuit unit can be reduced by injecting fluorine into a circuit constituting the ADC circuit unit 12, in particular, an inverter circuit included in the comparator 26. Thereby, it is possible to realize a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus using the solid-state imaging device having low noise performance.
　（まとめ）
　本発明の態様１に係る固体撮像素子１は、画素領域１１と、画素領域１１に配置された画素５１から出力される電圧信号をアナログ‐デジタル変換するアナログ‐デジタル変換回路部１２とを備え、アナログ‐デジタル変換回路部１２は、シリコン基板１００とシリコン基板１００上に配置されたゲート酸化膜１０２との界面の近傍にフッ素が集積されているＭＯＳトランジスタ（ｐ型ＭＯＳトランジスタ３２及び／又はｎ型ＭＯＳトランジスタ３３）を含む。 (Summary)
The solid-state imaging device 1 according to the first aspect of the present invention includes a pixel region 11 and an analog-digital conversion circuit unit 12 that performs analog-digital conversion on a voltage signal output from the pixel 51 arranged in the pixel region 11; The analog-digital conversion circuit unit 12 includes a MOS transistor (p-type MOS transistor 32 and / or n-type) in which fluorine is integrated in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102 disposed on the silicon substrate 100. MOS transistor 33).
　上記構成によれば、アナログ‐デジタル変換回路部起因の１／ｆノイズを低減することによって、さらなる性能向上が図られる。 According to the above configuration, further performance improvement can be achieved by reducing 1 / f noise caused by the analog-digital conversion circuit section.
　本発明の態様２に係る固体撮像素子１は、上記態様１において、ＭＯＳトランジスタ（ｐ型ＭＯＳトランジスタ３２及び／又はｎ型ＭＯＳトランジスタ３３）は、前記界面に存在するダングリングボンドがフッ素により終端されていることが好ましい。 The solid-state imaging device 1 according to aspect 2 of the present invention is the above-described aspect 1, wherein the MOS transistor (p-type MOS transistor 32 and / or n-type MOS transistor 33) has a dangling bond existing at the interface terminated with fluorine. It is preferable.
　本発明の態様３に係る固体撮像素子１は、上記態様１又は２において、シリコン基板１００、ゲート酸化膜１０２及びゲート酸化膜１０２上に配置されたゲート電極１０３における、シリコン基板１００に対して垂直な方向に沿ったフッ素濃度プロファイルは、前記界面の近傍において最大値をとることが好ましい。 The solid-state imaging device 1 according to Aspect 3 of the present invention is perpendicular to the silicon substrate 100 in the silicon substrate 100, the gate oxide film 102, and the gate electrode 103 disposed on the gate oxide film 102 in the above aspect 1 or 2. It is preferable that the fluorine concentration profile along any direction has a maximum value in the vicinity of the interface.
　本発明の態様４に係る固体撮像素子１は、上記態様３において、ゲート電極１０３からシリコン基板１００に向う方向に沿ったイオン注入によるフッ素の平均飛程は、ゲート電極１０３の内部における、ゲート電極１０３の中間厚位置からゲート電極１０３とゲート酸化膜１０２との界面までの範囲にあることが好ましい。 In the solid-state imaging device 1 according to the aspect 4 of the present invention, the average range of fluorine by ion implantation along the direction from the gate electrode 103 toward the silicon substrate 100 in the aspect 3 is the gate electrode in the gate electrode 103. It is preferable to be in the range from the intermediate thickness position of 103 to the interface between the gate electrode 103 and the gate oxide film 102.
　本発明の態様５に係る固体撮像素子１は、上記態様１～４のいずれかにおいて、アナログ‐デジタル変換回路部１２は、画素５１から出力される電圧信号のレベルが基準値に達しているか否かを判断する比較器（Ｃｏｍｐａｒａｔｏｒ２６）を含み、比較器（Ｃｏｍｐａｒａｔｏｒ２６）は、ＭＯＳトランジスタ（ｐ型ＭＯＳトランジスタ３２及び／又はｎ型ＭＯＳトランジスタ３３）を含むＣＭＯＳトランジスタから構成されたインバータ回路３１であることが好ましい。 In the solid-state imaging device 1 according to aspect 5 of the present invention, in any of the above aspects 1 to 4, the analog-digital conversion circuit unit 12 determines whether or not the level of the voltage signal output from the pixel 51 has reached the reference value. The comparator (Comparator 26) is an inverter circuit 31 composed of CMOS transistors including MOS transistors (p-type MOS transistor 32 and / or n-type MOS transistor 33). Is preferred.
　本発明の態様６に係る固体撮像素子１の製造方法は、上記態様１～５のいずれかにおいて、シリコン基板１００上に、ゲート酸化膜１０２及びゲート電極１０３を、この順で形成する形成工程と、シリコン基板１００とゲート酸化膜１０２との界面の近傍にフッ素を集積する集積工程とを含む。 The manufacturing method of the solid-state imaging device 1 according to Aspect 6 of the present invention includes a formation step in which the gate oxide film 102 and the gate electrode 103 are formed in this order on the silicon substrate 100 in any one of the above Aspects 1 to 5. And an integration step of integrating fluorine in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102.
　本発明の態様７に係る固体撮像素子１の製造方法は、上記態様６において、前記集積工程において、ゲート電極１０３に含まれるフッ素を前記界面に存在するダングリングボンドをフッ素で終端することが好ましい。 In the manufacturing method of the solid-state imaging device 1 according to Aspect 7 of the present invention, in the Aspect 6, the dangling bond in which fluorine contained in the gate electrode 103 exists at the interface is terminated with fluorine in the integration step. .
　本発明の態様８に係る固体撮像素子１の製造方法は、上記態様７において、前記集積工程において、ゲート電極１０３からゲート酸化膜１０２に向う方向に沿ったイオン注入によりゲート電極１０３にフッ素を導入することが好ましい。 The manufacturing method of the solid-state imaging device 1 according to aspect 8 of the present invention is the method of manufacturing the solid-state imaging device 1 according to aspect 7, in which fluorine is introduced into the gate electrode 103 by ion implantation along the direction from the gate electrode 103 toward the gate oxide film 102 in the integration step. It is preferable to do.
　本発明の態様９に係る固体撮像素子１の製造方法は、上記態様８において、前記イオン注入のドーズ量は、１×１０１５／ｃｍ２以上、１×１０１６／ｃｍ２以下であることが好ましい。 In the manufacturing method of the solid-state imaging device 1 according to aspect 9 of the present invention, in the aspect 8, the dose amount of the ion implantation is 1 × 10 15 / cm 2 or more and 1 × 10 16 / cm 2 or less. preferable.
　本発明の態様１０に係る電子機器は、上記態様１～５のいずれかにおいて、固体撮像素子１を備える。 The electronic device according to the tenth aspect of the present invention includes the solid-state imaging device 1 according to any one of the first to fifth aspects.
　以上のように、本発明の好ましい実施形態を用いて本発明を例示してきたが、本発明は、この実施形態に限定して解釈されるべきものではない。本発明は、特許請求の範囲によってのみその範囲が解釈されるべきであることが理解される。当業者は、本発明の具体的な好ましい実施形態の記載から、本発明の記載および技術常識に基づいて等価な範囲を実施することができることが理解される。本明細書において引用した特許、特許出願および文献は、その内容自体が具体的に本明細書に記載されているのと同様にその内容が本明細書に対する参考として援用されるべきであることが理解される。 As described above, the present invention has been exemplified using the preferred embodiment of the present invention, but the present invention should not be construed as being limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.
　１　固体撮像素子
　１１　画素領域
　１２　アナログ‐デジタル変換回路部
　１３　周辺回路部
　２２　ＲＡＭＰ
　２３　ＣｏｌｕｍｎＡ／Ｄ
　２４　Ｇｒａｙ　Ｃｏｄｅ　Ｃｏｕｎｔｅｒ
　２５　Ｃａｐａｃｉｔｏｒ
　２６　Ｃｏｍｐａｒａｔｏｒ（比較器）
　２７　Ｗ－Ｌａｔｃｈ
　３１　インバータ回路
　３２　ｐ型ＭＯＳトランジスタ
　３３　ｎ型ＭＯＳトランジスタ
　５０　Ｓｅｎｓｏｒ　Ａｒｒａｙ
　５１　画素
　１００　シリコン基板（半導体基板）
　１０１　素子分離領域
　１０２　ゲート酸化膜
　１０３　ゲート電極
　１０４　低濃度不純物拡散領域
　１０５　注入保護膜
　１０６　サイドウォールスペーサ
　１０７　レジスト膜
　１０８　注入ダメージ層
　１０９　注入保護膜
　１１０　高濃度不純物拡散領域
　１１１　シリサイド膜
　１１２　ストッパ層
　１１３　層間絶縁膜
　１１４　コンタクトプラグ
　１１５　配線 DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 11 Pixel area 12 Analog-digital conversion circuit part 13 Peripheral circuit part 22 RAMP
23 Column A / D
24 Gray Code Counter
25 Capacitor
26 Comparator
27 W-Latch
31 Inverter circuit 32 p-type MOS transistor 33 n-type MOS transistor 50 Sensor Array
51 pixels 100 silicon substrate (semiconductor substrate)
DESCRIPTION OF SYMBOLS 101 Element isolation region 102 Gate oxide film 103 Gate electrode 104 Low concentration impurity diffusion region 105 Implantation protection film 106 Side wall spacer 107 Resist film 108 Injection damage layer 109 Injection protection film 110 High concentration impurity diffusion region 111 Silicide film 112 Stopper layer 113 Interlayer Insulating film 114 Contact plug 115 Wiring

Claims (10)

  1. 　画素領域と、
    　前記画素領域に配置された画素から出力される電圧信号をアナログ‐デジタル変換するアナログ‐デジタル変換回路部と
    を備え、
    　前記アナログ‐デジタル変換回路部は、半導体基板と当該半導体基板上に配置されたゲート酸化膜との界面の近傍にフッ素が集積されているＭＯＳトランジスタを含むことを特徴とする固体撮像素子。     A pixel area;
    An analog-digital conversion circuit unit that performs analog-digital conversion on a voltage signal output from a pixel arranged in the pixel region;
    The analog-digital conversion circuit section includes a MOS transistor in which fluorine is integrated in the vicinity of an interface between a semiconductor substrate and a gate oxide film disposed on the semiconductor substrate.
  2. 　前記ＭＯＳトランジスタは、前記界面に存在するダングリングボンドがフッ素により終端されていることを特徴とする請求項１に記載の固体撮像素子。 The solid-state imaging device according to claim 1, wherein the MOS transistor has a dangling bond existing at the interface terminated with fluorine.
  3. 　前記半導体基板、前記ゲート酸化膜及び前記ゲート酸化膜上に配置されたゲート電極における、前記半導体基板に対して垂直な方向に沿ったフッ素濃度プロファイルは、前記界面の近傍において最大値をとることを特徴とする請求項１又は２に記載の固体撮像素子。 The fluorine concentration profile along the direction perpendicular to the semiconductor substrate in the semiconductor substrate, the gate oxide film, and the gate electrode disposed on the gate oxide film has a maximum value in the vicinity of the interface. The solid-state imaging device according to claim 1 or 2, characterized in that
  4. 　前記ゲート電極から前記半導体基板に向う方向に沿ったイオン注入によるフッ素の平均飛程は、前記ゲート電極の内部における、前記ゲート電極の中間厚位置から前記ゲート電極と前記ゲート酸化膜との界面までの範囲にあることを特徴とする請求項３に記載の固体撮像素子。 The average range of fluorine by ion implantation along the direction from the gate electrode to the semiconductor substrate is from the intermediate thickness position of the gate electrode to the interface between the gate electrode and the gate oxide film inside the gate electrode. The solid-state imaging device according to claim 3, wherein the solid-state imaging device is in the range of.
  5. 　前記アナログ‐デジタル変換回路部は、前記画素から出力される電圧信号のレベルが基準値に達しているか否かを判断する比較器を含み、
    　前記比較器は、前記ＭＯＳトランジスタを含むＣＭＯＳトランジスタから構成されたインバータ回路であることを特徴とする請求項１から４のいずれか１項に記載の固体撮像素子。     The analog-digital conversion circuit unit includes a comparator that determines whether a level of a voltage signal output from the pixel reaches a reference value,
    5. The solid-state imaging device according to claim 1, wherein the comparator is an inverter circuit including a CMOS transistor including the MOS transistor. 6.
  6. 　請求項１から５のいずれか１項に記載の固体撮像素子の製造方法であって、
    　半導体基板上に、ゲート酸化膜及びゲート電極を、この順で形成する形成工程と、
    　前記半導体基板と前記ゲート酸化膜との界面の近傍にフッ素を集積する集積工程と
    を含むことを特徴とする固体撮像素子の製造方法。     It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 5,
    Forming a gate oxide film and a gate electrode in this order on a semiconductor substrate;
    A solid-state imaging device manufacturing method comprising: an integration step of integrating fluorine in the vicinity of an interface between the semiconductor substrate and the gate oxide film.
  7. 　前記集積工程において、前記ゲート電極に含まれるフッ素を前記界面の近傍まで熱拡散させて前記界面に存在するダングリングボンドをフッ素で終端することを特徴とする請求項６に記載の固体撮像素子の製造方法。 The solid-state imaging device according to claim 6, wherein in the integration step, fluorine contained in the gate electrode is thermally diffused to the vicinity of the interface, and dangling bonds existing at the interface are terminated with fluorine. Production method.
  8. 　前記集積工程において、前記ゲート電極から前記ゲート酸化膜に向う方向に沿ったイオン注入により前記ゲート電極にフッ素を導入することを特徴とする請求項７に記載の固体撮像素子の製造方法。 The method of manufacturing a solid-state imaging device according to claim 7, wherein in the integration step, fluorine is introduced into the gate electrode by ion implantation along a direction from the gate electrode toward the gate oxide film.
  9. 　前記イオン注入のドーズ量は、１×１０１５／ｃｍ２以上、１×１０１６／ｃｍ２以下であることを特徴とする請求項８に記載の固体撮像素子の製造方法。 9. The method of manufacturing a solid-state imaging device according to claim 8, wherein the dose amount of the ion implantation is 1 × 10 15 / cm 2 or more and 1 × 10 16 / cm 2 or less.
  10. 　請求項１～５のいずれか１項に記載の固体撮像素子を備える電子機器。 An electronic device comprising the solid-state imaging device according to any one of claims 1 to 5.
PCT/JP2018/008806 2017-05-22 2018-03-07 Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device WO2018216309A1 (en)

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