CN103441763A - Infrared focal-plane array and analog-digital converter of reading circuit thereof - Google Patents
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Abstract
The invention discloses an analog-digital converter of a reading circuit of an infrared focal-plane array. The analog-digital converter of the reading circuit of the infrared focal-plane array comprises a comparator, a bias circuit, a linear ramp generator, a latch and a nonlinear compensated counter, wherein the nonlinear compensated counter carries out counting on a counting clock sequence of unequal cycles, the counting clock sequence of the unequal cycles comprises at least two counting clock subsequences, and the counting clock cycles in all the counting clock subsequences are different. According to the analog-digital converter, due to the fact that the nonlinear compensated counter is used, compensation can be effectively carried out on the nonlinearity of digital output and the nonlinearity of target temperature, output nonlinearity caused by nonlinear radiation is eliminated, linearity of the response ratio of voltages is improved, and the response range of the linear temperature is expanded. Further, due to the fact that the nonlinear compensated counter of the analog-digital converter has the function of being adjustable in starting time, the availability of numeric codes is improved, and the effective resolution ratio is improved.
Description
Technical field
The present invention relates to the non-refrigerate infrared focal plane array seeker field, especially relate to a kind of analog to digital converter and infrared focal plane array thereof of infrared focal plane array reading circuit.
Background technology
Development along with cmos vlsi technology, infrared focus plane technology and digital integrated circuit technology, people recognize gradually changes the analog output signal of infrared focus plane into digital signal output, can improve the antijamming capability of signal in transmitting procedure, improve the signal to noise ratio of signal, this is also the continuous miniaturization of third generation infrared focus plane technology, improves constantly the development trend of integrated level simultaneously.
Analog to digital converter on the infrared focus plane sheet (ADC) technology is to realize the infrared focus plane analog signal output is changed into a very crucial technology of digital signal output, on the sheet of reading circuit, ADC is device very crucial in the infrared focal plane read-out circuit digitlization, for the final performance after the infrared focus plane digitlization, plays conclusive impact.Kind and the framework of ADC are many, make in the design process of reading circuit and often run into multiple choices.
Non-refrigerated infrared focal plane probe is at room temperature worked, and has the advantages such as low cost, low-power consumption, miniaturization and high reliability, is widely used in the military and civilian field.It wishes the voltage response rate that obtains larger temperature response scope and have good linearity by reading circuit in use, and most of follow-up Non-uniformity Correction Algorithm is all at the supposition probe unit, to the response characteristic of target temperature, to be to carry out on linear basis.And, by changing the relation of incident black body radiation investigation responsiveness and incident radiation, obtain the Infrared Detectors output voltage and present very important non-linear relation with the radiant flux be radiated in photosensitive unit.
Change from Planck law and target temperature the relation that causes detector sensing unit variations in temperature, the sensing unit temperature is nonlinear change with target temperature, and nonlinear radiation to make biasing circuit produce voltage response be also nonlinear, target temperature makes simulation output be nonlinear change, the infrared radiation of sensing unit being experienced through traditional reading circuit ADC carries out analog-to-digital conversion, and the numeral output obtained also is non-linear with target temperature.So it is significant to study on a kind of sheet of the non-refrigerating infrared focal plane reading circuit with non-linear radiation compensation function ADC.
Summary of the invention
One of purpose of the present invention is to provide a kind of analog to digital converter and infrared focal plane array thereof with infrared focal plane array reading circuit of non-linear radiation compensation function, to realize the linearisation of reading circuit output signal.
The disclosed technical scheme of the embodiment of the present invention comprises:
A kind of analog to digital converter of infrared focal plane array reading circuit is provided, has it is characterized in that, having comprised: comparator, described comparator comprises in-phase input end, inverting input and output; Biasing circuit, the output of described biasing circuit is connected to the described inverting input of described comparator; Linear ramp generator, the output of described linear ramp generator is connected to the said in-phase input end of described comparator; Latch, described latch comprises control input end and latch data input, the output of described comparator is connected to the described control input end of described latch; The nonlinear compensation counter, the enumeration data output of described nonlinear compensation counter is connected to the described latch data input of described latch; Described nonlinear compensation counter arrives described latch to not waiting cycle counting clock sequence to count also output count data; The wherein said cycle counting clock sequence that do not wait comprises at least two counting clock subsequences, and wherein the counting clock cycle at least one counting clock subsequence different from the counting clock cycle in all the other counting clock subsequences.
In one embodiment of the invention, described nonlinear compensation counter comprises: fundamental clock; Do not wait the cycle clock generator, the output of described fundamental clock is connected to the described input that does not wait the cycle clock generator, and the described clock signal that does not wait the cycle clock generator to provide according to described fundamental clock generates the described cycle counting clock sequence that do not wait; Counter, the described output that does not wait the cycle clock generator is connected to the counting clock input of described counter, and the output of described counter is the enumeration data output of described nonlinear compensation counter; Wherein said counter is counted the described cycle counting clock sequence that do not wait.
In one embodiment of the invention, the described cycle counting clock sequence that do not wait comprises an initial clock subsequence and at least two counting clock subsequences.
In one embodiment of the invention, the clock signal in described initial clock subsequence remains low level.
In one embodiment of the invention, the described cycle counting clock sequence that do not wait comprises m counting clock subsequence, wherein
,
expression rounds up, and M is for meeting
minimum value, be wherein controlling elements, ψ
ifor i straightway of the function relation curve between the comparison time of the output of the numeral of the described latch of linear approximation and described comparator, the numeral that ψ is described latch is exported and the function relation curve between comparison time of described comparator,
the norm that means above-mentioned two functions in i time period.
In one embodiment of the invention, the number of the counting clock in each described counting clock subsequence is identical.
A kind of infrared focal plane array also is provided in embodiments of the invention, has comprised reading circuit, it is characterized in that: described reading circuit comprises previously described any one analog to digital converter.
In the analog to digital converter of embodiments of the invention, use the nonlinear compensation counter, can effectively compensate numeral output and the non-linear of target temperature, eliminate by non-linear radiation-induced output nonlinear, improve the linearity of voltage response rate, expansion linear temperature response range.And the nonlinear compensation counter of this analog to digital converter has the adjustable function of zero-time, improved the availability of digital code, improved effective resolution.
The analog to digital converter of embodiments of the invention is highly suitable in the Infrared Detectors of low power consumption and small volume and applies, and has great market development potentiality.
The accompanying drawing explanation
Fig. 1 is the electrical block diagram of existing analog to digital converter.
Fig. 2 is the schematic diagram that concerns of the output of existing analog to digital converter and target temperature.
Fig. 3 is the electrical block diagram of the analog to digital converter of one embodiment of the invention.
Fig. 4 is the schematic diagram that concerns of the output of analog to digital converter of one embodiment of the invention and target temperature.
Fig. 5 is the sequential schematic diagram of the nonlinear compensation counter of one embodiment of the invention.
Embodiment
Describe below with reference to the accompanying drawings embodiments of the invention in detail.
The analog to digital converter of infrared focal plane array reading circuit of the prior art (ADC) generally includes biasing circuit 10, linear ramp generator 12, comparator 15, latch 16 sum counters 18.Its electrical block diagram as shown in Figure 1, is not described in detail at this.
In the analog to digital converter of the infrared focal plane array reading circuit of the prior art shown in Fig. 1, adopted conventional counter 18.The analog output voltage Vout obtained in this circuit is:
In formula, V
rEFfor reference voltage, Vs is the sensing unit bias voltage, I
bfor the reference electric current; R
s0for the initial resistance of sensing unit, α is temperature coefficient of resistance (TCR); t
iNTfor the time of integration, C
iNTfor integrating capacitor.Can be by the Taylor expansion abbreviation:
When ignoring TCR and change with temperature, the thermal radiation of the known detection of a target because of infrared focal plane array is nonlinear, the voltage response of infrared focal plane array is also nonlinear, rising along with target temperature, the output voltage of focal plane array raises gradually, and changes during low temperature slowly, during high temperature, changes rapidly, therefore show cryogenic object detection details unintelligible, and high temp objects is crossed the phenomenon of response.
The schematic diagram that target temperature changes the variation cause output as shown in Figure 2.Be followed successively by analog output voltage and target temperature relation curve, analog output voltage and relatively time curve, numeral output and relatively time curve and numeral output and target temperature relation curve by (a) to (d) in Fig. 2.
By Fig. 2 (a), can be found out, target temperature makes simulation output V
outbe nonlinear change.The impact of ramp generator on output in Fig. 2 (b) corresponding A DC, the impact of Fig. 2 (c) corresponding A DC Counter on output.
By Fig. 2 (d), can be found out, because the low temperature response is lower, from 0V to 1V, there is the response output voltage hardly in left and right, and lower digital code is output in actual use hardly, has reduced effective resolution simultaneously.
The structural representation of the analog to digital converter of a kind of infrared focal plane array reading circuit that Fig. 3 is one embodiment of the invention.As shown in Figure 3, in the present embodiment, the analog to digital converter of infrared focal plane array reading circuit comprises comparator offset circuit 10, linear ramp generator 12, comparator 15, latch 16 and nonlinear compensation counter 28.
Comparator 15 comprises in-phase input end, inverting input and output, and the output of biasing circuit 10 is connected to the inverting input of comparator.Here, the concrete structure of biasing circuit 10 can be identical with the bias circuit construction in the analog to digital converter of infrared focal plane array reading circuit commonly used in this area, at this, is not described in detail.
The output of linear ramp generator 12 is connected to the in-phase input end of comparator 15.Linear ramp generator 12 is for generation of linear oblique wave, and its concrete structure can be identical with linear ramp generator commonly used in this area, at this, is not described in detail.
Latch 16 comprises control input end and latch data input.The output of comparator 15 is connected to the control input end of latch 16.The figure place of latch can be N.Here, N is greater than zero integer.
The enumeration data output of nonlinear compensation counter 28 is connected to the latch data input of latch 16.
In embodiments of the invention, 28 pairs, nonlinear compensation counter do not wait cycle counting clock sequence count and output count data to latch 15.Wherein, in embodiments of the invention, this does not wait cycle counting clock sequence to comprise at least two counting clock subsequences, and wherein the counting clock cycle at least one counting clock subsequence different from the counting clock cycle in all the other counting clock subsequences.
Herein, said " counting clock sequence " refers to have a series of clock pulse signals, and its Counter is counted these clock pulse signals; Said " counting clock subsequence " refers to subset or the part in these a series of clock pulse signals.
As seen from Figure 3, the linearity output oblique wave V that linear ramp generator 12 produces
rampthe in-phase input end of access comparator 15, the analog output voltage V that becomes non-linear relation with target temperature that biasing circuit 10 produces
outthe inverting input of access comparator 15, comparator 15 is at V
out=V
rampthe Shi Jinhang upset; The output of comparator 15 connects N position latch 16, and wherein N is greater than zero integer, and N position latch 16 is exported N bit digital output signal D under the control of comparator 15
-out.
In embodiments of the invention, adopted a nonlinear compensation counter 28 to replace conventional counter.As shown in Figure 3, this nonlinear compensation counter 28 comprises fundamental clock 282, does not wait cycle clock generator 286 sum counters 280.
The output of fundamental clock 282 is connected to the input that does not wait cycle clock generator 286, for not waiting cycle clock generator 286, provides basic clock signal.The fundamental clock 282 here can be clock source commonly used, such as crystal oscillator etc.
The clock signal that does not wait cycle clock generator 286 to provide according to fundamental clock 282 generates the aforesaid cycle counting clock sequence (hereinafter describing in detail) that do not wait.
Do not wait the output of cycle clock generator 286 to be connected to the counting clock input of counter 280, here, the output of this counter 280 is the enumeration data output of this nonlinear compensation counter 28.Here, the cycle counting clock sequence that do not wait that 280 pairs, this counter does not wait cycle clock generator 286 to provide is counted.In embodiments of the invention, counter 280 can be conventional counter.
As shown in Figure 5, wherein clk is a fundamental clock to the counting sequence figure of an example of counter 280, i.e. the clock signal of fundamental clock 282 outputs, the namely counting clock of conventional counter; clk
outfor the aforesaid example that does not wait cycle counting clock sequence, the namely example of the counting clock of nonlinear compensation counter 28.
Below describe in detail and do not wait cycle counting clock sequence and production process thereof.
In the analog-digital converter structure of the embodiment of the present invention, target temperature change cause output variation as shown in Figure 4, below in conjunction with Fig. 4, Fig. 5, this nonlinear compensation counter is further described in detail.
Fig. 4 (a) is analog output voltage V
outwith target temperature T
trelation, suppose that the functional relation of the two is
, Fig. 4 (b) is analog output voltage V
outrelation with comparing time t, be expressed as
, in order to make digital output signal D-in Fig. 4 (d)
outwith target temperature T
tlinear
, can be from Fig. 4 (c) digital output signal D-
outset about with the relation that compares time t, try to achieve the function expression satisfied condition.Method for solving can be as follows:
First obtain in Fig. 4 (a)
inverse function,
, then by Fig. 4 (b)
, in Fig. 4 (d)
the substitution above formula, obtain digital output signal D-
outwith the functional relation that compares time t, be
, be designated as
.
The cycle counting clock sequence that do not wait in the embodiment of the present invention can be according to function
counted.From this function, numeral output is nonlinear curve with the relation curve that compares the time, can be approached and be formed by m section straight linear, and every section straight line is designated as ψ
i, 1≤i≤m wherein.For meeting above-mentioned non-linear relation, the counting clock cycle in different sections should not waited; For realizing the nonlinear compensation function, the counting number of every section straight line Counter should equate.
The m value of dividing hop count is satisfied by solving
minimum M value come to determine,
, be wherein controlling elements, be used for controlling the approximation ratio of straightway to curve, can select as required, less, the M value is larger, and straightway is better to the fitting effect of curve; Solve the functional problem, while determining M, time shaft has been divided into to the M section; ψ
inumeral output V for linear approximation latch 16
outand i straightway of the function relation curve between the comparison time t of comparator 15.
In Fig. 4 (b) and Fig. 4 (c), according to the m value of trying to achieve, time shaft is divided into to the m+1 section, the concrete division according to solving the functional problem, while determining M, the M section of having divided suitably is similar to and divides.Be designated as successively T
0time period, T
1time period ..., T
mtime period.At T
1~ T
min time period, the number of every section accrued same number, be assumed to be n, and the output area of N position ADC is 0～2
n-1, the counting maximum of corresponding counter is 2
n,
.The nonlinear compensation counter, within m the time period of dividing, is counted by the different time cycles, counts the n number for every section.All clock pulse in this m+1 time period have formed the aforesaid cycle counting clock sequence that do not wait, namely the counting clock sequence of nonlinear compensation counter 28.
At T
0in time period, the counting output clock clk of non-linear radiation compensation counter
outkeep low level always, wait for the beginning of counting.Just because of this T is arranged
0the stand-by period of time period, make non-linear radiation compensation counter there is the adjustable function of counting zero-time, make counting not from the zero point of time coordinate axle, correspond in the numeral output and target temperature graph of a relation of Fig. 4 (d), start just to have the response output voltage from 0V, make all digital codes all obtain abundant use.
For example, at T1, in the time period, count the n number, every
1 number of time meter, here, computing "
" mean to round up computing, make
integral multiple for fundamental clock clk.Output clock clk
outat T
1clock cycle clk1 in time period is
, from high level, through a clk1 counting, add 1, until the T1 time period finishes, one has amounted to the n number.
Similarly, at T
2in time period, also to count the n number, every
time meter 1 number, output clock clk
outat T
2clock cycle clk2 in time period is
, from high level, add 1 through a clk2 counting, until T
2time period finishes, and has counted again the n number, and now one has amounted to the 2n number.
The rest may be inferred, at T
3clk in time period
outcount cycle be
..., at T
mclk in time period
outcount cycle be
, each time period meter n number, divided m+1 time period, and removing first time period is the stand-by period section, and total m the time period, at counting, always amounted to
number, in the present invention that hence one can see that on sheet the precision of ADC be
bit, wherein
expression rounds up.
As shown in Figure 4 (c), the digital relation with the time of counting is no longer the linear relationship of conventional counter to the relation that obtains digital code and gate time according to this counting sequence, and presents a kind of piecewise linear relation.T
1~ T
meach is unequal, in each time period the nonlinear compensation counter count cycle clk1 ~ clk m is also unequal, and increase successively.The division of time period is closeer, corresponding diagram 4(c) in curve more level and smooth, the digital more approaching non-linear relation with gamma curve characteristic of relation with the time of counting.The mode that this gamma curve is arranged just, make the nonlinear compensation counter in the present invention have the function of gamma correction, and gamma correction is a compensation of nonlinearity process.Correspond in the numeral output and target temperature graph of a relation of Fig. 4 (d), can find out by the nonlinear curve of nonlinear compensation counter, eliminated the nonlinearity of output signal, to numeral output D
outcompensate with the non-linear of target temperature, make the relation of digital output signal and target temperature become linearity.
Herein, by this T
0clock pulse sequence in time period is called " initial clock subsequence ", and the counting clock pulse sequence in all the other time periods is called " counting clock subsequence ".Therefore, in above, in one embodiment of the present of invention, do not wait cycle counting clock sequence can comprise an initial clock subsequence and at least two counting clock subsequences.
In embodiments of the invention, can also provide a kind of infrared focal plane array, this infrared focal plane array comprises reading circuit, this reading circuit any one analog to digital converter described in comprising above.
In the analog to digital converter of embodiments of the invention, use the nonlinear compensation counter, can effectively compensate numeral output and the non-linear of target temperature, eliminate by non-linear radiation-induced output nonlinear, improve the linearity of voltage response rate, expansion linear temperature response range.And the nonlinear compensation counter of this analog to digital converter has the adjustable function of zero-time, improved the availability of digital code, improved effective resolution.
Abovely by specific embodiment, describe the present invention, but the present invention is not limited to these specific embodiments.It will be understood by those skilled in the art that and can also make various modifications to the present invention, be equal to replacement, change etc., these conversion, all should be within protection scope of the present invention as long as do not deviate from spirit of the present invention.In addition, above many places described " embodiment " means different embodiment, can certainly be by its all or part of combination in one embodiment.
Claims (7)
1. the analog to digital converter of an infrared focal plane array reading circuit, is characterized in that, comprising:
Comparator, described comparator comprises in-phase input end, inverting input and output;
Biasing circuit, the output of described biasing circuit is connected to the described inverting input of described comparator;
Linear ramp generator, the output of described linear ramp generator is connected to the said in-phase input end of described comparator;
Latch, described latch comprises control input end and latch data input, the output of described comparator is connected to the described control input end of described latch;
The nonlinear compensation counter, the enumeration data output of described nonlinear compensation counter is connected to the described latch data input of described latch;
Described nonlinear compensation counter arrives described latch to not waiting cycle counting clock sequence to count also output count data;
The wherein said cycle counting clock sequence that do not wait comprises at least two counting clock subsequences, and wherein the counting clock cycle at least one counting clock subsequence different from the counting clock cycle in all the other counting clock subsequences.
2. analog to digital converter as claimed in claim 1, is characterized in that, described nonlinear compensation counter comprises:
Fundamental clock;
Do not wait the cycle clock generator, the output of described fundamental clock is connected to the described input that does not wait the cycle clock generator, and the described clock signal that does not wait the cycle clock generator to provide according to described fundamental clock generates the described cycle counting clock sequence that do not wait;
Counter, the described output that does not wait the cycle clock generator is connected to the counting clock input of described counter, and the output of described counter is the enumeration data output of described nonlinear compensation counter;
Wherein said counter is counted the described cycle counting clock sequence that do not wait.
3. as claim 1 or 2 described analog to digital converters, it is characterized in that:
The described cycle counting clock sequence that do not wait comprises an initial clock subsequence and at least two counting clock subsequences.
4. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:
Clock signal in described initial clock subsequence remains low level.
5. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:
The described cycle counting clock sequence that do not wait comprises m counting clock subsequence, wherein
,
expression rounds up, and M is for meeting
minimum value, be wherein controlling elements, ψ
ifor i straightway of the function relation curve between the comparison time of the output of the numeral of the described latch of linear approximation and described comparator, the numeral that ψ is described latch is exported and the function relation curve between comparison time of described comparator,
the norm that means i time period inner function.
6. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:
The number of the counting clock in each described counting clock subsequence is identical.
7. an infrared focal plane array, comprise reading circuit, it is characterized in that: described reading circuit comprises the described analog to digital converter of any one in claim 1 to 6.
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| CN107462334B (en) * | 2017-09-14 | 2019-07-02 | 电子科技大学 | Infrared focal plane read-out circuit and its feedback control loop |
| US11543297B2 (en) | 2019-07-19 | 2023-01-03 | Industrial Technology Research Institute | Sensing devices |
| CN111263090A (en) * | 2020-03-02 | 2020-06-09 | 上海集成电路研发中心有限公司 | Reading circuit structure and working time sequence control method thereof |
| CN111263090B (en) * | 2020-03-02 | 2022-02-22 | 上海集成电路研发中心有限公司 | Reading circuit structure and working time sequence control method thereof |
| CN112003617A (en) * | 2020-08-28 | 2020-11-27 | 电子科技大学 | Analog-digital conversion device and method with substrate temperature compensation for infrared focal plane |
| CN112003617B (en) * | 2020-08-28 | 2022-11-08 | 电子科技大学 | Analog-digital conversion device and method with substrate temperature compensation for infrared focal plane |
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